From: "Michael S. Tsirkin" <mst@redhat.com>
To: David Vrabel <david.vrabel@nutanix.com>
Cc: "qemu-devel@nongnu.org" <qemu-devel@nongnu.org>,
"Zhao Liu" <zhao1.liu@intel.com>,
"Philippe Mathieu-Daudé" <philmd@oss.qualcomm.com>,
"Paolo Bonzini" <pbonzini@redhat.com>,
"Pierrick Bouvier" <pierrick.bouvier@oss.qualcomm.com>
Subject: Re: [PATCH v3 0/4] hw/pci-bridge: Configurable apparent bandwidth for the PCIe topology
Date: Tue, 27 Oct 2026 07:49:20 -0400 [thread overview]
Message-ID: <20261027074859-mutt-send-email-mst@kernel.org> (raw)
In-Reply-To: <712fbce9-8b13-47c1-b0cb-b9f20807f05f@nutanix.com>
On Tue, Oct 27, 2026 at 11:18:27AM +0000, David Vrabel wrote:
> Hi Michael,
>
> On 15/10/2026 15:10, Michael S. Tsirkin wrote:
> >
> > On Thu, Oct 15, 2026 at 02:41:55PM +0100, David Vrabel wrote:
> > >
> > > ping?
> > > On 28/09/2026 16:24, David Vrabel wrote:
> > > > When a VM has been assigned a number of PCIe devices behind a common
> > > > PCIe switch and the VM intends to use peer-to-peer (P2P) transfers
> > > > between the devices, it is useful to be able to more report the
> > > > apparent PCIe bandwidth so it reflects the real handwidth of the
> > > > underlying hardware. This allows software in the VM (such as NCCL[1])
> > > > to make better decisions about whether to use P2P or not.
> >
> > will merge, thanks!
>
> I appreciate you might be swamped by a pile of AI-generated security work,
> or perhaps I'm missing some QEMU-specific process (merge window?), but can
> you estimate when this might be merged, thanks?
>
> If it helps I can prepare a gitlab pull request.
>
> David
This week, sorry about the delay.
--
MST
prev parent reply other threads:[~2026-10-27 11:50 UTC|newest]
Thread overview: 9+ messages / expand[flat|nested] mbox.gz Atom feed top
2026-09-28 15:24 [PATCH v3 0/4] hw/pci-bridge: Configurable apparent bandwidth for the PCIe topology David Vrabel
2026-09-28 15:24 ` [PATCH v3 1/4] hw/pci-bridge: Add generic PCIe switch upstream and downstream ports David Vrabel
2026-09-28 15:24 ` [PATCH v3 2/4] hw/pci-bridge: Make speed and width for PCIe ports non-experimental David Vrabel
2026-09-28 15:24 ` [PATCH v3 3/4] hw/pci-bridge: Default the generic PCIe root port as Gen6 capable David Vrabel
2026-09-28 15:24 ` [PATCH v3 4/4] hw/pci: Ensure PCIe link speed/width is consistent between both ends David Vrabel
2026-10-15 13:41 ` [PATCH v3 0/4] hw/pci-bridge: Configurable apparent bandwidth for the PCIe topology David Vrabel
2026-10-15 14:10 ` Michael S. Tsirkin
2026-10-27 11:18 ` David Vrabel
2026-10-27 11:49 ` Michael S. Tsirkin [this message]
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