* [PATCH] drm/amd/display: add missing CRC engine 1 registers
@ 2026-10-28 9:14 Wayne Lin
2026-10-28 11:16 ` Mikhail Gavrilov
2026-10-28 13:57 ` Chung, ChiaHsuan (Tom)
0 siblings, 2 replies; 3+ messages in thread
From: Wayne Lin @ 2026-10-28 9:14 UTC (permalink / raw)
To: amd-gfx; +Cc: Harry Wentland, Leo Li, Tom Chung, Mikhail Gavrilov, Wayne Lin
[why]
Opening the CRTC CRC debugfs file programs every CRC engine. On
several generations the engine 1 window and data entries were missing,
so configure hits a zero field mask and WARNs. DCN4.2, DCN4.2B, and
DCN6.0 already had those entries, but configure still writes
OTG_CRC1_SELECT with no mask check. DCN6.0 also lacks OTG_CRC1_EN, so
optc1_configure_crc() writes OTG_CRC_EN instead. The ASIC headers
already define the addresses and fields. The driver tables did not
list them.
[how]
How the missing entries are filled in:
1. DCN3.0 through DCN3.0.3 use OPTC_COMMON_*_DCN3_BASE. Add the six
engine 1 addresses and the window, data, and OTG_CRC1_SELECT masks.
These headers have no OTG_CRC1_EN bit, so that field is not added.
2. DCN3.1 uses OPTC_COMMON_*_DCN3_1. Add the same addresses and masks,
including OTG_CRC1_EN. dcn_3_1_2 defines that bit. DCN3.1.5
and DCN3.1.6 expand DCN3_1 through DCN31X. DCN3.1.4 has its own
list. OTG_CRC1_EN was already on it, so only addresses, SELECT,
window, and data are added.
3. DCN3.2 and DCN3.2.1 already had OTG_CRC1_EN and OTG_CRC1_SELECT.
Add the window and data masks in the OPTC header and the addresses
in the resource header. DCN3.2 fills addresses at init from
ctx->dcn_reg_offsets[].
4. DCN4.0.1 also uses optc1_configure_crc() and was missing SELECT,
window, and data. Add those masks and the six addresses.
OTG_CRC1_EN was already present.
5. DCN3.5, DCN3.5.1, and DCN3.6 already have the addresses and program
engine 1 through optc35_configure_crc(). Their mask list included
DCN3.2 and then repeated the CRC1 window and data fields. Drop the
duplicates.
6. DCN2.0, DCN2.0.1, and DCN2.1 are left unchanged. They inherit the
DCN1.0 lists, which already name engine 1 window, data, and
OTG_CRC1_SELECT. Their headers have no OTG_CRC1_EN bit.
7. DCN4.2 and DCN4.2B use optc35_configure_crc(). Window, data, and
OTG_CRC1_EN were already present. Add OTG_CRC1_SELECT. DCN6.0 uses
optc1_configure_crc(). Window and data were already present. Add
OTG_CRC1_SELECT and OTG_CRC1_EN.
Fixes: ef45aaf73717 ("drm/amd/display: Configure all CRC engines in pipe CRC source path")
Cc: Mikhail Gavrilov <mikhail.v.gavrilov@gmail.com>
Reported-by: Mikhail Gavrilov <mikhail.v.gavrilov@gmail.com>
Signed-off-by: Wayne Lin <Wayne.Lin@amd.com>
Assisted-by: Cursor:Grok 4.7
---
.../amd/display/dc/optc/dcn30/dcn30_optc.h | 18 +++++++++++++++
.../amd/display/dc/optc/dcn31/dcn31_optc.h | 22 +++++++++++++++++--
.../amd/display/dc/optc/dcn314/dcn314_optc.h | 18 +++++++++++++++
.../amd/display/dc/optc/dcn32/dcn32_optc.h | 11 ++++++++++
.../amd/display/dc/optc/dcn35/dcn35_optc.h | 11 ----------
.../amd/display/dc/optc/dcn401/dcn401_optc.h | 12 ++++++++++
.../amd/display/dc/optc/dcn42/dcn42_optc.h | 2 ++
.../amd/display/dc/optc/dcn60/dcn60_optc.h | 2 ++
.../dc/resource/dcn32/dcn32_resource.h | 6 +++++
.../dc/resource/dcn401/dcn401_resource.h | 6 +++++
10 files changed, 95 insertions(+), 13 deletions(-)
diff --git a/drivers/gpu/drm/amd/display/dc/optc/dcn30/dcn30_optc.h b/drivers/gpu/drm/amd/display/dc/optc/dcn30/dcn30_optc.h
index 16c5610b49ac..b801989f10cf 100644
--- a/drivers/gpu/drm/amd/display/dc/optc/dcn30/dcn30_optc.h
+++ b/drivers/gpu/drm/amd/display/dc/optc/dcn30/dcn30_optc.h
@@ -91,6 +91,12 @@
SRI(OTG_CRC0_WINDOWA_Y_CONTROL, OTG, inst),\
SRI(OTG_CRC0_WINDOWB_X_CONTROL, OTG, inst),\
SRI(OTG_CRC0_WINDOWB_Y_CONTROL, OTG, inst),\
+ SRI(OTG_CRC1_DATA_RG, OTG, inst),\
+ SRI(OTG_CRC1_DATA_B, OTG, inst),\
+ SRI(OTG_CRC1_WINDOWA_X_CONTROL, OTG, inst),\
+ SRI(OTG_CRC1_WINDOWA_Y_CONTROL, OTG, inst),\
+ SRI(OTG_CRC1_WINDOWB_X_CONTROL, OTG, inst),\
+ SRI(OTG_CRC1_WINDOWB_Y_CONTROL, OTG, inst),\
SR(GSL_SOURCE_SELECT),\
SRI(OTG_TRIGA_MANUAL_TRIG, OTG, inst),\
SRI(OTG_DRR_CONTROL, OTG, inst)
@@ -229,6 +235,7 @@
SF(OTG0_OTG_GSL_CONTROL, OTG_GSL_CHECK_ALL_FIELDS, mask_sh),\
SF(OTG0_OTG_CRC_CNTL, OTG_CRC_CONT_EN, mask_sh),\
SF(OTG0_OTG_CRC_CNTL, OTG_CRC0_SELECT, mask_sh),\
+ SF(OTG0_OTG_CRC_CNTL, OTG_CRC1_SELECT, mask_sh),\
SF(OTG0_OTG_CRC_CNTL, OTG_CRC_EN, mask_sh),\
SF(OTG0_OTG_CRC_CNTL2, OTG_CRC_DSC_MODE, mask_sh),\
SF(OTG0_OTG_CRC_CNTL2, OTG_CRC_DATA_STREAM_COMBINE_MODE, mask_sh),\
@@ -245,6 +252,17 @@
SF(OTG0_OTG_CRC0_WINDOWB_X_CONTROL, OTG_CRC0_WINDOWB_X_END, mask_sh),\
SF(OTG0_OTG_CRC0_WINDOWB_Y_CONTROL, OTG_CRC0_WINDOWB_Y_START, mask_sh),\
SF(OTG0_OTG_CRC0_WINDOWB_Y_CONTROL, OTG_CRC0_WINDOWB_Y_END, mask_sh),\
+ SF(OTG0_OTG_CRC1_DATA_RG, CRC1_R_CR, mask_sh),\
+ SF(OTG0_OTG_CRC1_DATA_RG, CRC1_G_Y, mask_sh),\
+ SF(OTG0_OTG_CRC1_DATA_B, CRC1_B_CB, mask_sh),\
+ SF(OTG0_OTG_CRC1_WINDOWA_X_CONTROL, OTG_CRC1_WINDOWA_X_START, mask_sh),\
+ SF(OTG0_OTG_CRC1_WINDOWA_X_CONTROL, OTG_CRC1_WINDOWA_X_END, mask_sh),\
+ SF(OTG0_OTG_CRC1_WINDOWA_Y_CONTROL, OTG_CRC1_WINDOWA_Y_START, mask_sh),\
+ SF(OTG0_OTG_CRC1_WINDOWA_Y_CONTROL, OTG_CRC1_WINDOWA_Y_END, mask_sh),\
+ SF(OTG0_OTG_CRC1_WINDOWB_X_CONTROL, OTG_CRC1_WINDOWB_X_START, mask_sh),\
+ SF(OTG0_OTG_CRC1_WINDOWB_X_CONTROL, OTG_CRC1_WINDOWB_X_END, mask_sh),\
+ SF(OTG0_OTG_CRC1_WINDOWB_Y_CONTROL, OTG_CRC1_WINDOWB_Y_START, mask_sh),\
+ SF(OTG0_OTG_CRC1_WINDOWB_Y_CONTROL, OTG_CRC1_WINDOWB_Y_END, mask_sh),\
SF(OTG0_OTG_TRIGA_MANUAL_TRIG, OTG_TRIGA_MANUAL_TRIG, mask_sh),\
SF(GSL_SOURCE_SELECT, GSL0_READY_SOURCE_SEL, mask_sh),\
SF(GSL_SOURCE_SELECT, GSL1_READY_SOURCE_SEL, mask_sh),\
diff --git a/drivers/gpu/drm/amd/display/dc/optc/dcn31/dcn31_optc.h b/drivers/gpu/drm/amd/display/dc/optc/dcn31/dcn31_optc.h
index 19d90c65a22b..c56512455338 100644
--- a/drivers/gpu/drm/amd/display/dc/optc/dcn31/dcn31_optc.h
+++ b/drivers/gpu/drm/amd/display/dc/optc/dcn31/dcn31_optc.h
@@ -83,6 +83,12 @@
SRI(OTG_CRC0_WINDOWA_Y_CONTROL, OTG, inst),\
SRI(OTG_CRC0_WINDOWB_X_CONTROL, OTG, inst),\
SRI(OTG_CRC0_WINDOWB_Y_CONTROL, OTG, inst),\
+ SRI(OTG_CRC1_DATA_RG, OTG, inst),\
+ SRI(OTG_CRC1_DATA_B, OTG, inst),\
+ SRI(OTG_CRC1_WINDOWA_X_CONTROL, OTG, inst),\
+ SRI(OTG_CRC1_WINDOWA_Y_CONTROL, OTG, inst),\
+ SRI(OTG_CRC1_WINDOWB_X_CONTROL, OTG, inst),\
+ SRI(OTG_CRC1_WINDOWB_Y_CONTROL, OTG, inst),\
SR(GSL_SOURCE_SELECT),\
SRI(OTG_TRIGA_MANUAL_TRIG, OTG, inst),\
SRI(OTG_GLOBAL_CONTROL1, OTG, inst),\
@@ -205,7 +211,9 @@
SF(OTG0_OTG_GSL_CONTROL, OTG_GSL_CHECK_ALL_FIELDS, mask_sh),\
SF(OTG0_OTG_CRC_CNTL, OTG_CRC_CONT_EN, mask_sh),\
SF(OTG0_OTG_CRC_CNTL, OTG_CRC0_SELECT, mask_sh),\
+ SF(OTG0_OTG_CRC_CNTL, OTG_CRC1_SELECT, mask_sh),\
SF(OTG0_OTG_CRC_CNTL, OTG_CRC_EN, mask_sh),\
+ SF(OTG0_OTG_CRC_CNTL, OTG_CRC1_EN, mask_sh),\
SF(OTG0_OTG_CRC0_DATA_RG, CRC0_R_CR, mask_sh),\
SF(OTG0_OTG_CRC0_DATA_RG, CRC0_G_Y, mask_sh),\
SF(OTG0_OTG_CRC0_DATA_B, CRC0_B_CB, mask_sh),\
@@ -217,6 +225,17 @@
SF(OTG0_OTG_CRC0_WINDOWB_X_CONTROL, OTG_CRC0_WINDOWB_X_END, mask_sh),\
SF(OTG0_OTG_CRC0_WINDOWB_Y_CONTROL, OTG_CRC0_WINDOWB_Y_START, mask_sh),\
SF(OTG0_OTG_CRC0_WINDOWB_Y_CONTROL, OTG_CRC0_WINDOWB_Y_END, mask_sh),\
+ SF(OTG0_OTG_CRC1_DATA_RG, CRC1_R_CR, mask_sh),\
+ SF(OTG0_OTG_CRC1_DATA_RG, CRC1_G_Y, mask_sh),\
+ SF(OTG0_OTG_CRC1_DATA_B, CRC1_B_CB, mask_sh),\
+ SF(OTG0_OTG_CRC1_WINDOWA_X_CONTROL, OTG_CRC1_WINDOWA_X_START, mask_sh),\
+ SF(OTG0_OTG_CRC1_WINDOWA_X_CONTROL, OTG_CRC1_WINDOWA_X_END, mask_sh),\
+ SF(OTG0_OTG_CRC1_WINDOWA_Y_CONTROL, OTG_CRC1_WINDOWA_Y_START, mask_sh),\
+ SF(OTG0_OTG_CRC1_WINDOWA_Y_CONTROL, OTG_CRC1_WINDOWA_Y_END, mask_sh),\
+ SF(OTG0_OTG_CRC1_WINDOWB_X_CONTROL, OTG_CRC1_WINDOWB_X_START, mask_sh),\
+ SF(OTG0_OTG_CRC1_WINDOWB_X_CONTROL, OTG_CRC1_WINDOWB_X_END, mask_sh),\
+ SF(OTG0_OTG_CRC1_WINDOWB_Y_CONTROL, OTG_CRC1_WINDOWB_Y_START, mask_sh),\
+ SF(OTG0_OTG_CRC1_WINDOWB_Y_CONTROL, OTG_CRC1_WINDOWB_Y_END, mask_sh),\
SF(OTG0_OTG_TRIGA_MANUAL_TRIG, OTG_TRIGA_MANUAL_TRIG, mask_sh),\
SF(GSL_SOURCE_SELECT, GSL0_READY_SOURCE_SEL, mask_sh),\
SF(GSL_SOURCE_SELECT, GSL1_READY_SOURCE_SEL, mask_sh),\
@@ -264,8 +283,7 @@
SF(OTG0_INTERRUPT_DEST, OTG0_IHC_OTG_VERTICAL_INTERRUPT2_DEST, mask_sh)
#define OPTC_COMMON_MASK_SH_LIST_DCN31X(mask_sh)\
- OPTC_COMMON_MASK_SH_LIST_DCN3_1(mask_sh),\
- SF(OTG0_OTG_CRC_CNTL, OTG_CRC1_EN, mask_sh)
+ OPTC_COMMON_MASK_SH_LIST_DCN3_1(mask_sh)
void dcn31_timing_generator_init(struct optc *optc1);
diff --git a/drivers/gpu/drm/amd/display/dc/optc/dcn314/dcn314_optc.h b/drivers/gpu/drm/amd/display/dc/optc/dcn314/dcn314_optc.h
index 7b43c3ecd46b..956eecf0a43a 100644
--- a/drivers/gpu/drm/amd/display/dc/optc/dcn314/dcn314_optc.h
+++ b/drivers/gpu/drm/amd/display/dc/optc/dcn314/dcn314_optc.h
@@ -84,6 +84,12 @@
SRI(OTG_CRC0_WINDOWA_Y_CONTROL, OTG, inst),\
SRI(OTG_CRC0_WINDOWB_X_CONTROL, OTG, inst),\
SRI(OTG_CRC0_WINDOWB_Y_CONTROL, OTG, inst),\
+ SRI(OTG_CRC1_DATA_RG, OTG, inst),\
+ SRI(OTG_CRC1_DATA_B, OTG, inst),\
+ SRI(OTG_CRC1_WINDOWA_X_CONTROL, OTG, inst),\
+ SRI(OTG_CRC1_WINDOWA_Y_CONTROL, OTG, inst),\
+ SRI(OTG_CRC1_WINDOWB_X_CONTROL, OTG, inst),\
+ SRI(OTG_CRC1_WINDOWB_Y_CONTROL, OTG, inst),\
SR(GSL_SOURCE_SELECT),\
SRI(OTG_TRIGA_MANUAL_TRIG, OTG, inst),\
SRI(OTG_GLOBAL_CONTROL1, OTG, inst),\
@@ -204,6 +210,7 @@
SF(OTG0_OTG_GSL_CONTROL, OTG_GSL_CHECK_ALL_FIELDS, mask_sh),\
SF(OTG0_OTG_CRC_CNTL, OTG_CRC_CONT_EN, mask_sh),\
SF(OTG0_OTG_CRC_CNTL, OTG_CRC0_SELECT, mask_sh),\
+ SF(OTG0_OTG_CRC_CNTL, OTG_CRC1_SELECT, mask_sh),\
SF(OTG0_OTG_CRC_CNTL, OTG_CRC_EN, mask_sh),\
SF(OTG0_OTG_CRC_CNTL, OTG_CRC1_EN, mask_sh),\
SF(OTG0_OTG_CRC0_DATA_RG, CRC0_R_CR, mask_sh),\
@@ -217,6 +224,17 @@
SF(OTG0_OTG_CRC0_WINDOWB_X_CONTROL, OTG_CRC0_WINDOWB_X_END, mask_sh),\
SF(OTG0_OTG_CRC0_WINDOWB_Y_CONTROL, OTG_CRC0_WINDOWB_Y_START, mask_sh),\
SF(OTG0_OTG_CRC0_WINDOWB_Y_CONTROL, OTG_CRC0_WINDOWB_Y_END, mask_sh),\
+ SF(OTG0_OTG_CRC1_DATA_RG, CRC1_R_CR, mask_sh),\
+ SF(OTG0_OTG_CRC1_DATA_RG, CRC1_G_Y, mask_sh),\
+ SF(OTG0_OTG_CRC1_DATA_B, CRC1_B_CB, mask_sh),\
+ SF(OTG0_OTG_CRC1_WINDOWA_X_CONTROL, OTG_CRC1_WINDOWA_X_START, mask_sh),\
+ SF(OTG0_OTG_CRC1_WINDOWA_X_CONTROL, OTG_CRC1_WINDOWA_X_END, mask_sh),\
+ SF(OTG0_OTG_CRC1_WINDOWA_Y_CONTROL, OTG_CRC1_WINDOWA_Y_START, mask_sh),\
+ SF(OTG0_OTG_CRC1_WINDOWA_Y_CONTROL, OTG_CRC1_WINDOWA_Y_END, mask_sh),\
+ SF(OTG0_OTG_CRC1_WINDOWB_X_CONTROL, OTG_CRC1_WINDOWB_X_START, mask_sh),\
+ SF(OTG0_OTG_CRC1_WINDOWB_X_CONTROL, OTG_CRC1_WINDOWB_X_END, mask_sh),\
+ SF(OTG0_OTG_CRC1_WINDOWB_Y_CONTROL, OTG_CRC1_WINDOWB_Y_START, mask_sh),\
+ SF(OTG0_OTG_CRC1_WINDOWB_Y_CONTROL, OTG_CRC1_WINDOWB_Y_END, mask_sh),\
SF(OTG0_OTG_TRIGA_MANUAL_TRIG, OTG_TRIGA_MANUAL_TRIG, mask_sh),\
SF(GSL_SOURCE_SELECT, GSL0_READY_SOURCE_SEL, mask_sh),\
SF(GSL_SOURCE_SELECT, GSL1_READY_SOURCE_SEL, mask_sh),\
diff --git a/drivers/gpu/drm/amd/display/dc/optc/dcn32/dcn32_optc.h b/drivers/gpu/drm/amd/display/dc/optc/dcn32/dcn32_optc.h
index 60c01ec28b65..492760779226 100644
--- a/drivers/gpu/drm/amd/display/dc/optc/dcn32/dcn32_optc.h
+++ b/drivers/gpu/drm/amd/display/dc/optc/dcn32/dcn32_optc.h
@@ -146,6 +146,17 @@
SF(OTG0_OTG_CRC0_WINDOWB_X_CONTROL, OTG_CRC0_WINDOWB_X_END, mask_sh),\
SF(OTG0_OTG_CRC0_WINDOWB_Y_CONTROL, OTG_CRC0_WINDOWB_Y_START, mask_sh),\
SF(OTG0_OTG_CRC0_WINDOWB_Y_CONTROL, OTG_CRC0_WINDOWB_Y_END, mask_sh),\
+ SF(OTG0_OTG_CRC1_DATA_RG, CRC1_R_CR, mask_sh),\
+ SF(OTG0_OTG_CRC1_DATA_RG, CRC1_G_Y, mask_sh),\
+ SF(OTG0_OTG_CRC1_DATA_B, CRC1_B_CB, mask_sh),\
+ SF(OTG0_OTG_CRC1_WINDOWA_X_CONTROL, OTG_CRC1_WINDOWA_X_START, mask_sh),\
+ SF(OTG0_OTG_CRC1_WINDOWA_X_CONTROL, OTG_CRC1_WINDOWA_X_END, mask_sh),\
+ SF(OTG0_OTG_CRC1_WINDOWA_Y_CONTROL, OTG_CRC1_WINDOWA_Y_START, mask_sh),\
+ SF(OTG0_OTG_CRC1_WINDOWA_Y_CONTROL, OTG_CRC1_WINDOWA_Y_END, mask_sh),\
+ SF(OTG0_OTG_CRC1_WINDOWB_X_CONTROL, OTG_CRC1_WINDOWB_X_START, mask_sh),\
+ SF(OTG0_OTG_CRC1_WINDOWB_X_CONTROL, OTG_CRC1_WINDOWB_X_END, mask_sh),\
+ SF(OTG0_OTG_CRC1_WINDOWB_Y_CONTROL, OTG_CRC1_WINDOWB_Y_START, mask_sh),\
+ SF(OTG0_OTG_CRC1_WINDOWB_Y_CONTROL, OTG_CRC1_WINDOWB_Y_END, mask_sh),\
SF(OTG0_OTG_TRIGA_MANUAL_TRIG, OTG_TRIGA_MANUAL_TRIG, mask_sh),\
SF(GSL_SOURCE_SELECT, GSL0_READY_SOURCE_SEL, mask_sh),\
SF(GSL_SOURCE_SELECT, GSL1_READY_SOURCE_SEL, mask_sh),\
diff --git a/drivers/gpu/drm/amd/display/dc/optc/dcn35/dcn35_optc.h b/drivers/gpu/drm/amd/display/dc/optc/dcn35/dcn35_optc.h
index 82e0818c8f9f..196596cc9fb6 100644
--- a/drivers/gpu/drm/amd/display/dc/optc/dcn35/dcn35_optc.h
+++ b/drivers/gpu/drm/amd/display/dc/optc/dcn35/dcn35_optc.h
@@ -32,23 +32,12 @@
#define OPTC_COMMON_MASK_SH_LIST_DCN3_5(mask_sh)\
OPTC_COMMON_MASK_SH_LIST_DCN3_2(mask_sh),\
SF(OTG0_OTG_CRC_CNTL, OTG_CRC_WINDOW_DB_EN, mask_sh),\
- SF(OTG0_OTG_CRC1_DATA_RG, CRC1_R_CR, mask_sh),\
- SF(OTG0_OTG_CRC1_DATA_RG, CRC1_G_Y, mask_sh),\
- SF(OTG0_OTG_CRC1_DATA_B, CRC1_B_CB, mask_sh),\
SF(OTG0_OTG_CRC2_DATA_RG, CRC2_R_CR, mask_sh),\
SF(OTG0_OTG_CRC2_DATA_RG, CRC2_G_Y, mask_sh),\
SF(OTG0_OTG_CRC2_DATA_B, CRC2_B_CB, mask_sh),\
SF(OTG0_OTG_CRC3_DATA_RG, CRC3_R_CR, mask_sh),\
SF(OTG0_OTG_CRC3_DATA_RG, CRC3_G_Y, mask_sh),\
SF(OTG0_OTG_CRC3_DATA_B, CRC3_B_CB, mask_sh),\
- SF(OTG0_OTG_CRC1_WINDOWA_X_CONTROL, OTG_CRC1_WINDOWA_X_START, mask_sh),\
- SF(OTG0_OTG_CRC1_WINDOWA_X_CONTROL, OTG_CRC1_WINDOWA_X_END, mask_sh),\
- SF(OTG0_OTG_CRC1_WINDOWA_Y_CONTROL, OTG_CRC1_WINDOWA_Y_START, mask_sh),\
- SF(OTG0_OTG_CRC1_WINDOWA_Y_CONTROL, OTG_CRC1_WINDOWA_Y_END, mask_sh),\
- SF(OTG0_OTG_CRC1_WINDOWB_X_CONTROL, OTG_CRC1_WINDOWB_X_START, mask_sh),\
- SF(OTG0_OTG_CRC1_WINDOWB_X_CONTROL, OTG_CRC1_WINDOWB_X_END, mask_sh),\
- SF(OTG0_OTG_CRC1_WINDOWB_Y_CONTROL, OTG_CRC1_WINDOWB_Y_START, mask_sh),\
- SF(OTG0_OTG_CRC1_WINDOWB_Y_CONTROL, OTG_CRC1_WINDOWB_Y_END, mask_sh),\
SF(OTG0_OTG_CRC0_WINDOWA_X_CONTROL_READBACK, OTG_CRC0_WINDOWA_X_START_READBACK, mask_sh),\
SF(OTG0_OTG_CRC0_WINDOWA_X_CONTROL_READBACK, OTG_CRC0_WINDOWA_X_END_READBACK, mask_sh),\
SF(OTG0_OTG_CRC0_WINDOWA_Y_CONTROL_READBACK, OTG_CRC0_WINDOWA_Y_START_READBACK, mask_sh),\
diff --git a/drivers/gpu/drm/amd/display/dc/optc/dcn401/dcn401_optc.h b/drivers/gpu/drm/amd/display/dc/optc/dcn401/dcn401_optc.h
index 3add972ca2ff..9e4e9d75400a 100644
--- a/drivers/gpu/drm/amd/display/dc/optc/dcn401/dcn401_optc.h
+++ b/drivers/gpu/drm/amd/display/dc/optc/dcn401/dcn401_optc.h
@@ -110,6 +110,7 @@
SF(OTG0_OTG_GSL_CONTROL, OTG_GSL_CHECK_ALL_FIELDS, mask_sh),\
SF(OTG0_OTG_CRC_CNTL, OTG_CRC_CONT_EN, mask_sh),\
SF(OTG0_OTG_CRC_CNTL, OTG_CRC0_SELECT, mask_sh),\
+ SF(OTG0_OTG_CRC_CNTL, OTG_CRC1_SELECT, mask_sh),\
SF(OTG0_OTG_CRC_CNTL, OTG_CRC_EN, mask_sh),\
SF(OTG0_OTG_CRC_CNTL, OTG_CRC1_EN, mask_sh),\
SF(OTG0_OTG_CRC0_DATA_RG, CRC0_R_CR, mask_sh),\
@@ -123,6 +124,17 @@
SF(OTG0_OTG_CRC0_WINDOWB_X_CONTROL, OTG_CRC0_WINDOWB_X_END, mask_sh),\
SF(OTG0_OTG_CRC0_WINDOWB_Y_CONTROL, OTG_CRC0_WINDOWB_Y_START, mask_sh),\
SF(OTG0_OTG_CRC0_WINDOWB_Y_CONTROL, OTG_CRC0_WINDOWB_Y_END, mask_sh),\
+ SF(OTG0_OTG_CRC1_DATA_RG, CRC1_R_CR, mask_sh),\
+ SF(OTG0_OTG_CRC1_DATA_RG, CRC1_G_Y, mask_sh),\
+ SF(OTG0_OTG_CRC1_DATA_B, CRC1_B_CB, mask_sh),\
+ SF(OTG0_OTG_CRC1_WINDOWA_X_CONTROL, OTG_CRC1_WINDOWA_X_START, mask_sh),\
+ SF(OTG0_OTG_CRC1_WINDOWA_X_CONTROL, OTG_CRC1_WINDOWA_X_END, mask_sh),\
+ SF(OTG0_OTG_CRC1_WINDOWA_Y_CONTROL, OTG_CRC1_WINDOWA_Y_START, mask_sh),\
+ SF(OTG0_OTG_CRC1_WINDOWA_Y_CONTROL, OTG_CRC1_WINDOWA_Y_END, mask_sh),\
+ SF(OTG0_OTG_CRC1_WINDOWB_X_CONTROL, OTG_CRC1_WINDOWB_X_START, mask_sh),\
+ SF(OTG0_OTG_CRC1_WINDOWB_X_CONTROL, OTG_CRC1_WINDOWB_X_END, mask_sh),\
+ SF(OTG0_OTG_CRC1_WINDOWB_Y_CONTROL, OTG_CRC1_WINDOWB_Y_START, mask_sh),\
+ SF(OTG0_OTG_CRC1_WINDOWB_Y_CONTROL, OTG_CRC1_WINDOWB_Y_END, mask_sh),\
SF(OTG0_OTG_TRIGA_MANUAL_TRIG, OTG_TRIGA_MANUAL_TRIG, mask_sh),\
SF(GSL_SOURCE_SELECT, GSL0_READY_SOURCE_SEL, mask_sh),\
SF(GSL_SOURCE_SELECT, GSL1_READY_SOURCE_SEL, mask_sh),\
diff --git a/drivers/gpu/drm/amd/display/dc/optc/dcn42/dcn42_optc.h b/drivers/gpu/drm/amd/display/dc/optc/dcn42/dcn42_optc.h
index bc641f6ecd7e..bdda94489a23 100644
--- a/drivers/gpu/drm/amd/display/dc/optc/dcn42/dcn42_optc.h
+++ b/drivers/gpu/drm/amd/display/dc/optc/dcn42/dcn42_optc.h
@@ -137,6 +137,7 @@
SF(OTG0_OTG_GSL_CONTROL, OTG_GSL_CHECK_ALL_FIELDS, mask_sh),\
SF(OTG0_OTG_CRC_CNTL, OTG_CRC_CONT_EN, mask_sh),\
SF(OTG0_OTG_CRC_CNTL, OTG_CRC0_SELECT, mask_sh),\
+ SF(OTG0_OTG_CRC_CNTL, OTG_CRC1_SELECT, mask_sh),\
SF(OTG0_OTG_CRC_CNTL, OTG_CRC_EN, mask_sh),\
SF(OTG0_OTG_CRC_CNTL, OTG_CRC1_EN, mask_sh),\
SF(OTG0_OTG_CRC0_DATA_R, CRC0_R_CR, mask_sh),\
@@ -316,6 +317,7 @@
SF(OTG0_OTG_GSL_CONTROL, OTG_GSL_CHECK_ALL_FIELDS, mask_sh),\
SF(OTG0_OTG_CRC_CNTL, OTG_CRC_CONT_EN, mask_sh),\
SF(OTG0_OTG_CRC_CNTL, OTG_CRC0_SELECT, mask_sh),\
+ SF(OTG0_OTG_CRC_CNTL, OTG_CRC1_SELECT, mask_sh),\
SF(OTG0_OTG_CRC_CNTL, OTG_CRC_EN, mask_sh),\
SF(OTG0_OTG_CRC_CNTL, OTG_CRC1_EN, mask_sh),\
SF(OTG0_OTG_CRC0_DATA_R, CRC0_R_CR, mask_sh),\
diff --git a/drivers/gpu/drm/amd/display/dc/optc/dcn60/dcn60_optc.h b/drivers/gpu/drm/amd/display/dc/optc/dcn60/dcn60_optc.h
index ba207c0e498e..ec40c9180030 100644
--- a/drivers/gpu/drm/amd/display/dc/optc/dcn60/dcn60_optc.h
+++ b/drivers/gpu/drm/amd/display/dc/optc/dcn60/dcn60_optc.h
@@ -109,7 +109,9 @@
SF(OTG0_OTG_GSL_CONTROL, OTG_GSL_FORCE_DELAY, mask_sh),\
SF(OTG0_OTG_CRC_CNTL, OTG_CRC_CONT_EN, mask_sh),\
SF(OTG0_OTG_CRC_CNTL, OTG_CRC0_SELECT, mask_sh),\
+ SF(OTG0_OTG_CRC_CNTL, OTG_CRC1_SELECT, mask_sh),\
SF(OTG0_OTG_CRC_CNTL, OTG_CRC_EN, mask_sh),\
+ SF(OTG0_OTG_CRC_CNTL, OTG_CRC1_EN, mask_sh),\
SF(OTG0_OTG_CRC0_DATA_R, CRC0_R_CR, mask_sh),\
SF(OTG0_OTG_CRC0_DATA_G, CRC0_G_Y, mask_sh),\
SF(OTG0_OTG_CRC0_DATA_B, CRC0_B_CB, mask_sh),\
diff --git a/drivers/gpu/drm/amd/display/dc/resource/dcn32/dcn32_resource.h b/drivers/gpu/drm/amd/display/dc/resource/dcn32/dcn32_resource.h
index 68e7140f1505..fa8cc89cb3f7 100644
--- a/drivers/gpu/drm/amd/display/dc/resource/dcn32/dcn32_resource.h
+++ b/drivers/gpu/drm/amd/display/dc/resource/dcn32/dcn32_resource.h
@@ -1054,6 +1054,12 @@ unsigned int dcn32_get_max_hw_cursor_size(const struct dc *dc,
SRI_ARR(OTG_CRC0_WINDOWA_Y_CONTROL, OTG, inst), \
SRI_ARR(OTG_CRC0_WINDOWB_X_CONTROL, OTG, inst), \
SRI_ARR(OTG_CRC0_WINDOWB_Y_CONTROL, OTG, inst), \
+ SRI_ARR(OTG_CRC1_DATA_RG, OTG, inst), \
+ SRI_ARR(OTG_CRC1_DATA_B, OTG, inst), \
+ SRI_ARR(OTG_CRC1_WINDOWA_X_CONTROL, OTG, inst), \
+ SRI_ARR(OTG_CRC1_WINDOWA_Y_CONTROL, OTG, inst), \
+ SRI_ARR(OTG_CRC1_WINDOWB_X_CONTROL, OTG, inst), \
+ SRI_ARR(OTG_CRC1_WINDOWB_Y_CONTROL, OTG, inst), \
SR_ARR(GSL_SOURCE_SELECT, inst), \
SRI_ARR(OTG_TRIGA_MANUAL_TRIG, OTG, inst), \
SRI_ARR(OTG_GLOBAL_CONTROL1, OTG, inst), \
diff --git a/drivers/gpu/drm/amd/display/dc/resource/dcn401/dcn401_resource.h b/drivers/gpu/drm/amd/display/dc/resource/dcn401/dcn401_resource.h
index 8e3473f86490..3cfc1a39a103 100644
--- a/drivers/gpu/drm/amd/display/dc/resource/dcn401/dcn401_resource.h
+++ b/drivers/gpu/drm/amd/display/dc/resource/dcn401/dcn401_resource.h
@@ -535,6 +535,12 @@ int dcn401_get_power_profile(const struct dc_state *context);
SRI_ARR(OTG_CRC0_WINDOWA_Y_CONTROL, OTG, inst), \
SRI_ARR(OTG_CRC0_WINDOWB_X_CONTROL, OTG, inst), \
SRI_ARR(OTG_CRC0_WINDOWB_Y_CONTROL, OTG, inst), \
+ SRI_ARR(OTG_CRC1_DATA_RG, OTG, inst), \
+ SRI_ARR(OTG_CRC1_DATA_B, OTG, inst), \
+ SRI_ARR(OTG_CRC1_WINDOWA_X_CONTROL, OTG, inst), \
+ SRI_ARR(OTG_CRC1_WINDOWA_Y_CONTROL, OTG, inst), \
+ SRI_ARR(OTG_CRC1_WINDOWB_X_CONTROL, OTG, inst), \
+ SRI_ARR(OTG_CRC1_WINDOWB_Y_CONTROL, OTG, inst), \
SR_ARR(GSL_SOURCE_SELECT, inst), \
SRI_ARR(OTG_TRIGA_MANUAL_TRIG, OTG, inst), \
SRI_ARR(OTG_GLOBAL_CONTROL1, OTG, inst), \
--
2.43.0
^ permalink raw reply related [flat|nested] 3+ messages in thread
* Re: [PATCH] drm/amd/display: add missing CRC engine 1 registers
2026-10-28 9:14 [PATCH] drm/amd/display: add missing CRC engine 1 registers Wayne Lin
@ 2026-10-28 11:16 ` Mikhail Gavrilov
2026-10-28 13:57 ` Chung, ChiaHsuan (Tom)
1 sibling, 0 replies; 3+ messages in thread
From: Mikhail Gavrilov @ 2026-10-28 11:16 UTC (permalink / raw)
To: Wayne Lin; +Cc: amd-gfx, Harry Wentland, Leo Li, Tom Chung
Tested on Navi 31 (DCN3.2) the same way as v2: a kernel built from
mainline 65ba8f34ec88 (7.4 merge window), with and without this patch,
opening crtc-0/crc/data for the first time after boot.
without: two WARNs from dc_helper.c:53 in set_reg_field_values(),
both reached from optc1_configure_crc() under
crtc_crc_open()
with: no WARN, and CRC capture on engine 0 works as before
I also checked the generations I cannot test. I expanded the OPTC
register and mask lists of every DCN3.0 and later resource with the
preprocessor against that ASIC's own offset and sh_mask headers,
before and after the patch. Every register and field the patch adds
is defined for each ASIC and each OTG instance it is used with, no
initializer gains a duplicate entry, and DCN3.5, 3.5.1 and 3.6 end up
with the same entries as before. The patch also applies cleanly to
v7.3.
You are right about DCN2.x: their lists start with
TG_COMMON_REG_LIST_DCN and TG_COMMON_MASK_SH_LIST_DCN, which already
have the engine 1 entries. My note in v2 that they were missing was
wrong.
A nit: checkpatch wants a Closes: or Link: right after Reported-by.
The bug was reported in v2 of my patch, so a Link: to it would do:
Link: https://lore.kernel.org/all/20260829085941.106318-1-mikhail.v.gavrilov@gmail.com/
Reviewed-by: Mikhail Gavrilov <mikhail.v.gavrilov@gmail.com>
Tested-by: Mikhail Gavrilov <mikhail.v.gavrilov@gmail.com> # Navi 31 (DCN3.2)
--
Thanks,
Mikhail
^ permalink raw reply [flat|nested] 3+ messages in thread
* Re: [PATCH] drm/amd/display: add missing CRC engine 1 registers
2026-10-28 9:14 [PATCH] drm/amd/display: add missing CRC engine 1 registers Wayne Lin
2026-10-28 11:16 ` Mikhail Gavrilov
@ 2026-10-28 13:57 ` Chung, ChiaHsuan (Tom)
1 sibling, 0 replies; 3+ messages in thread
From: Chung, ChiaHsuan (Tom) @ 2026-10-28 13:57 UTC (permalink / raw)
To: Wayne Lin, amd-gfx; +Cc: Harry Wentland, Leo Li, Mikhail Gavrilov
Reviewed-by: Tom Chung <chiahsuan.chung@amd.com>
On 10/28/2026 5:14 PM, Wayne Lin wrote:
> [why]
> Opening the CRTC CRC debugfs file programs every CRC engine. On
> several generations the engine 1 window and data entries were missing,
> so configure hits a zero field mask and WARNs. DCN4.2, DCN4.2B, and
> DCN6.0 already had those entries, but configure still writes
> OTG_CRC1_SELECT with no mask check. DCN6.0 also lacks OTG_CRC1_EN, so
> optc1_configure_crc() writes OTG_CRC_EN instead. The ASIC headers
> already define the addresses and fields. The driver tables did not
> list them.
>
> [how]
> How the missing entries are filled in:
>
> 1. DCN3.0 through DCN3.0.3 use OPTC_COMMON_*_DCN3_BASE. Add the six
> engine 1 addresses and the window, data, and OTG_CRC1_SELECT masks.
> These headers have no OTG_CRC1_EN bit, so that field is not added.
>
> 2. DCN3.1 uses OPTC_COMMON_*_DCN3_1. Add the same addresses and masks,
> including OTG_CRC1_EN. dcn_3_1_2 defines that bit. DCN3.1.5
> and DCN3.1.6 expand DCN3_1 through DCN31X. DCN3.1.4 has its own
> list. OTG_CRC1_EN was already on it, so only addresses, SELECT,
> window, and data are added.
>
> 3. DCN3.2 and DCN3.2.1 already had OTG_CRC1_EN and OTG_CRC1_SELECT.
> Add the window and data masks in the OPTC header and the addresses
> in the resource header. DCN3.2 fills addresses at init from
> ctx->dcn_reg_offsets[].
>
> 4. DCN4.0.1 also uses optc1_configure_crc() and was missing SELECT,
> window, and data. Add those masks and the six addresses.
> OTG_CRC1_EN was already present.
>
> 5. DCN3.5, DCN3.5.1, and DCN3.6 already have the addresses and program
> engine 1 through optc35_configure_crc(). Their mask list included
> DCN3.2 and then repeated the CRC1 window and data fields. Drop the
> duplicates.
>
> 6. DCN2.0, DCN2.0.1, and DCN2.1 are left unchanged. They inherit the
> DCN1.0 lists, which already name engine 1 window, data, and
> OTG_CRC1_SELECT. Their headers have no OTG_CRC1_EN bit.
>
> 7. DCN4.2 and DCN4.2B use optc35_configure_crc(). Window, data, and
> OTG_CRC1_EN were already present. Add OTG_CRC1_SELECT. DCN6.0 uses
> optc1_configure_crc(). Window and data were already present. Add
> OTG_CRC1_SELECT and OTG_CRC1_EN.
>
> Fixes: ef45aaf73717 ("drm/amd/display: Configure all CRC engines in pipe CRC source path")
> Cc: Mikhail Gavrilov <mikhail.v.gavrilov@gmail.com>
> Reported-by: Mikhail Gavrilov <mikhail.v.gavrilov@gmail.com>
> Signed-off-by: Wayne Lin <Wayne.Lin@amd.com>
> Assisted-by: Cursor:Grok 4.7
> ---
> .../amd/display/dc/optc/dcn30/dcn30_optc.h | 18 +++++++++++++++
> .../amd/display/dc/optc/dcn31/dcn31_optc.h | 22 +++++++++++++++++--
> .../amd/display/dc/optc/dcn314/dcn314_optc.h | 18 +++++++++++++++
> .../amd/display/dc/optc/dcn32/dcn32_optc.h | 11 ++++++++++
> .../amd/display/dc/optc/dcn35/dcn35_optc.h | 11 ----------
> .../amd/display/dc/optc/dcn401/dcn401_optc.h | 12 ++++++++++
> .../amd/display/dc/optc/dcn42/dcn42_optc.h | 2 ++
> .../amd/display/dc/optc/dcn60/dcn60_optc.h | 2 ++
> .../dc/resource/dcn32/dcn32_resource.h | 6 +++++
> .../dc/resource/dcn401/dcn401_resource.h | 6 +++++
> 10 files changed, 95 insertions(+), 13 deletions(-)
>
> diff --git a/drivers/gpu/drm/amd/display/dc/optc/dcn30/dcn30_optc.h b/drivers/gpu/drm/amd/display/dc/optc/dcn30/dcn30_optc.h
> index 16c5610b49ac..b801989f10cf 100644
> --- a/drivers/gpu/drm/amd/display/dc/optc/dcn30/dcn30_optc.h
> +++ b/drivers/gpu/drm/amd/display/dc/optc/dcn30/dcn30_optc.h
> @@ -91,6 +91,12 @@
> SRI(OTG_CRC0_WINDOWA_Y_CONTROL, OTG, inst),\
> SRI(OTG_CRC0_WINDOWB_X_CONTROL, OTG, inst),\
> SRI(OTG_CRC0_WINDOWB_Y_CONTROL, OTG, inst),\
> + SRI(OTG_CRC1_DATA_RG, OTG, inst),\
> + SRI(OTG_CRC1_DATA_B, OTG, inst),\
> + SRI(OTG_CRC1_WINDOWA_X_CONTROL, OTG, inst),\
> + SRI(OTG_CRC1_WINDOWA_Y_CONTROL, OTG, inst),\
> + SRI(OTG_CRC1_WINDOWB_X_CONTROL, OTG, inst),\
> + SRI(OTG_CRC1_WINDOWB_Y_CONTROL, OTG, inst),\
> SR(GSL_SOURCE_SELECT),\
> SRI(OTG_TRIGA_MANUAL_TRIG, OTG, inst),\
> SRI(OTG_DRR_CONTROL, OTG, inst)
> @@ -229,6 +235,7 @@
> SF(OTG0_OTG_GSL_CONTROL, OTG_GSL_CHECK_ALL_FIELDS, mask_sh),\
> SF(OTG0_OTG_CRC_CNTL, OTG_CRC_CONT_EN, mask_sh),\
> SF(OTG0_OTG_CRC_CNTL, OTG_CRC0_SELECT, mask_sh),\
> + SF(OTG0_OTG_CRC_CNTL, OTG_CRC1_SELECT, mask_sh),\
> SF(OTG0_OTG_CRC_CNTL, OTG_CRC_EN, mask_sh),\
> SF(OTG0_OTG_CRC_CNTL2, OTG_CRC_DSC_MODE, mask_sh),\
> SF(OTG0_OTG_CRC_CNTL2, OTG_CRC_DATA_STREAM_COMBINE_MODE, mask_sh),\
> @@ -245,6 +252,17 @@
> SF(OTG0_OTG_CRC0_WINDOWB_X_CONTROL, OTG_CRC0_WINDOWB_X_END, mask_sh),\
> SF(OTG0_OTG_CRC0_WINDOWB_Y_CONTROL, OTG_CRC0_WINDOWB_Y_START, mask_sh),\
> SF(OTG0_OTG_CRC0_WINDOWB_Y_CONTROL, OTG_CRC0_WINDOWB_Y_END, mask_sh),\
> + SF(OTG0_OTG_CRC1_DATA_RG, CRC1_R_CR, mask_sh),\
> + SF(OTG0_OTG_CRC1_DATA_RG, CRC1_G_Y, mask_sh),\
> + SF(OTG0_OTG_CRC1_DATA_B, CRC1_B_CB, mask_sh),\
> + SF(OTG0_OTG_CRC1_WINDOWA_X_CONTROL, OTG_CRC1_WINDOWA_X_START, mask_sh),\
> + SF(OTG0_OTG_CRC1_WINDOWA_X_CONTROL, OTG_CRC1_WINDOWA_X_END, mask_sh),\
> + SF(OTG0_OTG_CRC1_WINDOWA_Y_CONTROL, OTG_CRC1_WINDOWA_Y_START, mask_sh),\
> + SF(OTG0_OTG_CRC1_WINDOWA_Y_CONTROL, OTG_CRC1_WINDOWA_Y_END, mask_sh),\
> + SF(OTG0_OTG_CRC1_WINDOWB_X_CONTROL, OTG_CRC1_WINDOWB_X_START, mask_sh),\
> + SF(OTG0_OTG_CRC1_WINDOWB_X_CONTROL, OTG_CRC1_WINDOWB_X_END, mask_sh),\
> + SF(OTG0_OTG_CRC1_WINDOWB_Y_CONTROL, OTG_CRC1_WINDOWB_Y_START, mask_sh),\
> + SF(OTG0_OTG_CRC1_WINDOWB_Y_CONTROL, OTG_CRC1_WINDOWB_Y_END, mask_sh),\
> SF(OTG0_OTG_TRIGA_MANUAL_TRIG, OTG_TRIGA_MANUAL_TRIG, mask_sh),\
> SF(GSL_SOURCE_SELECT, GSL0_READY_SOURCE_SEL, mask_sh),\
> SF(GSL_SOURCE_SELECT, GSL1_READY_SOURCE_SEL, mask_sh),\
> diff --git a/drivers/gpu/drm/amd/display/dc/optc/dcn31/dcn31_optc.h b/drivers/gpu/drm/amd/display/dc/optc/dcn31/dcn31_optc.h
> index 19d90c65a22b..c56512455338 100644
> --- a/drivers/gpu/drm/amd/display/dc/optc/dcn31/dcn31_optc.h
> +++ b/drivers/gpu/drm/amd/display/dc/optc/dcn31/dcn31_optc.h
> @@ -83,6 +83,12 @@
> SRI(OTG_CRC0_WINDOWA_Y_CONTROL, OTG, inst),\
> SRI(OTG_CRC0_WINDOWB_X_CONTROL, OTG, inst),\
> SRI(OTG_CRC0_WINDOWB_Y_CONTROL, OTG, inst),\
> + SRI(OTG_CRC1_DATA_RG, OTG, inst),\
> + SRI(OTG_CRC1_DATA_B, OTG, inst),\
> + SRI(OTG_CRC1_WINDOWA_X_CONTROL, OTG, inst),\
> + SRI(OTG_CRC1_WINDOWA_Y_CONTROL, OTG, inst),\
> + SRI(OTG_CRC1_WINDOWB_X_CONTROL, OTG, inst),\
> + SRI(OTG_CRC1_WINDOWB_Y_CONTROL, OTG, inst),\
> SR(GSL_SOURCE_SELECT),\
> SRI(OTG_TRIGA_MANUAL_TRIG, OTG, inst),\
> SRI(OTG_GLOBAL_CONTROL1, OTG, inst),\
> @@ -205,7 +211,9 @@
> SF(OTG0_OTG_GSL_CONTROL, OTG_GSL_CHECK_ALL_FIELDS, mask_sh),\
> SF(OTG0_OTG_CRC_CNTL, OTG_CRC_CONT_EN, mask_sh),\
> SF(OTG0_OTG_CRC_CNTL, OTG_CRC0_SELECT, mask_sh),\
> + SF(OTG0_OTG_CRC_CNTL, OTG_CRC1_SELECT, mask_sh),\
> SF(OTG0_OTG_CRC_CNTL, OTG_CRC_EN, mask_sh),\
> + SF(OTG0_OTG_CRC_CNTL, OTG_CRC1_EN, mask_sh),\
> SF(OTG0_OTG_CRC0_DATA_RG, CRC0_R_CR, mask_sh),\
> SF(OTG0_OTG_CRC0_DATA_RG, CRC0_G_Y, mask_sh),\
> SF(OTG0_OTG_CRC0_DATA_B, CRC0_B_CB, mask_sh),\
> @@ -217,6 +225,17 @@
> SF(OTG0_OTG_CRC0_WINDOWB_X_CONTROL, OTG_CRC0_WINDOWB_X_END, mask_sh),\
> SF(OTG0_OTG_CRC0_WINDOWB_Y_CONTROL, OTG_CRC0_WINDOWB_Y_START, mask_sh),\
> SF(OTG0_OTG_CRC0_WINDOWB_Y_CONTROL, OTG_CRC0_WINDOWB_Y_END, mask_sh),\
> + SF(OTG0_OTG_CRC1_DATA_RG, CRC1_R_CR, mask_sh),\
> + SF(OTG0_OTG_CRC1_DATA_RG, CRC1_G_Y, mask_sh),\
> + SF(OTG0_OTG_CRC1_DATA_B, CRC1_B_CB, mask_sh),\
> + SF(OTG0_OTG_CRC1_WINDOWA_X_CONTROL, OTG_CRC1_WINDOWA_X_START, mask_sh),\
> + SF(OTG0_OTG_CRC1_WINDOWA_X_CONTROL, OTG_CRC1_WINDOWA_X_END, mask_sh),\
> + SF(OTG0_OTG_CRC1_WINDOWA_Y_CONTROL, OTG_CRC1_WINDOWA_Y_START, mask_sh),\
> + SF(OTG0_OTG_CRC1_WINDOWA_Y_CONTROL, OTG_CRC1_WINDOWA_Y_END, mask_sh),\
> + SF(OTG0_OTG_CRC1_WINDOWB_X_CONTROL, OTG_CRC1_WINDOWB_X_START, mask_sh),\
> + SF(OTG0_OTG_CRC1_WINDOWB_X_CONTROL, OTG_CRC1_WINDOWB_X_END, mask_sh),\
> + SF(OTG0_OTG_CRC1_WINDOWB_Y_CONTROL, OTG_CRC1_WINDOWB_Y_START, mask_sh),\
> + SF(OTG0_OTG_CRC1_WINDOWB_Y_CONTROL, OTG_CRC1_WINDOWB_Y_END, mask_sh),\
> SF(OTG0_OTG_TRIGA_MANUAL_TRIG, OTG_TRIGA_MANUAL_TRIG, mask_sh),\
> SF(GSL_SOURCE_SELECT, GSL0_READY_SOURCE_SEL, mask_sh),\
> SF(GSL_SOURCE_SELECT, GSL1_READY_SOURCE_SEL, mask_sh),\
> @@ -264,8 +283,7 @@
> SF(OTG0_INTERRUPT_DEST, OTG0_IHC_OTG_VERTICAL_INTERRUPT2_DEST, mask_sh)
>
> #define OPTC_COMMON_MASK_SH_LIST_DCN31X(mask_sh)\
> - OPTC_COMMON_MASK_SH_LIST_DCN3_1(mask_sh),\
> - SF(OTG0_OTG_CRC_CNTL, OTG_CRC1_EN, mask_sh)
> + OPTC_COMMON_MASK_SH_LIST_DCN3_1(mask_sh)
>
> void dcn31_timing_generator_init(struct optc *optc1);
>
> diff --git a/drivers/gpu/drm/amd/display/dc/optc/dcn314/dcn314_optc.h b/drivers/gpu/drm/amd/display/dc/optc/dcn314/dcn314_optc.h
> index 7b43c3ecd46b..956eecf0a43a 100644
> --- a/drivers/gpu/drm/amd/display/dc/optc/dcn314/dcn314_optc.h
> +++ b/drivers/gpu/drm/amd/display/dc/optc/dcn314/dcn314_optc.h
> @@ -84,6 +84,12 @@
> SRI(OTG_CRC0_WINDOWA_Y_CONTROL, OTG, inst),\
> SRI(OTG_CRC0_WINDOWB_X_CONTROL, OTG, inst),\
> SRI(OTG_CRC0_WINDOWB_Y_CONTROL, OTG, inst),\
> + SRI(OTG_CRC1_DATA_RG, OTG, inst),\
> + SRI(OTG_CRC1_DATA_B, OTG, inst),\
> + SRI(OTG_CRC1_WINDOWA_X_CONTROL, OTG, inst),\
> + SRI(OTG_CRC1_WINDOWA_Y_CONTROL, OTG, inst),\
> + SRI(OTG_CRC1_WINDOWB_X_CONTROL, OTG, inst),\
> + SRI(OTG_CRC1_WINDOWB_Y_CONTROL, OTG, inst),\
> SR(GSL_SOURCE_SELECT),\
> SRI(OTG_TRIGA_MANUAL_TRIG, OTG, inst),\
> SRI(OTG_GLOBAL_CONTROL1, OTG, inst),\
> @@ -204,6 +210,7 @@
> SF(OTG0_OTG_GSL_CONTROL, OTG_GSL_CHECK_ALL_FIELDS, mask_sh),\
> SF(OTG0_OTG_CRC_CNTL, OTG_CRC_CONT_EN, mask_sh),\
> SF(OTG0_OTG_CRC_CNTL, OTG_CRC0_SELECT, mask_sh),\
> + SF(OTG0_OTG_CRC_CNTL, OTG_CRC1_SELECT, mask_sh),\
> SF(OTG0_OTG_CRC_CNTL, OTG_CRC_EN, mask_sh),\
> SF(OTG0_OTG_CRC_CNTL, OTG_CRC1_EN, mask_sh),\
> SF(OTG0_OTG_CRC0_DATA_RG, CRC0_R_CR, mask_sh),\
> @@ -217,6 +224,17 @@
> SF(OTG0_OTG_CRC0_WINDOWB_X_CONTROL, OTG_CRC0_WINDOWB_X_END, mask_sh),\
> SF(OTG0_OTG_CRC0_WINDOWB_Y_CONTROL, OTG_CRC0_WINDOWB_Y_START, mask_sh),\
> SF(OTG0_OTG_CRC0_WINDOWB_Y_CONTROL, OTG_CRC0_WINDOWB_Y_END, mask_sh),\
> + SF(OTG0_OTG_CRC1_DATA_RG, CRC1_R_CR, mask_sh),\
> + SF(OTG0_OTG_CRC1_DATA_RG, CRC1_G_Y, mask_sh),\
> + SF(OTG0_OTG_CRC1_DATA_B, CRC1_B_CB, mask_sh),\
> + SF(OTG0_OTG_CRC1_WINDOWA_X_CONTROL, OTG_CRC1_WINDOWA_X_START, mask_sh),\
> + SF(OTG0_OTG_CRC1_WINDOWA_X_CONTROL, OTG_CRC1_WINDOWA_X_END, mask_sh),\
> + SF(OTG0_OTG_CRC1_WINDOWA_Y_CONTROL, OTG_CRC1_WINDOWA_Y_START, mask_sh),\
> + SF(OTG0_OTG_CRC1_WINDOWA_Y_CONTROL, OTG_CRC1_WINDOWA_Y_END, mask_sh),\
> + SF(OTG0_OTG_CRC1_WINDOWB_X_CONTROL, OTG_CRC1_WINDOWB_X_START, mask_sh),\
> + SF(OTG0_OTG_CRC1_WINDOWB_X_CONTROL, OTG_CRC1_WINDOWB_X_END, mask_sh),\
> + SF(OTG0_OTG_CRC1_WINDOWB_Y_CONTROL, OTG_CRC1_WINDOWB_Y_START, mask_sh),\
> + SF(OTG0_OTG_CRC1_WINDOWB_Y_CONTROL, OTG_CRC1_WINDOWB_Y_END, mask_sh),\
> SF(OTG0_OTG_TRIGA_MANUAL_TRIG, OTG_TRIGA_MANUAL_TRIG, mask_sh),\
> SF(GSL_SOURCE_SELECT, GSL0_READY_SOURCE_SEL, mask_sh),\
> SF(GSL_SOURCE_SELECT, GSL1_READY_SOURCE_SEL, mask_sh),\
> diff --git a/drivers/gpu/drm/amd/display/dc/optc/dcn32/dcn32_optc.h b/drivers/gpu/drm/amd/display/dc/optc/dcn32/dcn32_optc.h
> index 60c01ec28b65..492760779226 100644
> --- a/drivers/gpu/drm/amd/display/dc/optc/dcn32/dcn32_optc.h
> +++ b/drivers/gpu/drm/amd/display/dc/optc/dcn32/dcn32_optc.h
> @@ -146,6 +146,17 @@
> SF(OTG0_OTG_CRC0_WINDOWB_X_CONTROL, OTG_CRC0_WINDOWB_X_END, mask_sh),\
> SF(OTG0_OTG_CRC0_WINDOWB_Y_CONTROL, OTG_CRC0_WINDOWB_Y_START, mask_sh),\
> SF(OTG0_OTG_CRC0_WINDOWB_Y_CONTROL, OTG_CRC0_WINDOWB_Y_END, mask_sh),\
> + SF(OTG0_OTG_CRC1_DATA_RG, CRC1_R_CR, mask_sh),\
> + SF(OTG0_OTG_CRC1_DATA_RG, CRC1_G_Y, mask_sh),\
> + SF(OTG0_OTG_CRC1_DATA_B, CRC1_B_CB, mask_sh),\
> + SF(OTG0_OTG_CRC1_WINDOWA_X_CONTROL, OTG_CRC1_WINDOWA_X_START, mask_sh),\
> + SF(OTG0_OTG_CRC1_WINDOWA_X_CONTROL, OTG_CRC1_WINDOWA_X_END, mask_sh),\
> + SF(OTG0_OTG_CRC1_WINDOWA_Y_CONTROL, OTG_CRC1_WINDOWA_Y_START, mask_sh),\
> + SF(OTG0_OTG_CRC1_WINDOWA_Y_CONTROL, OTG_CRC1_WINDOWA_Y_END, mask_sh),\
> + SF(OTG0_OTG_CRC1_WINDOWB_X_CONTROL, OTG_CRC1_WINDOWB_X_START, mask_sh),\
> + SF(OTG0_OTG_CRC1_WINDOWB_X_CONTROL, OTG_CRC1_WINDOWB_X_END, mask_sh),\
> + SF(OTG0_OTG_CRC1_WINDOWB_Y_CONTROL, OTG_CRC1_WINDOWB_Y_START, mask_sh),\
> + SF(OTG0_OTG_CRC1_WINDOWB_Y_CONTROL, OTG_CRC1_WINDOWB_Y_END, mask_sh),\
> SF(OTG0_OTG_TRIGA_MANUAL_TRIG, OTG_TRIGA_MANUAL_TRIG, mask_sh),\
> SF(GSL_SOURCE_SELECT, GSL0_READY_SOURCE_SEL, mask_sh),\
> SF(GSL_SOURCE_SELECT, GSL1_READY_SOURCE_SEL, mask_sh),\
> diff --git a/drivers/gpu/drm/amd/display/dc/optc/dcn35/dcn35_optc.h b/drivers/gpu/drm/amd/display/dc/optc/dcn35/dcn35_optc.h
> index 82e0818c8f9f..196596cc9fb6 100644
> --- a/drivers/gpu/drm/amd/display/dc/optc/dcn35/dcn35_optc.h
> +++ b/drivers/gpu/drm/amd/display/dc/optc/dcn35/dcn35_optc.h
> @@ -32,23 +32,12 @@
> #define OPTC_COMMON_MASK_SH_LIST_DCN3_5(mask_sh)\
> OPTC_COMMON_MASK_SH_LIST_DCN3_2(mask_sh),\
> SF(OTG0_OTG_CRC_CNTL, OTG_CRC_WINDOW_DB_EN, mask_sh),\
> - SF(OTG0_OTG_CRC1_DATA_RG, CRC1_R_CR, mask_sh),\
> - SF(OTG0_OTG_CRC1_DATA_RG, CRC1_G_Y, mask_sh),\
> - SF(OTG0_OTG_CRC1_DATA_B, CRC1_B_CB, mask_sh),\
> SF(OTG0_OTG_CRC2_DATA_RG, CRC2_R_CR, mask_sh),\
> SF(OTG0_OTG_CRC2_DATA_RG, CRC2_G_Y, mask_sh),\
> SF(OTG0_OTG_CRC2_DATA_B, CRC2_B_CB, mask_sh),\
> SF(OTG0_OTG_CRC3_DATA_RG, CRC3_R_CR, mask_sh),\
> SF(OTG0_OTG_CRC3_DATA_RG, CRC3_G_Y, mask_sh),\
> SF(OTG0_OTG_CRC3_DATA_B, CRC3_B_CB, mask_sh),\
> - SF(OTG0_OTG_CRC1_WINDOWA_X_CONTROL, OTG_CRC1_WINDOWA_X_START, mask_sh),\
> - SF(OTG0_OTG_CRC1_WINDOWA_X_CONTROL, OTG_CRC1_WINDOWA_X_END, mask_sh),\
> - SF(OTG0_OTG_CRC1_WINDOWA_Y_CONTROL, OTG_CRC1_WINDOWA_Y_START, mask_sh),\
> - SF(OTG0_OTG_CRC1_WINDOWA_Y_CONTROL, OTG_CRC1_WINDOWA_Y_END, mask_sh),\
> - SF(OTG0_OTG_CRC1_WINDOWB_X_CONTROL, OTG_CRC1_WINDOWB_X_START, mask_sh),\
> - SF(OTG0_OTG_CRC1_WINDOWB_X_CONTROL, OTG_CRC1_WINDOWB_X_END, mask_sh),\
> - SF(OTG0_OTG_CRC1_WINDOWB_Y_CONTROL, OTG_CRC1_WINDOWB_Y_START, mask_sh),\
> - SF(OTG0_OTG_CRC1_WINDOWB_Y_CONTROL, OTG_CRC1_WINDOWB_Y_END, mask_sh),\
> SF(OTG0_OTG_CRC0_WINDOWA_X_CONTROL_READBACK, OTG_CRC0_WINDOWA_X_START_READBACK, mask_sh),\
> SF(OTG0_OTG_CRC0_WINDOWA_X_CONTROL_READBACK, OTG_CRC0_WINDOWA_X_END_READBACK, mask_sh),\
> SF(OTG0_OTG_CRC0_WINDOWA_Y_CONTROL_READBACK, OTG_CRC0_WINDOWA_Y_START_READBACK, mask_sh),\
> diff --git a/drivers/gpu/drm/amd/display/dc/optc/dcn401/dcn401_optc.h b/drivers/gpu/drm/amd/display/dc/optc/dcn401/dcn401_optc.h
> index 3add972ca2ff..9e4e9d75400a 100644
> --- a/drivers/gpu/drm/amd/display/dc/optc/dcn401/dcn401_optc.h
> +++ b/drivers/gpu/drm/amd/display/dc/optc/dcn401/dcn401_optc.h
> @@ -110,6 +110,7 @@
> SF(OTG0_OTG_GSL_CONTROL, OTG_GSL_CHECK_ALL_FIELDS, mask_sh),\
> SF(OTG0_OTG_CRC_CNTL, OTG_CRC_CONT_EN, mask_sh),\
> SF(OTG0_OTG_CRC_CNTL, OTG_CRC0_SELECT, mask_sh),\
> + SF(OTG0_OTG_CRC_CNTL, OTG_CRC1_SELECT, mask_sh),\
> SF(OTG0_OTG_CRC_CNTL, OTG_CRC_EN, mask_sh),\
> SF(OTG0_OTG_CRC_CNTL, OTG_CRC1_EN, mask_sh),\
> SF(OTG0_OTG_CRC0_DATA_RG, CRC0_R_CR, mask_sh),\
> @@ -123,6 +124,17 @@
> SF(OTG0_OTG_CRC0_WINDOWB_X_CONTROL, OTG_CRC0_WINDOWB_X_END, mask_sh),\
> SF(OTG0_OTG_CRC0_WINDOWB_Y_CONTROL, OTG_CRC0_WINDOWB_Y_START, mask_sh),\
> SF(OTG0_OTG_CRC0_WINDOWB_Y_CONTROL, OTG_CRC0_WINDOWB_Y_END, mask_sh),\
> + SF(OTG0_OTG_CRC1_DATA_RG, CRC1_R_CR, mask_sh),\
> + SF(OTG0_OTG_CRC1_DATA_RG, CRC1_G_Y, mask_sh),\
> + SF(OTG0_OTG_CRC1_DATA_B, CRC1_B_CB, mask_sh),\
> + SF(OTG0_OTG_CRC1_WINDOWA_X_CONTROL, OTG_CRC1_WINDOWA_X_START, mask_sh),\
> + SF(OTG0_OTG_CRC1_WINDOWA_X_CONTROL, OTG_CRC1_WINDOWA_X_END, mask_sh),\
> + SF(OTG0_OTG_CRC1_WINDOWA_Y_CONTROL, OTG_CRC1_WINDOWA_Y_START, mask_sh),\
> + SF(OTG0_OTG_CRC1_WINDOWA_Y_CONTROL, OTG_CRC1_WINDOWA_Y_END, mask_sh),\
> + SF(OTG0_OTG_CRC1_WINDOWB_X_CONTROL, OTG_CRC1_WINDOWB_X_START, mask_sh),\
> + SF(OTG0_OTG_CRC1_WINDOWB_X_CONTROL, OTG_CRC1_WINDOWB_X_END, mask_sh),\
> + SF(OTG0_OTG_CRC1_WINDOWB_Y_CONTROL, OTG_CRC1_WINDOWB_Y_START, mask_sh),\
> + SF(OTG0_OTG_CRC1_WINDOWB_Y_CONTROL, OTG_CRC1_WINDOWB_Y_END, mask_sh),\
> SF(OTG0_OTG_TRIGA_MANUAL_TRIG, OTG_TRIGA_MANUAL_TRIG, mask_sh),\
> SF(GSL_SOURCE_SELECT, GSL0_READY_SOURCE_SEL, mask_sh),\
> SF(GSL_SOURCE_SELECT, GSL1_READY_SOURCE_SEL, mask_sh),\
> diff --git a/drivers/gpu/drm/amd/display/dc/optc/dcn42/dcn42_optc.h b/drivers/gpu/drm/amd/display/dc/optc/dcn42/dcn42_optc.h
> index bc641f6ecd7e..bdda94489a23 100644
> --- a/drivers/gpu/drm/amd/display/dc/optc/dcn42/dcn42_optc.h
> +++ b/drivers/gpu/drm/amd/display/dc/optc/dcn42/dcn42_optc.h
> @@ -137,6 +137,7 @@
> SF(OTG0_OTG_GSL_CONTROL, OTG_GSL_CHECK_ALL_FIELDS, mask_sh),\
> SF(OTG0_OTG_CRC_CNTL, OTG_CRC_CONT_EN, mask_sh),\
> SF(OTG0_OTG_CRC_CNTL, OTG_CRC0_SELECT, mask_sh),\
> + SF(OTG0_OTG_CRC_CNTL, OTG_CRC1_SELECT, mask_sh),\
> SF(OTG0_OTG_CRC_CNTL, OTG_CRC_EN, mask_sh),\
> SF(OTG0_OTG_CRC_CNTL, OTG_CRC1_EN, mask_sh),\
> SF(OTG0_OTG_CRC0_DATA_R, CRC0_R_CR, mask_sh),\
> @@ -316,6 +317,7 @@
> SF(OTG0_OTG_GSL_CONTROL, OTG_GSL_CHECK_ALL_FIELDS, mask_sh),\
> SF(OTG0_OTG_CRC_CNTL, OTG_CRC_CONT_EN, mask_sh),\
> SF(OTG0_OTG_CRC_CNTL, OTG_CRC0_SELECT, mask_sh),\
> + SF(OTG0_OTG_CRC_CNTL, OTG_CRC1_SELECT, mask_sh),\
> SF(OTG0_OTG_CRC_CNTL, OTG_CRC_EN, mask_sh),\
> SF(OTG0_OTG_CRC_CNTL, OTG_CRC1_EN, mask_sh),\
> SF(OTG0_OTG_CRC0_DATA_R, CRC0_R_CR, mask_sh),\
> diff --git a/drivers/gpu/drm/amd/display/dc/optc/dcn60/dcn60_optc.h b/drivers/gpu/drm/amd/display/dc/optc/dcn60/dcn60_optc.h
> index ba207c0e498e..ec40c9180030 100644
> --- a/drivers/gpu/drm/amd/display/dc/optc/dcn60/dcn60_optc.h
> +++ b/drivers/gpu/drm/amd/display/dc/optc/dcn60/dcn60_optc.h
> @@ -109,7 +109,9 @@
> SF(OTG0_OTG_GSL_CONTROL, OTG_GSL_FORCE_DELAY, mask_sh),\
> SF(OTG0_OTG_CRC_CNTL, OTG_CRC_CONT_EN, mask_sh),\
> SF(OTG0_OTG_CRC_CNTL, OTG_CRC0_SELECT, mask_sh),\
> + SF(OTG0_OTG_CRC_CNTL, OTG_CRC1_SELECT, mask_sh),\
> SF(OTG0_OTG_CRC_CNTL, OTG_CRC_EN, mask_sh),\
> + SF(OTG0_OTG_CRC_CNTL, OTG_CRC1_EN, mask_sh),\
> SF(OTG0_OTG_CRC0_DATA_R, CRC0_R_CR, mask_sh),\
> SF(OTG0_OTG_CRC0_DATA_G, CRC0_G_Y, mask_sh),\
> SF(OTG0_OTG_CRC0_DATA_B, CRC0_B_CB, mask_sh),\
> diff --git a/drivers/gpu/drm/amd/display/dc/resource/dcn32/dcn32_resource.h b/drivers/gpu/drm/amd/display/dc/resource/dcn32/dcn32_resource.h
> index 68e7140f1505..fa8cc89cb3f7 100644
> --- a/drivers/gpu/drm/amd/display/dc/resource/dcn32/dcn32_resource.h
> +++ b/drivers/gpu/drm/amd/display/dc/resource/dcn32/dcn32_resource.h
> @@ -1054,6 +1054,12 @@ unsigned int dcn32_get_max_hw_cursor_size(const struct dc *dc,
> SRI_ARR(OTG_CRC0_WINDOWA_Y_CONTROL, OTG, inst), \
> SRI_ARR(OTG_CRC0_WINDOWB_X_CONTROL, OTG, inst), \
> SRI_ARR(OTG_CRC0_WINDOWB_Y_CONTROL, OTG, inst), \
> + SRI_ARR(OTG_CRC1_DATA_RG, OTG, inst), \
> + SRI_ARR(OTG_CRC1_DATA_B, OTG, inst), \
> + SRI_ARR(OTG_CRC1_WINDOWA_X_CONTROL, OTG, inst), \
> + SRI_ARR(OTG_CRC1_WINDOWA_Y_CONTROL, OTG, inst), \
> + SRI_ARR(OTG_CRC1_WINDOWB_X_CONTROL, OTG, inst), \
> + SRI_ARR(OTG_CRC1_WINDOWB_Y_CONTROL, OTG, inst), \
> SR_ARR(GSL_SOURCE_SELECT, inst), \
> SRI_ARR(OTG_TRIGA_MANUAL_TRIG, OTG, inst), \
> SRI_ARR(OTG_GLOBAL_CONTROL1, OTG, inst), \
> diff --git a/drivers/gpu/drm/amd/display/dc/resource/dcn401/dcn401_resource.h b/drivers/gpu/drm/amd/display/dc/resource/dcn401/dcn401_resource.h
> index 8e3473f86490..3cfc1a39a103 100644
> --- a/drivers/gpu/drm/amd/display/dc/resource/dcn401/dcn401_resource.h
> +++ b/drivers/gpu/drm/amd/display/dc/resource/dcn401/dcn401_resource.h
> @@ -535,6 +535,12 @@ int dcn401_get_power_profile(const struct dc_state *context);
> SRI_ARR(OTG_CRC0_WINDOWA_Y_CONTROL, OTG, inst), \
> SRI_ARR(OTG_CRC0_WINDOWB_X_CONTROL, OTG, inst), \
> SRI_ARR(OTG_CRC0_WINDOWB_Y_CONTROL, OTG, inst), \
> + SRI_ARR(OTG_CRC1_DATA_RG, OTG, inst), \
> + SRI_ARR(OTG_CRC1_DATA_B, OTG, inst), \
> + SRI_ARR(OTG_CRC1_WINDOWA_X_CONTROL, OTG, inst), \
> + SRI_ARR(OTG_CRC1_WINDOWA_Y_CONTROL, OTG, inst), \
> + SRI_ARR(OTG_CRC1_WINDOWB_X_CONTROL, OTG, inst), \
> + SRI_ARR(OTG_CRC1_WINDOWB_Y_CONTROL, OTG, inst), \
> SR_ARR(GSL_SOURCE_SELECT, inst), \
> SRI_ARR(OTG_TRIGA_MANUAL_TRIG, OTG, inst), \
> SRI_ARR(OTG_GLOBAL_CONTROL1, OTG, inst), \
^ permalink raw reply [flat|nested] 3+ messages in thread
end of thread, other threads:[~2026-10-28 13:58 UTC | newest]
Thread overview: 3+ messages (download: mbox.gz follow: Atom feed
-- links below jump to the message on this page --
2026-10-28 9:14 [PATCH] drm/amd/display: add missing CRC engine 1 registers Wayne Lin
2026-10-28 11:16 ` Mikhail Gavrilov
2026-10-28 13:57 ` Chung, ChiaHsuan (Tom)
This is an external index of several public inboxes,
see mirroring instructions on how to clone and mirror
all data and code used by this external index.