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From: Rishab Pradeep via qemu development <qemu-devel@nongnu.org>
To: qemu-devel@nongnu.org
Cc: qemu-riscv@nongnu.org, Palmer Dabbelt <palmer@dabbelt.com>,
	Alistair Francis <alistair.francis@wdc.com>,
	Weiwei Li <liwei1518@gmail.com>,
	Daniel Henrique Barboza <daniel.barboza@oss.qualcomm.com>,
	Liu Zhiwei <zhiwei_liu@linux.alibaba.com>,
	Chao Liu <chao.liu@processmission.com>,
	Tarun Patanjali <tarun.patanjali@utexas.edu>,
	Chris Elwood <christopher.elwood2024@gmail.com>,
	Rishab Pradeep <rishab@rispop.dev>
Subject: [PATCH 1/2] target/riscv: Factor out pointer-masking address adjustment
Date: Thu, 29 Oct 2026 13:37:50 -0500	[thread overview]
Message-ID: <20261029183751.11143-2-rishab@rispop.dev> (raw)
In-Reply-To: <20261029183751.11143-1-rishab@rispop.dev>

Move the addr_xl/addr_signed extract, which applies address-width
truncation and the pointer-masking ignore transformation, out of
get_address() and get_address_indexed() into a new helper,
gen_pm_adjust_addr(), so it can be applied to addresses that are not
formed from a GPR. No functional change.

Co-developed-by: Tarun Patanjali <tarun.patanjali@utexas.edu>
Signed-off-by: Tarun Patanjali <tarun.patanjali@utexas.edu>
Co-developed-by: Chris Elwood <christopher.elwood2024@gmail.com>
Signed-off-by: Chris Elwood <christopher.elwood2024@gmail.com>
Signed-off-by: Rishab Pradeep <rishab@rispop.dev>
---
 target/riscv/tcg/translate.c | 21 +++++++++++----------
 1 file changed, 11 insertions(+), 10 deletions(-)

diff --git a/target/riscv/tcg/translate.c b/target/riscv/tcg/translate.c
index 79b0f444ef..72d36764d8 100644
--- a/target/riscv/tcg/translate.c
+++ b/target/riscv/tcg/translate.c
@@ -654,6 +654,15 @@ static void gen_jal(DisasContext *ctx, int rd, target_ulong imm)
     ctx->base.is_jmp = DISAS_NORETURN;
 }
 
+static void gen_pm_adjust_addr(DisasContext *ctx, TCGv dest, TCGv src)
+{
+    if (ctx->addr_signed) {
+        tcg_gen_sextract_tl(dest, src, 0, ctx->addr_xl);
+    } else {
+        tcg_gen_extract_tl(dest, src, 0, ctx->addr_xl);
+    }
+}
+
 /* Compute a canonical address from a register plus offset. */
 static TCGv get_address(DisasContext *ctx, int rs1, int imm)
 {
@@ -661,11 +670,7 @@ static TCGv get_address(DisasContext *ctx, int rs1, int imm)
     TCGv src1 = get_gpr(ctx, rs1, EXT_NONE);
 
     tcg_gen_addi_tl(addr, src1, imm);
-    if (ctx->addr_signed) {
-        tcg_gen_sextract_tl(addr, addr, 0, ctx->addr_xl);
-    } else {
-        tcg_gen_extract_tl(addr, addr, 0, ctx->addr_xl);
-    }
+    gen_pm_adjust_addr(ctx, addr, addr);
 
     return addr;
 }
@@ -677,11 +682,7 @@ static TCGv get_address_indexed(DisasContext *ctx, int rs1, TCGv offs)
     TCGv src1 = get_gpr(ctx, rs1, EXT_NONE);
 
     tcg_gen_add_tl(addr, src1, offs);
-    if (ctx->addr_signed) {
-        tcg_gen_sextract_tl(addr, addr, 0, ctx->addr_xl);
-    } else {
-        tcg_gen_extract_tl(addr, addr, 0, ctx->addr_xl);
-    }
+    gen_pm_adjust_addr(ctx, addr, addr);
 
     return addr;
 }
-- 
2.54.0 (Apple Git-157)



WARNING: multiple messages have this Message-ID (diff)
From: Rishab Pradeep via <qemu-riscv@nongnu.org>
To: qemu-devel@nongnu.org
Cc: qemu-riscv@nongnu.org, Palmer Dabbelt <palmer@dabbelt.com>,
	Alistair Francis <alistair.francis@wdc.com>,
	Weiwei Li <liwei1518@gmail.com>,
	Daniel Henrique Barboza <daniel.barboza@oss.qualcomm.com>,
	Liu Zhiwei <zhiwei_liu@linux.alibaba.com>,
	Chao Liu <chao.liu@processmission.com>,
	Tarun Patanjali <tarun.patanjali@utexas.edu>,
	Chris Elwood <christopher.elwood2024@gmail.com>,
	Rishab Pradeep <rishab@rispop.dev>
Subject: [PATCH 1/2] target/riscv: Factor out pointer-masking address adjustment
Date: Thu, 29 Oct 2026 13:37:50 -0500	[thread overview]
Message-ID: <20261029183751.11143-2-rishab@rispop.dev> (raw)
In-Reply-To: <20261029183751.11143-1-rishab@rispop.dev>

Move the addr_xl/addr_signed extract, which applies address-width
truncation and the pointer-masking ignore transformation, out of
get_address() and get_address_indexed() into a new helper,
gen_pm_adjust_addr(), so it can be applied to addresses that are not
formed from a GPR. No functional change.

Co-developed-by: Tarun Patanjali <tarun.patanjali@utexas.edu>
Signed-off-by: Tarun Patanjali <tarun.patanjali@utexas.edu>
Co-developed-by: Chris Elwood <christopher.elwood2024@gmail.com>
Signed-off-by: Chris Elwood <christopher.elwood2024@gmail.com>
Signed-off-by: Rishab Pradeep <rishab@rispop.dev>
---
 target/riscv/tcg/translate.c | 21 +++++++++++----------
 1 file changed, 11 insertions(+), 10 deletions(-)

diff --git a/target/riscv/tcg/translate.c b/target/riscv/tcg/translate.c
index 79b0f444ef..72d36764d8 100644
--- a/target/riscv/tcg/translate.c
+++ b/target/riscv/tcg/translate.c
@@ -654,6 +654,15 @@ static void gen_jal(DisasContext *ctx, int rd, target_ulong imm)
     ctx->base.is_jmp = DISAS_NORETURN;
 }
 
+static void gen_pm_adjust_addr(DisasContext *ctx, TCGv dest, TCGv src)
+{
+    if (ctx->addr_signed) {
+        tcg_gen_sextract_tl(dest, src, 0, ctx->addr_xl);
+    } else {
+        tcg_gen_extract_tl(dest, src, 0, ctx->addr_xl);
+    }
+}
+
 /* Compute a canonical address from a register plus offset. */
 static TCGv get_address(DisasContext *ctx, int rs1, int imm)
 {
@@ -661,11 +670,7 @@ static TCGv get_address(DisasContext *ctx, int rs1, int imm)
     TCGv src1 = get_gpr(ctx, rs1, EXT_NONE);
 
     tcg_gen_addi_tl(addr, src1, imm);
-    if (ctx->addr_signed) {
-        tcg_gen_sextract_tl(addr, addr, 0, ctx->addr_xl);
-    } else {
-        tcg_gen_extract_tl(addr, addr, 0, ctx->addr_xl);
-    }
+    gen_pm_adjust_addr(ctx, addr, addr);
 
     return addr;
 }
@@ -677,11 +682,7 @@ static TCGv get_address_indexed(DisasContext *ctx, int rs1, TCGv offs)
     TCGv src1 = get_gpr(ctx, rs1, EXT_NONE);
 
     tcg_gen_add_tl(addr, src1, offs);
-    if (ctx->addr_signed) {
-        tcg_gen_sextract_tl(addr, addr, 0, ctx->addr_xl);
-    } else {
-        tcg_gen_extract_tl(addr, addr, 0, ctx->addr_xl);
-    }
+    gen_pm_adjust_addr(ctx, addr, addr);
 
     return addr;
 }
-- 
2.54.0 (Apple Git-157)



  reply	other threads:[~2026-10-29 19:47 UTC|newest]

Thread overview: 6+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2026-10-29 18:37 [PATCH 0/2] target/riscv: Apply pointer masking to SSPUSH/SSPOPCHK Rishab Pradeep via qemu development
2026-10-29 18:37 ` Rishab Pradeep via
2026-10-29 18:37 ` Rishab Pradeep via qemu development [this message]
2026-10-29 18:37   ` [PATCH 1/2] target/riscv: Factor out pointer-masking address adjustment Rishab Pradeep via
2026-10-29 18:37 ` [PATCH 2/2] target/riscv: Apply pointer masking to SSPUSH/SSPOPCHK addresses Rishab Pradeep via qemu development
2026-10-29 18:37   ` Rishab Pradeep via

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