[PATCH 2/6] drm/xe/bb: drop per-batch prefetch padding

[Matthew Auld <matthew.auld@intel.com>]

xe_bb_new() currently appends bb_prefetch() (512B or 1K) to every
batch suballocation, inflating a 36B identity-mapped clear batch to
~1K and also causing xe_sa_bo_flush_write() to copy up to 1K of unused
padding to VRAM on every batch.

However, both kernel_bb_pool and usm.bb_pool are initialised via
xe_sa_bo_manager_init(), which already reserves a 4K guard region at
the end of the backing BO to cover CS prefetch, and prefetching into
adjacent suballocations within the mapped pool should be harmless. Drop
bb_prefetch().

This should reduce pressure on the bb pool.

Assisted-by: LLM
Link: https://gitlab.freedesktop.org/drm/xe/kernel/-/work_items/9644
Signed-off-by: Matthew Auld <matthew.auld@intel.com>
Cc: Thomas Hellström <thomas.hellstrom@linux.intel.com>
Cc: Matthew Brost <matthew.brost@intel.com>
---
 drivers/gpu/drm/xe/xe_bb.c | 26 ++++++--------------------
 1 file changed, 6 insertions(+), 20 deletions(-)

diff --git a/drivers/gpu/drm/xe/xe_bb.c b/drivers/gpu/drm/xe/xe_bb.c
index b896b6f6615c..b2603902c147 100644
--- a/drivers/gpu/drm/xe/xe_bb.c
+++ b/drivers/gpu/drm/xe/xe_bb.c
@@ -14,20 +14,6 @@
 #include "xe_sched_job.h"
 #include "xe_vm_types.h"
 
-static int bb_prefetch(struct xe_gt *gt)
-{
-	struct xe_device *xe = gt_to_xe(gt);
-
-	if (GRAPHICS_VERx100(xe) >= 1250 && xe_gt_is_main_type(gt))
-		/*
-		 * RCS and CCS require 1K, although other engines would be
-		 * okay with 512.
-		 */
-		return SZ_1K;
-	else
-		return SZ_512;
-}
-
 struct xe_bb *xe_bb_new(struct xe_gt *gt, u32 dwords, bool usm)
 {
 	struct xe_tile *tile = gt_to_tile(gt);
@@ -38,13 +24,13 @@ struct xe_bb *xe_bb_new(struct xe_gt *gt, u32 dwords, bool usm)
 		return ERR_PTR(-ENOMEM);
 
 	/*
-	 * We need to allocate space for the requested number of dwords,
-	 * one additional MI_BATCH_BUFFER_END dword, and additional buffer
-	 * space to accommodate the platform-specific hardware prefetch
-	 * requirements.
+	 * We need to allocate space for the requested number of dwords and
+	 * one additional MI_BATCH_BUFFER_END dword. Hardware CS prefetch
+	 * at the end of the pool BO is covered by the SZ_4K guard region
+	 * reserved by xe_sa_bo_manager_init().
 	 */
 	bb->bo = xe_sa_bo_new(!usm ? tile->mem.kernel_bb_pool : gt->usm.bb_pool,
-			      4 * (dwords + 1) + bb_prefetch(gt));
+			      4 * (dwords + 1));
 	if (IS_ERR(bb->bo)) {
 		err = PTR_ERR(bb->bo);
 		goto err;
@@ -129,7 +115,7 @@ __xe_bb_create_job(struct xe_exec_queue *q, struct xe_bb *bb, u64 *addr)
 	if (bb->len == 0 || bb->cs[bb->len - 1] != MI_BATCH_BUFFER_END)
 		bb->cs[bb->len++] = MI_BATCH_BUFFER_END;
 
-	xe_gt_assert(q->gt, bb->len * 4 + bb_prefetch(q->gt) <= size);
+	xe_gt_assert(q->gt, bb->len * 4 <= size);
 
 	xe_sa_bo_flush_write(bb->bo);
 

-- 
2.56.0