[PATCH] clk: renesas: r9a08g046: Propagate clk rate for ETH TX mux clocks

[PATCH] clk: renesas: r9a08g046: Propagate clk rate for ETH TX mux clocks

[Biju Das]

Add CLK_SET_RATE_PARENT flag to the sel_eth0_tx and sel_eth1_tx mux
clocks so that rate-setting requests on these clocks propagate up to
their parent clocks. Without this flag, a clk_set_rate() call on the
downstream GBETH clocks has no effect on the actual PLL/divider
chain feeding the TX clock, leaving the requested rate unapplied.

Fixes: d55a0dfec40b ("clk: renesas: r9a08g046: Add GBETH clocks and resets")
Signed-off-by: Biju Das <biju.das.jz@bp.renesas.com>
---
 drivers/clk/renesas/r9a08g046-cpg.c | 6 ++++--
 1 file changed, 4 insertions(+), 2 deletions(-)

diff --git a/drivers/clk/renesas/r9a08g046-cpg.c b/drivers/clk/renesas/r9a08g046-cpg.c
index 2c5ca5ab5f57..92c76c4a1e89 100644
--- a/drivers/clk/renesas/r9a08g046-cpg.c
+++ b/drivers/clk/renesas/r9a08g046-cpg.c
@@ -307,10 +307,12 @@ static const struct cpg_core_clk r9a08g046_core_clks[] __initconst = {
 	DEF_MUX(".sel_rspi0", CLK_SEL_RSPI0, G3L_SEL_RSPI0, sel_rsci_rspi),
 	DEF_MUX(".sel_rspi1", CLK_SEL_RSPI1, G3L_SEL_RSPI1, sel_rsci_rspi),
 	DEF_MUX(".sel_rspi2", CLK_SEL_RSPI2, G3L_SEL_RSPI2, sel_rsci_rspi),
-	DEF_MUX(".sel_eth0_tx", CLK_SEL_ETH0_TX, G3L_SEL_ETH0_TX, sel_eth0_tx),
+	DEF_MUX_FLAGS(".sel_eth0_tx", CLK_SEL_ETH0_TX, G3L_SEL_ETH0_TX, sel_eth0_tx,
+		      CLK_SET_RATE_PARENT),
 	DEF_MUX(".sel_eth0_rx", CLK_SEL_ETH0_RX, G3L_SEL_ETH0_RX, sel_eth0_rx),
 	DEF_MUX(".sel_eth0_rm", CLK_SEL_ETH0_RM, G3L_SEL_ETH0_RM, sel_eth0_rm),
-	DEF_MUX(".sel_eth1_tx", CLK_SEL_ETH1_TX, G3L_SEL_ETH1_TX, sel_eth1_tx),
+	DEF_MUX_FLAGS(".sel_eth1_tx", CLK_SEL_ETH1_TX, G3L_SEL_ETH1_TX, sel_eth1_tx,
+		      CLK_SET_RATE_PARENT),
 	DEF_MUX(".sel_eth1_rx", CLK_SEL_ETH1_RX, G3L_SEL_ETH1_RX, sel_eth1_rx),
 	DEF_MUX(".sel_eth1_rm", CLK_SEL_ETH1_RM, G3L_SEL_ETH1_RM, sel_eth1_rm),
 	DEF_DIV(".div_eth0_tr", CLK_ETH0_TR, CLK_PLL6, G3L_SDIV_ETH_A, dtable_4_200),
-- 
2.43.0

Re: [PATCH] clk: renesas: r9a08g046: Propagate clk rate for ETH TX mux clocks

[Geert Uytterhoeven]

On Mon, 14 Sept 2026 at 18:51, Biju Das <biju.das.jz@bp.renesas.com> wrote:
> Add CLK_SET_RATE_PARENT flag to the sel_eth0_tx and sel_eth1_tx mux
> clocks so that rate-setting requests on these clocks propagate up to
> their parent clocks. Without this flag, a clk_set_rate() call on the
> downstream GBETH clocks has no effect on the actual PLL/divider
> chain feeding the TX clock, leaving the requested rate unapplied.
>
> Fixes: d55a0dfec40b ("clk: renesas: r9a08g046: Add GBETH clocks and resets")
> Signed-off-by: Biju Das <biju.das.jz@bp.renesas.com>

Reviewed-by: Geert Uytterhoeven <geert+renesas@glider.be>
i.e. will queue in renesas-clk for v7.4.

Gr{oetje,eeting}s,

                        Geert

-- 
Geert Uytterhoeven -- There's lots of Linux beyond ia32 -- geert@linux-m68k.org

In personal conversations with technical people, I call myself a hacker. But
when I'm talking to journalists I just say "programmer" or something like that.
                                -- Linus Torvalds

RE: [PATCH] clk: renesas: r9a08g046: Propagate clk rate for ETH TX mux clocks

[Biju Das]

Hi Greg/Sasha,

Sorry, I missed adding Cc: <stable@vger.kernel.org> for the below Fixes commit

Commit e018c27e6052 "clk: renesas: r9a08g046: Propagate clk rate for ETH TX mux clocks"
in Linux-next.

So, can it be backported to 7.3 and stable kernels?

Cheers,
Biju

> -----Original Message-----
> From: Biju Das <biju.das.jz@bp.renesas.com>
> Sent: 14 September 2026 17:50
> Subject: [PATCH] clk: renesas: r9a08g046: Propagate clk rate for ETH TX mux clocks
> 
> Add CLK_SET_RATE_PARENT flag to the sel_eth0_tx and sel_eth1_tx mux clocks so that rate-setting requests
> on these clocks propagate up to their parent clocks. Without this flag, a clk_set_rate() call on the
> downstream GBETH clocks has no effect on the actual PLL/divider chain feeding the TX clock, leaving the
> requested rate unapplied.
> 
> Fixes: d55a0dfec40b ("clk: renesas: r9a08g046: Add GBETH clocks and resets")
> Signed-off-by: Biju Das <biju.das.jz@bp.renesas.com>
> ---
>  drivers/clk/renesas/r9a08g046-cpg.c | 6 ++++--
>  1 file changed, 4 insertions(+), 2 deletions(-)
> 
> diff --git a/drivers/clk/renesas/r9a08g046-cpg.c b/drivers/clk/renesas/r9a08g046-cpg.c
> index 2c5ca5ab5f57..92c76c4a1e89 100644
> --- a/drivers/clk/renesas/r9a08g046-cpg.c
> +++ b/drivers/clk/renesas/r9a08g046-cpg.c
> @@ -307,10 +307,12 @@ static const struct cpg_core_clk r9a08g046_core_clks[] __initconst = {
>  	DEF_MUX(".sel_rspi0", CLK_SEL_RSPI0, G3L_SEL_RSPI0, sel_rsci_rspi),
>  	DEF_MUX(".sel_rspi1", CLK_SEL_RSPI1, G3L_SEL_RSPI1, sel_rsci_rspi),
>  	DEF_MUX(".sel_rspi2", CLK_SEL_RSPI2, G3L_SEL_RSPI2, sel_rsci_rspi),
> -	DEF_MUX(".sel_eth0_tx", CLK_SEL_ETH0_TX, G3L_SEL_ETH0_TX, sel_eth0_tx),
> +	DEF_MUX_FLAGS(".sel_eth0_tx", CLK_SEL_ETH0_TX, G3L_SEL_ETH0_TX, sel_eth0_tx,
> +		      CLK_SET_RATE_PARENT),
>  	DEF_MUX(".sel_eth0_rx", CLK_SEL_ETH0_RX, G3L_SEL_ETH0_RX, sel_eth0_rx),
>  	DEF_MUX(".sel_eth0_rm", CLK_SEL_ETH0_RM, G3L_SEL_ETH0_RM, sel_eth0_rm),
> -	DEF_MUX(".sel_eth1_tx", CLK_SEL_ETH1_TX, G3L_SEL_ETH1_TX, sel_eth1_tx),
> +	DEF_MUX_FLAGS(".sel_eth1_tx", CLK_SEL_ETH1_TX, G3L_SEL_ETH1_TX, sel_eth1_tx,
> +		      CLK_SET_RATE_PARENT),
>  	DEF_MUX(".sel_eth1_rx", CLK_SEL_ETH1_RX, G3L_SEL_ETH1_RX, sel_eth1_rx),
>  	DEF_MUX(".sel_eth1_rm", CLK_SEL_ETH1_RM, G3L_SEL_ETH1_RM, sel_eth1_rm),
>  	DEF_DIV(".div_eth0_tr", CLK_ETH0_TR, CLK_PLL6, G3L_SDIV_ETH_A, dtable_4_200),
> --
> 2.43.0

Re: [PATCH] clk: renesas: r9a08g046: Propagate clk rate for ETH TX mux clocks

[Greg Kroah-Hartman]

On Mon, Oct 26, 2026 at 10:22:38AM +0000, Biju Das wrote:
> 
> Hi Greg/Sasha,
> 
> Sorry, I missed adding Cc: <stable@vger.kernel.org> for the below Fixes commit
> 
> Commit e018c27e6052 "clk: renesas: r9a08g046: Propagate clk rate for ETH TX mux clocks"
> in Linux-next.
> 
> So, can it be backported to 7.3 and stable kernels?

Applied to 7.3.y now, thanks.

greg k-h