* [PATCH 0/5] riscv: spacemit: k3: Add SPL LPDDR5 initialization
@ 2026-11-05 16:40 Junhui Liu
2026-11-05 16:40 ` [PATCH 1/5] ram: spacemit: Add DDR driver for K3 SoC Junhui Liu
` (4 more replies)
0 siblings, 5 replies; 9+ messages in thread
From: Junhui Liu @ 2026-11-05 16:40 UTC (permalink / raw)
To: u-boot, Yao Zi, u-boot-spacemit
Cc: Tom Rini, Yixun Lan, Junhui Liu, Tim Ouyang, Leo Liang, E Shattow,
Huan Zhou, Eric Chung
Add initial SPL support for LPDDR5 initialization on the SpacemiT K3
SoC.
The DDR driver follows the vendor initialization sequence, selects a
memory profile using the DDR part number read from the board's EEPROM,
and configures both DDR controllers and PHYs to perform LPDDR5 training.
Loading the next boot stage is not implemented yet. SPL currently
returns BOOT_DEVICE_NONE and stops with "Unsupported Boot Device!"
after successful DRAM initialization. No LPDDR4X boards are currently
available for testing, so LPDDR4X support will be added in a separate
series in the future.
Tested on 8 GiB and 16 GiB Pico-ITX boards and an 8 GiB COM260 board by
entering BootROM USB download mode and running:
fastboot stage spl/u-boot-spl-mkimage.bin && fastboot continue
---
Junhui Liu (5):
ram: spacemit: Add DDR driver for K3 SoC
riscv: spacemit: k3: Add SPL initialization support
riscv: dts: spacemit: k3: Add SPL device and image descriptions
configs: spacemit: k3: Enable SPL support
doc: spacemit: k3: Add SPL build instructions
arch/riscv/cpu/k3/Kconfig | 6 +-
arch/riscv/cpu/k3/Makefile | 1 +
arch/riscv/cpu/k3/spl.c | 52 +
arch/riscv/dts/spacemit-k3-binman.dtsi | 24 +
arch/riscv/dts/spacemit-k3-u-boot.dtsi | 54 +
arch/riscv/include/asm/arch-k3/csr.h | 20 +
arch/riscv/include/asm/arch-k3/spl.h | 11 +
board/spacemit/k3/Makefile | 5 +
board/spacemit/k3/spl.c | 127 ++
configs/spacemit_k3_defconfig | 22 +
doc/board/spacemit/spacemit-pico-itx.rst | 12 +-
drivers/ram/Kconfig | 1 +
drivers/ram/Makefile | 1 +
drivers/ram/spacemit/Kconfig | 6 +
drivers/ram/spacemit/Makefile | 3 +
drivers/ram/spacemit/k3/Makefile | 9 +
drivers/ram/spacemit/k3/k3_ddr.c | 134 ++
drivers/ram/spacemit/k3/k3_ddr.h | 169 +++
drivers/ram/spacemit/k3/k3_ddr_ctrl.c | 73 ++
drivers/ram/spacemit/k3/k3_ddr_lpddr5.c | 538 ++++++++
drivers/ram/spacemit/k3/k3_ddr_lpddr5_tables.c | 1668 ++++++++++++++++++++++++
drivers/ram/spacemit/k3/k3_ddr_phy.c | 149 +++
drivers/ram/spacemit/k3/k3_ddr_profile.c | 54 +
include/configs/spacemit-k3.h | 3 +
include/soc/spacemit/k3-ddr.h | 13 +
25 files changed, 3150 insertions(+), 5 deletions(-)
---
base-commit: d1d45c926a571fb6c1e6d7105c280833646915ea
change-id: 20261104-k3-ddr-85685cac0f02
Best regards,
--
Junhui Liu <junhui.liu@pigmoral.tech>
^ permalink raw reply [flat|nested] 9+ messages in thread
* [PATCH 1/5] ram: spacemit: Add DDR driver for K3 SoC
2026-11-05 16:40 [PATCH 0/5] riscv: spacemit: k3: Add SPL LPDDR5 initialization Junhui Liu
@ 2026-11-05 16:40 ` Junhui Liu
2026-11-05 16:40 ` [PATCH 2/5] riscv: spacemit: k3: Add SPL initialization support Junhui Liu
` (3 subsequent siblings)
4 siblings, 0 replies; 9+ messages in thread
From: Junhui Liu @ 2026-11-05 16:40 UTC (permalink / raw)
To: u-boot, Yao Zi, u-boot-spacemit
Cc: Tom Rini, Yixun Lan, Junhui Liu, Tim Ouyang, Leo Liang, E Shattow,
Huan Zhou, Eric Chung
The SpacemiT K3 SoC integrates two DDR controllers, each paired with a
Synopsys DDR PHY, supporting LPDDR4X and LPDDR5 memory. Add an SPL RAM
driver with initial support for LPDDR5 to configure both controllers
and PHYs, run training, and report the combined capacity through the
RAM uclass.
The board code must read the DDR part number from EEPROM and populate
the driver's platform data before probing the device. The driver uses
this part number to select the corresponding memory profile.
Preserve the vendor register tables, part-specific overrides and PHY
write sequence. Package the PMU IMEM firmware as an external binary
through binman.
Signed-off-by: Junhui Liu <junhui.liu@pigmoral.tech>
---
drivers/ram/Kconfig | 1 +
drivers/ram/Makefile | 1 +
drivers/ram/spacemit/Kconfig | 6 +
drivers/ram/spacemit/Makefile | 3 +
drivers/ram/spacemit/k3/Makefile | 9 +
drivers/ram/spacemit/k3/k3_ddr.c | 134 ++
drivers/ram/spacemit/k3/k3_ddr.h | 169 +++
drivers/ram/spacemit/k3/k3_ddr_ctrl.c | 73 ++
drivers/ram/spacemit/k3/k3_ddr_lpddr5.c | 538 ++++++++
drivers/ram/spacemit/k3/k3_ddr_lpddr5_tables.c | 1668 ++++++++++++++++++++++++
drivers/ram/spacemit/k3/k3_ddr_phy.c | 149 +++
drivers/ram/spacemit/k3/k3_ddr_profile.c | 54 +
include/soc/spacemit/k3-ddr.h | 13 +
13 files changed, 2818 insertions(+)
diff --git a/drivers/ram/Kconfig b/drivers/ram/Kconfig
index acd6d9cfd6a..d3a4c6f8d27 100644
--- a/drivers/ram/Kconfig
+++ b/drivers/ram/Kconfig
@@ -145,6 +145,7 @@ source "drivers/ram/octeon/Kconfig"
source "drivers/ram/renesas/Kconfig"
source "drivers/ram/rockchip/Kconfig"
source "drivers/ram/sifive/Kconfig"
+source "drivers/ram/spacemit/Kconfig"
source "drivers/ram/stm32mp1/Kconfig"
source "drivers/ram/starfive/Kconfig"
source "drivers/ram/sunxi/Kconfig"
diff --git a/drivers/ram/Makefile b/drivers/ram/Makefile
index 82afd5fcbcc..e9c2674206c 100644
--- a/drivers/ram/Makefile
+++ b/drivers/ram/Makefile
@@ -21,6 +21,7 @@ obj-$(CONFIG_IMXRT_SDRAM) += imxrt_sdram.o
obj-$(CONFIG_RAM_SIFIVE) += sifive/
ifdef CONFIG_XPL_BUILD
+obj-$(CONFIG_SPL_SPACEMIT_K3_DDR) += spacemit/
obj-$(CONFIG_SPL_STARFIVE_DDR) += starfive/
endif
diff --git a/drivers/ram/spacemit/Kconfig b/drivers/ram/spacemit/Kconfig
new file mode 100644
index 00000000000..8f45c96220c
--- /dev/null
+++ b/drivers/ram/spacemit/Kconfig
@@ -0,0 +1,6 @@
+config SPL_SPACEMIT_K3_DDR
+ bool "SpacemiT K3 DDR controller support"
+ depends on SPL_RAM && SPACEMIT_K3
+ select SPL_BINMAN_SYMBOLS
+ help
+ This enables DDR support for SpacemiT K3 platforms.
diff --git a/drivers/ram/spacemit/Makefile b/drivers/ram/spacemit/Makefile
new file mode 100644
index 00000000000..0db2546cf16
--- /dev/null
+++ b/drivers/ram/spacemit/Makefile
@@ -0,0 +1,3 @@
+# SPDX-License-Identifier: GPL-2.0-or-later
+
+obj-$(CONFIG_SPL_SPACEMIT_K3_DDR) += k3/
diff --git a/drivers/ram/spacemit/k3/Makefile b/drivers/ram/spacemit/k3/Makefile
new file mode 100644
index 00000000000..9cf82d34f68
--- /dev/null
+++ b/drivers/ram/spacemit/k3/Makefile
@@ -0,0 +1,9 @@
+# SPDX-License-Identifier: GPL-2.0-or-later
+
+obj-y += k3_ddr.o
+obj-y += k3_ddr_ctrl.o
+obj-y += k3_ddr_phy.o
+obj-y += k3_ddr_profile.o
+
+obj-y += k3_ddr_lpddr5.o
+obj-y += k3_ddr_lpddr5_tables.o
diff --git a/drivers/ram/spacemit/k3/k3_ddr.c b/drivers/ram/spacemit/k3/k3_ddr.c
new file mode 100644
index 00000000000..9c1e8d513be
--- /dev/null
+++ b/drivers/ram/spacemit/k3/k3_ddr.c
@@ -0,0 +1,134 @@
+// SPDX-License-Identifier: GPL-2.0-or-later
+/*
+ * Copyright (C) 2026 Junhui Liu <junhui.liu@pigmoral.tech>
+ */
+
+#include <binman_sym.h>
+#include <dm.h>
+#include <dm/device_compat.h>
+#include <dm/ofnode.h>
+#include <errno.h>
+#include <linux/sizes.h>
+#include <ram.h>
+#include <soc/spacemit/k3-ddr.h>
+#include <spl.h>
+
+#include "k3_ddr.h"
+
+struct k3_ddr_priv {
+ struct k3_ddr ddr;
+ struct ram_info info;
+};
+
+binman_sym_declare(ulong, u_boot_spl, image_pos);
+binman_sym_declare(ulong, lpddr5_imem, image_pos);
+binman_sym_declare(ulong, lpddr5_imem, size);
+
+static int k3_ddr_get_firmware(struct k3_ddr *ddr)
+{
+ ulong fw_pos = binman_sym(ulong, lpddr5_imem, image_pos);
+ ulong spl_pos = binman_sym(ulong, u_boot_spl, image_pos);
+ ulong size = binman_sym(ulong, lpddr5_imem, size);
+
+ if (!BINMAN_SYMS_OK)
+ return -ENOENT;
+
+ if (!size || size > K3_PHY_PMU_IMEM_SIZE * sizeof(u16))
+ return -EINVAL;
+
+ ddr->imem_fw = (const u8 *)(CONFIG_SPL_TEXT_BASE + fw_pos - spl_pos);
+ ddr->imem_fw_size = size;
+
+ return 0;
+}
+
+static int k3_ddr_get_info(struct udevice *dev, struct ram_info *info)
+{
+ struct k3_ddr_priv *priv = dev_get_priv(dev);
+
+ *info = priv->info;
+
+ return 0;
+}
+
+static int k3_ddr_probe(struct udevice *dev)
+{
+ struct k3_ddr_priv *priv = dev_get_priv(dev);
+ struct k3_ddr_plat *plat = dev_get_plat(dev);
+ const char *part_number = plat->part_number;
+ struct ofnode_phandle_args apmu_args;
+ fdt_addr_t addr;
+ int i, ret;
+
+ priv->ddr.dev = dev;
+
+ for (i = 0; i < K3_DDR_NUM_CHANNELS; i++) {
+ priv->ddr.ctrl[i] = dev_read_addr_index_ptr(dev, i);
+ if (!priv->ddr.ctrl[i])
+ return -EINVAL;
+
+ priv->ddr.cfg[i] = priv->ddr.ctrl[i] + K3_DDR_CFG_OFFSET;
+ priv->ddr.phy[i] = priv->ddr.ctrl[i] + K3_DDR_PHY_OFFSET;
+ }
+
+ ret = dev_read_phandle_with_args(dev, "spacemit,apmu", NULL, 1, 0, &apmu_args);
+ if (ret)
+ return ret;
+
+ addr = ofnode_get_addr(apmu_args.node);
+ if (addr == FDT_ADDR_T_NONE)
+ return -EINVAL;
+
+ priv->ddr.apmu = (void __iomem *)addr;
+ priv->ddr.apmu_offset = apmu_args.args[0];
+
+ if (!part_number[0]) {
+ dev_err(dev, "DDR part number not configured\n");
+ return -EINVAL;
+ }
+
+ priv->ddr.profile = k3_ddr_find_profile(part_number);
+ if (!priv->ddr.profile) {
+ dev_err(dev, "unsupported DDR part: %s\n", part_number);
+ return -EOPNOTSUPP;
+ }
+
+ ret = k3_ddr_get_firmware(&priv->ddr);
+ if (ret) {
+ dev_err(dev, "invalid or missing DDR PMU firmware: %d\n", ret);
+ return ret;
+ }
+
+ debug("DDR: %s, %u MiB/channel, %u ranks, x%u\n", part_number,
+ priv->ddr.profile->part_size_mb, priv->ddr.profile->ranks,
+ priv->ddr.profile->device_width);
+
+ ret = k3_ddr_lpddr5_init(&priv->ddr);
+ if (ret)
+ return ret;
+
+ priv->info.base = 0x100000000ULL;
+ priv->info.size = (phys_size_t)priv->ddr.profile->part_size_mb *
+ K3_DDR_NUM_CHANNELS * SZ_1M;
+
+ return 0;
+}
+
+static const struct ram_ops k3_ddr_ops = {
+ .get_info = k3_ddr_get_info,
+};
+
+static const struct udevice_id k3_ddr_ids[] = {
+ { .compatible = "spacemit,k3-ddrc" },
+ { /* sentinel */ }
+};
+
+U_BOOT_DRIVER(spacemit_k3_ddr) = {
+ .name = "spacemit_k3_ddr",
+ .id = UCLASS_RAM,
+ .of_match = k3_ddr_ids,
+ .probe = k3_ddr_probe,
+ .ops = &k3_ddr_ops,
+ .priv_auto = sizeof(struct k3_ddr_priv),
+ .plat_auto = sizeof(struct k3_ddr_plat),
+};
diff --git a/drivers/ram/spacemit/k3/k3_ddr.h b/drivers/ram/spacemit/k3/k3_ddr.h
new file mode 100644
index 00000000000..78d2d6b3e2c
--- /dev/null
+++ b/drivers/ram/spacemit/k3/k3_ddr.h
@@ -0,0 +1,169 @@
+/* SPDX-License-Identifier: GPL-2.0-or-later */
+/*
+ * Copyright (C) 2026 Junhui Liu <junhui.liu@pigmoral.tech>
+ */
+
+#ifndef _SPACEMIT_K3_DDR_H_
+#define _SPACEMIT_K3_DDR_H_
+
+#include <linux/bitops.h>
+#include <linux/kernel.h>
+#include <linux/types.h>
+
+#define K3_DDR_NUM_CHANNELS 2
+#define K3_DDR_REG_TIMEOUT_US 100000
+
+/* PHY PMU memory bases and sizes are in 16-bit CSR words. */
+#define K3_PHY_PMU_IMEM_BASE 0x50000
+#define K3_PHY_PMU_IMEM_SIZE 0x8000
+#define K3_PHY_PMU_DMEM_BASE 0x58000
+#define K3_PHY_PMU_DMEM_SIZE 0x8000
+
+#define K3_DDR_PHY_OFFSET 0x800000
+#define K3_DDR_CFG_OFFSET 0x600000
+
+#define K3_DDR_SWCTL 0x10c80
+#define K3_DDR_SWSTAT 0x10c84
+#define K3_DDR_PWRCTL 0x10180
+
+#define K3_DDR_CFG_PLL_SWCR2 0x0c
+#define K3_DDR_PLLA_SWCR2_MMD_EN BIT(22)
+#define K3_DDR_PLLA_SWCR2_EN BIT(16)
+#define K3_DDR_PLLA_SWCR2_OUT_EN GENMASK(7, 0)
+
+#define K3_DDR_CFG_PLL_STATUS 0x1c
+#define K3_DDR_CFG_PLL_LOCK BIT(0)
+
+#define K3_DDR_CFG_CLK_CTRL 0x18
+#define K3_DDR_CFG_CLK_FC BIT(25)
+#define K3_DDR_CFG_CLK_SEL GENMASK(21, 19)
+#define K3_DDR_CFG_CLK_DIV GENMASK(18, 16)
+#define K3_DDR_CFG_CLK_EN BIT(0)
+
+#define K3_DDR_PHY_CFG_OP GENMASK(31, 24)
+#define K3_DDR_PHY_CFG_ADDR GENMASK(23, 0)
+
+#define K3_DDR_PHY_CFG_SINGLE 0
+#define K3_DDR_PHY_CFG_RANGE 1
+
+#define K3_DDR_PHY_SKIP BIT(0)
+
+struct k3_ddr_phy_cfg {
+ /* Bits [31:24] encode the operation. Bits [23:0] hold the PHY CSR address. */
+ u32 opaddr;
+ union {
+ u16 value;
+ struct {
+ const u16 *values;
+ u16 count;
+ } range;
+ };
+};
+
+#define K3_DDR_PHY_WRITE_SINGLE(_csr, _value) \
+{ \
+ .opaddr = (_csr) | (K3_DDR_PHY_CFG_SINGLE << 24), \
+ .value = (_value), \
+}
+
+#define K3_DDR_PHY_WRITE_RANGE(_csr, _values) \
+{ \
+ .opaddr = (_csr) | (K3_DDR_PHY_CFG_RANGE << 24), \
+ .range = { \
+ .values = (_values), \
+ .count = ARRAY_SIZE(_values), \
+ }, \
+}
+
+struct k3_ddr_phy_table {
+ const struct k3_ddr_phy_cfg *cfg;
+ size_t count;
+};
+
+struct k3_ddr_phy_override {
+ u32 csr;
+ u16 value;
+ u16 flags;
+};
+
+struct k3_ddr_phy_overrides {
+ const struct k3_ddr_phy_override *regs;
+ size_t count;
+};
+
+enum k3_ddr_phy_odt {
+ K3_DDR_PHY_R_OFF = 0,
+ K3_DDR_PHY_R_120 = 0x08,
+ K3_DDR_PHY_R_60 = 0x0c,
+ K3_DDR_PHY_R_40 = 0x0e,
+ K3_DDR_PHY_R_30 = 0x0f,
+};
+
+enum k3_ddr_odt {
+ K3_DDR_R_OFF = 0,
+ K3_DDR_R_240,
+ K3_DDR_R_120,
+ K3_DDR_R_80,
+ K3_DDR_R_60,
+ K3_DDR_R_48,
+ K3_DDR_R_40,
+};
+
+struct k3_ddr_io_para {
+ u8 write_ds;
+ u8 rx_odt;
+ u8 pdds;
+ u8 dq_odt;
+ u8 ca_odt;
+ u8 nt_odt;
+ u8 soc_odt;
+};
+
+struct k3_ddr_profile {
+ const char *part_number;
+ u32 part_size_mb;
+ u8 ranks;
+ u8 device_width;
+};
+
+struct k3_ddr {
+ struct udevice *dev;
+ const struct k3_ddr_profile *profile;
+
+ void __iomem *ctrl[K3_DDR_NUM_CHANNELS];
+ void __iomem *cfg[K3_DDR_NUM_CHANNELS];
+ void __iomem *phy[K3_DDR_NUM_CHANNELS];
+
+ void __iomem *apmu;
+ u32 apmu_offset;
+
+ const u8 *imem_fw;
+ size_t imem_fw_size;
+};
+
+extern const struct k3_ddr_phy_table k3_ddr_lpddr5_phy_init_table;
+extern const struct k3_ddr_phy_table k3_ddr_lpddr5_pre_train_table;
+extern const struct k3_ddr_phy_table k3_ddr_lpddr5_post_train_table;
+
+extern const struct k3_ddr_phy_overrides k3_ddr_lpddr5_pre_srank_x16_overrides;
+extern const struct k3_ddr_phy_overrides k3_ddr_lpddr5_pre_drank_x16_overrides;
+extern const struct k3_ddr_phy_overrides k3_ddr_lpddr5_post_srank_x16_overrides;
+extern const struct k3_ddr_phy_overrides k3_ddr_lpddr5_post_drank_x16_overrides;
+
+int k3_ddr_clock_init(struct k3_ddr *ddr, unsigned int channel);
+void k3_ddr_start_sw_done(struct k3_ddr *ddr, unsigned int channel);
+int k3_ddr_wait_sw_done_ack(struct k3_ddr *ddr, unsigned int channel);
+void k3_ddr_configure_sar(struct k3_ddr *ddr, unsigned int channel);
+
+void k3_phy_write(struct k3_ddr *ddr, unsigned int channel, u32 csr, u16 value);
+int k3_ddr_phy_load_imem(struct k3_ddr *ddr, unsigned int channel);
+void k3_ddr_phy_zero_dmem(struct k3_ddr *ddr, unsigned int channel);
+void k3_ddr_phy_start_pmu(struct k3_ddr *ddr, unsigned int channel);
+void k3_ddr_phy_halt_pmu(struct k3_ddr *ddr, unsigned int channel);
+int k3_ddr_phy_wait_training(struct k3_ddr *ddr, unsigned int channel);
+
+const struct k3_ddr_profile *k3_ddr_find_profile(const char *part_number);
+
+int k3_ddr_lpddr5_init(struct k3_ddr *ddr);
+
+#endif /* _SPACEMIT_K3_DDR_H_ */
diff --git a/drivers/ram/spacemit/k3/k3_ddr_ctrl.c b/drivers/ram/spacemit/k3/k3_ddr_ctrl.c
new file mode 100644
index 00000000000..fca7176643d
--- /dev/null
+++ b/drivers/ram/spacemit/k3/k3_ddr_ctrl.c
@@ -0,0 +1,73 @@
+// SPDX-License-Identifier: GPL-2.0-or-later
+/*
+ * Copyright (C) 2025 SpacemiT
+ * Copyright (C) 2026 Junhui Liu <junhui.liu@pigmoral.tech>
+ */
+
+#include <asm/io.h>
+#include <linux/bitfield.h>
+#include <linux/bitops.h>
+#include <linux/iopoll.h>
+
+#include "k3_ddr.h"
+
+#define K3_DDR_SARBASE(n) (0x200c0 + (n) * 8)
+#define K3_DDR_SARSIZE(n) (0x200c4 + (n) * 8)
+
+int k3_ddr_clock_init(struct k3_ddr *ddr, unsigned int channel)
+{
+ void __iomem *cfg = ddr->cfg[channel];
+ u32 value;
+ int ret;
+
+ setbits_le32(cfg + K3_DDR_CFG_PLL_SWCR2, K3_DDR_PLLA_SWCR2_OUT_EN | K3_DDR_PLLA_SWCR2_EN |
+ K3_DDR_PLLA_SWCR2_MMD_EN);
+ ret = readl_poll_timeout(cfg + K3_DDR_CFG_PLL_STATUS, value, value & K3_DDR_CFG_PLL_LOCK,
+ K3_DDR_REG_TIMEOUT_US);
+ if (ret)
+ return ret;
+
+ clrsetbits_le32(cfg + K3_DDR_CFG_CLK_CTRL, K3_DDR_CFG_CLK_SEL | K3_DDR_CFG_CLK_DIV,
+ FIELD_PREP(K3_DDR_CFG_CLK_SEL, 2));
+
+ setbits_le32(cfg + K3_DDR_CFG_CLK_CTRL, K3_DDR_CFG_CLK_FC);
+ ret = readl_poll_timeout(cfg + K3_DDR_CFG_CLK_CTRL, value, !(value & K3_DDR_CFG_CLK_FC),
+ K3_DDR_REG_TIMEOUT_US);
+ if (ret)
+ return ret;
+
+ setbits_le32(cfg + K3_DDR_CFG_CLK_CTRL, K3_DDR_CFG_CLK_EN);
+
+ return 0;
+}
+
+void k3_ddr_start_sw_done(struct k3_ddr *ddr, unsigned int channel)
+{
+ writel(0, ddr->ctrl[channel] + K3_DDR_SWCTL);
+}
+
+int k3_ddr_wait_sw_done_ack(struct k3_ddr *ddr, unsigned int channel)
+{
+ void __iomem *ctrl = ddr->ctrl[channel];
+ u32 value;
+
+ writel(1, ctrl + K3_DDR_SWCTL);
+
+ return readl_poll_timeout(ctrl + K3_DDR_SWSTAT, value, value & BIT(0),
+ K3_DDR_REG_TIMEOUT_US);
+}
+
+void k3_ddr_configure_sar(struct k3_ddr *ddr, unsigned int channel)
+{
+ void __iomem *ctrl = ddr->ctrl[channel];
+ u32 region_blocks;
+ int region;
+
+ /* Four equal SARs (System Address Regions), in units of 256 MiB. */
+ region_blocks = ddr->profile->part_size_mb / 4 / 256;
+
+ for (region = 0; region < 4; region++) {
+ writel(8 + region_blocks * region, ctrl + K3_DDR_SARBASE(region));
+ writel(region_blocks - 1, ctrl + K3_DDR_SARSIZE(region));
+ }
+}
diff --git a/drivers/ram/spacemit/k3/k3_ddr_lpddr5.c b/drivers/ram/spacemit/k3/k3_ddr_lpddr5.c
new file mode 100644
index 00000000000..b881191f29d
--- /dev/null
+++ b/drivers/ram/spacemit/k3/k3_ddr_lpddr5.c
@@ -0,0 +1,538 @@
+// SPDX-License-Identifier: GPL-2.0-or-later
+/*
+ * SpacemiT K3 LPDDR5 initialization
+ *
+ * Copyright (C) 2025 SpacemiT
+ * Copyright (C) 2026 Junhui Liu <junhui.liu@pigmoral.tech>
+ */
+
+#include <asm/io.h>
+#include <dm.h>
+#include <dm/device_compat.h>
+#include <linux/bitfield.h>
+#include <linux/errno.h>
+#include <linux/iopoll.h>
+#include <linux/sizes.h>
+
+#include "k3_ddr.h"
+
+#define K3_DDR_STAT 0x10014
+#define K3_DDR_RFSHCTL0 0x10208
+#define K3_DDR_ZQCTL0 0x10280
+#define K3_DDR_ZQCTL2 0x10288
+#define K3_DDR_DFIUPD0 0x10508
+#define K3_DDR_DFIMISC 0x10510
+#define K3_DDR_DFISTAT 0x10514
+#define K3_DDR_OPCTRL1 0x10b84
+#define K3_DDR_INITTMG0 0x10d00
+
+#define K3_DDR_ADDRMAP(n) (0x30000 + (n) * 4)
+
+#define K3_PHY_MB_MR3 0x58031
+#define K3_PHY_MB_MR11 0x58035
+#define K3_PHY_MB_MR17 0x58041
+#define K3_PHY_MB_MR41 0x58065
+#define K3_PHY_MB_DISABLE_2D 0x58067
+
+static const struct k3_ddr_io_para k3_ddr_lpddr5_io_para = {
+ .write_ds = K3_DDR_PHY_R_30,
+ .rx_odt = K3_DDR_PHY_R_60,
+ .pdds = K3_DDR_R_40,
+ .dq_odt = K3_DDR_R_60,
+ .ca_odt = K3_DDR_R_80,
+ .nt_odt = K3_DDR_R_OFF,
+ .soc_odt = K3_DDR_R_OFF,
+};
+
+static void k3_lpddr5_configure_controller(struct k3_ddr *ddr, unsigned int channel)
+{
+ const struct k3_ddr_profile *profile = ddr->profile;
+ void __iomem *ctrl = ddr->ctrl[channel];
+ bool x8 = profile->device_width == 8;
+
+ writel(profile->ranks > 1 ? 0x03080008 : 0x01080008, ctrl + 0x00010000);
+ clrsetbits_le32(ddr->apmu + ddr->apmu_offset, GENMASK(31, 24),
+ FIELD_PREP(GENMASK(31, 24), readl(ctrl + 0x00010000) & 0xff));
+
+ writel(0x00000000, ctrl + 0x00010008);
+ writel(0x00010005, ctrl + 0x00010510);
+ writel(0x70000000, ctrl + 0x00010518);
+ writel(0x00000000, ctrl + 0x00010208);
+
+ if (profile->ranks == 1)
+ writel(0x010003f3, ctrl + 0x00010200);
+ else
+ writel(0x00000361, ctrl + 0x00010200);
+
+ writel(0x00000000, ctrl + 0x00010280);
+ writel(0x0a000100, ctrl + 0x00010220);
+ writel(0x00000000, ctrl + 0x00010224);
+ writel(0x00000000, ctrl + 0x00010288);
+ writel(0x80012010, ctrl + 0x00010380);
+ writel(0x00000020, ctrl + 0x00010100);
+ writel(x8 ? 0x0000000f : 0x00000005, ctrl + 0x00010104);
+ writel(x8 ? 0x0000000f : 0x00000005, ctrl + 0x00010108);
+ writel(0x00000000, ctrl + 0x00010118);
+ writel(0x0000000f, ctrl + 0x00010c90);
+ writel(0x00000000, ctrl + 0x00010b80);
+ writel(0x00400040, ctrl + 0x00010300);
+ writel(0x00002000, ctrl + 0x00010384);
+ writel(0x04040208, ctrl + 0x0001038c);
+ writel(0x08400810, ctrl + 0x00010390);
+ writel(0x00100000, ctrl + 0x00010500);
+ writel(0xc0000000, ctrl + 0x00010508);
+ writel(0x00000000, ctrl + 0x00010ca0);
+ writel(0x00000001, ctrl + 0x00010c80);
+ writel(0x80008200, ctrl + 0x00010f00);
+ writel(0x00110011, ctrl + 0x00010580);
+ writel(0x00000000, ctrl + 0x00010ca4);
+ writel(0x00000000, ctrl + 0x00010308);
+ writel(0x0000003f, ctrl + 0x0001018c);
+ writel(0x00000003, ctrl + 0x00010184);
+ writel(0x00000001, ctrl + 0x00010114);
+ writel(0x00000000, ctrl + 0x00010128);
+ writel(0x00000001, ctrl + 0x00010c94);
+ writel(0x00000003, ctrl + 0x00010b84);
+ writel(0x00000011, ctrl + 0x00010180);
+ writel(0x00020002, ctrl + 0x00010d00);
+ writel(0x00000100, ctrl + 0x00010010);
+ writel(0x00000000, ctrl + 0x00010084);
+ writel(0x00000000, ctrl + 0x00010284);
+ writel(0x00000000, ctrl + 0x00010b8c);
+ writel(0x00000000, ctrl + 0x00010b98);
+ writel(0x71a4000d, ctrl + 0x000005a8);
+ writel(0x00000000, ctrl + 0x000005a0);
+ writel(0x00000300, ctrl + 0x000005a4);
+ writel(0x00000004, ctrl + 0x000005b0);
+ writel(0x00000001, ctrl + 0x00000d00);
+ writel(0xe000012c, ctrl + 0x000005b4);
+}
+
+static void k3_lpddr5_configure_parameters(struct k3_ddr *ddr, unsigned int channel)
+{
+ bool x8 = ddr->profile->device_width == 8;
+ void __iomem *ctrl = ddr->ctrl[channel];
+
+ writel(x8 ? 0x29103622 : 0x28103622, ctrl + 0x00000000);
+ writel(0x00100630, ctrl + 0x00000004);
+ writel(x8 ? 0x09121219 : 0x09111117, ctrl + 0x00000008);
+ writel(x8 ? 0x000c2230 : 0x000c212f, ctrl + 0x0000000c);
+ writel(0x0f04040f, ctrl + 0x00000010);
+ writel(0x02040c09, ctrl + 0x00000014);
+ writel(0x00000012, ctrl + 0x00000018);
+ writel(0x00c90003, ctrl + 0x0000001c);
+ writel(x8 ? 0x00020412 : 0x00020410, ctrl + 0x00000024);
+ writel(0x00030000, ctrl + 0x00000030);
+ writel(0x0c100002, ctrl + 0x00000034);
+ writel(0x002000e6, ctrl + 0x00000038);
+ writel(x8 ? 0x0010170e : 0x000f160e, ctrl + 0x00000060);
+ writel(x8 ? 0x00002906 : 0x00002806, ctrl + 0x00000064);
+ writel(x8 ? 0x001a1419 : 0x00191318, ctrl + 0x00000078);
+ writel(0x00030408, ctrl + 0x00000080);
+ writel(0xc03f0c34, ctrl + 0x00000600);
+ writel(0x00e00070, ctrl + 0x00000604);
+ writel(0x06480000, ctrl + 0x00000608);
+ writel(0x3f000000, ctrl + 0x0000060c);
+ writel(0x00000000, ctrl + 0x00000610);
+ writel(0x001804d7, ctrl + 0x00000800);
+ writel(0x02800100, ctrl + 0x00000804);
+ writel(0x00400010, ctrl + 0x00000d0c);
+ writel(0x0f00007f, ctrl + 0x00000c84);
+ writel(0x00000000, ctrl + 0x00000b80);
+ writel(0x1024100a, ctrl + 0x00000b04);
+ writel(0x00000033, ctrl + 0x00000b08);
+ writel(0x00800000, ctrl + 0x00000b00);
+ writel(0x00000e12, ctrl + 0x00000d04);
+ writel(x8 ? 0x0343021f : 0x033f021f, ctrl + 0x00000580);
+ writel(0x00080303, ctrl + 0x00000584);
+ writel(x8 ? 0x0018431f : 0x00183f1f, ctrl + 0x00000588);
+ writel(x8 ? 0x1c0c0403 : 0x180c0403, ctrl + 0x00000590);
+ writel(0x0410000f, ctrl + 0x00000594);
+ writel(0x00000000, ctrl + 0x00000500);
+ writel(0x00000000, ctrl + 0x00000504);
+ writel(0x00000000, ctrl + 0x00000508);
+ writel(0x00000000, ctrl + 0x0000050c);
+ writel(0x009d0009, ctrl + 0x0000005c);
+ writel(0x00000000, ctrl + 0x00000c00);
+ writel(0x00010001, ctrl + 0x000005ac);
+ writel(0x12c00147, ctrl + 0x000005b8);
+ writel(0x00000070, ctrl + 0x00000a80);
+ writel(x8 ? 0x0000160a : 0x0000150b, ctrl + 0x00000d08);
+ writel(0x0f000001, ctrl + 0x00000c80);
+ writel(0x0f00007f, ctrl + 0x00000c88);
+ writel(0x00000098, ctrl + 0x00000650);
+ writel(0x002faf09, ctrl + 0x00000d30);
+ writel(0x180009c5, ctrl + 0x00000d34);
+}
+
+static void k3_lpddr5_configure_ports(struct k3_ddr *ddr, unsigned int channel)
+{
+ void __iomem *ctrl = ddr->ctrl[channel];
+
+ writel(0x00000000, ctrl + 0x00020000);
+ writel(0x0000501f, ctrl + 0x00020004);
+ writel(0x0000501f, ctrl + 0x00021004);
+ writel(0x0000501f, ctrl + 0x00022004);
+ writel(0x0000501f, ctrl + 0x00023004);
+ writel(0x0000501f, ctrl + 0x00024004);
+ writel(0x0000501f, ctrl + 0x00020008);
+ writel(0x0000501f, ctrl + 0x00021008);
+ writel(0x0000501f, ctrl + 0x00022008);
+ writel(0x0000501f, ctrl + 0x00023008);
+ writel(0x0000501f, ctrl + 0x00024008);
+ writel(0x00000000, ctrl + 0x00020090);
+ writel(0x00000000, ctrl + 0x00021090);
+ writel(0x00000000, ctrl + 0x00022090);
+ writel(0x00000000, ctrl + 0x00023090);
+ writel(0x00000000, ctrl + 0x00024090);
+ writel(0x00000000, ctrl + 0x00020094);
+ writel(0x00000000, ctrl + 0x00021094);
+ writel(0x00000000, ctrl + 0x00022094);
+ writel(0x00000000, ctrl + 0x00023094);
+ writel(0x00000000, ctrl + 0x00024094);
+ writel(0x00000000, ctrl + 0x00020098);
+ writel(0x00000000, ctrl + 0x00021098);
+ writel(0x00000000, ctrl + 0x00022098);
+ writel(0x00000000, ctrl + 0x00023098);
+ writel(0x00000000, ctrl + 0x00024098);
+ writel(0x00000e00, ctrl + 0x0002009c);
+ writel(0x00000e00, ctrl + 0x0002109c);
+ writel(0x00000e00, ctrl + 0x0002209c);
+ writel(0x00000e00, ctrl + 0x0002309c);
+ writel(0x00000e00, ctrl + 0x0002409c);
+ writel(0x00000000, ctrl + 0x000200a0);
+ writel(0x00000000, ctrl + 0x000210a0);
+ writel(0x00000000, ctrl + 0x000220a0);
+ writel(0x00000000, ctrl + 0x000230a0);
+ writel(0x00000000, ctrl + 0x000240a0);
+}
+
+static int k3_lpddr5_configure_addrmap(struct k3_ddr *ddr, unsigned int channel)
+{
+ const struct k3_ddr_profile *profile = ddr->profile;
+ void __iomem *ctrl = ddr->ctrl[channel];
+ u32 cs_map, addrmap7;
+ u32 addrmap12 = 0;
+
+ switch (profile->part_size_mb) {
+ case SZ_4G / SZ_1M:
+ cs_map = 0x0000003f;
+ addrmap7 = 0x1f1f0808;
+ break;
+ case SZ_8G / SZ_1M:
+ cs_map = 0x00000018;
+ addrmap7 = 0x1f1f0808;
+ break;
+ case (SZ_8G + SZ_4G) / SZ_1M:
+ cs_map = 0x00000019;
+ addrmap7 = 0x1f080808;
+ /* Exclude the unused quarter of the 16 GiB address range. */
+ addrmap12 = 0x00000004;
+ break;
+ case SZ_16G / SZ_1M:
+ cs_map = 0x00000019;
+ addrmap7 = 0x1f080808;
+ break;
+ default:
+ return -EOPNOTSUPP;
+ }
+
+ writel(cs_map, ctrl + K3_DDR_ADDRMAP(1));
+ writel(0x003f0903, ctrl + K3_DDR_ADDRMAP(3));
+ writel(0x00000101, ctrl + K3_DDR_ADDRMAP(4));
+ writel(0x1f030303, ctrl + K3_DDR_ADDRMAP(5));
+ writel(0x03030300, ctrl + K3_DDR_ADDRMAP(6));
+ writel(addrmap7, ctrl + K3_DDR_ADDRMAP(7));
+ writel(0x08080808, ctrl + K3_DDR_ADDRMAP(8));
+ writel(0x08080808, ctrl + K3_DDR_ADDRMAP(9));
+ writel(0x08080808, ctrl + K3_DDR_ADDRMAP(10));
+ writel(0x00000808, ctrl + K3_DDR_ADDRMAP(11));
+ writel(addrmap12, ctrl + K3_DDR_ADDRMAP(12));
+
+ return 0;
+}
+
+static int k3_lpddr5_controller_pre_train(struct k3_ddr *ddr, unsigned int channel)
+{
+ void __iomem *ctrl = ddr->ctrl[channel];
+ int ret;
+
+ writel(0x00000002, ctrl + K3_DDR_OPCTRL1);
+ writel(0xc0020002, ctrl + K3_DDR_INITTMG0);
+ writel(0x00000811, ctrl + K3_DDR_PWRCTL);
+ writel(0x00000800, ctrl + K3_DDR_PWRCTL);
+ writel(0x00000001, ctrl + K3_DDR_RFSHCTL0);
+
+ setbits_le32(ddr->cfg[channel] + K3_DDR_CFG_CLK_CTRL, BIT(22));
+ setbits_le32(ddr->cfg[channel] + K3_DDR_CFG_CLK_CTRL, BIT(1));
+
+ writel(0x80000000, ctrl + K3_DDR_ZQCTL0);
+ writel(0xc000012c, ctrl + 0x000005b4);
+
+ k3_ddr_start_sw_done(ddr, channel);
+ writel(0x00000001, ctrl + K3_DDR_ZQCTL2);
+ ret = k3_ddr_wait_sw_done_ack(ddr, channel);
+ if (ret)
+ return ret;
+
+ k3_ddr_start_sw_done(ddr, channel);
+ writel(0x00010014, ctrl + K3_DDR_DFIMISC);
+ ret = k3_ddr_wait_sw_done_ack(ddr, channel);
+ if (ret)
+ return ret;
+
+ writel(0x00000000, ctrl + K3_DDR_RFSHCTL0);
+
+ return 0;
+}
+
+static int k3_lpddr5_ctrl_init(struct k3_ddr *ddr, unsigned int channel)
+{
+ int ret;
+
+ ret = k3_ddr_clock_init(ddr, channel);
+ if (ret)
+ return ret;
+
+ k3_lpddr5_configure_controller(ddr, channel);
+ k3_lpddr5_configure_parameters(ddr, channel);
+ k3_lpddr5_configure_ports(ddr, channel);
+ k3_ddr_configure_sar(ddr, channel);
+
+ ret = k3_lpddr5_configure_addrmap(ddr, channel);
+ if (ret)
+ return ret;
+
+ return k3_lpddr5_controller_pre_train(ddr, channel);
+}
+
+static u16 k3_lpddr5_phy_io_value(bool x8, u32 csr, u16 value)
+{
+ const struct k3_ddr_io_para *io = &k3_ddr_lpddr5_io_para;
+ u32 reg_offset = csr & 0xfff;
+ u32 reg_base = csr & ~0xfff;
+
+ if (reg_base >= 0x10000 && reg_base <= 0x13000) {
+ switch (reg_offset) {
+ case 0x40:
+ case 0x42:
+ case 0x43:
+ case 0x44:
+ case 0x45:
+ return io->write_ds | (io->write_ds << 8);
+ }
+ }
+
+ if ((reg_base == 0x30000 || reg_base == 0x31000) &&
+ reg_offset >= 0x40 && reg_offset <= 0x43)
+ return io->write_ds | (io->write_ds << 8);
+
+ if (reg_base >= 0x10000 && reg_base <= 0x13000) {
+ switch (reg_offset) {
+ case 0x48:
+ case 0x4a:
+ case 0x4b:
+ case 0x4c:
+ case 0x4d:
+ return io->rx_odt << 8;
+ }
+ }
+
+ if (csr == K3_PHY_MB_MR3 || csr == K3_PHY_MB_MR3 + 1)
+ return io->pdds | (io->pdds << 8);
+
+ if (csr == K3_PHY_MB_MR11 || csr == K3_PHY_MB_MR11 + 1) {
+ value = io->dq_odt | (io->ca_odt << 4);
+ value |= (io->nt_odt != K3_DDR_R_OFF) << 3;
+ return value | (value << 8);
+ }
+
+ if (csr == K3_PHY_MB_MR17 || csr == K3_PHY_MB_MR17 + 1) {
+ value = BIT(3) | BIT(5);
+ value |= io->soc_odt | (io->soc_odt << 8);
+ value |= (x8 << 7) | (x8 << 15);
+ return value;
+ }
+
+ if (csr == K3_PHY_MB_MR41 || csr == K3_PHY_MB_MR41 + 1) {
+ value = io->nt_odt << 5;
+ return value | (value << 8);
+ }
+
+ /* Always enable 2D training (0) for supported LPDDR5 profiles. */
+ if (csr == K3_PHY_MB_DISABLE_2D)
+ return 0;
+
+ return value;
+}
+
+static void k3_lpddr5_phy_write_cfg(struct k3_ddr *ddr, unsigned int channel,
+ const struct k3_ddr_phy_table *table,
+ const struct k3_ddr_phy_overrides *overrides)
+{
+ const struct k3_ddr_phy_override *regs = overrides->regs;
+ bool x8 = ddr->profile->device_width == 8;
+ const struct k3_ddr_phy_cfg *cfg;
+ const u16 *values;
+ u32 base, csr;
+ int i, j, k;
+ int count;
+ u16 value;
+
+ for (i = 0; i < table->count; i++) {
+ cfg = &table->cfg[i];
+ base = FIELD_GET(K3_DDR_PHY_CFG_ADDR, cfg->opaddr);
+
+ if (FIELD_GET(K3_DDR_PHY_CFG_OP, cfg->opaddr) == K3_DDR_PHY_CFG_RANGE) {
+ values = cfg->range.values;
+ count = cfg->range.count;
+ } else {
+ values = &cfg->value;
+ count = 1;
+ }
+
+ for (j = 0; j < count; j++) {
+ value = values[j];
+ csr = base + j;
+
+ for (k = 0; k < overrides->count; k++) {
+ if (regs[k].csr == csr)
+ break;
+ }
+
+ if (k < overrides->count) {
+ if (regs[k].flags & K3_DDR_PHY_SKIP)
+ continue;
+
+ value = regs[k].value;
+ }
+
+ value = k3_lpddr5_phy_io_value(x8, csr, value);
+
+ k3_phy_write(ddr, channel, csr, value);
+ }
+ }
+}
+
+static int k3_lpddr5_phy_train(struct k3_ddr *ddr, unsigned int channel)
+{
+ const struct k3_ddr_profile *profile = ddr->profile;
+ struct k3_ddr_phy_overrides post = {};
+ struct k3_ddr_phy_overrides pre = {};
+ int ret;
+
+ if (profile->device_width == 16) {
+ if (profile->ranks == 1) {
+ pre = k3_ddr_lpddr5_pre_srank_x16_overrides;
+ post = k3_ddr_lpddr5_post_srank_x16_overrides;
+ } else {
+ pre = k3_ddr_lpddr5_pre_drank_x16_overrides;
+ post = k3_ddr_lpddr5_post_drank_x16_overrides;
+ }
+ }
+
+ k3_lpddr5_phy_write_cfg(ddr, channel, &k3_ddr_lpddr5_phy_init_table, &pre);
+
+ ret = k3_ddr_phy_load_imem(ddr, channel);
+ if (ret)
+ return ret;
+
+ k3_ddr_phy_zero_dmem(ddr, channel);
+ k3_lpddr5_phy_write_cfg(ddr, channel, &k3_ddr_lpddr5_pre_train_table, &pre);
+
+ setbits_le32(ddr->ctrl[channel] + K3_DDR_PWRCTL, BIT(11));
+
+ k3_ddr_phy_start_pmu(ddr, channel);
+ ret = k3_ddr_phy_wait_training(ddr, channel);
+ k3_ddr_phy_halt_pmu(ddr, channel);
+ if (ret)
+ return ret;
+
+ k3_lpddr5_phy_write_cfg(ddr, channel, &k3_ddr_lpddr5_post_train_table, &post);
+
+ return 0;
+}
+
+static int k3_lpddr5_ctrl_enable(struct k3_ddr *ddr, unsigned int channel)
+{
+ void __iomem *ctrl = ddr->ctrl[channel];
+ int port, ret;
+ u32 value;
+
+ k3_ddr_start_sw_done(ddr, channel);
+ writel(0x00010034, ctrl + K3_DDR_DFIMISC);
+ ret = k3_ddr_wait_sw_done_ack(ddr, channel);
+ if (ret)
+ return ret;
+
+ ret = readl_poll_timeout(ctrl + K3_DDR_DFISTAT, value, value & BIT(0),
+ K3_DDR_REG_TIMEOUT_US);
+ if (ret)
+ return ret;
+
+ k3_ddr_start_sw_done(ddr, channel);
+ writel(0x00010015, ctrl + K3_DDR_DFIMISC);
+ ret = k3_ddr_wait_sw_done_ack(ddr, channel);
+ if (ret)
+ return ret;
+
+ writel(0, ctrl + K3_DDR_PWRCTL);
+
+ ret = readl_poll_timeout(ctrl + K3_DDR_STAT, value, (value & GENMASK(1, 0)) == 1,
+ K3_DDR_REG_TIMEOUT_US);
+ if (ret)
+ return ret;
+
+ k3_ddr_start_sw_done(ddr, channel);
+ writel(0xc0000000, ctrl + K3_DDR_DFIUPD0);
+ ret = k3_ddr_wait_sw_done_ack(ddr, channel);
+ if (ret)
+ return ret;
+
+ writel(0, ctrl + K3_DDR_ZQCTL0);
+
+ k3_ddr_start_sw_done(ddr, channel);
+ writel(0, ctrl + K3_DDR_ZQCTL2);
+ ret = k3_ddr_wait_sw_done_ack(ddr, channel);
+ if (ret)
+ return ret;
+
+ writel(0, ctrl + K3_DDR_RFSHCTL0);
+ writel(0x10, ctrl + K3_DDR_PWRCTL);
+ writel(0xe000012c, ctrl + 0x5b4);
+ writel(0, ctrl + K3_DDR_OPCTRL1);
+
+ for (port = 0; port < 5; port++)
+ writel(1, ctrl + 0x20090 + port * 0x1000);
+
+ return 0;
+}
+
+int k3_ddr_lpddr5_init(struct k3_ddr *ddr)
+{
+ unsigned int channel;
+ int ret;
+
+ for (channel = 0; channel < K3_DDR_NUM_CHANNELS; channel++) {
+ ret = k3_lpddr5_ctrl_init(ddr, channel);
+ if (ret) {
+ dev_err(ddr->dev, "channel %u controller init failed: %d\n", channel, ret);
+ return ret;
+ }
+
+ ret = k3_lpddr5_phy_train(ddr, channel);
+ if (ret) {
+ dev_err(ddr->dev, "channel %u PHY training failed: %d\n", channel, ret);
+ return ret;
+ }
+
+ ret = k3_lpddr5_ctrl_enable(ddr, channel);
+ if (ret) {
+ dev_err(ddr->dev, "channel %u controller enable failed: %d\n",
+ channel, ret);
+ return ret;
+ }
+ }
+
+ return 0;
+}
diff --git a/drivers/ram/spacemit/k3/k3_ddr_lpddr5_tables.c b/drivers/ram/spacemit/k3/k3_ddr_lpddr5_tables.c
new file mode 100644
index 00000000000..b096c7050d0
--- /dev/null
+++ b/drivers/ram/spacemit/k3/k3_ddr_lpddr5_tables.c
@@ -0,0 +1,1668 @@
+// SPDX-License-Identifier: GPL-2.0-or-later
+/*
+ * Copyright (C) 2025 SpacemiT
+ * Copyright (C) 2026 Junhui Liu <junhui.liu@pigmoral.tech>
+ */
+
+#include <linux/kernel.h>
+
+#include "k3_ddr.h"
+
+static const struct k3_ddr_phy_cfg lp5_phy_init_cfg[] = {
+ K3_DDR_PHY_WRITE_SINGLE(0x20060, 0x0002),
+ K3_DDR_PHY_WRITE_SINGLE(0x200a5, 0x0001),
+ K3_DDR_PHY_WRITE_SINGLE(0xd0036, 0x0000),
+ K3_DDR_PHY_WRITE_SINGLE(0x200bd, 0x00ff),
+ K3_DDR_PHY_WRITE_SINGLE(0x20300, 0x0808),
+ K3_DDR_PHY_WRITE_SINGLE(0x20303, 0x0009),
+ K3_DDR_PHY_WRITE_SINGLE(0x20302, 0x0026),
+ K3_DDR_PHY_WRITE_SINGLE(0x20328, 0x0000),
+ K3_DDR_PHY_WRITE_SINGLE(0x20301, 0x0003),
+ K3_DDR_PHY_WRITE_SINGLE(0x2030b, 0x0000),
+ K3_DDR_PHY_WRITE_SINGLE(0x300a7, 0x0000),
+ K3_DDR_PHY_WRITE_SINGLE(0x310a7, 0x0000),
+ K3_DDR_PHY_WRITE_SINGLE(0x300ae, 0x0080),
+ K3_DDR_PHY_WRITE_SINGLE(0x300ad, 0x0080),
+ K3_DDR_PHY_WRITE_SINGLE(0x300ac, 0x0080),
+ K3_DDR_PHY_WRITE_SINGLE(0x310ae, 0x0080),
+ K3_DDR_PHY_WRITE_SINGLE(0x310ad, 0x0080),
+ K3_DDR_PHY_WRITE_SINGLE(0x310ac, 0x0080),
+ K3_DDR_PHY_WRITE_SINGLE(0xc0086, 0x0001),
+ K3_DDR_PHY_WRITE_SINGLE(0x2011b, 0x0000),
+ K3_DDR_PHY_WRITE_SINGLE(0x100a3, 0x0b33),
+ K3_DDR_PHY_WRITE_SINGLE(0x110a3, 0x0b33),
+ K3_DDR_PHY_WRITE_SINGLE(0x120a3, 0x0b33),
+ K3_DDR_PHY_WRITE_SINGLE(0x130a3, 0x0b33),
+ K3_DDR_PHY_WRITE_SINGLE(0xc00f1, 0x6000),
+ K3_DDR_PHY_WRITE_SINGLE(0xc00f2, 0x00a9),
+ K3_DDR_PHY_WRITE_SINGLE(0xc00f3, 0x8000),
+ K3_DDR_PHY_WRITE_SINGLE(0xc00f4, 0x0005),
+ K3_DDR_PHY_WRITE_SINGLE(0xc00f5, 0x4000),
+ K3_DDR_PHY_WRITE_SINGLE(0xc00f6, 0x0002),
+ K3_DDR_PHY_WRITE_SINGLE(0xc00f7, 0xf000),
+ K3_DDR_PHY_WRITE_SINGLE(0xc00f9, 0x6000),
+ K3_DDR_PHY_WRITE_SINGLE(0xc00fa, 0x00a9),
+ K3_DDR_PHY_WRITE_SINGLE(0xc00fb, 0x8000),
+ K3_DDR_PHY_WRITE_SINGLE(0xc00fd, 0x4000),
+ K3_DDR_PHY_WRITE_SINGLE(0xc00ff, 0xf000),
+ K3_DDR_PHY_WRITE_SINGLE(0x908ff, 0x000f),
+ K3_DDR_PHY_WRITE_SINGLE(0x10093, 0x0000),
+ K3_DDR_PHY_WRITE_SINGLE(0x11093, 0x0000),
+ K3_DDR_PHY_WRITE_SINGLE(0x12093, 0x0000),
+ K3_DDR_PHY_WRITE_SINGLE(0x13093, 0x0000),
+ K3_DDR_PHY_WRITE_SINGLE(0x20051, 0x0003),
+};
+
+const struct k3_ddr_phy_table k3_ddr_lpddr5_phy_init_table = {
+ .cfg = lp5_phy_init_cfg,
+ .count = ARRAY_SIZE(lp5_phy_init_cfg),
+};
+
+static const u16 lp5_pre_training_table_54[] = {
+ 0x0100, 0x0000, 0x0030, 0x1900, 0x0004, 0x0004, 0x0000, 0x0000,
+ 0x125f, 0x0004, 0x0000, 0x0001, 0x0000, 0x8b00, 0x000f, 0x0000,
+ 0x0000, 0x0000, 0x0310, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000,
+ 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x1000,
+ 0x0003, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000,
+ 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0xb0b0, 0xb0b0, 0xbbbb,
+ 0xbbbb, 0x0606, 0x0606, 0x5858, 0x5858, 0x3434, 0x3434, 0x2727,
+ 0x2727, 0x0000, 0x0000, 0x2828, 0x2828, 0x2828, 0x2828, 0x0000,
+ 0x0000, 0x2e2e, 0x2e2e, 0x0d0d, 0x0d0d, 0x0000, 0x0000, 0x0202,
+ 0x0202, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000,
+ 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000,
+ 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000,
+ 0x0000, 0x4040, 0x4040, 0x4040, 0x4040, 0x0000, 0x0000, 0x0000,
+ 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000,
+ 0x0000, 0x0000, 0x0000, 0x0000, 0x002e, 0x0050, 0x0000, 0x0000,
+ 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000,
+ 0x0001, 0x4b00, 0x0043, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000,
+ 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000,
+ 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000,
+ 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000,
+ 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000,
+ 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000,
+ 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000,
+ 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000,
+ 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000,
+ 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000,
+ 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000,
+ 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000,
+ 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000,
+ 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000,
+ 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000,
+ 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000,
+ 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000,
+ 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000,
+ 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000,
+ 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000,
+ 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000,
+ 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000,
+ 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000,
+ 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000,
+ 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000,
+ 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000,
+ 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000,
+ 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000,
+ 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000,
+ 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000,
+ 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000,
+ 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000,
+ 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000,
+ 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000,
+ 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000,
+ 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000,
+ 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000,
+ 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000,
+ 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000,
+ 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000,
+ 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000,
+ 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000,
+ 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000,
+ 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000,
+ 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000,
+ 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000,
+ 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000,
+ 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000,
+ 0x0000, 0x0000, 0x0000, 0x0000, 0x0500, 0x0000, 0x0000, 0x0000,
+ 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000,
+ 0x0000, 0x0000, 0x6745, 0x00f2, 0x0000, 0x0000, 0x0000, 0x0000,
+ 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0004, 0x0000, 0x0000,
+ 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000,
+ 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0004, 0x0000, 0x0000,
+ 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0004, 0x0e0c, 0x180f,
+ 0x001e, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000,
+ 0x1210, 0x0201, 0x1403, 0x1c0a, 0x2e29, 0x0b11, 0x150d, 0x1916,
+ 0x0e0c, 0x180f, 0x131e, 0x0000, 0x0000, 0x0003, 0x0000, 0x0001,
+ 0x0000, 0x0002, 0x0000, 0x0009, 0x0006, 0x0008, 0x0002, 0x0005,
+ 0x0024, 0x0010, 0x0026, 0x0012, 0x004e, 0x0050, 0x0012, 0x0186,
+ 0x0187, 0x000a, 0x0017, 0x0015, 0x004e, 0x000d, 0x006e, 0x0002,
+ 0x0001, 0x0060, 0x0007, 0x0000, 0x0011, 0x0007, 0x0000, 0x005a,
+ 0x002a, 0x0060, 0x005e, 0x0028, 0x005c, 0x0062, 0x0020, 0x0064,
+ 0x0066, 0x000c, 0x00d9, 0x00af, 0x00ad, 0x0000, 0x0015, 0x0016,
+ 0x00d0, 0x00d1, 0x00d2, 0x00d3, 0x00d4, 0x0005, 0x000b, 0x0007,
+ 0x0028, 0x0215, 0x000a, 0x0085, 0x0004, 0x0004, 0x0001, 0x0001,
+ 0x0001, 0x0003, 0x0004, 0x0215, 0x042b, 0x0085, 0x010b, 0x0004,
+ 0x0006, 0x0000, 0x0002, 0x0002, 0x0003, 0x0005, 0x042b, 0x0640,
+ 0x010b, 0x0190, 0x0006, 0x0008, 0x0001, 0x0003, 0x0002, 0x0004,
+ 0x0006, 0x0640, 0x0855, 0x0190, 0x0215, 0x0008, 0x000a, 0x0002,
+ 0x0004, 0x0003, 0x0004, 0x0007, 0x0855, 0x0abe, 0x0215, 0x02b0,
+ 0x0008, 0x000e, 0x0001, 0x0007, 0x0004, 0x0004, 0x0008, 0x0abe,
+ 0x0c80, 0x02b0, 0x0320, 0x000a, 0x0010, 0x0003, 0x0009, 0x0004,
+ 0x0004, 0x0008, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000,
+ 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000,
+ 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000,
+ 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000,
+ 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000,
+ 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000,
+ 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000,
+ 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000,
+ 0x0000, 0x0000, 0x0000, 0x0000, 0x0028, 0x0215, 0x0005, 0x0043,
+ 0x0002, 0x0002, 0x0000, 0x0000, 0x0001, 0x0002, 0x0003, 0x0215,
+ 0x042b, 0x0043, 0x0085, 0x0002, 0x0003, 0x0000, 0x0001, 0x0001,
+ 0x0002, 0x0003, 0x042b, 0x0640, 0x0085, 0x00c8, 0x0003, 0x0004,
+ 0x0001, 0x0002, 0x0001, 0x0002, 0x0003, 0x0640, 0x0855, 0x00c8,
+ 0x010b, 0x0004, 0x0005, 0x0001, 0x0002, 0x0002, 0x0002, 0x0004,
+ 0x0855, 0x0abe, 0x010b, 0x0158, 0x0004, 0x0007, 0x0001, 0x0004,
+ 0x0002, 0x0002, 0x0004, 0x0abe, 0x0c80, 0x0158, 0x0190, 0x0005,
+ 0x0008, 0x0002, 0x0005, 0x0002, 0x0002, 0x0004, 0x0c80, 0x0e95,
+ 0x0190, 0x01d3, 0x0006, 0x0009, 0x0002, 0x0005, 0x0003, 0x0002,
+ 0x0005, 0x0e95, 0x10ab, 0x01d3, 0x0215, 0x0006, 0x000b, 0x0002,
+ 0x0007, 0x0003, 0x0002, 0x0005, 0x10ab, 0x12c0, 0x0215, 0x0258,
+ 0x0007, 0x000c, 0x0003, 0x0008, 0x0003, 0x0002, 0x0005, 0x12c0,
+ 0x157c, 0x0258, 0x02b0, 0x0008, 0x000e, 0x0003, 0x0009, 0x0004,
+ 0x0002, 0x0006, 0x157c, 0x1770, 0x02b0, 0x02ee, 0x0009, 0x000f,
+ 0x0004, 0x000a, 0x0004, 0x0002, 0x0006, 0x1770, 0x1900, 0x02ee,
+ 0x0320, 0x0009, 0x0010, 0x0004, 0x000b, 0x0004, 0x0002, 0x0006,
+ 0x0028, 0x0215, 0x000a, 0x0085, 0x0006, 0x0006, 0x0006, 0x0000,
+ 0x0000, 0x0000, 0x0001, 0x0006, 0x0007, 0x0215, 0x042b, 0x0085,
+ 0x010b, 0x0008, 0x0008, 0x0008, 0x0000, 0x0000, 0x0000, 0x0002,
+ 0x0007, 0x0009, 0x042b, 0x0640, 0x010b, 0x0190, 0x000a, 0x000a,
+ 0x000c, 0x0001, 0x0001, 0x0003, 0x0002, 0x0008, 0x000a, 0x0640,
+ 0x0855, 0x0190, 0x0215, 0x000c, 0x000e, 0x000e, 0x0002, 0x0004,
+ 0x0004, 0x0003, 0x0008, 0x000b, 0x0855, 0x0abe, 0x0215, 0x02b0,
+ 0x0010, 0x0010, 0x0012, 0x0003, 0x0003, 0x0005, 0x0004, 0x000a,
+ 0x000e, 0x0abe, 0x0c80, 0x02b0, 0x0320, 0x0012, 0x0014, 0x0014,
+ 0x0005, 0x0007, 0x0007, 0x0004, 0x000a, 0x000e, 0x0000, 0x0000,
+ 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000,
+ 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000,
+ 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000,
+ 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000,
+ 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000,
+ 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000,
+ 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000,
+ 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000,
+ 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000,
+ 0x0000, 0x0000, 0x0000, 0x0000, 0x0028, 0x0215, 0x0005, 0x0043,
+ 0x0003, 0x0003, 0x0003, 0x0000, 0x0000, 0x0000, 0x0001, 0x0003,
+ 0x0004, 0x0215, 0x042b, 0x0043, 0x0085, 0x0004, 0x0004, 0x0004,
+ 0x0000, 0x0000, 0x0000, 0x0001, 0x0004, 0x0005, 0x042b, 0x0640,
+ 0x0085, 0x00c8, 0x0005, 0x0005, 0x0005, 0x0001, 0x0001, 0x0002,
+ 0x0001, 0x0004, 0x0005, 0x0640, 0x0855, 0x00c8, 0x010b, 0x0006,
+ 0x0007, 0x0007, 0x0001, 0x0002, 0x0002, 0x0002, 0x0004, 0x0006,
+ 0x0855, 0x0abe, 0x010b, 0x0158, 0x0008, 0x0008, 0x0009, 0x0002,
+ 0x0002, 0x0003, 0x0002, 0x0005, 0x0007, 0x0abe, 0x0c80, 0x0158,
+ 0x0190, 0x0009, 0x000a, 0x000a, 0x0003, 0x0004, 0x0004, 0x0002,
+ 0x0005, 0x0007, 0x0c80, 0x0e95, 0x0190, 0x01d3, 0x000a, 0x000b,
+ 0x000c, 0x0003, 0x0004, 0x0005, 0x0003, 0x0005, 0x0008, 0x0e95,
+ 0x10ab, 0x01d3, 0x0215, 0x000c, 0x000d, 0x000e, 0x0004, 0x0005,
+ 0x0006, 0x0003, 0x0006, 0x0009, 0x10ab, 0x12c0, 0x0215, 0x0258,
+ 0x000d, 0x000e, 0x000f, 0x0005, 0x0006, 0x0007, 0x0003, 0x0006,
+ 0x0009, 0x12c0, 0x157c, 0x0258, 0x02b0, 0x000f, 0x0010, 0x0011,
+ 0x0006, 0x0007, 0x0008, 0x0004, 0x0006, 0x000a, 0x157c, 0x1770,
+ 0x02b0, 0x02ee, 0x0010, 0x0011, 0x0013, 0x0006, 0x0007, 0x0009,
+ 0x0004, 0x0007, 0x000b, 0x1770, 0x1900, 0x02ee, 0x0320, 0x0011,
+ 0x0012, 0x0014, 0x0007, 0x0008, 0x000a, 0x0004, 0x0007, 0x000b,
+ 0x0607, 0x0405, 0x0203, 0x0001, 0x0a09, 0x0c0b, 0x0e0d, 0x000f,
+ 0x008b, 0x0001,
+};
+
+static const struct k3_ddr_phy_cfg lp5_pre_train_cfg[] = {
+ K3_DDR_PHY_WRITE_SINGLE(0x90802, 0x0001),
+ K3_DDR_PHY_WRITE_SINGLE(0x2004c, 0x2e8f),
+ K3_DDR_PHY_WRITE_SINGLE(0x2004d, 0x0000),
+ K3_DDR_PHY_WRITE_SINGLE(0x20002, 0x0002),
+ K3_DDR_PHY_WRITE_SINGLE(0x20000, 0x0002),
+ K3_DDR_PHY_WRITE_SINGLE(0x90801, 0x004d),
+ K3_DDR_PHY_WRITE_SINGLE(0x90809, 0x7000),
+ K3_DDR_PHY_WRITE_SINGLE(0x1005e, 0x0366),
+ K3_DDR_PHY_WRITE_SINGLE(0x10060, 0x0366),
+ K3_DDR_PHY_WRITE_SINGLE(0x10062, 0x0366),
+ K3_DDR_PHY_WRITE_SINGLE(0x10064, 0x0366),
+ K3_DDR_PHY_WRITE_SINGLE(0x1005f, 0x0366),
+ K3_DDR_PHY_WRITE_SINGLE(0x10061, 0x0366),
+ K3_DDR_PHY_WRITE_SINGLE(0x10063, 0x0366),
+ K3_DDR_PHY_WRITE_SINGLE(0x10065, 0x0366),
+ K3_DDR_PHY_WRITE_SINGLE(0x1105e, 0x0366),
+ K3_DDR_PHY_WRITE_SINGLE(0x11060, 0x0366),
+ K3_DDR_PHY_WRITE_SINGLE(0x11062, 0x0366),
+ K3_DDR_PHY_WRITE_SINGLE(0x11064, 0x0366),
+ K3_DDR_PHY_WRITE_SINGLE(0x1105f, 0x0366),
+ K3_DDR_PHY_WRITE_SINGLE(0x11061, 0x0366),
+ K3_DDR_PHY_WRITE_SINGLE(0x11063, 0x0366),
+ K3_DDR_PHY_WRITE_SINGLE(0x11065, 0x0366),
+ K3_DDR_PHY_WRITE_SINGLE(0x1205e, 0x0366),
+ K3_DDR_PHY_WRITE_SINGLE(0x12060, 0x0366),
+ K3_DDR_PHY_WRITE_SINGLE(0x12062, 0x0366),
+ K3_DDR_PHY_WRITE_SINGLE(0x12064, 0x0366),
+ K3_DDR_PHY_WRITE_SINGLE(0x1205f, 0x0366),
+ K3_DDR_PHY_WRITE_SINGLE(0x12061, 0x0366),
+ K3_DDR_PHY_WRITE_SINGLE(0x12063, 0x0366),
+ K3_DDR_PHY_WRITE_SINGLE(0x12065, 0x0366),
+ K3_DDR_PHY_WRITE_SINGLE(0x1305e, 0x0366),
+ K3_DDR_PHY_WRITE_SINGLE(0x13060, 0x0366),
+ K3_DDR_PHY_WRITE_SINGLE(0x13062, 0x0366),
+ K3_DDR_PHY_WRITE_SINGLE(0x13064, 0x0366),
+ K3_DDR_PHY_WRITE_SINGLE(0x1305f, 0x0366),
+ K3_DDR_PHY_WRITE_SINGLE(0x13061, 0x0366),
+ K3_DDR_PHY_WRITE_SINGLE(0x13063, 0x0366),
+ K3_DDR_PHY_WRITE_SINGLE(0x13065, 0x0366),
+ K3_DDR_PHY_WRITE_SINGLE(0x10005, 0x0000),
+ K3_DDR_PHY_WRITE_SINGLE(0x1000b, 0x0000),
+ K3_DDR_PHY_WRITE_SINGLE(0x11005, 0x0000),
+ K3_DDR_PHY_WRITE_SINGLE(0x1100b, 0x0000),
+ K3_DDR_PHY_WRITE_SINGLE(0x12005, 0x0000),
+ K3_DDR_PHY_WRITE_SINGLE(0x1200b, 0x0000),
+ K3_DDR_PHY_WRITE_SINGLE(0x13005, 0x0000),
+ K3_DDR_PHY_WRITE_SINGLE(0x1300b, 0x0000),
+ K3_DDR_PHY_WRITE_SINGLE(0x20007, 0x0000),
+ K3_DDR_PHY_WRITE_SINGLE(0x20013, 0x002c),
+ K3_DDR_PHY_WRITE_SINGLE(0x30038, 0x0003),
+ K3_DDR_PHY_WRITE_SINGLE(0x30039, 0x0003),
+ K3_DDR_PHY_WRITE_SINGLE(0x3003a, 0x0003),
+ K3_DDR_PHY_WRITE_SINGLE(0x31038, 0x0003),
+ K3_DDR_PHY_WRITE_SINGLE(0x31039, 0x0003),
+ K3_DDR_PHY_WRITE_SINGLE(0x3103a, 0x0003),
+ K3_DDR_PHY_WRITE_SINGLE(0x10038, 0x0003),
+ K3_DDR_PHY_WRITE_SINGLE(0x1003a, 0x0003),
+ K3_DDR_PHY_WRITE_SINGLE(0x11038, 0x0003),
+ K3_DDR_PHY_WRITE_SINGLE(0x1103a, 0x0003),
+ K3_DDR_PHY_WRITE_SINGLE(0x12038, 0x0003),
+ K3_DDR_PHY_WRITE_SINGLE(0x1203a, 0x0003),
+ K3_DDR_PHY_WRITE_SINGLE(0x13038, 0x0003),
+ K3_DDR_PHY_WRITE_SINGLE(0x1303a, 0x0003),
+ K3_DDR_PHY_WRITE_SINGLE(0x1003b, 0x0003),
+ K3_DDR_PHY_WRITE_SINGLE(0x1103b, 0x0003),
+ K3_DDR_PHY_WRITE_SINGLE(0x1203b, 0x0003),
+ K3_DDR_PHY_WRITE_SINGLE(0x1303b, 0x0003),
+ K3_DDR_PHY_WRITE_SINGLE(0x10009, 0x0000),
+ K3_DDR_PHY_WRITE_SINGLE(0x10037, 0x0000),
+ K3_DDR_PHY_WRITE_SINGLE(0x11009, 0x0000),
+ K3_DDR_PHY_WRITE_SINGLE(0x11037, 0x0000),
+ K3_DDR_PHY_WRITE_SINGLE(0x12009, 0x0000),
+ K3_DDR_PHY_WRITE_SINGLE(0x12037, 0x0000),
+ K3_DDR_PHY_WRITE_SINGLE(0x13009, 0x0000),
+ K3_DDR_PHY_WRITE_SINGLE(0x13037, 0x0000),
+ K3_DDR_PHY_WRITE_SINGLE(0x10004, 0x0000),
+ K3_DDR_PHY_WRITE_SINGLE(0x10003, 0x0000),
+ K3_DDR_PHY_WRITE_SINGLE(0x11004, 0x0000),
+ K3_DDR_PHY_WRITE_SINGLE(0x11003, 0x0000),
+ K3_DDR_PHY_WRITE_SINGLE(0x12004, 0x0000),
+ K3_DDR_PHY_WRITE_SINGLE(0x12003, 0x0000),
+ K3_DDR_PHY_WRITE_SINGLE(0x13004, 0x0000),
+ K3_DDR_PHY_WRITE_SINGLE(0x13003, 0x0000),
+ K3_DDR_PHY_WRITE_SINGLE(0x20004, 0x0320),
+ K3_DDR_PHY_WRITE_SINGLE(0x30050, 0x0035),
+ K3_DDR_PHY_WRITE_SINGLE(0x30051, 0x0035),
+ K3_DDR_PHY_WRITE_SINGLE(0x30052, 0x0035),
+ K3_DDR_PHY_WRITE_SINGLE(0x30053, 0x0035),
+ K3_DDR_PHY_WRITE_SINGLE(0x31050, 0x0035),
+ K3_DDR_PHY_WRITE_SINGLE(0x31051, 0x0035),
+ K3_DDR_PHY_WRITE_SINGLE(0x31052, 0x0035),
+ K3_DDR_PHY_WRITE_SINGLE(0x31053, 0x0035),
+ K3_DDR_PHY_WRITE_SINGLE(0x1004e, 0x0035),
+ K3_DDR_PHY_WRITE_SINGLE(0x1004f, 0x0035),
+ K3_DDR_PHY_WRITE_SINGLE(0x10050, 0x0035),
+ K3_DDR_PHY_WRITE_SINGLE(0x10051, 0x0035),
+ K3_DDR_PHY_WRITE_SINGLE(0x1014e, 0x0035),
+ K3_DDR_PHY_WRITE_SINGLE(0x1014f, 0x0035),
+ K3_DDR_PHY_WRITE_SINGLE(0x10150, 0x0035),
+ K3_DDR_PHY_WRITE_SINGLE(0x10151, 0x0035),
+ K3_DDR_PHY_WRITE_SINGLE(0x1024e, 0x0035),
+ K3_DDR_PHY_WRITE_SINGLE(0x1024f, 0x0035),
+ K3_DDR_PHY_WRITE_SINGLE(0x10250, 0x0035),
+ K3_DDR_PHY_WRITE_SINGLE(0x10251, 0x0035),
+ K3_DDR_PHY_WRITE_SINGLE(0x1034e, 0x0035),
+ K3_DDR_PHY_WRITE_SINGLE(0x1034f, 0x0035),
+ K3_DDR_PHY_WRITE_SINGLE(0x10350, 0x0035),
+ K3_DDR_PHY_WRITE_SINGLE(0x10351, 0x0035),
+ K3_DDR_PHY_WRITE_SINGLE(0x1044e, 0x0035),
+ K3_DDR_PHY_WRITE_SINGLE(0x1044f, 0x0035),
+ K3_DDR_PHY_WRITE_SINGLE(0x10450, 0x0035),
+ K3_DDR_PHY_WRITE_SINGLE(0x10451, 0x0035),
+ K3_DDR_PHY_WRITE_SINGLE(0x1054e, 0x0035),
+ K3_DDR_PHY_WRITE_SINGLE(0x1054f, 0x0035),
+ K3_DDR_PHY_WRITE_SINGLE(0x10550, 0x0035),
+ K3_DDR_PHY_WRITE_SINGLE(0x10551, 0x0035),
+ K3_DDR_PHY_WRITE_SINGLE(0x1064e, 0x0035),
+ K3_DDR_PHY_WRITE_SINGLE(0x1064f, 0x0035),
+ K3_DDR_PHY_WRITE_SINGLE(0x10650, 0x0035),
+ K3_DDR_PHY_WRITE_SINGLE(0x10651, 0x0035),
+ K3_DDR_PHY_WRITE_SINGLE(0x1074e, 0x0035),
+ K3_DDR_PHY_WRITE_SINGLE(0x1074f, 0x0035),
+ K3_DDR_PHY_WRITE_SINGLE(0x10750, 0x0035),
+ K3_DDR_PHY_WRITE_SINGLE(0x10751, 0x0035),
+ K3_DDR_PHY_WRITE_SINGLE(0x1084e, 0x0035),
+ K3_DDR_PHY_WRITE_SINGLE(0x1084f, 0x0035),
+ K3_DDR_PHY_WRITE_SINGLE(0x10850, 0x0035),
+ K3_DDR_PHY_WRITE_SINGLE(0x10851, 0x0035),
+ K3_DDR_PHY_WRITE_SINGLE(0x1104e, 0x0035),
+ K3_DDR_PHY_WRITE_SINGLE(0x1104f, 0x0035),
+ K3_DDR_PHY_WRITE_SINGLE(0x11050, 0x0035),
+ K3_DDR_PHY_WRITE_SINGLE(0x11051, 0x0035),
+ K3_DDR_PHY_WRITE_SINGLE(0x1114e, 0x0035),
+ K3_DDR_PHY_WRITE_SINGLE(0x1114f, 0x0035),
+ K3_DDR_PHY_WRITE_SINGLE(0x11150, 0x0035),
+ K3_DDR_PHY_WRITE_SINGLE(0x11151, 0x0035),
+ K3_DDR_PHY_WRITE_SINGLE(0x1124e, 0x0035),
+ K3_DDR_PHY_WRITE_SINGLE(0x1124f, 0x0035),
+ K3_DDR_PHY_WRITE_SINGLE(0x11250, 0x0035),
+ K3_DDR_PHY_WRITE_SINGLE(0x11251, 0x0035),
+ K3_DDR_PHY_WRITE_SINGLE(0x1134e, 0x0035),
+ K3_DDR_PHY_WRITE_SINGLE(0x1134f, 0x0035),
+ K3_DDR_PHY_WRITE_SINGLE(0x11350, 0x0035),
+ K3_DDR_PHY_WRITE_SINGLE(0x11351, 0x0035),
+ K3_DDR_PHY_WRITE_SINGLE(0x1144e, 0x0035),
+ K3_DDR_PHY_WRITE_SINGLE(0x1144f, 0x0035),
+ K3_DDR_PHY_WRITE_SINGLE(0x11450, 0x0035),
+ K3_DDR_PHY_WRITE_SINGLE(0x11451, 0x0035),
+ K3_DDR_PHY_WRITE_SINGLE(0x1154e, 0x0035),
+ K3_DDR_PHY_WRITE_SINGLE(0x1154f, 0x0035),
+ K3_DDR_PHY_WRITE_SINGLE(0x11550, 0x0035),
+ K3_DDR_PHY_WRITE_SINGLE(0x11551, 0x0035),
+ K3_DDR_PHY_WRITE_SINGLE(0x1164e, 0x0035),
+ K3_DDR_PHY_WRITE_SINGLE(0x1164f, 0x0035),
+ K3_DDR_PHY_WRITE_SINGLE(0x11650, 0x0035),
+ K3_DDR_PHY_WRITE_SINGLE(0x11651, 0x0035),
+ K3_DDR_PHY_WRITE_SINGLE(0x1174e, 0x0035),
+ K3_DDR_PHY_WRITE_SINGLE(0x1174f, 0x0035),
+ K3_DDR_PHY_WRITE_SINGLE(0x11750, 0x0035),
+ K3_DDR_PHY_WRITE_SINGLE(0x11751, 0x0035),
+ K3_DDR_PHY_WRITE_SINGLE(0x1184e, 0x0035),
+ K3_DDR_PHY_WRITE_SINGLE(0x1184f, 0x0035),
+ K3_DDR_PHY_WRITE_SINGLE(0x11850, 0x0035),
+ K3_DDR_PHY_WRITE_SINGLE(0x11851, 0x0035),
+ K3_DDR_PHY_WRITE_SINGLE(0x1204e, 0x0035),
+ K3_DDR_PHY_WRITE_SINGLE(0x1204f, 0x0035),
+ K3_DDR_PHY_WRITE_SINGLE(0x12050, 0x0035),
+ K3_DDR_PHY_WRITE_SINGLE(0x12051, 0x0035),
+ K3_DDR_PHY_WRITE_SINGLE(0x1214e, 0x0035),
+ K3_DDR_PHY_WRITE_SINGLE(0x1214f, 0x0035),
+ K3_DDR_PHY_WRITE_SINGLE(0x12150, 0x0035),
+ K3_DDR_PHY_WRITE_SINGLE(0x12151, 0x0035),
+ K3_DDR_PHY_WRITE_SINGLE(0x1224e, 0x0035),
+ K3_DDR_PHY_WRITE_SINGLE(0x1224f, 0x0035),
+ K3_DDR_PHY_WRITE_SINGLE(0x12250, 0x0035),
+ K3_DDR_PHY_WRITE_SINGLE(0x12251, 0x0035),
+ K3_DDR_PHY_WRITE_SINGLE(0x1234e, 0x0035),
+ K3_DDR_PHY_WRITE_SINGLE(0x1234f, 0x0035),
+ K3_DDR_PHY_WRITE_SINGLE(0x12350, 0x0035),
+ K3_DDR_PHY_WRITE_SINGLE(0x12351, 0x0035),
+ K3_DDR_PHY_WRITE_SINGLE(0x1244e, 0x0035),
+ K3_DDR_PHY_WRITE_SINGLE(0x1244f, 0x0035),
+ K3_DDR_PHY_WRITE_SINGLE(0x12450, 0x0035),
+ K3_DDR_PHY_WRITE_SINGLE(0x12451, 0x0035),
+ K3_DDR_PHY_WRITE_SINGLE(0x1254e, 0x0035),
+ K3_DDR_PHY_WRITE_SINGLE(0x1254f, 0x0035),
+ K3_DDR_PHY_WRITE_SINGLE(0x12550, 0x0035),
+ K3_DDR_PHY_WRITE_SINGLE(0x12551, 0x0035),
+ K3_DDR_PHY_WRITE_SINGLE(0x1264e, 0x0035),
+ K3_DDR_PHY_WRITE_SINGLE(0x1264f, 0x0035),
+ K3_DDR_PHY_WRITE_SINGLE(0x12650, 0x0035),
+ K3_DDR_PHY_WRITE_SINGLE(0x12651, 0x0035),
+ K3_DDR_PHY_WRITE_SINGLE(0x1274e, 0x0035),
+ K3_DDR_PHY_WRITE_SINGLE(0x1274f, 0x0035),
+ K3_DDR_PHY_WRITE_SINGLE(0x12750, 0x0035),
+ K3_DDR_PHY_WRITE_SINGLE(0x12751, 0x0035),
+ K3_DDR_PHY_WRITE_SINGLE(0x1284e, 0x0035),
+ K3_DDR_PHY_WRITE_SINGLE(0x1284f, 0x0035),
+ K3_DDR_PHY_WRITE_SINGLE(0x12850, 0x0035),
+ K3_DDR_PHY_WRITE_SINGLE(0x12851, 0x0035),
+ K3_DDR_PHY_WRITE_SINGLE(0x1304e, 0x0035),
+ K3_DDR_PHY_WRITE_SINGLE(0x1304f, 0x0035),
+ K3_DDR_PHY_WRITE_SINGLE(0x13050, 0x0035),
+ K3_DDR_PHY_WRITE_SINGLE(0x13051, 0x0035),
+ K3_DDR_PHY_WRITE_SINGLE(0x1314e, 0x0035),
+ K3_DDR_PHY_WRITE_SINGLE(0x1314f, 0x0035),
+ K3_DDR_PHY_WRITE_SINGLE(0x13150, 0x0035),
+ K3_DDR_PHY_WRITE_SINGLE(0x13151, 0x0035),
+ K3_DDR_PHY_WRITE_SINGLE(0x1324e, 0x0035),
+ K3_DDR_PHY_WRITE_SINGLE(0x1324f, 0x0035),
+ K3_DDR_PHY_WRITE_SINGLE(0x13250, 0x0035),
+ K3_DDR_PHY_WRITE_SINGLE(0x13251, 0x0035),
+ K3_DDR_PHY_WRITE_SINGLE(0x1334e, 0x0035),
+ K3_DDR_PHY_WRITE_SINGLE(0x1334f, 0x0035),
+ K3_DDR_PHY_WRITE_SINGLE(0x13350, 0x0035),
+ K3_DDR_PHY_WRITE_SINGLE(0x13351, 0x0035),
+ K3_DDR_PHY_WRITE_SINGLE(0x1344e, 0x0035),
+ K3_DDR_PHY_WRITE_SINGLE(0x1344f, 0x0035),
+ K3_DDR_PHY_WRITE_SINGLE(0x13450, 0x0035),
+ K3_DDR_PHY_WRITE_SINGLE(0x13451, 0x0035),
+ K3_DDR_PHY_WRITE_SINGLE(0x1354e, 0x0035),
+ K3_DDR_PHY_WRITE_SINGLE(0x1354f, 0x0035),
+ K3_DDR_PHY_WRITE_SINGLE(0x13550, 0x0035),
+ K3_DDR_PHY_WRITE_SINGLE(0x13551, 0x0035),
+ K3_DDR_PHY_WRITE_SINGLE(0x1364e, 0x0035),
+ K3_DDR_PHY_WRITE_SINGLE(0x1364f, 0x0035),
+ K3_DDR_PHY_WRITE_SINGLE(0x13650, 0x0035),
+ K3_DDR_PHY_WRITE_SINGLE(0x13651, 0x0035),
+ K3_DDR_PHY_WRITE_SINGLE(0x1374e, 0x0035),
+ K3_DDR_PHY_WRITE_SINGLE(0x1374f, 0x0035),
+ K3_DDR_PHY_WRITE_SINGLE(0x13750, 0x0035),
+ K3_DDR_PHY_WRITE_SINGLE(0x13751, 0x0035),
+ K3_DDR_PHY_WRITE_SINGLE(0x1384e, 0x0035),
+ K3_DDR_PHY_WRITE_SINGLE(0x1384f, 0x0035),
+ K3_DDR_PHY_WRITE_SINGLE(0x13850, 0x0035),
+ K3_DDR_PHY_WRITE_SINGLE(0x13851, 0x0035),
+ K3_DDR_PHY_WRITE_SINGLE(0x30030, 0x0000),
+ K3_DDR_PHY_WRITE_SINGLE(0x30031, 0x0000),
+ K3_DDR_PHY_WRITE_SINGLE(0x30035, 0x0000),
+ K3_DDR_PHY_WRITE_SINGLE(0x31030, 0x0000),
+ K3_DDR_PHY_WRITE_SINGLE(0x31031, 0x0000),
+ K3_DDR_PHY_WRITE_SINGLE(0x31035, 0x0000),
+ K3_DDR_PHY_WRITE_SINGLE(0x10030, 0x0000),
+ K3_DDR_PHY_WRITE_SINGLE(0x10035, 0x0000),
+ K3_DDR_PHY_WRITE_SINGLE(0x10036, 0x0000),
+ K3_DDR_PHY_WRITE_SINGLE(0x11030, 0x0000),
+ K3_DDR_PHY_WRITE_SINGLE(0x11035, 0x0000),
+ K3_DDR_PHY_WRITE_SINGLE(0x11036, 0x0000),
+ K3_DDR_PHY_WRITE_SINGLE(0x12030, 0x0000),
+ K3_DDR_PHY_WRITE_SINGLE(0x12035, 0x0000),
+ K3_DDR_PHY_WRITE_SINGLE(0x12036, 0x0000),
+ K3_DDR_PHY_WRITE_SINGLE(0x13030, 0x0000),
+ K3_DDR_PHY_WRITE_SINGLE(0x13035, 0x0000),
+ K3_DDR_PHY_WRITE_SINGLE(0x13036, 0x0000),
+ K3_DDR_PHY_WRITE_SINGLE(0x3003c, 0x0005),
+ K3_DDR_PHY_WRITE_SINGLE(0x3103c, 0x0005),
+ K3_DDR_PHY_WRITE_SINGLE(0x1003c, 0x0005),
+ K3_DDR_PHY_WRITE_SINGLE(0x1003d, 0x0005),
+ K3_DDR_PHY_WRITE_SINGLE(0x1003e, 0x0005),
+ K3_DDR_PHY_WRITE_SINGLE(0x1103c, 0x0005),
+ K3_DDR_PHY_WRITE_SINGLE(0x1103d, 0x0005),
+ K3_DDR_PHY_WRITE_SINGLE(0x1103e, 0x0005),
+ K3_DDR_PHY_WRITE_SINGLE(0x1203c, 0x0005),
+ K3_DDR_PHY_WRITE_SINGLE(0x1203d, 0x0005),
+ K3_DDR_PHY_WRITE_SINGLE(0x1203e, 0x0005),
+ K3_DDR_PHY_WRITE_SINGLE(0x1303c, 0x0005),
+ K3_DDR_PHY_WRITE_SINGLE(0x1303d, 0x0005),
+ K3_DDR_PHY_WRITE_SINGLE(0x1303e, 0x0005),
+ K3_DDR_PHY_WRITE_SINGLE(0x20003, 0x0001),
+ K3_DDR_PHY_WRITE_SINGLE(0x20001, 0x1122),
+ K3_DDR_PHY_WRITE_SINGLE(0x20009, 0x0000),
+ K3_DDR_PHY_WRITE_SINGLE(0x20008, 0x0000),
+ K3_DDR_PHY_WRITE_SINGLE(0x200d9, 0x0000),
+ K3_DDR_PHY_WRITE_SINGLE(0x30eef, 0x0000),
+ K3_DDR_PHY_WRITE_SINGLE(0x31eef, 0x0000),
+ K3_DDR_PHY_WRITE_SINGLE(0x20014, 0x1300),
+ K3_DDR_PHY_WRITE_SINGLE(0x9080a, 0x1300),
+ K3_DDR_PHY_WRITE_SINGLE(0x10040, 0x0c0c),
+ K3_DDR_PHY_WRITE_SINGLE(0x10042, 0x0c0c),
+ K3_DDR_PHY_WRITE_SINGLE(0x9080d, 0x0000),
+ K3_DDR_PHY_WRITE_SINGLE(0x10043, 0x0000),
+ K3_DDR_PHY_WRITE_SINGLE(0x10044, 0x0c0c),
+ K3_DDR_PHY_WRITE_SINGLE(0x10045, 0x0c0c),
+ K3_DDR_PHY_WRITE_SINGLE(0x11040, 0x0c0c),
+ K3_DDR_PHY_WRITE_SINGLE(0x11042, 0x0c0c),
+ K3_DDR_PHY_WRITE_SINGLE(0x9080d, 0x0000),
+ K3_DDR_PHY_WRITE_SINGLE(0x11043, 0x0000),
+ K3_DDR_PHY_WRITE_SINGLE(0x11044, 0x0c0c),
+ K3_DDR_PHY_WRITE_SINGLE(0x11045, 0x0c0c),
+ K3_DDR_PHY_WRITE_SINGLE(0x12040, 0x0c0c),
+ K3_DDR_PHY_WRITE_SINGLE(0x12042, 0x0c0c),
+ K3_DDR_PHY_WRITE_SINGLE(0x9080d, 0x0000),
+ K3_DDR_PHY_WRITE_SINGLE(0x12043, 0x0000),
+ K3_DDR_PHY_WRITE_SINGLE(0x12044, 0x0c0c),
+ K3_DDR_PHY_WRITE_SINGLE(0x12045, 0x0c0c),
+ K3_DDR_PHY_WRITE_SINGLE(0x13040, 0x0c0c),
+ K3_DDR_PHY_WRITE_SINGLE(0x13042, 0x0c0c),
+ K3_DDR_PHY_WRITE_SINGLE(0x9080d, 0x0000),
+ K3_DDR_PHY_WRITE_SINGLE(0x13043, 0x0000),
+ K3_DDR_PHY_WRITE_SINGLE(0x13044, 0x0c0c),
+ K3_DDR_PHY_WRITE_SINGLE(0x13045, 0x0c0c),
+ K3_DDR_PHY_WRITE_SINGLE(0x30040, 0x0e0e),
+ K3_DDR_PHY_WRITE_SINGLE(0x30041, 0x0e0e),
+ K3_DDR_PHY_WRITE_SINGLE(0x30042, 0x0e0e),
+ K3_DDR_PHY_WRITE_SINGLE(0x30043, 0x0e0e),
+ K3_DDR_PHY_WRITE_SINGLE(0x30330, 0x0033),
+ K3_DDR_PHY_WRITE_SINGLE(0x31040, 0x0e0e),
+ K3_DDR_PHY_WRITE_SINGLE(0x31041, 0x0e0e),
+ K3_DDR_PHY_WRITE_SINGLE(0x31042, 0x0e0e),
+ K3_DDR_PHY_WRITE_SINGLE(0x31043, 0x0e0e),
+ K3_DDR_PHY_WRITE_SINGLE(0x31330, 0x0033),
+ K3_DDR_PHY_WRITE_SINGLE(0x20331, 0x0033),
+ K3_DDR_PHY_WRITE_SINGLE(0x10048, 0x0c00),
+ K3_DDR_PHY_WRITE_SINGLE(0x1004a, 0x0c00),
+ K3_DDR_PHY_WRITE_SINGLE(0x1004b, 0x0c00),
+ K3_DDR_PHY_WRITE_SINGLE(0x1004c, 0x0c00),
+ K3_DDR_PHY_WRITE_SINGLE(0x1004d, 0x0c00),
+ K3_DDR_PHY_WRITE_SINGLE(0x11048, 0x0c00),
+ K3_DDR_PHY_WRITE_SINGLE(0x1104a, 0x0c00),
+ K3_DDR_PHY_WRITE_SINGLE(0x1104b, 0x0c00),
+ K3_DDR_PHY_WRITE_SINGLE(0x1104c, 0x0c00),
+ K3_DDR_PHY_WRITE_SINGLE(0x1104d, 0x0c00),
+ K3_DDR_PHY_WRITE_SINGLE(0x12048, 0x0c00),
+ K3_DDR_PHY_WRITE_SINGLE(0x1204a, 0x0c00),
+ K3_DDR_PHY_WRITE_SINGLE(0x1204b, 0x0c00),
+ K3_DDR_PHY_WRITE_SINGLE(0x1204c, 0x0c00),
+ K3_DDR_PHY_WRITE_SINGLE(0x1204d, 0x0c00),
+ K3_DDR_PHY_WRITE_SINGLE(0x13048, 0x0c00),
+ K3_DDR_PHY_WRITE_SINGLE(0x1304a, 0x0c00),
+ K3_DDR_PHY_WRITE_SINGLE(0x1304b, 0x0c00),
+ K3_DDR_PHY_WRITE_SINGLE(0x1304c, 0x0c00),
+ K3_DDR_PHY_WRITE_SINGLE(0x1304d, 0x0c00),
+ K3_DDR_PHY_WRITE_SINGLE(0x30048, 0x0c00),
+ K3_DDR_PHY_WRITE_SINGLE(0x30049, 0x0c00),
+ K3_DDR_PHY_WRITE_SINGLE(0x3004a, 0x0c00),
+ K3_DDR_PHY_WRITE_SINGLE(0x3004b, 0x0c00),
+ K3_DDR_PHY_WRITE_SINGLE(0x31048, 0x0c00),
+ K3_DDR_PHY_WRITE_SINGLE(0x31049, 0x0c00),
+ K3_DDR_PHY_WRITE_SINGLE(0x3104a, 0x0c00),
+ K3_DDR_PHY_WRITE_SINGLE(0x3104b, 0x0c00),
+ K3_DDR_PHY_WRITE_SINGLE(0x30033, 0x0000),
+ K3_DDR_PHY_WRITE_SINGLE(0x30034, 0x0000),
+ K3_DDR_PHY_WRITE_SINGLE(0x3002e, 0x0000),
+ K3_DDR_PHY_WRITE_SINGLE(0x31033, 0x0000),
+ K3_DDR_PHY_WRITE_SINGLE(0x31034, 0x0000),
+ K3_DDR_PHY_WRITE_SINGLE(0x3102e, 0x0000),
+ K3_DDR_PHY_WRITE_SINGLE(0x10033, 0x0000),
+ K3_DDR_PHY_WRITE_SINGLE(0x1002e, 0x0000),
+ K3_DDR_PHY_WRITE_SINGLE(0x1002f, 0x0000),
+ K3_DDR_PHY_WRITE_SINGLE(0x11033, 0x0000),
+ K3_DDR_PHY_WRITE_SINGLE(0x1102e, 0x0000),
+ K3_DDR_PHY_WRITE_SINGLE(0x1102f, 0x0000),
+ K3_DDR_PHY_WRITE_SINGLE(0x12033, 0x0000),
+ K3_DDR_PHY_WRITE_SINGLE(0x1202e, 0x0000),
+ K3_DDR_PHY_WRITE_SINGLE(0x1202f, 0x0000),
+ K3_DDR_PHY_WRITE_SINGLE(0x13033, 0x0000),
+ K3_DDR_PHY_WRITE_SINGLE(0x1302e, 0x0000),
+ K3_DDR_PHY_WRITE_SINGLE(0x1302f, 0x0000),
+ K3_DDR_PHY_WRITE_SINGLE(0x20015, 0x0000),
+ K3_DDR_PHY_WRITE_SINGLE(0x90806, 0x0000),
+ K3_DDR_PHY_WRITE_SINGLE(0x100e8, 0x0000),
+ K3_DDR_PHY_WRITE_SINGLE(0x100e9, 0x0035),
+ K3_DDR_PHY_WRITE_SINGLE(0x110e8, 0x0000),
+ K3_DDR_PHY_WRITE_SINGLE(0x110e9, 0x0035),
+ K3_DDR_PHY_WRITE_SINGLE(0x120e8, 0x0000),
+ K3_DDR_PHY_WRITE_SINGLE(0x120e9, 0x0035),
+ K3_DDR_PHY_WRITE_SINGLE(0x130e8, 0x0000),
+ K3_DDR_PHY_WRITE_SINGLE(0x130e9, 0x0035),
+ K3_DDR_PHY_WRITE_SINGLE(0x10001, 0x0000),
+ K3_DDR_PHY_WRITE_SINGLE(0x11001, 0x0000),
+ K3_DDR_PHY_WRITE_SINGLE(0x12001, 0x0000),
+ K3_DDR_PHY_WRITE_SINGLE(0x13001, 0x0000),
+ K3_DDR_PHY_WRITE_SINGLE(0x20012, 0xa1a1),
+ K3_DDR_PHY_WRITE_SINGLE(0x20017, 0x0040),
+ K3_DDR_PHY_WRITE_SINGLE(0x2000a, 0x0040),
+ K3_DDR_PHY_WRITE_SINGLE(0x20186, 0x00a1),
+ K3_DDR_PHY_WRITE_SINGLE(0x20187, 0x0040),
+ K3_DDR_PHY_WRITE_SINGLE(0x20010, 0x005a),
+ K3_DDR_PHY_WRITE_SINGLE(0x20011, 0x006f),
+ K3_DDR_PHY_WRITE_SINGLE(0x9080b, 0x002f),
+ K3_DDR_PHY_WRITE_SINGLE(0x9080c, 0x006f),
+ K3_DDR_PHY_WRITE_SINGLE(0x100a5, 0x0001),
+ K3_DDR_PHY_WRITE_SINGLE(0x110a5, 0x0001),
+ K3_DDR_PHY_WRITE_SINGLE(0x120a5, 0x0001),
+ K3_DDR_PHY_WRITE_SINGLE(0x130a5, 0x0001),
+ K3_DDR_PHY_WRITE_SINGLE(0x10014, 0x3232),
+ K3_DDR_PHY_WRITE_SINGLE(0x11014, 0x3232),
+ K3_DDR_PHY_WRITE_SINGLE(0x12014, 0x3232),
+ K3_DDR_PHY_WRITE_SINGLE(0x13014, 0x3232),
+ K3_DDR_PHY_WRITE_SINGLE(0x1000f, 0x1086),
+ K3_DDR_PHY_WRITE_SINGLE(0x1100f, 0x1086),
+ K3_DDR_PHY_WRITE_SINGLE(0x1200f, 0x1086),
+ K3_DDR_PHY_WRITE_SINGLE(0x1300f, 0x1086),
+ K3_DDR_PHY_WRITE_SINGLE(0x20035, 0x100c),
+ K3_DDR_PHY_WRITE_SINGLE(0x20036, 0x100c),
+ K3_DDR_PHY_WRITE_SINGLE(0x20037, 0x041c),
+ K3_DDR_PHY_WRITE_SINGLE(0x20037, 0x045c),
+ K3_DDR_PHY_WRITE_SINGLE(0x20038, 0x1b20),
+ K3_DDR_PHY_WRITE_SINGLE(0x20039, 0x101c),
+ K3_DDR_PHY_WRITE_SINGLE(0x2003a, 0x101c),
+ K3_DDR_PHY_WRITE_SINGLE(0x2003b, 0x042c),
+ K3_DDR_PHY_WRITE_SINGLE(0x2003c, 0x2f30),
+ K3_DDR_PHY_WRITE_SINGLE(0x2003d, 0x1004),
+ K3_DDR_PHY_WRITE_SINGLE(0x2003e, 0x1004),
+ K3_DDR_PHY_WRITE_SINGLE(0x2003f, 0x0414),
+ K3_DDR_PHY_WRITE_SINGLE(0x20040, 0x1318),
+ K3_DDR_PHY_WRITE_SINGLE(0x2002c, 0x0843),
+ K3_DDR_PHY_WRITE_SINGLE(0x2002d, 0x0843),
+ K3_DDR_PHY_WRITE_SINGLE(0x20030, 0x0843),
+ K3_DDR_PHY_WRITE_SINGLE(0x2002e, 0x081f),
+ K3_DDR_PHY_WRITE_SINGLE(0x2002f, 0x081f),
+ K3_DDR_PHY_WRITE_SINGLE(0x2000c, 0x0000),
+ K3_DDR_PHY_WRITE_SINGLE(0x2001b, 0x0000),
+ K3_DDR_PHY_WRITE_SINGLE(0x10007, 0x0000),
+ K3_DDR_PHY_WRITE_SINGLE(0x11007, 0x0000),
+ K3_DDR_PHY_WRITE_SINGLE(0x12007, 0x0000),
+ K3_DDR_PHY_WRITE_SINGLE(0x13007, 0x0000),
+ K3_DDR_PHY_WRITE_SINGLE(0xc0080, 0x0003),
+ K3_DDR_PHY_WRITE_SINGLE(0xd0000, 0x0000),
+ K3_DDR_PHY_WRITE_RANGE(K3_PHY_PMU_DMEM_BASE, lp5_pre_training_table_54),
+};
+
+const struct k3_ddr_phy_table k3_ddr_lpddr5_pre_train_table = {
+ .cfg = lp5_pre_train_cfg,
+ .count = ARRAY_SIZE(lp5_pre_train_cfg),
+};
+
+static const struct k3_ddr_phy_override lp5_pre_srank_x16_override[] = {
+ {0x300ae, 0x0280, 0},
+ {0x300ad, 0x0280, 0},
+ {0x300ac, 0x0280, 0},
+ {0x310ae, 0x0280, 0},
+ {0x310ad, 0x0280, 0},
+ {0x310ac, 0x0280, 0},
+ {0x100a3, 0x0911, 0},
+ {0x110a3, 0x091d, 0},
+ {0x120a3, 0x0911, 0},
+ {0x130a3, 0x091d, 0},
+ {0x1005f, 0, K3_DDR_PHY_SKIP},
+ {0x10061, 0, K3_DDR_PHY_SKIP},
+ {0x10063, 0, K3_DDR_PHY_SKIP},
+ {0x10065, 0, K3_DDR_PHY_SKIP},
+ {0x1105f, 0, K3_DDR_PHY_SKIP},
+ {0x11061, 0, K3_DDR_PHY_SKIP},
+ {0x11063, 0, K3_DDR_PHY_SKIP},
+ {0x11065, 0, K3_DDR_PHY_SKIP},
+ {0x1205f, 0, K3_DDR_PHY_SKIP},
+ {0x12061, 0, K3_DDR_PHY_SKIP},
+ {0x12063, 0, K3_DDR_PHY_SKIP},
+ {0x12065, 0, K3_DDR_PHY_SKIP},
+ {0x1305f, 0, K3_DDR_PHY_SKIP},
+ {0x13061, 0, K3_DDR_PHY_SKIP},
+ {0x13063, 0, K3_DDR_PHY_SKIP},
+ {0x13065, 0, K3_DDR_PHY_SKIP},
+ {0x20039, 0x1018, 0},
+ {0x2003a, 0x1018, 0},
+ {0x2003b, 0x0428, 0},
+ {0x2003c, 0x2f2c, 0},
+ {0x2002c, 0x083f, 0},
+ {0x2002d, 0x083f, 0},
+ {0x20030, 0x083f, 0},
+ {0x5800e, 0x0000, 0},
+ {0x58012, 0x0110, 0},
+ {0x58020, 0x0001, 0},
+ {0x58081, 0x4300, 0},
+ {0x58082, 0x003f, 0},
+};
+
+const struct k3_ddr_phy_overrides k3_ddr_lpddr5_pre_srank_x16_overrides = {
+ .regs = lp5_pre_srank_x16_override,
+ .count = ARRAY_SIZE(lp5_pre_srank_x16_override),
+};
+
+static const struct k3_ddr_phy_override lp5_pre_drank_x16_override[] = {
+ {0x110a3, 0x0b3f, 0},
+ {0x130a3, 0x0b3f, 0},
+ {0x20039, 0x1018, 0},
+ {0x2003a, 0x1018, 0},
+ {0x2003b, 0x0428, 0},
+ {0x2003c, 0x2f2c, 0},
+ {0x2002c, 0x083f, 0},
+ {0x2002d, 0x083f, 0},
+ {0x20030, 0x083f, 0},
+ {0x5800e, 0x0000, 0},
+ {0x58081, 0x4300, 0},
+ {0x58082, 0x003f, 0},
+};
+
+const struct k3_ddr_phy_overrides k3_ddr_lpddr5_pre_drank_x16_overrides = {
+ .regs = lp5_pre_drank_x16_override,
+ .count = ARRAY_SIZE(lp5_pre_drank_x16_override),
+};
+
+static const u16 lp5_post_training_table_2[] = {
+ 0xc9d8, 0x0000, 0x0000, 0x0000, 0xc008, 0x0000, 0x0000, 0x0000,
+ 0x0000, 0x0000, 0x0000, 0x2b00, 0x0000, 0x0000, 0x0000, 0x0000,
+ 0xc958, 0x0000, 0x0000, 0x0000, 0xc688, 0x0000, 0x0000, 0x0000,
+ 0x0000, 0x0000, 0x0000, 0x2b00, 0x0000, 0x0000, 0x0000, 0x0000,
+ 0xc0d8, 0x0000, 0x0000, 0x0000, 0xd848, 0x0000, 0x0000, 0x0000,
+ 0x0000, 0x0000, 0x0000, 0x2b00, 0x0000, 0x0000, 0x0000, 0x0000,
+ 0xc158, 0x0000, 0x0000, 0x0000, 0xddc8, 0x0000, 0x0000, 0x0000,
+ 0x0000, 0x0000, 0x0000, 0x2b00, 0x0000, 0x0000, 0x0000, 0x0000,
+ 0xc1d8, 0x0000, 0x0000, 0x0000, 0xc308, 0x0000, 0x0000, 0x0000,
+ 0x0000, 0x0000, 0x0000, 0x2b00, 0x0000, 0x0000, 0x0000, 0x0000,
+ 0xc558, 0x0000, 0x0000, 0x0000, 0xec08, 0x0000, 0x0000, 0x0000,
+ 0x0000, 0x0000, 0x0000, 0x2b00, 0x0000, 0x0000, 0x0000, 0x0000,
+ 0xc5d8, 0x0000, 0x0000, 0x0000, 0xda08, 0x0000, 0x0000, 0x0000,
+ 0x0000, 0x0000, 0x0000, 0x2b00, 0x0000, 0x0000, 0x0000, 0x0000,
+ 0x48d8, 0x0000, 0x0000, 0x0000, 0x5708, 0x0000, 0x0000, 0x0000,
+ 0x88d8, 0x0000, 0x0000, 0x0000, 0x9708, 0x0000, 0x0000, 0x0000,
+ 0x0000, 0x0000, 0x0000, 0x2b00, 0x0000, 0x0000, 0x0000, 0x0000,
+ 0xca58, 0x0000, 0x0000, 0x0000, 0xc108, 0x0000, 0x0000, 0x0000,
+ 0x0000, 0x0000, 0x0000, 0x2b00, 0x0000, 0x0000, 0x0000, 0x0000,
+ 0xcb58, 0x0000, 0x0000, 0x0000, 0xc008, 0x0000, 0x0000, 0x0000,
+ 0x0000, 0x0000, 0x0000, 0x2b00, 0x0000, 0x0000, 0x0000, 0x0000,
+ 0xd4d8, 0x0000, 0x0000, 0x0000, 0xc008, 0x0000, 0x0000, 0x0000,
+};
+
+static const u16 lp5_post_training_table_16[] = {
+ 0xc028, 0x0000, 0x0000, 0x0010, 0x0000, 0x0000, 0x0000, 0x0000,
+ 0x0000, 0x0000, 0x0000, 0x0400, 0x0000, 0x0000, 0x0000, 0x0000,
+ 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000,
+ 0xc858, 0x0000, 0x0000, 0x0010, 0xe088, 0x0000, 0x0000, 0x0010,
+ 0xe038, 0x0000, 0x0000, 0x0010, 0xc858, 0x0000, 0x0000, 0x0010,
+ 0xc088, 0x0000, 0x0000, 0x0010, 0x0000, 0x0000, 0x0000, 0x0000,
+ 0xc028, 0x0000, 0x0000, 0x0010, 0x0000, 0x0000, 0x0000, 0x0000,
+ 0x0000, 0x0000, 0x0000, 0x0400, 0x0000, 0x0000, 0x0000, 0x0000,
+ 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000,
+ 0xc858, 0x0000, 0x0000, 0x0010, 0xe208, 0x0000, 0x0000, 0x0010,
+ 0xe038, 0x0000, 0x0000, 0x0010, 0xc858, 0x0000, 0x0000, 0x0010,
+ 0xc208, 0x0000, 0x0000, 0x0010, 0x0000, 0x0000, 0x0000, 0x0000,
+ 0xce58, 0x0000, 0x0000, 0x0010, 0xc208, 0x0000, 0x0000, 0x0010,
+ 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000,
+ 0xc370, 0x0000, 0x0000, 0x0010, 0x0000, 0x0000, 0x0000, 0x0000,
+ 0xc040, 0x0000, 0x0000, 0x0010, 0x0000, 0x0000, 0x0000, 0x0010,
+ 0xd2d8, 0x0000, 0x0000, 0x0010, 0xe008, 0x0000, 0x0000, 0x0010,
+ 0x0000, 0x0000, 0x0000, 0x5b00, 0x0000, 0x0000, 0x0000, 0x0000,
+ 0xc0f0, 0x0000, 0x0000, 0x0010, 0x0000, 0x0000, 0x0000, 0x0000,
+ 0xcfd8, 0x0000, 0x0000, 0x0010, 0xc008, 0x0000, 0x0000, 0x0010,
+ 0x0000, 0x0000, 0x0000, 0x2b00, 0x0000, 0x0000, 0x0000, 0x0000,
+ 0xd058, 0x0000, 0x0000, 0x0010, 0xc008, 0x0000, 0x0000, 0x0010,
+ 0x0000, 0x0000, 0x0000, 0x2b00, 0x0000, 0x0000, 0x0000, 0x0000,
+ 0xd0d8, 0x0000, 0x0000, 0x0010, 0xc088, 0x0000, 0x0000, 0x0010,
+ 0x0000, 0x0000, 0x0000, 0x2b00, 0x0000, 0x0000, 0x0000, 0x0000,
+ 0xd158, 0x0000, 0x0000, 0x0010, 0xc008, 0x0000, 0x0000, 0x0010,
+ 0x0000, 0x0000, 0x0000, 0x5b00, 0x0000, 0x0000, 0x0000, 0x0000,
+ 0x402c, 0x0d00, 0x0001, 0x0400, 0x4050, 0x0800, 0x0000, 0x0000,
+ 0x0000, 0x0000, 0x0000, 0x0400, 0x0000, 0x0000, 0x0000, 0x0000,
+ 0x0000, 0x0000, 0x0000, 0x0400, 0x4050, 0x0803, 0x0000, 0x0000,
+ 0x0000, 0x0000, 0x0000, 0x7f00, 0x0000, 0x0000, 0x0000, 0x0400,
+ 0x407c, 0x0000, 0x0000, 0x0400, 0x0000, 0x0000, 0x0000, 0x0000,
+ 0x0000, 0x0000, 0x0000, 0x0400, 0x0000, 0x0000, 0x0001, 0x0000,
+ 0x0000, 0x0000, 0x0000, 0x0400, 0x0000, 0x0000, 0x0000, 0x0000,
+ 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000,
+ 0x802c, 0x0d00, 0x0001, 0x0410, 0x8050, 0x0800, 0x0000, 0x0010,
+ 0x0000, 0x0000, 0x0000, 0x0400, 0x0000, 0x0000, 0x0000, 0x0000,
+ 0x0000, 0x0000, 0x0000, 0x0400, 0x8050, 0x0803, 0x0000, 0x0010,
+ 0x0000, 0x0000, 0x0000, 0x7f00, 0x0000, 0x0000, 0x0000, 0x0400,
+ 0x807c, 0x0000, 0x0000, 0x0410, 0x0000, 0x0000, 0x0000, 0x0000,
+ 0x0000, 0x0000, 0x0000, 0x0400, 0x0000, 0x0000, 0x0001, 0x0000,
+ 0x0000, 0x0000, 0x0000, 0x0400, 0x0000, 0x0000, 0x0000, 0x0000,
+ 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000,
+ 0x402c, 0x0d00, 0x0001, 0x0000, 0x4050, 0x0800, 0x0000, 0x0000,
+ 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000,
+ 0x0000, 0x0000, 0x0000, 0x0000, 0x4050, 0x0803, 0x0000, 0x0000,
+ 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000,
+ 0x0000, 0x0000, 0x0000, 0x0000, 0x4050, 0x0800, 0x0000, 0x0000,
+ 0x0000, 0x0000, 0x0000, 0x6b00, 0x0000, 0x0000, 0x0000, 0x0400,
+ 0x0000, 0x0000, 0x0000, 0x0000, 0x407c, 0x0000, 0x0000, 0x0000,
+ 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000,
+ 0x0000, 0x0000, 0x0001, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000,
+ 0x0000, 0x0000, 0x0000, 0x4b00, 0x0000, 0x0000, 0x0000, 0x1800,
+ 0x0000, 0x0000, 0x0000, 0x0000, 0x802c, 0x0d00, 0x0001, 0x0010,
+ 0x8050, 0x0800, 0x0000, 0x0010, 0x0000, 0x0000, 0x0000, 0x0000,
+ 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000,
+ 0x8050, 0x0803, 0x0000, 0x0010, 0x0000, 0x0000, 0x0000, 0x0000,
+ 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000,
+ 0x8050, 0x0800, 0x0000, 0x0010, 0x0000, 0x0000, 0x0000, 0x0000,
+ 0x0000, 0x0000, 0x0000, 0x6b00, 0x0000, 0x0000, 0x0000, 0x0400,
+ 0x807c, 0x0000, 0x0000, 0x0010, 0x0000, 0x0000, 0x0000, 0x0000,
+ 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0001, 0x0000,
+ 0x0000, 0x0000, 0x0000, 0x7b00, 0x0000, 0x0000, 0x0000, 0x2000,
+ 0x402c, 0x0d00, 0x0001, 0x0000, 0x5198, 0x0803, 0x0000, 0x0000,
+ 0x0000, 0x0000, 0x0000, 0x3b00, 0x0000, 0x0000, 0x0000, 0x0000,
+ 0x5218, 0x0803, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000,
+ 0x0000, 0x0000, 0x0000, 0x6b00, 0x0000, 0x0000, 0x0000, 0x0400,
+ 0x407c, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000,
+ 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0001, 0x0000,
+ 0x0000, 0x0000, 0x0000, 0x1b00, 0x0000, 0x0000, 0x0000, 0x0000,
+ 0x0000, 0x0000, 0x0000, 0x0000, 0x802c, 0x0d00, 0x0001, 0x0010,
+ 0x9198, 0x0803, 0x0000, 0x0010, 0x0000, 0x0000, 0x0000, 0x0000,
+ 0x0000, 0x0000, 0x0000, 0x2b00, 0x0000, 0x0000, 0x0000, 0x0000,
+ 0x0000, 0x0000, 0x0000, 0x0000, 0x9218, 0x0803, 0x0000, 0x0010,
+ 0x0000, 0x0000, 0x0000, 0x6b00, 0x0000, 0x0000, 0x0000, 0x0400,
+ 0x0000, 0x0000, 0x0000, 0x0000, 0x807c, 0x0000, 0x0000, 0x0010,
+ 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000,
+ 0x0000, 0x0000, 0x0001, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000,
+ 0x0000, 0x0000, 0x0000, 0x0b00, 0x0000, 0x0000, 0x0000, 0x0400,
+ 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000,
+ 0x401c, 0x00d0, 0x0001, 0x0000, 0x4060, 0x0084, 0x0000, 0x0000,
+ 0x0000, 0x0000, 0x0000, 0x0b00, 0x0000, 0x0000, 0x0000, 0x0800,
+ 0x407c, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000,
+ 0x0000, 0x0000, 0x0000, 0x0000, 0x4000, 0x0000, 0x0001, 0x0000,
+ 0x0000, 0x0000, 0x0000, 0x0000, 0x402c, 0x0d00, 0x0001, 0x0000,
+ 0x4020, 0x0803, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000,
+ 0x0000, 0x0000, 0x0000, 0x2b00, 0x0000, 0x0000, 0x0000, 0x0800,
+ 0x0000, 0x0000, 0x0000, 0x0000, 0x407c, 0x0000, 0x0000, 0x0000,
+ 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000,
+ 0x0000, 0x0000, 0x0001, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000,
+ 0x801c, 0x00d0, 0x0001, 0x0010, 0x8060, 0x0084, 0x0000, 0x0010,
+ 0x0000, 0x0000, 0x0000, 0x0b00, 0x0000, 0x0000, 0x0000, 0x0800,
+ 0x807c, 0x0000, 0x0000, 0x0010, 0x0000, 0x0000, 0x0000, 0x0000,
+ 0x0000, 0x0000, 0x0000, 0x0000, 0x8000, 0x0000, 0x0001, 0x0010,
+ 0x0000, 0x0000, 0x0000, 0x0000, 0x802c, 0x0d00, 0x0001, 0x0010,
+ 0x8020, 0x0803, 0x0000, 0x0010, 0x0000, 0x0000, 0x0000, 0x0000,
+ 0x0000, 0x0000, 0x0000, 0x2b00, 0x0000, 0x0000, 0x0000, 0x0800,
+ 0x0000, 0x0000, 0x0000, 0x0000, 0x807c, 0x0000, 0x0000, 0x0010,
+ 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000,
+ 0x0000, 0x0000, 0x0001, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000,
+ 0x402c, 0x0d00, 0x0001, 0x0000, 0x4050, 0x0803, 0x0000, 0x0000,
+ 0x0000, 0x0000, 0x0000, 0x1b00, 0x0000, 0x0000, 0x0000, 0x0000,
+ 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000,
+ 0x4050, 0x0803, 0x0000, 0x5a00, 0x0000, 0x0000, 0x0000, 0x0000,
+ 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000,
+ 0x0000, 0x0000, 0x0000, 0x0100, 0x0000, 0x0000, 0x0000, 0x0000,
+ 0x4050, 0x0803, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000,
+ 0x0000, 0x0000, 0x0000, 0x6b00, 0x0000, 0x0000, 0x0000, 0x0400,
+ 0x407c, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000,
+ 0x0000, 0x0000, 0x0000, 0x3b00, 0x0000, 0x0000, 0x0000, 0x0000,
+ 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0001, 0x0000,
+ 0x5758, 0x0000, 0x0000, 0x0000, 0x4208, 0x0000, 0x0000, 0x0000,
+ 0x0000, 0x0000, 0x0000, 0x4b00, 0x0000, 0x0000, 0x0000, 0x0000,
+ 0x0000, 0x0000, 0x0000, 0x0000, 0x401c, 0x00d0, 0x0001, 0x0000,
+ 0x4060, 0x0084, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000,
+ 0x0000, 0x0000, 0x0000, 0x7b00, 0x0000, 0x0000, 0x0000, 0x0000,
+ 0x407c, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000,
+ 0x0000, 0x0000, 0x0000, 0x0000, 0x4000, 0x0000, 0x0001, 0x0000,
+ 0x0000, 0x0000, 0x0000, 0x0000, 0x402c, 0x0d00, 0x0001, 0x0000,
+ 0x4020, 0x0803, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000,
+ 0x0000, 0x0000, 0x0000, 0x2b00, 0x0000, 0x0000, 0x0000, 0x0800,
+ 0x0000, 0x0000, 0x0000, 0x0000, 0x407c, 0x0000, 0x0000, 0x0000,
+ 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000,
+ 0x4000, 0x0000, 0x0001, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000,
+ 0x5758, 0x0000, 0x0000, 0x0000, 0x4008, 0x0000, 0x0000, 0x0000,
+ 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000,
+ 0x802c, 0x0d00, 0x0001, 0x0010, 0x8050, 0x0803, 0x0000, 0x0010,
+ 0x0000, 0x0000, 0x0000, 0x1b00, 0x0000, 0x0000, 0x0000, 0x0000,
+ 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000,
+ 0x8050, 0x0803, 0x0000, 0x5a10, 0x0000, 0x0000, 0x0000, 0x0000,
+ 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000,
+ 0x0000, 0x0000, 0x0000, 0x0100, 0x0000, 0x0000, 0x0000, 0x0000,
+ 0x8050, 0x0803, 0x0000, 0x0010, 0x0000, 0x0000, 0x0000, 0x0000,
+ 0x0000, 0x0000, 0x0000, 0x6b00, 0x0000, 0x0000, 0x0000, 0x0400,
+ 0x807c, 0x0000, 0x0000, 0x0010, 0x0000, 0x0000, 0x0000, 0x0000,
+ 0x0000, 0x0000, 0x0000, 0x3b00, 0x0000, 0x0000, 0x0000, 0x0000,
+ 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0001, 0x0000,
+ 0x9758, 0x0000, 0x0000, 0x0010, 0x8208, 0x0000, 0x0000, 0x0010,
+ 0x0000, 0x0000, 0x0000, 0x4b00, 0x0000, 0x0000, 0x0000, 0x0000,
+ 0x0000, 0x0000, 0x0000, 0x0000, 0x801c, 0x00d0, 0x0001, 0x0010,
+ 0x8060, 0x0084, 0x0000, 0x0010, 0x0000, 0x0000, 0x0000, 0x0000,
+ 0x0000, 0x0000, 0x0000, 0x7b00, 0x0000, 0x0000, 0x0000, 0x0000,
+ 0x807c, 0x0000, 0x0000, 0x0010, 0x0000, 0x0000, 0x0000, 0x0000,
+ 0x0000, 0x0000, 0x0000, 0x0000, 0x8000, 0x0000, 0x0001, 0x0010,
+ 0x0000, 0x0000, 0x0000, 0x0000, 0x802c, 0x0d00, 0x0001, 0x0010,
+ 0x8020, 0x0803, 0x0000, 0x0010, 0x0000, 0x0000, 0x0000, 0x0000,
+ 0x0000, 0x0000, 0x0000, 0x2b00, 0x0000, 0x0000, 0x0000, 0x0800,
+ 0x0000, 0x0000, 0x0000, 0x0000, 0x807c, 0x0000, 0x0000, 0x0010,
+ 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000,
+ 0x8000, 0x0000, 0x0001, 0x0010, 0x0000, 0x0000, 0x0000, 0x0000,
+ 0x9758, 0x0000, 0x0000, 0x0010, 0x8008, 0x0000, 0x0000, 0x0010,
+ 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000,
+ 0xc068, 0x0000, 0x0000, 0x0010, 0x0000, 0x0000, 0x0000, 0x0000,
+ 0xd2d8, 0x0000, 0x0000, 0x0010, 0xe008, 0x0000, 0x0000, 0x0010,
+ 0x0000, 0x0000, 0x0000, 0x5b00, 0x0000, 0x0000, 0x0000, 0x0000,
+ 0xc0f0, 0x0000, 0x0000, 0x0010, 0x0000, 0x0000, 0x0000, 0x0000,
+ 0xcfd8, 0x0000, 0x0000, 0x0010, 0xc008, 0x0000, 0x0000, 0x0010,
+ 0x0000, 0x0000, 0x0000, 0x2b00, 0x0000, 0x0000, 0x0000, 0x0000,
+ 0xd058, 0x0000, 0x0000, 0x0010, 0xc008, 0x0000, 0x0000, 0x0010,
+ 0x0000, 0x0000, 0x0000, 0x2b00, 0x0000, 0x0000, 0x0000, 0x0000,
+ 0xd0d8, 0x0000, 0x0000, 0x0010, 0xc088, 0x0000, 0x0000, 0x0010,
+ 0x0000, 0x0000, 0x0000, 0x2b00, 0x0000, 0x0000, 0x0000, 0x0000,
+ 0xd158, 0x0000, 0x0000, 0x0010, 0xc008, 0x0000, 0x0000, 0x0010,
+ 0x0000, 0x0000, 0x0000, 0x5b00, 0x0000, 0x0000, 0x0000, 0x0000,
+ 0x402c, 0x0d00, 0x0001, 0x0400, 0x4050, 0x0800, 0x0000, 0x0000,
+ 0x0000, 0x0000, 0x0000, 0x0400, 0x4050, 0x0803, 0x0000, 0x0000,
+ 0x0000, 0x0000, 0x0000, 0x6f00, 0x0000, 0x0000, 0x0000, 0x0400,
+ 0x407c, 0x0000, 0x0000, 0x0400, 0x0000, 0x0000, 0x0000, 0x0000,
+ 0x0000, 0x0000, 0x0000, 0x0400, 0x0000, 0x0000, 0x0001, 0x0000,
+ 0x0000, 0x0000, 0x0000, 0x0400, 0x0000, 0x0000, 0x0000, 0x0000,
+ 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000,
+ 0x802c, 0x0d00, 0x0001, 0x0410, 0x8050, 0x0800, 0x0000, 0x0010,
+ 0x0000, 0x0000, 0x0000, 0x0400, 0x8050, 0x0803, 0x0000, 0x0010,
+ 0x0000, 0x0000, 0x0000, 0x6f00, 0x0000, 0x0000, 0x0000, 0x0400,
+ 0x807c, 0x0000, 0x0000, 0x0410, 0x0000, 0x0000, 0x0000, 0x0000,
+ 0x0000, 0x0000, 0x0000, 0x0400, 0x0000, 0x0000, 0x0001, 0x0000,
+ 0x0000, 0x0000, 0x0000, 0x0400, 0x0000, 0x0000, 0x0000, 0x0000,
+ 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000,
+ 0x402c, 0x0d00, 0x0001, 0x0000, 0x4050, 0x0800, 0x0000, 0x0000,
+ 0x0000, 0x0000, 0x0000, 0x0000, 0x4050, 0x0803, 0x0000, 0x0000,
+ 0x0000, 0x0000, 0x0000, 0x0000, 0x4050, 0x0800, 0x0000, 0x0000,
+ 0x0000, 0x0000, 0x0000, 0x4b00, 0x0000, 0x0000, 0x0000, 0x0400,
+ 0x0000, 0x0000, 0x0000, 0x0000, 0x407c, 0x0000, 0x0000, 0x0000,
+ 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000,
+ 0x0000, 0x0000, 0x0001, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000,
+ 0x0000, 0x0000, 0x0000, 0x4b00, 0x0000, 0x0000, 0x0000, 0x1800,
+ 0x0000, 0x0000, 0x0000, 0x0000, 0x802c, 0x0d00, 0x0001, 0x0010,
+ 0x8050, 0x0800, 0x0000, 0x0010, 0x0000, 0x0000, 0x0000, 0x0000,
+ 0x8050, 0x0803, 0x0000, 0x0010, 0x0000, 0x0000, 0x0000, 0x0000,
+ 0x8050, 0x0800, 0x0000, 0x0010, 0x0000, 0x0000, 0x0000, 0x0000,
+ 0x0000, 0x0000, 0x0000, 0x4b00, 0x0000, 0x0000, 0x0000, 0x0400,
+ 0x807c, 0x0000, 0x0000, 0x0010, 0x0000, 0x0000, 0x0000, 0x0000,
+ 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0001, 0x0000,
+ 0x0000, 0x0000, 0x0000, 0x5b00, 0x0000, 0x0000, 0x0000, 0x2000,
+ 0x402c, 0x0d00, 0x0001, 0x0000, 0x5198, 0x0803, 0x0000, 0x0000,
+ 0x0000, 0x0000, 0x0000, 0x1b00, 0x0000, 0x0000, 0x0000, 0x0000,
+ 0x5218, 0x0803, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000,
+ 0x0000, 0x0000, 0x0000, 0x4b00, 0x0000, 0x0000, 0x0000, 0x0400,
+ 0x407c, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000,
+ 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0001, 0x0000,
+ 0x0000, 0x0000, 0x0000, 0x1b00, 0x0000, 0x0000, 0x0000, 0x0000,
+ 0x0000, 0x0000, 0x0000, 0x0000, 0x802c, 0x0d00, 0x0001, 0x0010,
+ 0x9198, 0x0803, 0x0000, 0x0010, 0x0000, 0x0000, 0x0000, 0x0000,
+ 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000,
+ 0x0000, 0x0000, 0x0000, 0x0000, 0x9218, 0x0803, 0x0000, 0x0010,
+ 0x0000, 0x0000, 0x0000, 0x4b00, 0x0000, 0x0000, 0x0000, 0x0400,
+ 0x0000, 0x0000, 0x0000, 0x0000, 0x807c, 0x0000, 0x0000, 0x0010,
+ 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000,
+ 0x0000, 0x0000, 0x0001, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000,
+ 0x0000, 0x0000, 0x0000, 0x0b00, 0x0000, 0x0000, 0x0000, 0x0400,
+ 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000,
+ 0x401c, 0x00d0, 0x0001, 0x0000, 0x4060, 0x0084, 0x0000, 0x0000,
+ 0x0000, 0x0000, 0x0000, 0x0b00, 0x0000, 0x0000, 0x0000, 0x0800,
+ 0x407c, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000,
+ 0x0000, 0x0000, 0x0000, 0x0000, 0x4000, 0x0000, 0x0001, 0x0000,
+ 0x0000, 0x0000, 0x0000, 0x0000, 0x402c, 0x0d00, 0x0001, 0x0000,
+ 0x4020, 0x0803, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000,
+ 0x0000, 0x0000, 0x0000, 0x2b00, 0x0000, 0x0000, 0x0000, 0x0800,
+ 0x0000, 0x0000, 0x0000, 0x0000, 0x407c, 0x0000, 0x0000, 0x0000,
+ 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000,
+ 0x0000, 0x0000, 0x0001, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000,
+ 0x801c, 0x00d0, 0x0001, 0x0010, 0x8060, 0x0084, 0x0000, 0x0010,
+ 0x0000, 0x0000, 0x0000, 0x0b00, 0x0000, 0x0000, 0x0000, 0x0800,
+ 0x807c, 0x0000, 0x0000, 0x0010, 0x0000, 0x0000, 0x0000, 0x0000,
+ 0x0000, 0x0000, 0x0000, 0x0000, 0x8000, 0x0000, 0x0001, 0x0010,
+ 0x0000, 0x0000, 0x0000, 0x0000, 0x802c, 0x0d00, 0x0001, 0x0010,
+ 0x8020, 0x0803, 0x0000, 0x0010, 0x0000, 0x0000, 0x0000, 0x0000,
+ 0x0000, 0x0000, 0x0000, 0x2b00, 0x0000, 0x0000, 0x0000, 0x0800,
+ 0x0000, 0x0000, 0x0000, 0x0000, 0x807c, 0x0000, 0x0000, 0x0010,
+ 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000,
+ 0x0000, 0x0000, 0x0001, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000,
+ 0x402c, 0x0d00, 0x0001, 0x0000, 0x4050, 0x0803, 0x0000, 0x0000,
+ 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000,
+ 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000,
+ 0x4050, 0x0803, 0x0000, 0x5a00, 0x0000, 0x0000, 0x0000, 0x0000,
+ 0x0000, 0x0000, 0x0000, 0x0100, 0x0000, 0x0000, 0x0000, 0x0000,
+ 0x4050, 0x0803, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000,
+ 0x0000, 0x0000, 0x0000, 0x4b00, 0x0000, 0x0000, 0x0000, 0x0400,
+ 0x407c, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000,
+ 0x0000, 0x0000, 0x0000, 0x3b00, 0x0000, 0x0000, 0x0000, 0x0000,
+ 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0001, 0x0000,
+ 0x5758, 0x0000, 0x0000, 0x0000, 0x4208, 0x0000, 0x0000, 0x0000,
+ 0x0000, 0x0000, 0x0000, 0x4b00, 0x0000, 0x0000, 0x0000, 0x0000,
+ 0x0000, 0x0000, 0x0000, 0x0000, 0x401c, 0x00d0, 0x0001, 0x0000,
+ 0x4060, 0x0084, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000,
+ 0x0000, 0x0000, 0x0000, 0x7b00, 0x0000, 0x0000, 0x0000, 0x0000,
+ 0x407c, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000,
+ 0x0000, 0x0000, 0x0000, 0x0000, 0x4000, 0x0000, 0x0001, 0x0000,
+ 0x0000, 0x0000, 0x0000, 0x0000, 0x402c, 0x0d00, 0x0001, 0x0000,
+ 0x4020, 0x0803, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000,
+ 0x0000, 0x0000, 0x0000, 0x2b00, 0x0000, 0x0000, 0x0000, 0x0800,
+ 0x0000, 0x0000, 0x0000, 0x0000, 0x407c, 0x0000, 0x0000, 0x0000,
+ 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000,
+ 0x4000, 0x0000, 0x0001, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000,
+ 0x5758, 0x0000, 0x0000, 0x0000, 0x4008, 0x0000, 0x0000, 0x0000,
+ 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000,
+ 0x802c, 0x0d00, 0x0001, 0x0010, 0x8050, 0x0803, 0x0000, 0x0010,
+ 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000,
+ 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000,
+ 0x8050, 0x0803, 0x0000, 0x5a10, 0x0000, 0x0000, 0x0000, 0x0000,
+ 0x0000, 0x0000, 0x0000, 0x0100, 0x0000, 0x0000, 0x0000, 0x0000,
+ 0x8050, 0x0803, 0x0000, 0x0010, 0x0000, 0x0000, 0x0000, 0x0000,
+ 0x0000, 0x0000, 0x0000, 0x4b00, 0x0000, 0x0000, 0x0000, 0x0400,
+ 0x807c, 0x0000, 0x0000, 0x0010, 0x0000, 0x0000, 0x0000, 0x0000,
+ 0x0000, 0x0000, 0x0000, 0x3b00, 0x0000, 0x0000, 0x0000, 0x0000,
+ 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0001, 0x0000,
+ 0x9758, 0x0000, 0x0000, 0x0010, 0x8208, 0x0000, 0x0000, 0x0010,
+ 0x0000, 0x0000, 0x0000, 0x4b00, 0x0000, 0x0000, 0x0000, 0x0000,
+ 0x0000, 0x0000, 0x0000, 0x0000, 0x801c, 0x00d0, 0x0001, 0x0010,
+ 0x8060, 0x0084, 0x0000, 0x0010, 0x0000, 0x0000, 0x0000, 0x0000,
+ 0x0000, 0x0000, 0x0000, 0x7b00, 0x0000, 0x0000, 0x0000, 0x0000,
+ 0x807c, 0x0000, 0x0000, 0x0010, 0x0000, 0x0000, 0x0000, 0x0000,
+ 0x0000, 0x0000, 0x0000, 0x0000, 0x8000, 0x0000, 0x0001, 0x0010,
+ 0x0000, 0x0000, 0x0000, 0x0000, 0x802c, 0x0d00, 0x0001, 0x0010,
+ 0x8020, 0x0803, 0x0000, 0x0010, 0x0000, 0x0000, 0x0000, 0x0000,
+ 0x0000, 0x0000, 0x0000, 0x2b00, 0x0000, 0x0000, 0x0000, 0x0800,
+ 0x0000, 0x0000, 0x0000, 0x0000, 0x807c, 0x0000, 0x0000, 0x0010,
+ 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000,
+ 0x8000, 0x0000, 0x0001, 0x0010, 0x0000, 0x0000, 0x0000, 0x0000,
+ 0x9758, 0x0000, 0x0000, 0x0010, 0x8008, 0x0000, 0x0000, 0x0010,
+ 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000,
+ 0xc068, 0x0000, 0x0000, 0x0010, 0x0000, 0x0000, 0x0000, 0x0000,
+};
+
+static const u16 lp5_post_training_table_17[] = {
+ 0x0010, 0x0400, 0x080e, 0x000b, 0x0480, 0x0809, 0x0009, 0x0308,
+ 0x0c09, 0x0028, 0x8160, 0x087c, 0x0098, 0x0820, 0x0c7e, 0x0002,
+ 0x0001, 0x0078, 0x000a, 0x0370, 0x0839, 0x0018, 0x8160, 0x083c,
+ 0x0009, 0x0150, 0x0839, 0x0070, 0x0392, 0x0039, 0x0078, 0x039a,
+ 0x0039, 0x0e09, 0x0100, 0x0839, 0x0002, 0x0001, 0x0038, 0x0000,
+ 0x0100, 0x0839, 0x0000, 0x0398, 0x0839, 0x0e19, 0x0100, 0x0839,
+ 0x0002, 0x0001, 0x0038, 0x0000, 0x0100, 0x0839, 0x0000, 0x0390,
+ 0x0839, 0x0078, 0x039a, 0x0039, 0x0e29, 0x0100, 0x0839, 0x0002,
+ 0x0001, 0x0038, 0x0000, 0x0100, 0x0839, 0x0070, 0x0392, 0x0039,
+ 0x0018, 0x8160, 0x08bc, 0x0008, 0x013a, 0x00b9, 0x024b, 0x0100,
+ 0x08b9, 0x0002, 0x0001, 0x00b8, 0x0000, 0x0100, 0x08b9, 0x0020,
+ 0x0004, 0x00b8, 0x0020, 0x0004, 0x00b8, 0x0005, 0x0000, 0x00b8,
+ 0x0479, 0xc7f8, 0x08bc, 0x0000, 0x0000, 0x00b8, 0x0000, 0x00a8,
+ 0x08b9, 0x0009, 0xc9c0, 0x0cbc, 0x0000, 0x0000, 0x00b8, 0x025b,
+ 0x0100, 0x0cb9, 0x0020, 0x0004, 0x00b8, 0x0020, 0x0004, 0x00b8,
+ 0x0020, 0x0004, 0x00b8, 0x0020, 0x0004, 0x00b8, 0x0010, 0x0400,
+ 0x089e, 0x0008, 0x0370, 0x0839, 0x033b, 0x0100, 0x08b9, 0x0000,
+ 0x0100, 0x08b9, 0x023b, 0x0100, 0x0c99, 0x0002, 0x0150, 0x0839,
+ 0x1800, 0x8660, 0x0839, 0x0000, 0x02a0, 0x0809, 0x0008, 0x1880,
+ 0x0839, 0x0008, 0x82b0, 0x0838, 0x0018, 0x00e0, 0x0809, 0x0000,
+ 0x00e0, 0x0869, 0x000f, 0x07c0, 0x0839, 0x000a, 0x0510, 0x0839,
+ 0x000a, 0x0700, 0x0849, 0x000a, 0x0700, 0x0859, 0x000a, 0x0708,
+ 0x0859, 0x0002, 0x0708, 0x0849, 0x0ff8, 0x8410, 0x0839, 0x7ff8,
+ 0x8498, 0x0838, 0x0010, 0x8160, 0x083c, 0x0000, 0x07c8, 0x0809,
+ 0x0000, 0x0001, 0x0008, 0x0000, 0x045a, 0x0089, 0x0000, 0x8018,
+ 0x0808, 0x0000, 0x8020, 0x0808, 0x0479, 0xc7f8, 0x080c, 0x0000,
+ 0x0000, 0x0008, 0x0000, 0x8018, 0x0808, 0x0000, 0x8020, 0x0808,
+ 0x0009, 0xc9c0, 0x0c0c, 0x0000, 0x00a8, 0x08c9, 0x0029, 0x8160,
+ 0x087c, 0x00b8, 0x0820, 0x0c7e, 0x0001, 0x0000, 0x0078, 0x0000,
+ 0x0001, 0x0078, 0x00d8, 0x0820, 0x0c7e, 0x0001, 0x0000, 0x0078,
+ 0x0000, 0x0001, 0x0078, 0x00f8, 0x0820, 0x0c7e, 0x0001, 0x0000,
+ 0x0078, 0x0000, 0x0001, 0x0078, 0x0000, 0x0700, 0x0849, 0x0000,
+ 0x0618, 0x0809, 0x3ff8, 0x84b8, 0x0808, 0x0000, 0x0000, 0x0008,
+ 0x0008, 0xc870, 0x0c0c, 0x0018, 0x0710, 0x0849, 0x0000, 0x0004,
+ 0x0048, 0x0000, 0x0004, 0x0048, 0x0010, 0x0710, 0x0849, 0x0000,
+ 0x0004, 0x0048, 0x0000, 0x0710, 0x0849, 0x0000, 0x0004, 0x0048,
+ 0x0000, 0x0004, 0x0018, 0x0000, 0x0004, 0x0018, 0x0000, 0x0004,
+ 0x0018, 0x0000, 0x8410, 0x0809, 0x0000, 0x8498, 0x0808, 0x0005,
+ 0x0510, 0x0809, 0x0198, 0x1000, 0x0809, 0x0009, 0x03c0, 0x0809,
+ 0x0010, 0x0510, 0x0809, 0x0000, 0x03c0, 0x0809, 0x0018, 0x0004,
+ 0x0008, 0x0002, 0x0510, 0x0809, 0x0002, 0x1000, 0x0809, 0x0068,
+ 0x801a, 0x0008, 0x0068, 0x8022, 0x0008, 0x0479, 0xc7f8, 0x080c,
+ 0x0000, 0x0000, 0x0008, 0x0068, 0x801a, 0x0008, 0x0068, 0x8022,
+ 0x0008, 0x0009, 0xc9c0, 0x0c0c, 0x0000, 0xc870, 0x0c0c, 0x0000,
+ 0x02a0, 0x0809, 0x0010, 0x8160, 0x089c, 0x0002, 0x07c8, 0x0809,
+ 0x0000, 0x0001, 0x0008, 0x0040, 0x1932, 0x0129, 0x000a, 0xc140,
+ 0x080c, 0x0098, 0x193a, 0x0129, 0x0090, 0x1932, 0x0329, 0x0090,
+ 0x193a, 0x0329, 0x0088, 0x1882, 0x0009, 0x0000, 0xc140, 0x080c,
+ 0x0010, 0x0400, 0x080e, 0x000b, 0x0370, 0x0809, 0x023b, 0x0100,
+ 0x0cf9, 0x0000, 0x02a0, 0x0809, 0x7800, 0x8660, 0x0809, 0x000d,
+ 0x07c0, 0x0809, 0x0000, 0x82b0, 0x0818, 0x0000, 0x82b0, 0x0868,
+ 0x0002, 0x07c8, 0x0a09, 0x0008, 0x0508, 0x0939, 0x0005, 0x07c0,
+ 0x0809, 0x0008, 0x82b0, 0x0868, 0x0008, 0x82b0, 0x0818, 0x0008,
+ 0x82b0, 0x0888, 0x0010, 0x0510, 0x0809, 0x0000, 0x00a8, 0x08c9,
+ 0x0009, 0x1900, 0x0d39, 0x0000, 0x0508, 0x0939, 0x0002, 0x07c8,
+ 0x0829, 0x000a, 0x03c8, 0x0c29, 0x0199, 0x03d0, 0x0c19, 0x0003,
+ 0x0000, 0x0018, 0x0038, 0x0004, 0x0018, 0x0199, 0x03d0, 0x0c09,
+ 0x0000, 0x0000, 0x0008, 0x0009, 0x0150, 0x0809, 0x0009, 0xc800,
+ 0x0c0c, 0x0018, 0x8160, 0x08cc, 0x0008, 0x013a, 0x00c9, 0x024b,
+ 0x0100, 0x08c9, 0x0002, 0x0001, 0x00c8, 0x0000, 0x0100, 0x08c9,
+ 0x0020, 0x0004, 0x00c8, 0x0020, 0x0004, 0x00c8, 0x0005, 0x0000,
+ 0x00c8, 0x0479, 0xc7f8, 0x08cc, 0x0000, 0x0000, 0x00c8, 0x0030,
+ 0x00aa, 0x00c9, 0x0009, 0xc9c0, 0x0ccc, 0x0000, 0x0000, 0x00c8,
+ 0x0479, 0xc7f8, 0x08bc, 0x0000, 0x0000, 0x00b8, 0x0030, 0x00aa,
+ 0x00b9, 0x0009, 0xc9c0, 0x0cbc, 0x0000, 0x0000, 0x00b8, 0x025b,
+ 0x0100, 0x0cc9, 0x0020, 0x0004, 0x00c8, 0x0020, 0x0004, 0x00c8,
+ 0x0020, 0x0004, 0x00a8, 0x0004, 0x0000, 0x00c8, 0x0009, 0xc800,
+ 0x0c6c, 0x026f, 0x0100, 0x0c19, 0x0008, 0x0004, 0x0018, 0x027f,
+ 0x0100, 0x0c19, 0x0479, 0xc7f8, 0x080c, 0x0000, 0x0000, 0x0008,
+ 0x0058, 0x008a, 0x0009, 0x0009, 0xc9c0, 0x0c0c, 0x0000, 0x0000,
+ 0x0008, 0x0018, 0x8160, 0x086c, 0x1008, 0x853b, 0x0868, 0x0c00,
+ 0x8588, 0x0868, 0x0008, 0x85a8, 0x0868, 0x0008, 0x85c8, 0x0868,
+ 0x0000, 0x8050, 0x0868, 0x0060, 0x0138, 0x0869, 0x0018, 0x8510,
+ 0x0868, 0x0018, 0x02c8, 0x0869, 0x0010, 0x8520, 0x0868, 0x1ff8,
+ 0x85d8, 0x0c68, 0x0000, 0xfdf0, 0x0868, 0x0008, 0x85f0, 0x0868,
+ 0x0008, 0xa5f0, 0x0868, 0x0298, 0x0100, 0x0869, 0x0002, 0x0001,
+ 0x0068, 0x0000, 0x0100, 0x0869, 0x0000, 0x85f0, 0x0868, 0x0000,
+ 0xa5f0, 0x0868, 0x033b, 0x0100, 0x08c9, 0x0000, 0x0100, 0x08c9,
+ 0x1ff8, 0x85d8, 0x0c68, 0x0008, 0x8df0, 0x0868, 0x0008, 0xadf0,
+ 0x0868, 0x02a8, 0x0100, 0x0869, 0x0002, 0x0001, 0x0068, 0x0000,
+ 0x0100, 0x0869, 0x0000, 0x8df0, 0x0868, 0x0000, 0xadf0, 0x0868,
+ 0x0010, 0x02c8, 0x0869, 0x0028, 0x0004, 0x0068, 0x000a, 0x0500,
+ 0x0c69, 0x0000, 0x8520, 0x0868, 0x0008, 0x8530, 0x0868, 0x02ba,
+ 0x0100, 0x0869, 0x0002, 0x0001, 0x0068, 0x0002, 0x0100, 0x0869,
+ 0x0000, 0x8530, 0x0868, 0x0000, 0x8510, 0x0868, 0x0000, 0x02c8,
+ 0x0869, 0x0008, 0x8050, 0x0868, 0x0030, 0x0004, 0x0068, 0x0008,
+ 0x8520, 0x0868, 0x0000, 0x8328, 0x086b, 0x02ca, 0x0100, 0x0869,
+ 0x0002, 0x0001, 0x0068, 0x0004, 0x0100, 0x0869, 0x0ff8, 0x8328,
+ 0x086b, 0x0009, 0x0500, 0x0c29, 0x0000, 0x8520, 0x0868, 0x0008,
+ 0x03c8, 0x0c29, 0x0000, 0x0150, 0x0809, 0x0002, 0x0370, 0x0809,
+ 0x0000, 0x0400, 0x080e, 0x0020, 0x82b0, 0x0808, 0x0479, 0xc7f8,
+ 0x080c, 0x0000, 0x0000, 0x0008, 0x0060, 0x008a, 0x0009, 0x0009,
+ 0xc9c0, 0x0c0c, 0x0000, 0x0000, 0x0008, 0x0008, 0x02a0, 0x0809,
+ 0x0048, 0xc822, 0x000c, 0x0048, 0xcc32, 0x000c, 0x0009, 0xc800,
+ 0x0c0c, 0x0000, 0x8168, 0x080c, 0x000a, 0xc140, 0x092c, 0x0088,
+ 0x1932, 0x0129, 0x0088, 0x193a, 0x0129, 0x0000, 0xc140, 0x092c,
+ 0x0008, 0x0300, 0x0819, 0x0010, 0x8160, 0x080c, 0x0008, 0x07c8,
+ 0x0931, 0x0008, 0x0000, 0x0008, 0x0008, 0x1880, 0x0809, 0x0010,
+ 0x8160, 0x080c, 0x1800, 0x8660, 0x0809, 0x4000, 0x8668, 0x0809,
+ 0x000f, 0x07c0, 0x0809, 0x0000, 0x02a0, 0x0809, 0x0008, 0x0618,
+ 0x0809, 0x0000, 0x84b8, 0x0808, 0x0ff8, 0x8410, 0x0809, 0x7ff8,
+ 0x8498, 0x0808, 0x0000, 0x07c8, 0x0809, 0x0008, 0x8168, 0x080c,
+ 0x0000, 0x0001, 0x0008, 0x0000, 0x0004, 0x0008, 0x0000, 0x0004,
+ 0x0008, 0x0018, 0x0300, 0x0809, 0x0000, 0x0480, 0x0809, 0x0008,
+ 0x0510, 0x0809, 0x7800, 0x8660, 0x0809, 0x0008, 0x07c8, 0x0801,
+ 0x0010, 0x0400, 0x080e, 0x0008, 0x0150, 0x0809, 0x0009, 0x0370,
+ 0x0809, 0x0018, 0x8160, 0x080c, 0x0008, 0xc800, 0x0c0c, 0x0008,
+ 0xc888, 0x0c04, 0x0020, 0x8302, 0x000b, 0x0018, 0x8582, 0x0008,
+ 0x9000, 0x8539, 0x0808, 0x0000, 0x8588, 0x0808, 0x0040, 0x85c8,
+ 0x0808, 0x0000, 0xfdf0, 0x0808, 0x0800, 0xc5f0, 0x0808, 0x1ff8,
+ 0xfdd8, 0x0c08, 0x0018, 0xfda8, 0x0808, 0x0040, 0x8520, 0x08d8,
+ 0x0080, 0x8520, 0x08e8, 0x030a, 0x0100, 0x08d9, 0x032a, 0x0100,
+ 0x08e9, 0x0000, 0x0001, 0x0008, 0x0000, 0x0100, 0x0809, 0x1ff8,
+ 0xfdd8, 0x0c08, 0x0008, 0xfda8, 0x0808, 0x0140, 0x8520, 0x08d8,
+ 0x0180, 0x8520, 0x08e8, 0x030a, 0x0100, 0x08d9, 0x032a, 0x0100,
+ 0x08e9, 0x0000, 0x0001, 0x0008, 0x0000, 0x0100, 0x0809, 0x0009,
+ 0x0500, 0x0c09, 0x0010, 0x82b0, 0x0808, 0x0000, 0x8520, 0x0808,
+ 0x0008, 0x03c8, 0x0c09, 0x0000, 0x0150, 0x0809, 0x0002, 0x0370,
+ 0x0809, 0x0000, 0x0400, 0x080e, 0x0008, 0xc848, 0x0c0c, 0x0000,
+ 0xc890, 0x0804, 0x0020, 0x8302, 0x000b, 0x0018, 0x8582, 0x0008,
+ 0x0000, 0x82b0, 0x0808, 0x1000, 0x8539, 0x0808, 0x0000, 0x8588,
+ 0x0808, 0x0040, 0x85c8, 0x0808, 0x07f8, 0xfdf0, 0x0808, 0x0800,
+ 0xc5f0, 0x0808, 0x0080, 0x8088, 0x080b, 0x1ff8, 0xfdd8, 0x0c08,
+ 0x0018, 0xfda8, 0x0808, 0x0200, 0x8520, 0x08d8, 0x0400, 0x8520,
+ 0x08e8, 0x02da, 0x0100, 0x08d9, 0x02ea, 0x0100, 0x08e9, 0x0002,
+ 0x0001, 0x0008, 0x0000, 0x0100, 0x0809, 0x1ff8, 0xfdd8, 0x0c08,
+ 0x0008, 0xfda8, 0x0808, 0x0a00, 0x8520, 0x08d8, 0x0c00, 0x8520,
+ 0x08e8, 0x02da, 0x0100, 0x08d9, 0x02ea, 0x0100, 0x08e9, 0x0000,
+ 0x0001, 0x0008, 0x0000, 0x0100, 0x0809, 0x0009, 0x0500, 0x0c09,
+ 0x0010, 0x82b0, 0x0808, 0x0000, 0x8520, 0x0808, 0x0008, 0x03c8,
+ 0x0c09, 0x0000, 0x0150, 0x0809, 0x0002, 0x0370, 0x0809, 0x0000,
+ 0x0400, 0x080e, 0x0008, 0xc848, 0x0c0c, 0x0000, 0xc890, 0x0804,
+ 0x1008, 0x853b, 0x0808, 0x0c00, 0x8588, 0x0808, 0x0008, 0x85a8,
+ 0x0808, 0x0008, 0x85c8, 0x0808, 0x0060, 0x0138, 0x0809, 0x0018,
+ 0x00c8, 0x0809, 0x0000, 0x00a4, 0x0809, 0x0000, 0x8510, 0x0808,
+ 0x02fa, 0x0100, 0x08d9, 0x031a, 0x0100, 0x08e9, 0x0002, 0x0001,
+ 0x0008, 0x0002, 0x0100, 0x0809, 0x0202, 0x8510, 0x0c08, 0x0050,
+ 0x00a2, 0x0009, 0x0000, 0x0000, 0x0008, 0x0000, 0x0000, 0x0008,
+ 0x0000, 0x0000, 0x0008, 0x0000, 0x00c8, 0x0809, 0x000b, 0x0508,
+ 0x0809, 0x0008, 0x1900, 0x0c09, 0x0002, 0x0000, 0x0008, 0x0000,
+ 0x0508, 0x0809, 0x0009, 0x0500, 0x0c09, 0x0010, 0x82b0, 0x0808,
+ 0x0000, 0x8520, 0x0808, 0x0008, 0x03c8, 0x0c09, 0x0000, 0x0150,
+ 0x0809, 0x0002, 0x0370, 0x0809, 0x0000, 0x0400, 0x080e, 0x0008,
+ 0xc848, 0x0c0c, 0x0000, 0xc890, 0x0804, 0x0020, 0x8302, 0x000b,
+ 0x0018, 0x8582, 0x0008, 0x1000, 0x8539, 0x0808, 0x0000, 0x8588,
+ 0x0808, 0x0040, 0x85c8, 0x0808, 0x0008, 0xfdf0, 0x0808, 0x0080,
+ 0x8088, 0x080b, 0x0000, 0x03b8, 0x0869, 0x1ff8, 0xfdd8, 0x0c08,
+ 0x0018, 0xfda8, 0x0808, 0x0040, 0x8520, 0x08d8, 0x0080, 0x8520,
+ 0x08e8, 0x02da, 0x0100, 0x08d9, 0x02ea, 0x0100, 0x08e9, 0x0002,
+ 0x0001, 0x0008, 0x0000, 0x0100, 0x0809, 0x1ff8, 0xfdd8, 0x0c08,
+ 0x0008, 0xfda8, 0x0808, 0x0140, 0x8520, 0x08d8, 0x0180, 0x8520,
+ 0x08e8, 0x02da, 0x0100, 0x08d9, 0x02ea, 0x0100, 0x08e9, 0x0000,
+ 0x0001, 0x0008, 0x0000, 0x0100, 0x0809, 0x0009, 0x0500, 0x0c09,
+ 0x0010, 0x82b0, 0x0808, 0x0000, 0x8520, 0x0808, 0x0008, 0x03c8,
+ 0x0c09, 0x0000,
+};
+
+static const u16 lp5_post_training_table_23[] = {
+ 0xc9d8, 0x0000, 0x0000, 0x0000, 0xc008, 0x0000, 0x0000, 0x0000,
+ 0x0000, 0x0000, 0x0000, 0x2b00, 0x0000, 0x0000, 0x0000, 0x0000,
+ 0xc958, 0x0000, 0x0000, 0x0000, 0xc688, 0x0000, 0x0000, 0x0000,
+ 0x0000, 0x0000, 0x0000, 0x2b00, 0x0000, 0x0000, 0x0000, 0x0000,
+ 0xc0d8, 0x0000, 0x0000, 0x0000, 0xd848, 0x0000, 0x0000, 0x0000,
+ 0x0000, 0x0000, 0x0000, 0x2b00, 0x0000, 0x0000, 0x0000, 0x0000,
+ 0xc158, 0x0000, 0x0000, 0x0000, 0xddc8, 0x0000, 0x0000, 0x0000,
+ 0x0000, 0x0000, 0x0000, 0x2b00, 0x0000, 0x0000, 0x0000, 0x0000,
+ 0xc1d8, 0x0000, 0x0000, 0x0000, 0xc308, 0x0000, 0x0000, 0x0000,
+ 0x0000, 0x0000, 0x0000, 0x2b00, 0x0000, 0x0000, 0x0000, 0x0000,
+ 0xc558, 0x0000, 0x0000, 0x0000, 0xec08, 0x0000, 0x0000, 0x0000,
+ 0x0000, 0x0000, 0x0000, 0x2b00, 0x0000, 0x0000, 0x0000, 0x0000,
+ 0xc5d8, 0x0000, 0x0000, 0x0000, 0xda08, 0x0000, 0x0000, 0x0000,
+ 0x0000, 0x0000, 0x0000, 0x2b00, 0x0000, 0x0000, 0x0000, 0x0000,
+ 0x48d8, 0x0000, 0x0000, 0x0000, 0x5708, 0x0000, 0x0000, 0x0000,
+ 0x88d8, 0x0000, 0x0000, 0x0000, 0x9708, 0x0000, 0x0000, 0x0000,
+ 0x0000, 0x0000, 0x0000, 0x2b00, 0x0000, 0x0000, 0x0000, 0x0000,
+ 0xca58, 0x0000, 0x0000, 0x0000, 0xc108, 0x0000, 0x0000, 0x0000,
+ 0x0000, 0x0000, 0x0000, 0x2b00, 0x0000, 0x0000, 0x0000, 0x0000,
+ 0xcb58, 0x0000, 0x0000, 0x0000, 0xc008, 0x0000, 0x0000, 0x0000,
+ 0x0000, 0x0000, 0x0000, 0x2b00, 0x0000, 0x0000, 0x0000, 0x0000,
+ 0xd4d8, 0x0000, 0x0000, 0x0000, 0xc008, 0x0000, 0x0000, 0x0000,
+};
+
+static const struct k3_ddr_phy_cfg lp5_post_train_cfg[] = {
+ K3_DDR_PHY_WRITE_SINGLE(0x908f0, 0x0065),
+ K3_DDR_PHY_WRITE_SINGLE(0x908f1, 0x012c),
+ K3_DDR_PHY_WRITE_SINGLE(0x908f2, 0x0000),
+ K3_DDR_PHY_WRITE_SINGLE(0x908f3, 0x0058),
+ K3_DDR_PHY_WRITE_SINGLE(0x908f4, 0x0014),
+ K3_DDR_PHY_WRITE_SINGLE(0x908f5, 0x0000),
+ K3_DDR_PHY_WRITE_SINGLE(0x908f6, 0x00b0),
+ K3_DDR_PHY_WRITE_SINGLE(0x908f7, 0x0000),
+ K3_DDR_PHY_WRITE_RANGE(0x41008, lp5_post_training_table_2),
+ K3_DDR_PHY_WRITE_SINGLE(0x20015, 0x0000),
+ K3_DDR_PHY_WRITE_SINGLE(0x3004a, 0x0000),
+ K3_DDR_PHY_WRITE_SINGLE(0x3004b, 0x0000),
+ K3_DDR_PHY_WRITE_SINGLE(0x3104a, 0x0000),
+ K3_DDR_PHY_WRITE_SINGLE(0x3104b, 0x0000),
+ K3_DDR_PHY_WRITE_SINGLE(0x2004c, 0x2c0f),
+ K3_DDR_PHY_WRITE_SINGLE(0x2004d, 0x0000),
+ K3_DDR_PHY_WRITE_SINGLE(0x20041, 0x0000),
+ K3_DDR_PHY_WRITE_SINGLE(0x90802, 0x0000),
+ K3_DDR_PHY_WRITE_SINGLE(0x20045, 0x0002),
+ K3_DDR_PHY_WRITE_SINGLE(0x10057, 0x0001),
+ K3_DDR_PHY_WRITE_SINGLE(0x11057, 0x0001),
+ K3_DDR_PHY_WRITE_SINGLE(0x12057, 0x0001),
+ K3_DDR_PHY_WRITE_SINGLE(0x13057, 0x0001),
+ K3_DDR_PHY_WRITE_SINGLE(0x1000f, 0x1089),
+ K3_DDR_PHY_WRITE_SINGLE(0x1100f, 0x1089),
+ K3_DDR_PHY_WRITE_SINGLE(0x1200f, 0x1089),
+ K3_DDR_PHY_WRITE_SINGLE(0x1300f, 0x1089),
+ K3_DDR_PHY_WRITE_SINGLE(0x90803, 0x0004),
+ K3_DDR_PHY_WRITE_SINGLE(0x90804, 0x0082),
+ K3_DDR_PHY_WRITE_SINGLE(0x90805, 0x0001),
+ K3_DDR_PHY_WRITE_SINGLE(0x90903, 0x0001),
+ K3_DDR_PHY_WRITE_SINGLE(0x9090b, 0x0002),
+ K3_DDR_PHY_WRITE_SINGLE(0x90811, 0x0000),
+ K3_DDR_PHY_WRITE_SINGLE(0x90812, 0xff00),
+ K3_DDR_PHY_WRITE_SINGLE(0x20072, 0x0003),
+ K3_DDR_PHY_WRITE_SINGLE(0x9080e, 0x0003),
+ K3_DDR_PHY_WRITE_SINGLE(0x20073, 0x0003),
+ K3_DDR_PHY_WRITE_SINGLE(0x9080f, 0x0003),
+ K3_DDR_PHY_WRITE_SINGLE(0xd0000, 0x0000),
+ K3_DDR_PHY_WRITE_SINGLE(0x41000, 0x0000),
+ K3_DDR_PHY_WRITE_SINGLE(0x41001, 0x0000),
+ K3_DDR_PHY_WRITE_SINGLE(0x41002, 0x0000),
+ K3_DDR_PHY_WRITE_SINGLE(0x41003, 0x0000),
+ K3_DDR_PHY_WRITE_SINGLE(0x41004, 0x0000),
+ K3_DDR_PHY_WRITE_SINGLE(0x41005, 0x0000),
+ K3_DDR_PHY_WRITE_SINGLE(0x41006, 0x0000),
+ K3_DDR_PHY_WRITE_SINGLE(0x41007, 0x0000),
+ K3_DDR_PHY_WRITE_RANGE(0x41388, lp5_post_training_table_16),
+ K3_DDR_PHY_WRITE_RANGE(0x9002e, lp5_post_training_table_17),
+ K3_DDR_PHY_WRITE_SINGLE(0x90500, 0x0150),
+ K3_DDR_PHY_WRITE_SINGLE(0x90501, 0x0809),
+ K3_DDR_PHY_WRITE_SINGLE(0x90502, 0x0002),
+ K3_DDR_PHY_WRITE_SINGLE(0x90503, 0x0370),
+ K3_DDR_PHY_WRITE_SINGLE(0x90504, 0x0809),
+ K3_DDR_PHY_WRITE_SINGLE(0x90505, 0x0000),
+ K3_DDR_PHY_WRITE_SINGLE(0x90506, 0x0400),
+ K3_DDR_PHY_WRITE_SINGLE(0x90507, 0x080e),
+ K3_DDR_PHY_WRITE_SINGLE(0x90508, 0x0008),
+ K3_DDR_PHY_WRITE_SINGLE(0x90509, 0xc848),
+ K3_DDR_PHY_WRITE_SINGLE(0x9050a, 0x0c0c),
+ K3_DDR_PHY_WRITE_SINGLE(0x9050b, 0x0000),
+ K3_DDR_PHY_WRITE_SINGLE(0x9050c, 0xc890),
+ K3_DDR_PHY_WRITE_SINGLE(0x9050d, 0x0804),
+ K3_DDR_PHY_WRITE_SINGLE(0xd00e7, 0x0600),
+ K3_DDR_PHY_WRITE_SINGLE(0x9001c, 0x0000),
+ K3_DDR_PHY_WRITE_SINGLE(0x90020, 0x0075),
+ K3_DDR_PHY_WRITE_SINGLE(0x90024, 0x0080),
+ K3_DDR_PHY_WRITE_SINGLE(0x90025, 0x002a),
+ K3_DDR_PHY_WRITE_SINGLE(0x90026, 0x002a),
+ K3_DDR_PHY_WRITE_SINGLE(0x9002b, 0x0103),
+ K3_DDR_PHY_WRITE_SINGLE(0x90708, 0x0118),
+ K3_DDR_PHY_WRITE_SINGLE(0x90700, 0x013e),
+ K3_DDR_PHY_WRITE_SINGLE(0x90701, 0x0160),
+ K3_DDR_PHY_WRITE_SINGLE(0x90702, 0x017f),
+ K3_DDR_PHY_WRITE_SINGLE(0x90703, 0x011e),
+ K3_DDR_PHY_WRITE_SINGLE(0x90704, 0x0000),
+ K3_DDR_PHY_WRITE_SINGLE(0x90705, 0x0000),
+ K3_DDR_PHY_WRITE_SINGLE(0x90706, 0x0000),
+ K3_DDR_PHY_WRITE_SINGLE(0x90707, 0x0000),
+ K3_DDR_PHY_WRITE_SINGLE(0x2018a, 0x0000),
+ K3_DDR_PHY_WRITE_SINGLE(0x20124, 0x0001),
+ K3_DDR_PHY_WRITE_SINGLE(0x2018b, 0x0016),
+ K3_DDR_PHY_WRITE_SINGLE(0x20125, 0x0039),
+ K3_DDR_PHY_WRITE_SINGLE(0x2018c, 0x004e),
+ K3_DDR_PHY_WRITE_SINGLE(0x20126, 0x0001),
+ K3_DDR_PHY_WRITE_SINGLE(0x2018d, 0x0016),
+ K3_DDR_PHY_WRITE_SINGLE(0x20127, 0x0039),
+ K3_DDR_PHY_WRITE_SINGLE(0x2018e, 0x004e),
+ K3_DDR_PHY_WRITE_SINGLE(0x20128, 0x0017),
+ K3_DDR_PHY_WRITE_SINGLE(0x2018f, 0x0027),
+ K3_DDR_PHY_WRITE_SINGLE(0x20129, 0x004f),
+ K3_DDR_PHY_WRITE_SINGLE(0x20190, 0x005f),
+ K3_DDR_PHY_WRITE_SINGLE(0x2012a, 0x0017),
+ K3_DDR_PHY_WRITE_SINGLE(0x20191, 0x0027),
+ K3_DDR_PHY_WRITE_SINGLE(0x2012b, 0x004f),
+ K3_DDR_PHY_WRITE_SINGLE(0x20192, 0x005f),
+ K3_DDR_PHY_WRITE_SINGLE(0x2012c, 0x0028),
+ K3_DDR_PHY_WRITE_SINGLE(0x20193, 0x0038),
+ K3_DDR_PHY_WRITE_SINGLE(0x2012d, 0x0060),
+ K3_DDR_PHY_WRITE_SINGLE(0x20194, 0x0070),
+ K3_DDR_PHY_WRITE_SINGLE(0x2012e, 0x0028),
+ K3_DDR_PHY_WRITE_SINGLE(0x20195, 0x0038),
+ K3_DDR_PHY_WRITE_SINGLE(0x2012f, 0x0060),
+ K3_DDR_PHY_WRITE_SINGLE(0x20196, 0x0070),
+ K3_DDR_PHY_WRITE_SINGLE(0x20130, 0x0080),
+ K3_DDR_PHY_WRITE_SINGLE(0x20197, 0x0080),
+ K3_DDR_PHY_WRITE_SINGLE(0x20131, 0x0080),
+ K3_DDR_PHY_WRITE_SINGLE(0x20198, 0x0080),
+ K3_DDR_PHY_WRITE_SINGLE(0x20132, 0x0080),
+ K3_DDR_PHY_WRITE_SINGLE(0x20199, 0x0080),
+ K3_DDR_PHY_WRITE_SINGLE(0x20133, 0x0080),
+ K3_DDR_PHY_WRITE_SINGLE(0x2019a, 0x0080),
+ K3_DDR_PHY_WRITE_SINGLE(0x20134, 0x0071),
+ K3_DDR_PHY_WRITE_SINGLE(0x2019b, 0x0074),
+ K3_DDR_PHY_WRITE_SINGLE(0x20135, 0x0077),
+ K3_DDR_PHY_WRITE_SINGLE(0x2019c, 0x007a),
+ K3_DDR_PHY_WRITE_SINGLE(0x20136, 0x0071),
+ K3_DDR_PHY_WRITE_SINGLE(0x2019d, 0x0074),
+ K3_DDR_PHY_WRITE_SINGLE(0x20137, 0x0077),
+ K3_DDR_PHY_WRITE_SINGLE(0x2019e, 0x007a),
+ K3_DDR_PHY_WRITE_SINGLE(0x20138, 0x0075),
+ K3_DDR_PHY_WRITE_SINGLE(0x2019f, 0x0076),
+ K3_DDR_PHY_WRITE_SINGLE(0x20139, 0x007b),
+ K3_DDR_PHY_WRITE_SINGLE(0x201a0, 0x007c),
+ K3_DDR_PHY_WRITE_SINGLE(0x2013a, 0x0075),
+ K3_DDR_PHY_WRITE_SINGLE(0x201a1, 0x0076),
+ K3_DDR_PHY_WRITE_SINGLE(0x2013b, 0x007b),
+ K3_DDR_PHY_WRITE_SINGLE(0x201a2, 0x007c),
+ K3_DDR_PHY_WRITE_SINGLE(0x2013c, 0x007d),
+ K3_DDR_PHY_WRITE_SINGLE(0x201a3, 0x007e),
+ K3_DDR_PHY_WRITE_SINGLE(0x2013d, 0x007d),
+ K3_DDR_PHY_WRITE_SINGLE(0x201a4, 0x007e),
+ K3_DDR_PHY_WRITE_SINGLE(0x2013e, 0x007d),
+ K3_DDR_PHY_WRITE_SINGLE(0x201a5, 0x007e),
+ K3_DDR_PHY_WRITE_SINGLE(0x2013f, 0x007d),
+ K3_DDR_PHY_WRITE_SINGLE(0x201a6, 0x007e),
+ K3_DDR_PHY_WRITE_SINGLE(0x20140, 0x007f),
+ K3_DDR_PHY_WRITE_SINGLE(0x201a7, 0x007f),
+ K3_DDR_PHY_WRITE_SINGLE(0x20141, 0x007f),
+ K3_DDR_PHY_WRITE_SINGLE(0x201a8, 0x007f),
+ K3_DDR_PHY_WRITE_SINGLE(0x20142, 0x007f),
+ K3_DDR_PHY_WRITE_SINGLE(0x201a9, 0x007f),
+ K3_DDR_PHY_WRITE_SINGLE(0x20143, 0x007f),
+ K3_DDR_PHY_WRITE_SINGLE(0x201aa, 0x007f),
+ K3_DDR_PHY_WRITE_SINGLE(0x20144, 0x0080),
+ K3_DDR_PHY_WRITE_SINGLE(0x201ab, 0x007f),
+ K3_DDR_PHY_WRITE_SINGLE(0x20145, 0x0080),
+ K3_DDR_PHY_WRITE_SINGLE(0x201ac, 0x007f),
+ K3_DDR_PHY_WRITE_SINGLE(0x20146, 0x0080),
+ K3_DDR_PHY_WRITE_SINGLE(0x201ad, 0x007f),
+ K3_DDR_PHY_WRITE_SINGLE(0x20147, 0x0080),
+ K3_DDR_PHY_WRITE_SINGLE(0x201ae, 0x007f),
+ K3_DDR_PHY_WRITE_SINGLE(0x20148, 0x0081),
+ K3_DDR_PHY_WRITE_SINGLE(0x201af, 0x0093),
+ K3_DDR_PHY_WRITE_SINGLE(0x20149, 0x0081),
+ K3_DDR_PHY_WRITE_SINGLE(0x201b0, 0x0093),
+ K3_DDR_PHY_WRITE_SINGLE(0x2014a, 0x010a),
+ K3_DDR_PHY_WRITE_SINGLE(0x201b1, 0x011b),
+ K3_DDR_PHY_WRITE_SINGLE(0x2014b, 0x010a),
+ K3_DDR_PHY_WRITE_SINGLE(0x201b2, 0x011b),
+ K3_DDR_PHY_WRITE_SINGLE(0x2014c, 0x0094),
+ K3_DDR_PHY_WRITE_SINGLE(0x201b3, 0x009b),
+ K3_DDR_PHY_WRITE_SINGLE(0x2014d, 0x0094),
+ K3_DDR_PHY_WRITE_SINGLE(0x201b4, 0x009b),
+ K3_DDR_PHY_WRITE_SINGLE(0x2014e, 0x011c),
+ K3_DDR_PHY_WRITE_SINGLE(0x201b5, 0x0122),
+ K3_DDR_PHY_WRITE_SINGLE(0x2014f, 0x011c),
+ K3_DDR_PHY_WRITE_SINGLE(0x201b6, 0x0122),
+ K3_DDR_PHY_WRITE_SINGLE(0x20150, 0x009c),
+ K3_DDR_PHY_WRITE_SINGLE(0x201b7, 0x00af),
+ K3_DDR_PHY_WRITE_SINGLE(0x20151, 0x009c),
+ K3_DDR_PHY_WRITE_SINGLE(0x201b8, 0x00af),
+ K3_DDR_PHY_WRITE_SINGLE(0x20152, 0x0123),
+ K3_DDR_PHY_WRITE_SINGLE(0x201b9, 0x0132),
+ K3_DDR_PHY_WRITE_SINGLE(0x20153, 0x0123),
+ K3_DDR_PHY_WRITE_SINGLE(0x201ba, 0x0132),
+ K3_DDR_PHY_WRITE_SINGLE(0x20154, 0x00b0),
+ K3_DDR_PHY_WRITE_SINGLE(0x201bb, 0x00c0),
+ K3_DDR_PHY_WRITE_SINGLE(0x20155, 0x00b0),
+ K3_DDR_PHY_WRITE_SINGLE(0x201bc, 0x00c0),
+ K3_DDR_PHY_WRITE_SINGLE(0x20156, 0x0133),
+ K3_DDR_PHY_WRITE_SINGLE(0x201bd, 0x0143),
+ K3_DDR_PHY_WRITE_SINGLE(0x20157, 0x0133),
+ K3_DDR_PHY_WRITE_SINGLE(0x201be, 0x0143),
+ K3_DDR_PHY_WRITE_SINGLE(0x20158, 0x00c1),
+ K3_DDR_PHY_WRITE_SINGLE(0x201bf, 0x00ca),
+ K3_DDR_PHY_WRITE_SINGLE(0x20159, 0x00c1),
+ K3_DDR_PHY_WRITE_SINGLE(0x201c0, 0x00ca),
+ K3_DDR_PHY_WRITE_SINGLE(0x2015a, 0x0144),
+ K3_DDR_PHY_WRITE_SINGLE(0x201c1, 0x014d),
+ K3_DDR_PHY_WRITE_SINGLE(0x2015b, 0x0144),
+ K3_DDR_PHY_WRITE_SINGLE(0x201c2, 0x014d),
+ K3_DDR_PHY_WRITE_SINGLE(0x2015c, 0x00cb),
+ K3_DDR_PHY_WRITE_SINGLE(0x201c3, 0x00d4),
+ K3_DDR_PHY_WRITE_SINGLE(0x2015d, 0x00cb),
+ K3_DDR_PHY_WRITE_SINGLE(0x201c4, 0x00d4),
+ K3_DDR_PHY_WRITE_SINGLE(0x2015e, 0x014e),
+ K3_DDR_PHY_WRITE_SINGLE(0x201c5, 0x0157),
+ K3_DDR_PHY_WRITE_SINGLE(0x2015f, 0x014e),
+ K3_DDR_PHY_WRITE_SINGLE(0x201c6, 0x0157),
+ K3_DDR_PHY_WRITE_SINGLE(0x20160, 0x00d5),
+ K3_DDR_PHY_WRITE_SINGLE(0x201c7, 0x00df),
+ K3_DDR_PHY_WRITE_SINGLE(0x20161, 0x00d5),
+ K3_DDR_PHY_WRITE_SINGLE(0x201c8, 0x00df),
+ K3_DDR_PHY_WRITE_SINGLE(0x20162, 0x0158),
+ K3_DDR_PHY_WRITE_SINGLE(0x201c9, 0x0161),
+ K3_DDR_PHY_WRITE_SINGLE(0x20163, 0x0158),
+ K3_DDR_PHY_WRITE_SINGLE(0x201ca, 0x0161),
+ K3_DDR_PHY_WRITE_SINGLE(0x20164, 0x00e0),
+ K3_DDR_PHY_WRITE_SINGLE(0x201cb, 0x00ee),
+ K3_DDR_PHY_WRITE_SINGLE(0x20165, 0x00e0),
+ K3_DDR_PHY_WRITE_SINGLE(0x201cc, 0x00ee),
+ K3_DDR_PHY_WRITE_SINGLE(0x20166, 0x0162),
+ K3_DDR_PHY_WRITE_SINGLE(0x201cd, 0x0170),
+ K3_DDR_PHY_WRITE_SINGLE(0x20167, 0x0162),
+ K3_DDR_PHY_WRITE_SINGLE(0x201ce, 0x0170),
+ K3_DDR_PHY_WRITE_SINGLE(0x20168, 0x00ef),
+ K3_DDR_PHY_WRITE_SINGLE(0x201cf, 0x00f9),
+ K3_DDR_PHY_WRITE_SINGLE(0x20169, 0x00ef),
+ K3_DDR_PHY_WRITE_SINGLE(0x201d0, 0x00f9),
+ K3_DDR_PHY_WRITE_SINGLE(0x2016a, 0x0171),
+ K3_DDR_PHY_WRITE_SINGLE(0x201d1, 0x017a),
+ K3_DDR_PHY_WRITE_SINGLE(0x2016b, 0x0171),
+ K3_DDR_PHY_WRITE_SINGLE(0x201d2, 0x017a),
+ K3_DDR_PHY_WRITE_SINGLE(0x2016c, 0x00fa),
+ K3_DDR_PHY_WRITE_SINGLE(0x201d3, 0x0108),
+ K3_DDR_PHY_WRITE_SINGLE(0x2016d, 0x00fa),
+ K3_DDR_PHY_WRITE_SINGLE(0x201d4, 0x0108),
+ K3_DDR_PHY_WRITE_SINGLE(0x2016e, 0x017b),
+ K3_DDR_PHY_WRITE_SINGLE(0x201d5, 0x0189),
+ K3_DDR_PHY_WRITE_SINGLE(0x2016f, 0x017b),
+ K3_DDR_PHY_WRITE_SINGLE(0x201d6, 0x0189),
+ K3_DDR_PHY_WRITE_SINGLE(0x20170, 0x0109),
+ K3_DDR_PHY_WRITE_SINGLE(0x201d7, 0x0109),
+ K3_DDR_PHY_WRITE_SINGLE(0x20171, 0x0109),
+ K3_DDR_PHY_WRITE_SINGLE(0x201d8, 0x0109),
+ K3_DDR_PHY_WRITE_SINGLE(0x20172, 0x018a),
+ K3_DDR_PHY_WRITE_SINGLE(0x201d9, 0x018a),
+ K3_DDR_PHY_WRITE_SINGLE(0x20173, 0x018a),
+ K3_DDR_PHY_WRITE_SINGLE(0x201da, 0x018a),
+ K3_DDR_PHY_WRITE_SINGLE(0x41613, 0x0b00),
+ K3_DDR_PHY_WRITE_SINGLE(0x41617, 0x0000),
+ K3_DDR_PHY_WRITE_SINGLE(0x4163b, 0x0b00),
+ K3_DDR_PHY_WRITE_SINGLE(0x4163f, 0x0000),
+ K3_DDR_PHY_WRITE_SINGLE(0x41663, 0x0b00),
+ K3_DDR_PHY_WRITE_SINGLE(0x41667, 0x0000),
+ K3_DDR_PHY_WRITE_SINGLE(0x4168b, 0x0b00),
+ K3_DDR_PHY_WRITE_SINGLE(0x4168f, 0x0000),
+ K3_DDR_PHY_WRITE_SINGLE(0x41723, 0x0b00),
+ K3_DDR_PHY_WRITE_SINGLE(0x41727, 0x0000),
+ K3_DDR_PHY_WRITE_SINGLE(0x4174b, 0x0b00),
+ K3_DDR_PHY_WRITE_SINGLE(0x4174f, 0x0000),
+ K3_DDR_PHY_WRITE_SINGLE(0x417f3, 0x0b00),
+ K3_DDR_PHY_WRITE_SINGLE(0x417f7, 0x0000),
+ K3_DDR_PHY_WRITE_SINGLE(0x4181b, 0x0b00),
+ K3_DDR_PHY_WRITE_SINGLE(0x4181f, 0x0000),
+ K3_DDR_PHY_WRITE_SINGLE(0x41a2b, 0x6b00),
+ K3_DDR_PHY_WRITE_SINGLE(0x41a2f, 0x0000),
+ K3_DDR_PHY_WRITE_SINGLE(0x41a53, 0x3b00),
+ K3_DDR_PHY_WRITE_SINGLE(0x41a57, 0x0800),
+ K3_DDR_PHY_WRITE_SINGLE(0x41a7b, 0x6b00),
+ K3_DDR_PHY_WRITE_SINGLE(0x41a7f, 0x0000),
+ K3_DDR_PHY_WRITE_SINGLE(0x41aa3, 0x3b00),
+ K3_DDR_PHY_WRITE_SINGLE(0x41aa7, 0x0800),
+ K3_DDR_PHY_WRITE_SINGLE(0x41b33, 0x6b00),
+ K3_DDR_PHY_WRITE_SINGLE(0x41b37, 0x0000),
+ K3_DDR_PHY_WRITE_SINGLE(0x41b5b, 0x3b00),
+ K3_DDR_PHY_WRITE_SINGLE(0x41b5f, 0x0800),
+ K3_DDR_PHY_WRITE_SINGLE(0x41bfb, 0x6b00),
+ K3_DDR_PHY_WRITE_SINGLE(0x41bff, 0x0000),
+ K3_DDR_PHY_WRITE_SINGLE(0x41c23, 0x3b00),
+ K3_DDR_PHY_WRITE_SINGLE(0x41c27, 0x0800),
+ K3_DDR_PHY_WRITE_RANGE(0x41008, lp5_post_training_table_23),
+ K3_DDR_PHY_WRITE_SINGLE(0xc0001, 0x5061),
+ K3_DDR_PHY_WRITE_SINGLE(0xc0002, 0x7098),
+ K3_DDR_PHY_WRITE_SINGLE(0xc0003, 0x0000),
+ K3_DDR_PHY_WRITE_SINGLE(0xc0000, 0xbedc),
+ K3_DDR_PHY_WRITE_SINGLE(0xc0006, 0xb0db),
+ K3_DDR_PHY_WRITE_SINGLE(0xc0007, 0x0000),
+ K3_DDR_PHY_WRITE_SINGLE(0x9070c, 0x0000),
+ K3_DDR_PHY_WRITE_SINGLE(0x9070d, 0x07ff),
+ K3_DDR_PHY_WRITE_SINGLE(0x9070e, 0x0668),
+ K3_DDR_PHY_WRITE_SINGLE(0x90c13, 0x0000),
+ K3_DDR_PHY_WRITE_SINGLE(0x9070f, 0x7910),
+ K3_DDR_PHY_WRITE_SINGLE(0x90710, 0x355e),
+ K3_DDR_PHY_WRITE_SINGLE(0x90711, 0xcbb5),
+ K3_DDR_PHY_WRITE_SINGLE(0x90713, 0xffff),
+ K3_DDR_PHY_WRITE_SINGLE(0x90714, 0x0710),
+ K3_DDR_PHY_WRITE_SINGLE(0x90715, 0x7800),
+ K3_DDR_PHY_WRITE_SINGLE(0x90c12, 0xff10),
+ K3_DDR_PHY_WRITE_SINGLE(0x90712, 0x2ee8),
+ K3_DDR_PHY_WRITE_SINGLE(0x90716, 0xffdf),
+ K3_DDR_PHY_WRITE_SINGLE(0x90717, 0x6f10),
+ K3_DDR_PHY_WRITE_SINGLE(0x90718, 0x6f10),
+ K3_DDR_PHY_WRITE_SINGLE(0x90719, 0x2868),
+ K3_DDR_PHY_WRITE_SINGLE(0x9071a, 0x2868),
+ K3_DDR_PHY_WRITE_SINGLE(0x9071b, 0xfeef),
+ K3_DDR_PHY_WRITE_SINGLE(0x90904, 0xe400),
+ K3_DDR_PHY_WRITE_SINGLE(0x90986, 0xe400),
+ K3_DDR_PHY_WRITE_SINGLE(0x90920, 0x0000),
+ K3_DDR_PHY_WRITE_SINGLE(0x90921, 0x0000),
+ K3_DDR_PHY_WRITE_SINGLE(0x90922, 0x0000),
+ K3_DDR_PHY_WRITE_SINGLE(0x90923, 0x0000),
+ K3_DDR_PHY_WRITE_SINGLE(0x90924, 0xff00),
+ K3_DDR_PHY_WRITE_SINGLE(0x90925, 0xff00),
+ K3_DDR_PHY_WRITE_SINGLE(0x90926, 0xff00),
+ K3_DDR_PHY_WRITE_SINGLE(0x90927, 0xff00),
+ K3_DDR_PHY_WRITE_SINGLE(0x90930, 0x4000),
+ K3_DDR_PHY_WRITE_SINGLE(0x90931, 0x2000),
+ K3_DDR_PHY_WRITE_SINGLE(0x90932, 0xff00),
+ K3_DDR_PHY_WRITE_SINGLE(0x90933, 0xff00),
+ K3_DDR_PHY_WRITE_SINGLE(0x9090a, 0x0000),
+ K3_DDR_PHY_WRITE_SINGLE(0x9090c, 0x0000),
+ K3_DDR_PHY_WRITE_SINGLE(0x9090d, 0x0001),
+ K3_DDR_PHY_WRITE_SINGLE(0x200f0, 0x27f7),
+ K3_DDR_PHY_WRITE_SINGLE(0x200f1, 0x2108),
+ K3_DDR_PHY_WRITE_SINGLE(0x200f2, 0x2108),
+ K3_DDR_PHY_WRITE_SINGLE(0x100b9, 0x0001),
+ K3_DDR_PHY_WRITE_SINGLE(0x100b1, 0x0180),
+ K3_DDR_PHY_WRITE_SINGLE(0x100ba, 0x0001),
+ K3_DDR_PHY_WRITE_SINGLE(0x100a2, 0x0000),
+ K3_DDR_PHY_WRITE_SINGLE(0x100b5, 0x0001),
+ K3_DDR_PHY_WRITE_SINGLE(0x110b9, 0x0001),
+ K3_DDR_PHY_WRITE_SINGLE(0x110b1, 0x0180),
+ K3_DDR_PHY_WRITE_SINGLE(0x110ba, 0x0001),
+ K3_DDR_PHY_WRITE_SINGLE(0x110a2, 0x0000),
+ K3_DDR_PHY_WRITE_SINGLE(0x110b5, 0x0001),
+ K3_DDR_PHY_WRITE_SINGLE(0x120b9, 0x0001),
+ K3_DDR_PHY_WRITE_SINGLE(0x120b1, 0x0180),
+ K3_DDR_PHY_WRITE_SINGLE(0x120ba, 0x0001),
+ K3_DDR_PHY_WRITE_SINGLE(0x120a2, 0x0000),
+ K3_DDR_PHY_WRITE_SINGLE(0x120b5, 0x0001),
+ K3_DDR_PHY_WRITE_SINGLE(0x130b9, 0x0001),
+ K3_DDR_PHY_WRITE_SINGLE(0x130b1, 0x0180),
+ K3_DDR_PHY_WRITE_SINGLE(0x130ba, 0x0001),
+ K3_DDR_PHY_WRITE_SINGLE(0x130a2, 0x0000),
+ K3_DDR_PHY_WRITE_SINGLE(0x130b5, 0x0001),
+ K3_DDR_PHY_WRITE_SINGLE(0x70024, 0x5a3c),
+ K3_DDR_PHY_WRITE_SINGLE(0x70025, 0x5a3c),
+ K3_DDR_PHY_WRITE_SINGLE(0x70026, 0x5a3c),
+ K3_DDR_PHY_WRITE_SINGLE(0x70027, 0x5a3c),
+ K3_DDR_PHY_WRITE_SINGLE(0x70028, 0x5a3c),
+ K3_DDR_PHY_WRITE_SINGLE(0x70029, 0x5a3c),
+ K3_DDR_PHY_WRITE_SINGLE(0x7002a, 0x5a3c),
+ K3_DDR_PHY_WRITE_SINGLE(0x7002b, 0x5a3c),
+ K3_DDR_PHY_WRITE_SINGLE(0x70124, 0x5a3c),
+ K3_DDR_PHY_WRITE_SINGLE(0x70125, 0x5a3c),
+ K3_DDR_PHY_WRITE_SINGLE(0x70126, 0x5a3c),
+ K3_DDR_PHY_WRITE_SINGLE(0x70127, 0x5a3c),
+ K3_DDR_PHY_WRITE_SINGLE(0x70128, 0x5a3c),
+ K3_DDR_PHY_WRITE_SINGLE(0x70129, 0x5a3c),
+ K3_DDR_PHY_WRITE_SINGLE(0x7012a, 0x5a3c),
+ K3_DDR_PHY_WRITE_SINGLE(0x7012b, 0x5a3c),
+ K3_DDR_PHY_WRITE_SINGLE(0x70224, 0x5a3c),
+ K3_DDR_PHY_WRITE_SINGLE(0x70225, 0x5a3c),
+ K3_DDR_PHY_WRITE_SINGLE(0x70226, 0x5a3c),
+ K3_DDR_PHY_WRITE_SINGLE(0x70227, 0x5a3c),
+ K3_DDR_PHY_WRITE_SINGLE(0x70228, 0x5a3c),
+ K3_DDR_PHY_WRITE_SINGLE(0x70229, 0x5a3c),
+ K3_DDR_PHY_WRITE_SINGLE(0x7022a, 0x5a3c),
+ K3_DDR_PHY_WRITE_SINGLE(0x7022b, 0x5a3c),
+ K3_DDR_PHY_WRITE_SINGLE(0x70324, 0x5a3c),
+ K3_DDR_PHY_WRITE_SINGLE(0x70325, 0x5a3c),
+ K3_DDR_PHY_WRITE_SINGLE(0x70326, 0x5a3c),
+ K3_DDR_PHY_WRITE_SINGLE(0x70327, 0x5a3c),
+ K3_DDR_PHY_WRITE_SINGLE(0x70328, 0x5a3c),
+ K3_DDR_PHY_WRITE_SINGLE(0x70329, 0x5a3c),
+ K3_DDR_PHY_WRITE_SINGLE(0x7032a, 0x5a3c),
+ K3_DDR_PHY_WRITE_SINGLE(0x7032b, 0x5a3c),
+ K3_DDR_PHY_WRITE_SINGLE(0x70424, 0x5a3c),
+ K3_DDR_PHY_WRITE_SINGLE(0x70425, 0x5a3c),
+ K3_DDR_PHY_WRITE_SINGLE(0x70426, 0x5a3c),
+ K3_DDR_PHY_WRITE_SINGLE(0x70427, 0x5a3c),
+ K3_DDR_PHY_WRITE_SINGLE(0x70428, 0x5a3c),
+ K3_DDR_PHY_WRITE_SINGLE(0x70429, 0x5a3c),
+ K3_DDR_PHY_WRITE_SINGLE(0x7042a, 0x5a3c),
+ K3_DDR_PHY_WRITE_SINGLE(0x7042b, 0x5a3c),
+ K3_DDR_PHY_WRITE_SINGLE(0x70524, 0x5a3c),
+ K3_DDR_PHY_WRITE_SINGLE(0x70525, 0x5a3c),
+ K3_DDR_PHY_WRITE_SINGLE(0x70526, 0x5a3c),
+ K3_DDR_PHY_WRITE_SINGLE(0x70527, 0x5a3c),
+ K3_DDR_PHY_WRITE_SINGLE(0x70528, 0x5a3c),
+ K3_DDR_PHY_WRITE_SINGLE(0x70529, 0x5a3c),
+ K3_DDR_PHY_WRITE_SINGLE(0x7052a, 0x5a3c),
+ K3_DDR_PHY_WRITE_SINGLE(0x7052b, 0x5a3c),
+ K3_DDR_PHY_WRITE_SINGLE(0x70624, 0x5a3c),
+ K3_DDR_PHY_WRITE_SINGLE(0x70625, 0x5a3c),
+ K3_DDR_PHY_WRITE_SINGLE(0x70626, 0x5a3c),
+ K3_DDR_PHY_WRITE_SINGLE(0x70627, 0x5a3c),
+ K3_DDR_PHY_WRITE_SINGLE(0x70628, 0x5a3c),
+ K3_DDR_PHY_WRITE_SINGLE(0x70629, 0x5a3c),
+ K3_DDR_PHY_WRITE_SINGLE(0x7062a, 0x5a3c),
+ K3_DDR_PHY_WRITE_SINGLE(0x7062b, 0x5a3c),
+ K3_DDR_PHY_WRITE_SINGLE(0x70724, 0x5a3c),
+ K3_DDR_PHY_WRITE_SINGLE(0x70725, 0x5a3c),
+ K3_DDR_PHY_WRITE_SINGLE(0x70726, 0x5a3c),
+ K3_DDR_PHY_WRITE_SINGLE(0x70727, 0x5a3c),
+ K3_DDR_PHY_WRITE_SINGLE(0x70728, 0x5a3c),
+ K3_DDR_PHY_WRITE_SINGLE(0x70729, 0x5a3c),
+ K3_DDR_PHY_WRITE_SINGLE(0x7072a, 0x5a3c),
+ K3_DDR_PHY_WRITE_SINGLE(0x7072b, 0x5a3c),
+ K3_DDR_PHY_WRITE_SINGLE(0x70824, 0x5a3c),
+ K3_DDR_PHY_WRITE_SINGLE(0x70825, 0x5a3c),
+ K3_DDR_PHY_WRITE_SINGLE(0x70826, 0x5a3c),
+ K3_DDR_PHY_WRITE_SINGLE(0x70827, 0x5a3c),
+ K3_DDR_PHY_WRITE_SINGLE(0x70828, 0x5a3c),
+ K3_DDR_PHY_WRITE_SINGLE(0x70829, 0x5a3c),
+ K3_DDR_PHY_WRITE_SINGLE(0x7082a, 0x5a3c),
+ K3_DDR_PHY_WRITE_SINGLE(0x7082b, 0x5a3c),
+ K3_DDR_PHY_WRITE_SINGLE(0x70065, 0x01ff),
+ K3_DDR_PHY_WRITE_SINGLE(0x2007e, 0x0033),
+ K3_DDR_PHY_WRITE_SINGLE(0x200ef, 0xffff),
+ K3_DDR_PHY_WRITE_SINGLE(0x90910, 0x0002),
+ K3_DDR_PHY_WRITE_SINGLE(0x20310, 0x0001),
+ K3_DDR_PHY_WRITE_SINGLE(0x20311, 0x0001),
+ K3_DDR_PHY_WRITE_SINGLE(0xc0080, 0x0002),
+ K3_DDR_PHY_WRITE_SINGLE(0xd0003, 0x0000),
+ K3_DDR_PHY_WRITE_SINGLE(0xd0000, 0x0001),
+};
+
+const struct k3_ddr_phy_table k3_ddr_lpddr5_post_train_table = {
+ .cfg = lp5_post_train_cfg,
+ .count = ARRAY_SIZE(lp5_post_train_cfg),
+};
+
+static const struct k3_ddr_phy_override lp5_post_srank_x16_override[] = {
+ {0x20072, 0x0001, 0},
+ {0x9080e, 0x0001, 0},
+ {0x20073, 0x0001, 0},
+ {0x9080f, 0x0001, 0},
+ {0x41a53, 0x2b00, 0},
+ {0x41aa3, 0x2b00, 0},
+ {0x41b5b, 0x2b00, 0},
+ {0x41c23, 0x2b00, 0},
+ {0x41a53, 0x2b00, 0},
+ {0x41aa3, 0x2b00, 0},
+ {0x41b5b, 0x2b00, 0},
+ {0x41c23, 0x2b00, 0},
+ {0x9090d, 0x0000, 0},
+ {0x2007e, 0x0011, 0},
+};
+
+const struct k3_ddr_phy_overrides k3_ddr_lpddr5_post_srank_x16_overrides = {
+ .regs = lp5_post_srank_x16_override,
+ .count = ARRAY_SIZE(lp5_post_srank_x16_override),
+};
+
+static const struct k3_ddr_phy_override lp5_post_drank_x16_override[] = {
+ {0x41a53, 0x2b00, 0},
+ {0x41aa3, 0x2b00, 0},
+ {0x41b5b, 0x2b00, 0},
+ {0x41c23, 0x2b00, 0},
+ {0x41a53, 0x2b00, 0},
+ {0x41aa3, 0x2b00, 0},
+ {0x41b5b, 0x2b00, 0},
+ {0x41c23, 0x2b00, 0},
+};
+
+const struct k3_ddr_phy_overrides k3_ddr_lpddr5_post_drank_x16_overrides = {
+ .regs = lp5_post_drank_x16_override,
+ .count = ARRAY_SIZE(lp5_post_drank_x16_override),
+};
diff --git a/drivers/ram/spacemit/k3/k3_ddr_phy.c b/drivers/ram/spacemit/k3/k3_ddr_phy.c
new file mode 100644
index 00000000000..9361ed8ae20
--- /dev/null
+++ b/drivers/ram/spacemit/k3/k3_ddr_phy.c
@@ -0,0 +1,149 @@
+// SPDX-License-Identifier: GPL-2.0-or-later
+/*
+ * Copyright (C) 2026 Junhui Liu <junhui.liu@pigmoral.tech>
+ */
+
+#include <asm/io.h>
+#include <errno.h>
+#include <linux/iopoll.h>
+
+#include "k3_ddr.h"
+
+#define K3_PHY_MICRO_MUX_SEL 0xd0000
+#define K3_PHY_MICRO_RESET 0xd0099
+
+#define K3_PHY_UCT_SHADOW_REGS 0xd0004
+#define K3_PHY_UCT_EMPTY BIT(0)
+#define K3_PHY_DCT_WRITE_PROT 0xd0031
+#define K3_PHY_UCT_WRITE_ONLY_SHADOW 0xd0032
+
+#define K3_PHY_MSG_STREAM 0x08
+#define K3_PHY_MSG_COMPLETE 0x07
+#define K3_PHY_MSG_ERROR 0xff
+
+#define K3_PHY_MSG_TIMEOUT_US 10000000
+
+void k3_phy_write(struct k3_ddr *ddr, unsigned int channel, u32 csr, u16 value)
+{
+ writel(value, ddr->phy[channel] + csr * sizeof(u32));
+}
+
+static u16 k3_phy_read(struct k3_ddr *ddr, unsigned int channel, u32 csr)
+{
+ return readl(ddr->phy[channel] + csr * sizeof(u32));
+}
+
+int k3_ddr_phy_load_imem(struct k3_ddr *ddr, unsigned int channel)
+{
+ const u16 *firmware = (const u16 *)ddr->imem_fw;
+ size_t words;
+ int i;
+
+ if (channel >= K3_DDR_NUM_CHANNELS || !firmware || ddr->imem_fw_size % sizeof(u16))
+ return -EINVAL;
+
+ words = ddr->imem_fw_size / sizeof(u16);
+
+ for (i = 0; i < words; i++)
+ k3_phy_write(ddr, channel, K3_PHY_PMU_IMEM_BASE + i, le16_to_cpu(firmware[i]));
+
+ return 0;
+}
+
+void k3_ddr_phy_zero_dmem(struct k3_ddr *ddr, unsigned int channel)
+{
+ u32 csr;
+
+ k3_phy_write(ddr, channel, K3_PHY_MICRO_MUX_SEL, 0);
+
+ for (csr = K3_PHY_PMU_DMEM_BASE; csr < K3_PHY_PMU_DMEM_BASE + K3_PHY_PMU_DMEM_SIZE; csr++)
+ k3_phy_write(ddr, channel, csr, 0);
+}
+
+void k3_ddr_phy_start_pmu(struct k3_ddr *ddr, unsigned int channel)
+{
+ k3_phy_write(ddr, channel, K3_PHY_MICRO_MUX_SEL, 1);
+
+ k3_phy_write(ddr, channel, K3_PHY_MICRO_RESET, 9);
+ k3_phy_write(ddr, channel, K3_PHY_MICRO_RESET, 1);
+ k3_phy_write(ddr, channel, K3_PHY_MICRO_RESET, 0);
+}
+
+void k3_ddr_phy_halt_pmu(struct k3_ddr *ddr, unsigned int channel)
+{
+ k3_phy_write(ddr, channel, K3_PHY_MICRO_RESET, 1);
+
+ k3_phy_write(ddr, channel, K3_PHY_MICRO_MUX_SEL, 0);
+}
+
+static int k3_phy_wait_mailbox(struct k3_ddr *ddr, unsigned int channel, bool empty)
+{
+ u16 value;
+
+ return read_poll_timeout(k3_phy_read, value, !!(value & K3_PHY_UCT_EMPTY) == empty,
+ 1, K3_PHY_MSG_TIMEOUT_US, ddr, channel, K3_PHY_UCT_SHADOW_REGS);
+}
+
+static int k3_phy_ack_message(struct k3_ddr *ddr, unsigned int channel)
+{
+ int ret;
+
+ k3_phy_write(ddr, channel, K3_PHY_DCT_WRITE_PROT, 0);
+
+ ret = k3_phy_wait_mailbox(ddr, channel, true);
+ if (ret)
+ return ret;
+
+ k3_phy_write(ddr, channel, K3_PHY_DCT_WRITE_PROT, 1);
+
+ return 0;
+}
+
+int k3_ddr_phy_wait_training(struct k3_ddr *ddr, unsigned int channel)
+{
+ u8 message_id;
+ u16 message;
+ int i, ret;
+ u16 count;
+
+ if (channel >= K3_DDR_NUM_CHANNELS)
+ return -EINVAL;
+
+ do {
+ ret = k3_phy_wait_mailbox(ddr, channel, false);
+ if (ret)
+ return ret;
+
+ message = k3_phy_read(ddr, channel, K3_PHY_UCT_WRITE_ONLY_SHADOW);
+ message_id = message & 0xff;
+
+ ret = k3_phy_ack_message(ddr, channel);
+ if (ret)
+ return ret;
+
+ if (message_id != K3_PHY_MSG_STREAM)
+ continue;
+
+ ret = k3_phy_wait_mailbox(ddr, channel, false);
+ if (ret)
+ return ret;
+
+ count = k3_phy_read(ddr, channel, K3_PHY_UCT_WRITE_ONLY_SHADOW);
+
+ ret = k3_phy_ack_message(ddr, channel);
+ if (ret)
+ return ret;
+
+ for (i = 0; i < count; i++) {
+ ret = k3_phy_wait_mailbox(ddr, channel, false);
+ if (ret)
+ return ret;
+
+ ret = k3_phy_ack_message(ddr, channel);
+ if (ret)
+ return ret;
+ }
+ } while (message_id != K3_PHY_MSG_COMPLETE && message_id != K3_PHY_MSG_ERROR);
+
+ return message_id == K3_PHY_MSG_COMPLETE ? 0 : -EIO;
+}
diff --git a/drivers/ram/spacemit/k3/k3_ddr_profile.c b/drivers/ram/spacemit/k3/k3_ddr_profile.c
new file mode 100644
index 00000000000..22ff4829968
--- /dev/null
+++ b/drivers/ram/spacemit/k3/k3_ddr_profile.c
@@ -0,0 +1,54 @@
+// SPDX-License-Identifier: GPL-2.0-or-later
+/*
+ * Copyright (C) 2025 SpacemiT
+ * Copyright (C) 2026 Junhui Liu <junhui.liu@pigmoral.tech>
+ */
+
+#include <linux/kernel.h>
+#include <linux/string.h>
+
+#include "k3_ddr.h"
+
+static const struct k3_ddr_profile k3_ddr_profiles[] = {
+ {
+ .part_number = "MT62F1G32D2DS",
+ .part_size_mb = 4096,
+ .ranks = 1,
+ .device_width = 16,
+ },
+ {
+ .part_number = "MT62F2G32D4DS",
+ .part_size_mb = 8192,
+ .ranks = 2,
+ .device_width = 16,
+ },
+ {
+ .part_number = "RS3G32LG5D8FDB",
+ .part_size_mb = 12288,
+ .ranks = 2,
+ .device_width = 8,
+ },
+ {
+ .part_number = "MT62F4G32D8DV",
+ .part_size_mb = 16384,
+ .ranks = 2,
+ .device_width = 8,
+ },
+};
+
+const struct k3_ddr_profile *k3_ddr_find_profile(const char *part_number)
+{
+ int i;
+
+ if (!part_number || !*part_number)
+ return NULL;
+
+ for (i = 0; i < ARRAY_SIZE(k3_ddr_profiles); i++) {
+ const struct k3_ddr_profile *profile = &k3_ddr_profiles[i];
+
+ if (!strcmp(part_number, profile->part_number))
+ return &k3_ddr_profiles[i];
+ }
+
+ return NULL;
+}
diff --git a/include/soc/spacemit/k3-ddr.h b/include/soc/spacemit/k3-ddr.h
new file mode 100644
index 00000000000..f89fe33a87b
--- /dev/null
+++ b/include/soc/spacemit/k3-ddr.h
@@ -0,0 +1,13 @@
+/* SPDX-License-Identifier: GPL-2.0-or-later */
+/* Copyright (C) 2026 Junhui Liu <junhui.liu@pigmoral.tech> */
+
+#ifndef _SOC_SPACEMIT_K3_DDR_H_
+#define _SOC_SPACEMIT_K3_DDR_H_
+
+#define K3_DDR_PART_NUMBER_LEN 32
+
+struct k3_ddr_plat {
+ char part_number[K3_DDR_PART_NUMBER_LEN];
+};
+
+#endif /* _SOC_SPACEMIT_K3_DDR_H_ */
--
2.56.0
^ permalink raw reply related [flat|nested] 9+ messages in thread
* [PATCH 2/5] riscv: spacemit: k3: Add SPL initialization support
2026-11-05 16:40 [PATCH 0/5] riscv: spacemit: k3: Add SPL LPDDR5 initialization Junhui Liu
2026-11-05 16:40 ` [PATCH 1/5] ram: spacemit: Add DDR driver for K3 SoC Junhui Liu
@ 2026-11-05 16:40 ` Junhui Liu
2026-11-05 16:40 ` [PATCH 3/5] riscv: dts: spacemit: k3: Add SPL device and image descriptions Junhui Liu
` (2 subsequent siblings)
4 siblings, 0 replies; 9+ messages in thread
From: Junhui Liu @ 2026-11-05 16:40 UTC (permalink / raw)
To: u-boot, Yao Zi, u-boot-spacemit
Cc: Tom Rini, Yixun Lan, Junhui Liu, Tim Ouyang, Leo Liang, E Shattow,
Huan Zhou, Eric Chung
Add SPL initialization support for SpacemiT K3. Enable instruction and
data caches and cache snooping during early hart initialization, and
provide the timer configuration needed for M-mode execution.
Initialize I2C and read the DDR part number from the board's TLV EEPROM.
Populate the RAM driver's platform data before probing it to initialize
DRAM. Set up the DRAM PMA boundary and record the RAM base and size in
global data.
Loading the next boot stage is not yet supported.
Signed-off-by: Junhui Liu <junhui.liu@pigmoral.tech>
---
arch/riscv/cpu/k3/Kconfig | 6 +-
arch/riscv/cpu/k3/Makefile | 1 +
arch/riscv/cpu/k3/spl.c | 52 ++++++++++++++
arch/riscv/include/asm/arch-k3/csr.h | 20 ++++++
arch/riscv/include/asm/arch-k3/spl.h | 11 +++
board/spacemit/k3/Makefile | 5 ++
board/spacemit/k3/spl.c | 127 +++++++++++++++++++++++++++++++++++
include/configs/spacemit-k3.h | 3 +
8 files changed, 224 insertions(+), 1 deletion(-)
diff --git a/arch/riscv/cpu/k3/Kconfig b/arch/riscv/cpu/k3/Kconfig
index 5474ac11243..dee79644b87 100644
--- a/arch/riscv/cpu/k3/Kconfig
+++ b/arch/riscv/cpu/k3/Kconfig
@@ -9,10 +9,14 @@ config SPACEMIT_K3
select BINMAN
select ARCH_EARLY_INIT_R
select SYS_CACHE_SHIFT_6
+ select SUPPORT_SPL
imply CPU
imply CPU_RISCV
- imply RISCV_TIMER if RISCV_SMODE
+ imply RISCV_TIMER if (RISCV_SMODE || SPL_RISCV_SMODE)
+ imply RISCV_ACLINT if RISCV_MMODE
+ imply SPL_RISCV_ACLINT if SPL_RISCV_MMODE
imply CMD_CPU
+ imply SPL_CPU
imply OF_UPSTREAM
endif
diff --git a/arch/riscv/cpu/k3/Makefile b/arch/riscv/cpu/k3/Makefile
index fba4e4b0a3f..6afe6caac69 100644
--- a/arch/riscv/cpu/k3/Makefile
+++ b/arch/riscv/cpu/k3/Makefile
@@ -3,3 +3,4 @@
# Copyright (C) 2026 Yixun Lan <dlan@kernel.org>
obj-y += dram.o
+obj-$(CONFIG_XPL_BUILD) += spl.o
diff --git a/arch/riscv/cpu/k3/spl.c b/arch/riscv/cpu/k3/spl.c
new file mode 100644
index 00000000000..e8ee32e37fd
--- /dev/null
+++ b/arch/riscv/cpu/k3/spl.c
@@ -0,0 +1,52 @@
+// SPDX-License-Identifier: GPL-2.0-or-later
+/*
+ * Copyright (C) 2026 Junhui Liu <junhui.liu@pigmoral.tech>
+ */
+
+#include <asm/arch/csr.h>
+#include <asm/arch/spl.h>
+#include <asm/csr.h>
+#include <asm/global_data.h>
+#include <dm.h>
+#include <ram.h>
+
+#define K3_DRAM_UPPER_LIMIT_ADDR 0x1100000000ULL
+
+DECLARE_GLOBAL_DATA_PTR;
+
+static void setup_dram_pma(void)
+{
+ csr_write(CSR_X100_PMAADDR8, K3_DRAM_UPPER_LIMIT_ADDR >> 2);
+ asm volatile("sfence.vma zero, zero" ::: "memory");
+}
+
+int spl_dram_init(void)
+{
+ struct ram_info info;
+ struct udevice *dev;
+ int ret;
+
+ ret = uclass_get_device(UCLASS_RAM, 0, &dev);
+ if (ret) {
+ printf("DRAM init failed: %d\n", ret);
+ return ret;
+ }
+
+ setup_dram_pma();
+
+ ret = ram_get_info(dev, &info);
+ if (ret)
+ return ret;
+
+ gd->ram_base = info.base;
+ gd->ram_size = info.size;
+
+ return 0;
+}
+
+void harts_early_init(void)
+{
+ csr_set(CSR_X100_CACHE_CTL, CSR_X100_CACHE_CTL_ICACHE_EN |
+ CSR_X100_CACHE_CTL_DCACHE_EN);
+ csr_set(CSR_X100_SNOOP_CTL, CSR_X100_SNOOP_CTL_EN);
+}
diff --git a/arch/riscv/include/asm/arch-k3/csr.h b/arch/riscv/include/asm/arch-k3/csr.h
new file mode 100644
index 00000000000..a6c3e6af9f5
--- /dev/null
+++ b/arch/riscv/include/asm/arch-k3/csr.h
@@ -0,0 +1,20 @@
+/* SPDX-License-Identifier: GPL-2.0-or-later */
+/*
+ * Copyright (C) 2026 Junhui Liu <junhui.liu@pigmoral.tech>
+ */
+
+#ifndef _ASM_ARCH_K3_CSR_H_
+#define _ASM_ARCH_K3_CSR_H_
+
+#include <linux/bitops.h>
+
+#define CSR_X100_CACHE_CTL 0x7c0
+#define CSR_X100_CACHE_CTL_ICACHE_EN BIT(1)
+#define CSR_X100_CACHE_CTL_DCACHE_EN BIT(0)
+
+#define CSR_X100_SNOOP_CTL 0x7f0
+#define CSR_X100_SNOOP_CTL_EN BIT(0)
+
+#define CSR_X100_PMAADDR8 0x7e8
+
+#endif /* _ASM_ARCH_K3_CSR_H_ */
diff --git a/arch/riscv/include/asm/arch-k3/spl.h b/arch/riscv/include/asm/arch-k3/spl.h
new file mode 100644
index 00000000000..7dda93cfda8
--- /dev/null
+++ b/arch/riscv/include/asm/arch-k3/spl.h
@@ -0,0 +1,11 @@
+/* SPDX-License-Identifier: GPL-2.0-or-later */
+/*
+ * Copyright (C) 2026 Junhui Liu <junhui.liu@pigmoral.tech>
+ */
+
+#ifndef _ASM_ARCH_K3_SPL_H_
+#define _ASM_ARCH_K3_SPL_H_
+
+int spl_dram_init(void);
+
+#endif /* _ASM_ARCH_K3_SPL_H_ */
diff --git a/board/spacemit/k3/Makefile b/board/spacemit/k3/Makefile
new file mode 100644
index 00000000000..67f30a40e6c
--- /dev/null
+++ b/board/spacemit/k3/Makefile
@@ -0,0 +1,5 @@
+# SPDX-License-Identifier: GPL-2.0-or-later
+#
+# Copyright (C) 2026 Junhui Liu <junhui.liu@pigmoral.tech>
+
+obj-$(CONFIG_SPL_BUILD) += spl.o
diff --git a/board/spacemit/k3/spl.c b/board/spacemit/k3/spl.c
new file mode 100644
index 00000000000..4798e5c9ebc
--- /dev/null
+++ b/board/spacemit/k3/spl.c
@@ -0,0 +1,127 @@
+// SPDX-License-Identifier: GPL-2.0-or-later
+/*
+ * Copyright (C) 2026 Junhui Liu <junhui.liu@pigmoral.tech>
+ */
+
+#include <asm/arch/spl.h>
+#include <asm/global_data.h>
+#include <asm/io.h>
+#include <display_options.h>
+#include <dm/device.h>
+#include <dm/uclass.h>
+#include <errno.h>
+#include <linux/delay.h>
+#include <linux/string.h>
+#include <soc/spacemit/k3-ddr.h>
+#include <spl.h>
+#include <tlv_eeprom.h>
+
+#define MUX_MODE5 5
+#define EDGE_NONE BIT(6)
+#define PULL_UP (6 << 13)
+#define I2C_PIN_CONFIG(x) ((x) | EDGE_NONE | PULL_UP)
+
+#define MFP_GPIO_46 0xd401e0b8
+#define MFP_GPIO_47 0xd401e0bc
+
+#define K3_TLV_CODE_DDR_PART_NUMBER 0x45
+
+DECLARE_GLOBAL_DATA_PTR;
+
+static void i2c_early_init(void)
+{
+ struct udevice *bus;
+
+ /* EEPROM uses I2C2 on GPIO46 and GPIO47. */
+ writel(I2C_PIN_CONFIG(MUX_MODE5), (void __iomem *)MFP_GPIO_46);
+ writel(I2C_PIN_CONFIG(MUX_MODE5), (void __iomem *)MFP_GPIO_47);
+
+ udelay(100);
+
+ uclass_first_device(UCLASS_I2C, &bus);
+ while (bus) {
+ uclass_next_device(&bus);
+ if (!bus)
+ break;
+ }
+}
+
+static int read_ddr_part_number(char *part, size_t part_size)
+{
+ struct tlvinfo_header *header;
+ u8 contents[TLV_INFO_MAX_LEN];
+ struct tlvinfo_tlv *entry;
+ u8 *end;
+ int ret;
+
+ ret = read_tlvinfo_tlv_eeprom(contents, &header, &entry, 0);
+ if (ret)
+ return ret;
+
+ end = (u8 *)(header + 1) + be16_to_cpu(header->totallen);
+
+ while ((u8 *)entry + sizeof(*entry) <= end) {
+ if ((u8 *)entry + sizeof(*entry) + entry->length > end)
+ return -EINVAL;
+
+ if (entry->type == TLV_CODE_CRC_32)
+ break;
+
+ if (entry->type == K3_TLV_CODE_DDR_PART_NUMBER) {
+ if (!entry->length || entry->length >= part_size)
+ return -EINVAL;
+
+ memcpy(part, entry->value, entry->length);
+ part[entry->length] = '\0';
+
+ return 0;
+ }
+
+ entry = (void *)(entry->value + entry->length);
+ }
+
+ return -ENOENT;
+}
+
+static int setup_ddr_plat(void)
+{
+ struct k3_ddr_plat *plat;
+ struct udevice *dev;
+
+ dev = uclass_try_first_device(UCLASS_RAM);
+ if (!dev)
+ return -ENODEV;
+
+ if (!device_is_compatible(dev, "spacemit,k3-ddrc"))
+ return -ENODEV;
+
+ plat = dev_get_plat(dev);
+
+ return read_ddr_part_number(plat->part_number, sizeof(plat->part_number));
+}
+
+int spl_board_init_f(void)
+{
+ int ret;
+
+ i2c_early_init();
+
+ ret = setup_ddr_plat();
+ if (ret) {
+ printf("DDR identification failed: %d\n", ret);
+ return ret;
+ }
+
+ puts("DRAM: ");
+ ret = spl_dram_init();
+ if (ret)
+ return ret;
+ print_size(gd->ram_size, "\n");
+
+ return 0;
+}
+
+u32 spl_boot_device(void)
+{
+ return BOOT_DEVICE_NONE;
+}
diff --git a/include/configs/spacemit-k3.h b/include/configs/spacemit-k3.h
index 9dd545e2a3b..ccd900ce91c 100644
--- a/include/configs/spacemit-k3.h
+++ b/include/configs/spacemit-k3.h
@@ -8,6 +8,9 @@
#define CFG_SYS_NS16550_IER 0x40
+#define RISCV_MMODE_TIMERBASE 0xf1810000
+#define RISCV_MMODE_TIMEROFF 0xbff8
+#define RISCV_MMODE_TIMER_FREQ 24000000
#define RISCV_SMODE_TIMER_FREQ 24000000
#endif /* __SPACEMIT_K3_H */
--
2.56.0
^ permalink raw reply related [flat|nested] 9+ messages in thread
* [PATCH 3/5] riscv: dts: spacemit: k3: Add SPL device and image descriptions
2026-11-05 16:40 [PATCH 0/5] riscv: spacemit: k3: Add SPL LPDDR5 initialization Junhui Liu
2026-11-05 16:40 ` [PATCH 1/5] ram: spacemit: Add DDR driver for K3 SoC Junhui Liu
2026-11-05 16:40 ` [PATCH 2/5] riscv: spacemit: k3: Add SPL initialization support Junhui Liu
@ 2026-11-05 16:40 ` Junhui Liu
2026-11-06 6:59 ` Yixun Lan
2026-11-05 16:40 ` [PATCH 4/5] configs: spacemit: k3: Enable SPL support Junhui Liu
2026-11-05 16:40 ` [PATCH 5/5] doc: spacemit: k3: Add SPL build instructions Junhui Liu
4 siblings, 1 reply; 9+ messages in thread
From: Junhui Liu @ 2026-11-05 16:40 UTC (permalink / raw)
To: u-boot, Yao Zi, u-boot-spacemit
Cc: Tom Rini, Yixun Lan, Junhui Liu, Tim Ouyang, Leo Liang, E Shattow,
Huan Zhou, Eric Chung
Add the DDR controller node and mark the UART, I2C EEPROM and required
clock and reset providers for use before DRAM initialization.
Add a binman description for spl/u-boot-spl-mkimage.bin, combining SPL
with the external LPDDR5 PMU IMEM firmware and wrapping the payload in
a SpacemiT K3 boot image header.
Signed-off-by: Junhui Liu <junhui.liu@pigmoral.tech>
---
arch/riscv/dts/spacemit-k3-binman.dtsi | 24 +++++++++++++++
arch/riscv/dts/spacemit-k3-u-boot.dtsi | 54 ++++++++++++++++++++++++++++++++++
2 files changed, 78 insertions(+)
diff --git a/arch/riscv/dts/spacemit-k3-binman.dtsi b/arch/riscv/dts/spacemit-k3-binman.dtsi
index f1c1c3ee6fd..3f77868a90c 100644
--- a/arch/riscv/dts/spacemit-k3-binman.dtsi
+++ b/arch/riscv/dts/spacemit-k3-binman.dtsi
@@ -4,3 +4,27 @@
*/
#include "binman.dtsi"
+
+&binman {
+#ifdef CONFIG_SPL
+ spl-img {
+ filename = "spl/u-boot-spl-mkimage.bin";
+
+ mkimage {
+ args = "-T", "smtimage", "-n", "k3";
+
+ u-boot-spl-ddr {
+ type = "section";
+
+ u-boot-spl {
+ };
+
+ lpddr5-imem {
+ filename = "lpddr5_imem.bin";
+ type = "blob-ext";
+ };
+ };
+ };
+ };
+#endif
+};
diff --git a/arch/riscv/dts/spacemit-k3-u-boot.dtsi b/arch/riscv/dts/spacemit-k3-u-boot.dtsi
index 352e85e7de8..0976b2647b5 100644
--- a/arch/riscv/dts/spacemit-k3-u-boot.dtsi
+++ b/arch/riscv/dts/spacemit-k3-u-boot.dtsi
@@ -4,3 +4,57 @@
*/
#include "spacemit-k3-binman.dtsi"
+
+&{/soc} {
+ ddrc@cb000000 {
+ compatible = "spacemit,k3-ddrc";
+ reg = <0x0 0xcb000000 0x0 0x01000000>,
+ <0x0 0xcc000000 0x0 0x01000000>;
+ spacemit,apmu = <&syscon_apmu 0x4e8>;
+ bootph-pre-ram;
+ };
+};
+
+&i2c2 {
+ bootph-pre-ram;
+
+ eeprom@50 {
+ bootph-pre-ram;
+ };
+};
+
+&osc_32k {
+ bootph-pre-ram;
+};
+
+&pll {
+ bootph-pre-ram;
+};
+
+&syscon_apbc {
+ bootph-pre-ram;
+};
+
+&syscon_apmu {
+ bootph-pre-ram;
+};
+
+&syscon_mpmu {
+ bootph-pre-ram;
+};
+
+&uart0 {
+ bootph-pre-ram;
+};
+
+&vctcxo_1m {
+ bootph-pre-ram;
+};
+
+&vctcxo_24m {
+ bootph-pre-ram;
+};
+
+&vctcxo_3m {
+ bootph-pre-ram;
+};
--
2.56.0
^ permalink raw reply related [flat|nested] 9+ messages in thread
* [PATCH 4/5] configs: spacemit: k3: Enable SPL support
2026-11-05 16:40 [PATCH 0/5] riscv: spacemit: k3: Add SPL LPDDR5 initialization Junhui Liu
` (2 preceding siblings ...)
2026-11-05 16:40 ` [PATCH 3/5] riscv: dts: spacemit: k3: Add SPL device and image descriptions Junhui Liu
@ 2026-11-05 16:40 ` Junhui Liu
2026-11-05 16:40 ` [PATCH 5/5] doc: spacemit: k3: Add SPL build instructions Junhui Liu
4 siblings, 0 replies; 9+ messages in thread
From: Junhui Liu @ 2026-11-05 16:40 UTC (permalink / raw)
To: u-boot, Yao Zi, u-boot-spacemit
Cc: Tom Rini, Yixun Lan, Junhui Liu, Tim Ouyang, Leo Liang, E Shattow,
Huan Zhou, Eric Chung
Enable the clock, reset, I2C and EEPROM support needed to read the DDR
part number, along with the K3 RAM driver for LPDDR5 initialization.
Place SPL at 0xc0801000, leaving 4 KiB at the start of SRAM for the boot
image header. Limit SPL to 256 KiB and allow another 64 KiB for the DDR
PMU firmware, placing BSS after this reserved area at 0xc0851000.
Reserve 4 KiB for BSS and set the initial stack top to the end of the
512 KiB SRAM window at 0xc0880000.
0xc0800000 +-------------------------+
| smtimage header | 4 KiB
0xc0801000 +-------------------------+
| SPL + DDR PMU firmware | 320 KiB budget
0xc0851000 +-------------------------+
| BSS | 4 KiB reserved
0xc0852000 +-------------------------+
| Free space |
| GD, early heap, stack |
0xc0880000 +-------------------------+ <- stack top
Signed-off-by: Junhui Liu <junhui.liu@pigmoral.tech>
---
configs/spacemit_k3_defconfig | 22 ++++++++++++++++++++++
1 file changed, 22 insertions(+)
diff --git a/configs/spacemit_k3_defconfig b/configs/spacemit_k3_defconfig
index f49442951c8..c2975759b51 100644
--- a/configs/spacemit_k3_defconfig
+++ b/configs/spacemit_k3_defconfig
@@ -8,8 +8,17 @@ CONFIG_ENV_SIZE=0x10000
CONFIG_ENV_OFFSET=0xa0000
CONFIG_DM_GPIO=y
CONFIG_DEFAULT_DEVICE_TREE="spacemit/k3-pico-itx"
+CONFIG_SPL_SYS_MALLOC_F_LEN=0x20000
+CONFIG_SPL_STACK=0xc0880000
+CONFIG_SPL_TEXT_BASE=0xc0801000
+CONFIG_SPL_BSS_START_ADDR=0xc0851000
+CONFIG_SPL_BSS_MAX_SIZE=0x1000
CONFIG_SYS_BOOTM_LEN=0xa000000
CONFIG_SYS_LOAD_ADDR=0x102000000
+# CONFIG_SPL_SHARES_INIT_SP_ADDR is not set
+CONFIG_SPL_HAVE_INIT_STACK=y
+CONFIG_SPL_SIZE_LIMIT=0x40000
+CONFIG_SPL=y
CONFIG_DEBUG_UART_BASE=0xd4017000
CONFIG_DEBUG_UART_CLOCK=14700000
CONFIG_TARGET_SPACEMIT_K3=y
@@ -17,14 +26,20 @@ CONFIG_ARCH_RV64I=y
CONFIG_CMODEL_MEDANY=y
CONFIG_RISCV_SMODE=y
CONFIG_RISCV_ISA_ZICBOM=y
+# CONFIG_SPL_SMP is not set
CONFIG_STACK_SIZE=0x100000
CONFIG_FIT=y
CONFIG_SUPPORT_RAW_INITRD=y
CONFIG_SYS_CBSIZE=256
CONFIG_SYS_PBSIZE=276
# CONFIG_BOARD_INIT is not set
+CONFIG_SPL_MAX_SIZE=0x40000
+# CONFIG_SPL_BINMAN_UBOOT_SYMBOLS is not set
+CONFIG_SPL_I2C=y
+CONFIG_SPL_DM_RESET=y
CONFIG_HUSH_PARSER=y
CONFIG_CMD_TLV_EEPROM=y
+CONFIG_SPL_CMD_TLV_EEPROM=y
CONFIG_CMD_GPIO=y
CONFIG_CMD_I2C=y
CONFIG_CMD_MTD=y
@@ -47,6 +62,8 @@ CONFIG_ENV_IS_IN_SPI_FLASH=y
CONFIG_NET_LWIP=y
CONFIG_NET_RANDOM_ETHADDR=y
CONFIG_SYSCON=y
+CONFIG_SPL_CLK=y
+CONFIG_SPL_CLK_CCF=y
CONFIG_CLK_SPACEMIT=y
CONFIG_CLK_SPACEMIT_K3=y
CONFIG_SPACEMIT_GPIO=y
@@ -54,6 +71,7 @@ CONFIG_DM_I2C=y
CONFIG_SYS_I2C_SPACEMIT_K1=y
CONFIG_MISC=y
CONFIG_I2C_EEPROM=y
+CONFIG_SPL_I2C_EEPROM=y
CONFIG_SPI_FLASH_GIGADEVICE=y
CONFIG_SPI_FLASH_WINBOND=y
CONFIG_SPI_FLASH_MTD=y
@@ -69,6 +87,9 @@ CONFIG_PMIC_SPACEMIT_P1=y
CONFIG_DM_REGULATOR=y
CONFIG_DM_REGULATOR_FIXED=y
CONFIG_DM_REGULATOR_SPACEMIT_P1=y
+CONFIG_RAM=y
+CONFIG_SPL_RAM=y
+CONFIG_SPL_SPACEMIT_K3_DDR=y
CONFIG_DEBUG_UART_NS16550=y
CONFIG_DEBUG_UART_SHIFT=2
CONFIG_DEBUG_UART_ANNOUNCE=y
@@ -77,3 +98,4 @@ CONFIG_SYS_NS16550_MEM32=y
CONFIG_SPI=y
CONFIG_FSL_QSPI=y
CONFIG_TIMER_EARLY=y
+CONFIG_SPL_LIB_RATIONAL=y
--
2.56.0
^ permalink raw reply related [flat|nested] 9+ messages in thread
* [PATCH 5/5] doc: spacemit: k3: Add SPL build instructions
2026-11-05 16:40 [PATCH 0/5] riscv: spacemit: k3: Add SPL LPDDR5 initialization Junhui Liu
` (3 preceding siblings ...)
2026-11-05 16:40 ` [PATCH 4/5] configs: spacemit: k3: Enable SPL support Junhui Liu
@ 2026-11-05 16:40 ` Junhui Liu
4 siblings, 0 replies; 9+ messages in thread
From: Junhui Liu @ 2026-11-05 16:40 UTC (permalink / raw)
To: u-boot, Yao Zi, u-boot-spacemit
Cc: Tom Rini, Yixun Lan, Junhui Liu, Tim Ouyang, Leo Liang, E Shattow,
Huan Zhou, Eric Chung
Document how to obtain the DDR firmware required to generate
spl/u-boot-spl-mkimage.bin.
Also switch the OpenSBI repository URL to upstream, which now includes
K3 support.
Signed-off-by: Junhui Liu <junhui.liu@pigmoral.tech>
---
doc/board/spacemit/spacemit-pico-itx.rst | 12 ++++++++----
1 file changed, 8 insertions(+), 4 deletions(-)
diff --git a/doc/board/spacemit/spacemit-pico-itx.rst b/doc/board/spacemit/spacemit-pico-itx.rst
index 18d11d6671b..8b3bf4d202c 100644
--- a/doc/board/spacemit/spacemit-pico-itx.rst
+++ b/doc/board/spacemit/spacemit-pico-itx.rst
@@ -19,8 +19,8 @@ Tree blob. OpenSBI may be first built as below:
.. code-block:: console
- # Clone OpenSBI fork sources with K3 specific patches
- git clone https://github.com/spacemit-com/opensbi-upstream opensbi
+ # Clone OpenSBI
+ git clone https://github.com/riscv-software-src/opensbi.git opensbi
cd opensbi
make PLATFORM=generic
@@ -29,14 +29,18 @@ Tree blob. OpenSBI may be first built as below:
.. code-block:: console
cd <U-Boot-dir>
+
+ # Download DDR firmware
+ wget https://github.com/spacemit-com/spacemit-firmware/raw/refs/heads/master/k3/k3-br-v1.0.10/lpddr5_imem.bin
+
make spacemit_k3_defconfig
make OPENSBI=<OpenSBI-dir>/build/platform/generic/firmware/fw_dynamic.bin
-This will generate u-boot.itb
+This will generate spl/u-boot-spl-mkimage.bin and u-boot.itb
Testing
~~~~~~~
-Currently there is no U-Boot SPL build target. It is required to use 'FSBL.bin' vendor
+Currently there is no full U-Boot SPL support. It is required to use 'FSBL.bin' vendor
board support package SPL for DDR initialization and testing u-boot.itb. Please test with
fastboot command via USB download.
--
2.56.0
^ permalink raw reply related [flat|nested] 9+ messages in thread
* Re: [PATCH 3/5] riscv: dts: spacemit: k3: Add SPL device and image descriptions
2026-11-05 16:40 ` [PATCH 3/5] riscv: dts: spacemit: k3: Add SPL device and image descriptions Junhui Liu
@ 2026-11-06 6:59 ` Yixun Lan
2026-11-07 9:06 ` Junhui Liu
0 siblings, 1 reply; 9+ messages in thread
From: Yixun Lan @ 2026-11-06 6:59 UTC (permalink / raw)
To: Junhui Liu
Cc: u-boot, Yao Zi, u-boot-spacemit, Tom Rini, Tim Ouyang, Leo Liang,
E Shattow, Huan Zhou, Eric Chung
Hi Junhui,
On 00:40 Fri 06 Nov , Junhui Liu wrote:
> Add the DDR controller node and mark the UART, I2C EEPROM and required
> clock and reset providers for use before DRAM initialization.
>
> Add a binman description for spl/u-boot-spl-mkimage.bin, combining SPL
> with the external LPDDR5 PMU IMEM firmware and wrapping the payload in
> a SpacemiT K3 boot image header.
>
> Signed-off-by: Junhui Liu <junhui.liu@pigmoral.tech>
> ---
> arch/riscv/dts/spacemit-k3-binman.dtsi | 24 +++++++++++++++
> arch/riscv/dts/spacemit-k3-u-boot.dtsi | 54 ++++++++++++++++++++++++++++++++++
> 2 files changed, 78 insertions(+)
>
..
> diff --git a/arch/riscv/dts/spacemit-k3-u-boot.dtsi b/arch/riscv/dts/spacemit-k3-u-boot.dtsi
> index 352e85e7de8..0976b2647b5 100644
> --- a/arch/riscv/dts/spacemit-k3-u-boot.dtsi
> +++ b/arch/riscv/dts/spacemit-k3-u-boot.dtsi
> @@ -4,3 +4,57 @@
> */
>
> #include "spacemit-k3-binman.dtsi"
> +
> +&{/soc} {
> + ddrc@cb000000 {
> + compatible = "spacemit,k3-ddrc";
> + reg = <0x0 0xcb000000 0x0 0x01000000>,
> + <0x0 0xcc000000 0x0 0x01000000>;
> + spacemit,apmu = <&syscon_apmu 0x4e8>;
> + bootph-pre-ram;
> + };
> +};
> +
I'm not sure if it's a good idea to also move "ddrc" to mainline kernel
dts, at least to reach a consensus about stable compatible name..
> +&i2c2 {
> + bootph-pre-ram;
> +
> + eeprom@50 {
> + bootph-pre-ram;
> + };
> +};
> +
For adding all "bootph-pre-ram" properties, I'd like to see patch
submission to mainline kernel tree, see similar thread for K1 SoC[1]
so eventually it will get synced to a proper directory under dts/upstream/..
But, I know it would take long time for the upstream dts hit into U-Boot
tree, so a compromised solution is that we temporarily accept this patch
before the sync, then fix it up later accordingly..
Link: https://lore.kernel.org/r/20261024092558.143621-1-alan.tseng.cs@gmail.com [1]
--
Yixun Lan (dlan)
^ permalink raw reply [flat|nested] 9+ messages in thread
* Re: [PATCH 3/5] riscv: dts: spacemit: k3: Add SPL device and image descriptions
2026-11-06 6:59 ` Yixun Lan
@ 2026-11-07 9:06 ` Junhui Liu
2026-11-07 11:08 ` E Shattow
0 siblings, 1 reply; 9+ messages in thread
From: Junhui Liu @ 2026-11-07 9:06 UTC (permalink / raw)
To: Yixun Lan, Junhui Liu
Cc: u-boot, Yao Zi, u-boot-spacemit, Tom Rini, Tim Ouyang, Leo Liang,
E Shattow, Huan Zhou, Eric Chung
Hi Yixun,
On Fri Nov 6, 2026 at 2:59 PM CST, Yixun Lan wrote:
> Hi Junhui,
>
> On 00:40 Fri 06 Nov , Junhui Liu wrote:
>> Add the DDR controller node and mark the UART, I2C EEPROM and required
>> clock and reset providers for use before DRAM initialization.
>>
>> Add a binman description for spl/u-boot-spl-mkimage.bin, combining SPL
>> with the external LPDDR5 PMU IMEM firmware and wrapping the payload in
>> a SpacemiT K3 boot image header.
>>
>> Signed-off-by: Junhui Liu <junhui.liu@pigmoral.tech>
>> ---
>> arch/riscv/dts/spacemit-k3-binman.dtsi | 24 +++++++++++++++
>> arch/riscv/dts/spacemit-k3-u-boot.dtsi | 54 ++++++++++++++++++++++++++++++++++
>> 2 files changed, 78 insertions(+)
>>
> ..
>> diff --git a/arch/riscv/dts/spacemit-k3-u-boot.dtsi b/arch/riscv/dts/spacemit-k3-u-boot.dtsi
>> index 352e85e7de8..0976b2647b5 100644
>> --- a/arch/riscv/dts/spacemit-k3-u-boot.dtsi
>> +++ b/arch/riscv/dts/spacemit-k3-u-boot.dtsi
>> @@ -4,3 +4,57 @@
>> */
>>
>> #include "spacemit-k3-binman.dtsi"
>> +
>> +&{/soc} {
>> + ddrc@cb000000 {
>> + compatible = "spacemit,k3-ddrc";
>> + reg = <0x0 0xcb000000 0x0 0x01000000>,
>> + <0x0 0xcc000000 0x0 0x01000000>;
>> + spacemit,apmu = <&syscon_apmu 0x4e8>;
>> + bootph-pre-ram;
>> + };
>> +};
>> +
> I'm not sure if it's a good idea to also move "ddrc" to mainline kernel
> dts, at least to reach a consensus about stable compatible name..
I see. I can try submitting a DT binding patch to the Linux kernel
mailing list later to get the DT node design reviewed and reach
consensus on the compatible string.
>
>> +&i2c2 {
>> + bootph-pre-ram;
>> +
>> + eeprom@50 {
>> + bootph-pre-ram;
>> + };
>> +};
>> +
> For adding all "bootph-pre-ram" properties, I'd like to see patch
> submission to mainline kernel tree, see similar thread for K1 SoC[1]
> so eventually it will get synced to a proper directory under dts/upstream/..
>
> But, I know it would take long time for the upstream dts hit into U-Boot
> tree, so a compromised solution is that we temporarily accept this patch
> before the sync, then fix it up later accordingly..
>
> Link: https://lore.kernel.org/r/20261024092558.143621-1-alan.tseng.cs@gmail.com [1]
I agree. However, since our SPL support is still incomplete, we may need
to add more nodes for pre-DRAM initialization. I'd prefer to wait until
the bring-up is complete and submit all the required DTS changes
together, rather than sending multiple incremental patches.
--
Best regards,
Junhui Liu
^ permalink raw reply [flat|nested] 9+ messages in thread
* Re: [PATCH 3/5] riscv: dts: spacemit: k3: Add SPL device and image descriptions
2026-11-07 9:06 ` Junhui Liu
@ 2026-11-07 11:08 ` E Shattow
0 siblings, 0 replies; 9+ messages in thread
From: E Shattow @ 2026-11-07 11:08 UTC (permalink / raw)
To: Junhui Liu, Yixun Lan
Cc: u-boot, Yao Zi, u-boot-spacemit, Tom Rini, Tim Ouyang, Leo Liang,
Huan Zhou, Eric Chung
Hi Junhui,
On 11/7/26 01:06, Junhui Liu wrote:
> Hi Yixun,
>
> On Fri Nov 6, 2026 at 2:59 PM CST, Yixun Lan wrote:
>> Hi Junhui,
>>
>> On 00:40 Fri 06 Nov , Junhui Liu wrote:
>>> Add the DDR controller node and mark the UART, I2C EEPROM and required
>>> clock and reset providers for use before DRAM initialization.
>>>
>>> Add a binman description for spl/u-boot-spl-mkimage.bin, combining SPL
>>> with the external LPDDR5 PMU IMEM firmware and wrapping the payload in
>>> a SpacemiT K3 boot image header.
>>>
>>> Signed-off-by: Junhui Liu <junhui.liu@pigmoral.tech>
>>> ---
>>> arch/riscv/dts/spacemit-k3-binman.dtsi | 24 +++++++++++++++
>>> arch/riscv/dts/spacemit-k3-u-boot.dtsi | 54 ++++++++++++++++++++++++++++++++++
>>> 2 files changed, 78 insertions(+)
>>>
>> ..
>>> diff --git a/arch/riscv/dts/spacemit-k3-u-boot.dtsi b/arch/riscv/dts/spacemit-k3-u-boot.dtsi
>>> index 352e85e7de8..0976b2647b5 100644
>>> --- a/arch/riscv/dts/spacemit-k3-u-boot.dtsi
>>> +++ b/arch/riscv/dts/spacemit-k3-u-boot.dtsi
>>> @@ -4,3 +4,57 @@
>>> */
>>>
>>> #include "spacemit-k3-binman.dtsi"
>>> +
>>> +&{/soc} {
>>> + ddrc@cb000000 {
>>> + compatible = "spacemit,k3-ddrc";
>>> + reg = <0x0 0xcb000000 0x0 0x01000000>,
>>> + <0x0 0xcc000000 0x0 0x01000000>;
>>> + spacemit,apmu = <&syscon_apmu 0x4e8>;
>>> + bootph-pre-ram;
>>> + };
>>> +};
>>> +
>> I'm not sure if it's a good idea to also move "ddrc" to mainline kernel
>> dts, at least to reach a consensus about stable compatible name..
>
> I see. I can try submitting a DT binding patch to the Linux kernel
> mailing list later to get the DT node design reviewed and reach
> consensus on the compatible string.
I think it is "memory-controller@cb000000" and then whatever compatible
is decided; for starfive JH7110 it is memory-controller@15700000 and
compatible "starfive,jh7110-dmc". Compatible "spacemit,k3-ddrc" is
equally likely to be accepted as anything else.
Send it upstream and insist on either a bootph-pre-ram hint for the
memory controller node or adding a label and see what happens with the
discussion. I don't think BootROM touches the memory controller, so it's
a weak justification but it may be less objectionable to seat a
bootph-pre-ram hint there than adding a label to reference it later on
as something that Linux will never see a driver for or reference in any
other way. I wouldn't complain if someone objected that had a clever
enough SPL they could argue that this was wasting valuable SRAM for, and
wanted to reverse that as not a strictly necessary or correct hardware
description; just flip it for a label upstream and whack it into U-Boot
&label { bootph-pre-ram; };. The label just seems like it will annoy
Linux maintainers more than sticking bootph-pre-ram in there directly.
Usually in Linux device tree, nodes are rejected unless there is an
driver in-tree that consumes the compatible. The notable situation of a
memory controller which does not, and logically will never have, any
driver in Linux because any driver necessarily is at a phase before
Linux is possible to have running; this is allowable to upstream that
node to Linux device tree on discretion of the maintainer.
>
>>
>>> +&i2c2 {
>>> + bootph-pre-ram;
>>> +
>>> + eeprom@50 {
>>> + bootph-pre-ram;
>>> + };
>>> +};
>>> +
>> For adding all "bootph-pre-ram" properties, I'd like to see patch
>> submission to mainline kernel tree, see similar thread for K1 SoC[1]
>> so eventually it will get synced to a proper directory under dts/upstream/..
I'd suggest just the BootROM SPL loader modes -adjacent nodes first...
that is going to be the bulk of it and the most effort but also does not
depend on what you do in SPL here now. Thankfully there is vendor
participation to answer questions about BootROM internals.
>>
>> But, I know it would take long time for the upstream dts hit into U-Boot
>> tree, so a compromised solution is that we temporarily accept this patch
>> before the sync, then fix it up later accordingly..
>>
>> Link: https://lore.kernel.org/r/20261024092558.143621-1-alan.tseng.cs@gmail.com [1]
>
> I agree. However, since our SPL support is still incomplete, we may need
> to add more nodes for pre-DRAM initialization. I'd prefer to wait until
> the bring-up is complete and submit all the required DTS changes
> together, rather than sending multiple incremental patches.
>
Device tree upstream is a hardware description for reference by software
and not the other way around. BootROM is hardware; what the possible
state of peripherals is as configured by BootROM SPL loader modes should
be described in devicetree for any SPL consumer loaded by the BootROM,
and bootph-pre-ram hints are a reasonable mechanism of filtering just
this for SRAM-constrained environment.
The additional bootph-pre-ram hints, not described by covering what
BootROM touches, might also be allowable but that is not guaranteed.
Start with sending a series to LKML with bootph-pre-ram hints for what
all BootROM SPL loader modes might configure.
-E
^ permalink raw reply [flat|nested] 9+ messages in thread
end of thread, other threads:[~2026-11-07 11:09 UTC | newest]
Thread overview: 9+ messages (download: mbox.gz follow: Atom feed
-- links below jump to the message on this page --
2026-11-05 16:40 [PATCH 0/5] riscv: spacemit: k3: Add SPL LPDDR5 initialization Junhui Liu
2026-11-05 16:40 ` [PATCH 1/5] ram: spacemit: Add DDR driver for K3 SoC Junhui Liu
2026-11-05 16:40 ` [PATCH 2/5] riscv: spacemit: k3: Add SPL initialization support Junhui Liu
2026-11-05 16:40 ` [PATCH 3/5] riscv: dts: spacemit: k3: Add SPL device and image descriptions Junhui Liu
2026-11-06 6:59 ` Yixun Lan
2026-11-07 9:06 ` Junhui Liu
2026-11-07 11:08 ` E Shattow
2026-11-05 16:40 ` [PATCH 4/5] configs: spacemit: k3: Enable SPL support Junhui Liu
2026-11-05 16:40 ` [PATCH 5/5] doc: spacemit: k3: Add SPL build instructions Junhui Liu
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