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From: Archit More <architmore303@gmail.com>
To: Pratyush Yadav <pratyush@kernel.org>, Michael Walle <mwalle@kernel.org>
Cc: linux-mtd@lists.infradead.org, linux-kernel@vger.kernel.org,
	Archit More <architmore303@gmail.com>
Subject: [PATCH] mtd: spi-nor: winbond: W25Q512NW-Q/N/M: Fill locking information
Date: Mon,  9 Nov 2026 00:55:18 +0530	[thread overview]
Message-ID: <20261108192518.46803-1-architmore303@gmail.com> (raw)

The W25Q512NW chips support standard Block Protection (BP0-BP3),
Top/Bottom selection (TB in Status Register 1 bit 6), and Complement
protection (CMP in Status Register 2 bit 6), matching the layout of
other NW-family parts (such as W25Q01NW and W25H512NW).

Add the missing flags so that software write protection and complement
features are properly enabled.

Signed-off-by: Archit More <architmore303@gmail.com>
---
 drivers/mtd/spi-nor/winbond.c | 4 ++++
 1 file changed, 4 insertions(+)

diff --git a/drivers/mtd/spi-nor/winbond.c b/drivers/mtd/spi-nor/winbond.c
index 51f6bcd3f8e5..6ba1a137a549 100644
--- a/drivers/mtd/spi-nor/winbond.c
+++ b/drivers/mtd/spi-nor/winbond.c
@@ -406,6 +406,8 @@ static const struct flash_info winbond_nor_parts[] = {
 		/* W25Q512NW-Q/N */
 		.id = SNOR_ID(0xef, 0x60, 0x20),
 		.name = "w25q512nwq",
+		.flags = SPI_NOR_HAS_LOCK | SPI_NOR_HAS_TB | SPI_NOR_TB_SR_BIT6 |
+			 SPI_NOR_4BIT_BP | SPI_NOR_HAS_CMP,
 		.otp = SNOR_OTP(256, 3, 0x1000, 0x1000),
 	}, {
 		/* W25Q01NW-Q/N */
@@ -500,6 +502,8 @@ static const struct flash_info winbond_nor_parts[] = {
 		/* W25Q512NW-M */
 		.id = SNOR_ID(0xef, 0x80, 0x20),
 		.name = "w25q512nwm",
+		.flags = SPI_NOR_HAS_LOCK | SPI_NOR_HAS_TB | SPI_NOR_TB_SR_BIT6 |
+			 SPI_NOR_4BIT_BP | SPI_NOR_HAS_CMP,
 		.otp = SNOR_OTP(256, 3, 0x1000, 0x1000),
 	}, {
 		/* W25Q01NW-M */
-- 
2.34.1


WARNING: multiple messages have this Message-ID (diff)
From: Archit More <architmore303@gmail.com>
To: Pratyush Yadav <pratyush@kernel.org>, Michael Walle <mwalle@kernel.org>
Cc: linux-mtd@lists.infradead.org, linux-kernel@vger.kernel.org,
	Archit More <architmore303@gmail.com>
Subject: [PATCH] mtd: spi-nor: winbond: W25Q512NW-Q/N/M: Fill locking information
Date: Mon,  9 Nov 2026 00:55:18 +0530	[thread overview]
Message-ID: <20261108192518.46803-1-architmore303@gmail.com> (raw)

The W25Q512NW chips support standard Block Protection (BP0-BP3),
Top/Bottom selection (TB in Status Register 1 bit 6), and Complement
protection (CMP in Status Register 2 bit 6), matching the layout of
other NW-family parts (such as W25Q01NW and W25H512NW).

Add the missing flags so that software write protection and complement
features are properly enabled.

Signed-off-by: Archit More <architmore303@gmail.com>
---
 drivers/mtd/spi-nor/winbond.c | 4 ++++
 1 file changed, 4 insertions(+)

diff --git a/drivers/mtd/spi-nor/winbond.c b/drivers/mtd/spi-nor/winbond.c
index 51f6bcd3f8e5..6ba1a137a549 100644
--- a/drivers/mtd/spi-nor/winbond.c
+++ b/drivers/mtd/spi-nor/winbond.c
@@ -406,6 +406,8 @@ static const struct flash_info winbond_nor_parts[] = {
 		/* W25Q512NW-Q/N */
 		.id = SNOR_ID(0xef, 0x60, 0x20),
 		.name = "w25q512nwq",
+		.flags = SPI_NOR_HAS_LOCK | SPI_NOR_HAS_TB | SPI_NOR_TB_SR_BIT6 |
+			 SPI_NOR_4BIT_BP | SPI_NOR_HAS_CMP,
 		.otp = SNOR_OTP(256, 3, 0x1000, 0x1000),
 	}, {
 		/* W25Q01NW-Q/N */
@@ -500,6 +502,8 @@ static const struct flash_info winbond_nor_parts[] = {
 		/* W25Q512NW-M */
 		.id = SNOR_ID(0xef, 0x80, 0x20),
 		.name = "w25q512nwm",
+		.flags = SPI_NOR_HAS_LOCK | SPI_NOR_HAS_TB | SPI_NOR_TB_SR_BIT6 |
+			 SPI_NOR_4BIT_BP | SPI_NOR_HAS_CMP,
 		.otp = SNOR_OTP(256, 3, 0x1000, 0x1000),
 	}, {
 		/* W25Q01NW-M */
-- 
2.34.1


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             reply	other threads:[~2026-11-08 19:25 UTC|newest]

Thread overview: 2+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2026-11-08 19:25 Archit More [this message]
2026-11-08 19:25 ` [PATCH] mtd: spi-nor: winbond: W25Q512NW-Q/N/M: Fill locking information Archit More

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