From: Rosen Penev <rosenp@gmail.com>
To: Thomas Bogendoerfer <tsbogend@alpha.franken.de>,
Stephen Boyd <sboyd@kernel.org>,
Brian Masney <bmasney+clk@redhat.com>,
Jerome Brunet <jbrunet+clk@baylibre.com>,
Alban Bedel <albeu@free.fr>,
Antony Pavlov <antonynpavlov@gmail.com>,
Rob Herring <robh@kernel.org>,
Krzysztof Kozlowski <krzk+dt@kernel.org>,
Conor Dooley <conor+dt@kernel.org>
Cc: linux-kernel@vger.kernel.org, linux-mips@vger.kernel.org,
linux-clk@vger.kernel.org, devicetree@vger.kernel.org
Subject: [PATCH v2 4/6] dt-bindings: clock: ath79: add the PCIe PLL clock
Date: Mon, 9 Nov 2026 17:36:44 -0800 [thread overview]
Message-ID: <20261110013646.1582970-5-rosenp@gmail.com> (raw)
In-Reply-To: <20261110013646.1582970-1-rosenp@gmail.com>
Add an ID for the PCIe PLL, which AR724x, AR934x, QCA953x, QCA955x and
QCA956x have, so the PCIe host controller nodes can reference it.
Signed-off-by: Rosen Penev <rosenp@gmail.com>
---
include/dt-bindings/clock/ath79-clk.h | 3 ++-
1 file changed, 2 insertions(+), 1 deletion(-)
diff --git a/include/dt-bindings/clock/ath79-clk.h b/include/dt-bindings/clock/ath79-clk.h
index f8a98e4d206d..e4956afd151d 100644
--- a/include/dt-bindings/clock/ath79-clk.h
+++ b/include/dt-bindings/clock/ath79-clk.h
@@ -12,7 +12,8 @@
#define ATH79_CLK_REF 3
#define ATH79_CLK_MDIO 4
#define ATH79_CLK_UART1 5
+#define ATH79_CLK_PCIE 6
-#define ATH79_CLK_END 6
+#define ATH79_CLK_END 7
#endif /* __DT_BINDINGS_ATH79_CLK_H */
--
2.56.0
next prev parent reply other threads:[~2026-11-10 1:36 UTC|newest]
Thread overview: 16+ messages / expand[flat|nested] mbox.gz Atom feed top
2026-11-10 1:36 [PATCH v2 0/6] clk: add a driver for the ath79 PLL controller Rosen Penev
2026-11-10 1:36 ` [PATCH v2 1/6] MIPS: ath79: apply the QCA956x timer workaround in setup Rosen Penev
2026-11-10 1:36 ` [PATCH v2 2/6] MIPS: ath79: move the bootstrap reference clock to setup Rosen Penev
2026-11-10 1:54 ` sashiko-bot
2026-11-10 1:36 ` [PATCH v2 3/6] dt-bindings: clock: ath79: add the UART1 clock Rosen Penev
2026-11-10 13:25 ` Krzysztof Kozlowski
2026-11-10 23:37 ` Rosen Penev
2026-11-10 1:36 ` Rosen Penev [this message]
2026-11-10 13:26 ` [PATCH v2 4/6] dt-bindings: clock: ath79: add the PCIe PLL clock Krzysztof Kozlowski
2026-11-10 1:36 ` [PATCH v2 5/6] clk: add a driver for the Atheros/Qualcomm ath79 PLL controller Rosen Penev
2026-11-10 1:59 ` sashiko-bot
2026-11-10 1:36 ` [PATCH v2 6/6] MIPS: ath79: remove the old clock code Rosen Penev
2026-11-10 2:25 ` [PATCH v2 0/6] clk: add a driver for the ath79 PLL controller Brian Masney
2026-11-10 2:35 ` Rosen Penev
2026-11-10 2:54 ` Brian Masney
2026-11-10 20:47 ` Rosen Penev
Reply instructions:
You may reply publicly to this message via plain-text email
using any one of the following methods:
* Save the following mbox file, import it into your mail client,
and reply-to-all from there: mbox
Avoid top-posting and favor interleaved quoting:
https://en.wikipedia.org/wiki/Posting_style#Interleaved_style
* Reply using the --to, --cc, and --in-reply-to
switches of git-send-email(1):
git send-email \
--in-reply-to=20261110013646.1582970-5-rosenp@gmail.com \
--to=rosenp@gmail.com \
--cc=albeu@free.fr \
--cc=antonynpavlov@gmail.com \
--cc=bmasney+clk@redhat.com \
--cc=conor+dt@kernel.org \
--cc=devicetree@vger.kernel.org \
--cc=jbrunet+clk@baylibre.com \
--cc=krzk+dt@kernel.org \
--cc=linux-clk@vger.kernel.org \
--cc=linux-kernel@vger.kernel.org \
--cc=linux-mips@vger.kernel.org \
--cc=robh@kernel.org \
--cc=sboyd@kernel.org \
--cc=tsbogend@alpha.franken.de \
/path/to/YOUR_REPLY
https://kernel.org/pub/software/scm/git/docs/git-send-email.html
* If your mail client supports setting the In-Reply-To header
via mailto: links, try the mailto: link
Be sure your reply has a Subject: header at the top and a blank line
before the message body.
This is an external index of several public inboxes,
see mirroring instructions on how to clone and mirror
all data and code used by this external index.