From: John Crispin <john@phrozen.org>
To: Lorenzo Bianconi <lorenzo@kernel.org>, Lee Jones <lee@kernel.org>,
Rob Herring <robh@kernel.org>,
Krzysztof Kozlowski <krzk+dt@kernel.org>,
Conor Dooley <conor+dt@kernel.org>,
Linus Walleij <linusw@kernel.org>,
Bartosz Golaszewski <brgl@kernel.org>
Cc: Ahmed Naseef <naseefkm@gmail.com>,
Benjamin Larsson <benjamin.larsson@genexis.eu>,
Christian Marangi <ansuelsmth@gmail.com>,
devicetree@vger.kernel.org, lei.dong@airoha.com,
Linqi.zhang@airoha.com, linux-gpio@vger.kernel.org,
linux-kernel@vger.kernel.org, linux-mediatek@lists.infradead.org,
mfd@lists.linux.dev,
Mikhail Kshevetskiy <mikhail.kshevetskiy@iopsys.eu>,
Rajeev.kumar@airoha.com, upstream@airoha.com,
Weifeng.xu@airoha.com, zhengping.zhang@airoha.com
Subject: [PATCH 0/7] pinctrl: airoha: add AN7589 support
Date: Tue, 10 Nov 2026 18:39:34 +0100 [thread overview]
Message-ID: <20261110173941.301478-1-john@phrozen.org> (raw)
The Airoha AN7589 has a GPIO controller like the EN7581 one, with a
third bank for 74 GPIOs in total. Its pin functions are selected
differently: a separate IOMUX block holds a 4 bit mode field per pin,
eight pins per register, and mode 0 makes any pin a GPIO.
The first four patches prepare the shared driver and change nothing
for the SoCs it serves today:
1. The GPIO register layout moves into the match data, so a SoC can
describe more than 64 pins.
2. A function group can carry one IOMUX mode per pin. A SoC
describes its IOMUX in the match data: the width of the mode
field and, from patch 4, the mode that makes a pin a GPIO.
3. The chip SCU becomes optional, as the AN7589 needs none.
4. A pin requested by gpiolib is put into GPIO mode through the
IOMUX, so no per pin gpio function is needed.
Patch 5 adds the bindings for the pin controller and the GPIO system
controller it sits under. Patch 6 moves the GPIO register offsets to
the common header, so the AN7589 data can describe its own register
table, with no functional change. Patch 7 adds the AN7589 pin data.
The series applies to next-20261105 and has no dependencies.
John Crispin (7):
pinctrl: airoha: make gpio register layout per SoC
pinctrl: airoha: add per pin mode field mux
pinctrl: airoha: make the chip SCU optional
pinctrl: airoha: mux a requested GPIO through the IOMUX
dt-bindings: pinctrl: airoha: add AN7589
pinctrl: airoha: move the GPIO register offsets to the common header
pinctrl: airoha: add support of an7589 SoC
.../mfd/airoha,an7589-gpio-sysctl.yaml | 66 ++
.../devicetree/bindings/mfd/syscon.yaml | 1 +
.../pinctrl/airoha,an7589-pinctrl.yaml | 533 +++++++++++++
MAINTAINERS | 3 +
drivers/pinctrl/airoha/Kconfig | 11 +
drivers/pinctrl/airoha/Makefile | 1 +
drivers/pinctrl/airoha/airoha-common.h | 41 +-
drivers/pinctrl/airoha/pinctrl-airoha.c | 119 ++-
drivers/pinctrl/airoha/pinctrl-an7563.c | 1 +
drivers/pinctrl/airoha/pinctrl-an7581.c | 1 +
drivers/pinctrl/airoha/pinctrl-an7583.c | 1 +
drivers/pinctrl/airoha/pinctrl-an7589.c | 721 ++++++++++++++++++
drivers/pinctrl/airoha/pinctrl-en7523.c | 1 +
drivers/pinctrl/airoha/pinctrl-en7528.c | 1 +
14 files changed, 1469 insertions(+), 32 deletions(-)
create mode 100644 Documentation/devicetree/bindings/mfd/airoha,an7589-gpio-sysctl.yaml
create mode 100644 Documentation/devicetree/bindings/pinctrl/airoha,an7589-pinctrl.yaml
create mode 100644 drivers/pinctrl/airoha/pinctrl-an7589.c
base-commit: ddfe51b0a0f5dc9e415cc2c8ad8db17532dd426b
--
2.34.1
next reply other threads:[~2026-11-10 17:39 UTC|newest]
Thread overview: 13+ messages / expand[flat|nested] mbox.gz Atom feed top
2026-11-10 17:39 John Crispin [this message]
2026-11-10 17:39 ` [PATCH 1/7] pinctrl: airoha: make gpio register layout per SoC John Crispin
2026-11-11 11:22 ` Lorenzo Bianconi
2026-11-10 17:39 ` [PATCH 2/7] pinctrl: airoha: add per pin mode field mux John Crispin
2026-11-10 17:39 ` [PATCH 3/7] pinctrl: airoha: make the chip SCU optional John Crispin
2026-11-11 11:27 ` Lorenzo Bianconi
2026-11-10 17:39 ` [PATCH 4/7] pinctrl: airoha: mux a requested GPIO through the IOMUX John Crispin
2026-11-10 17:39 ` [PATCH 5/7] dt-bindings: pinctrl: airoha: add AN7589 John Crispin
2026-11-10 18:27 ` Conor Dooley
2026-11-10 17:39 ` [PATCH 6/7] pinctrl: airoha: move the GPIO register offsets to the common header John Crispin
2026-11-11 11:29 ` Lorenzo Bianconi
2026-11-10 17:39 ` [PATCH 7/7] pinctrl: airoha: add support of an7589 SoC John Crispin
2026-11-11 11:32 ` Lorenzo Bianconi
Reply instructions:
You may reply publicly to this message via plain-text email
using any one of the following methods:
* Save the following mbox file, import it into your mail client,
and reply-to-all from there: mbox
Avoid top-posting and favor interleaved quoting:
https://en.wikipedia.org/wiki/Posting_style#Interleaved_style
* Reply using the --to, --cc, and --in-reply-to
switches of git-send-email(1):
git send-email \
--in-reply-to=20261110173941.301478-1-john@phrozen.org \
--to=john@phrozen.org \
--cc=Linqi.zhang@airoha.com \
--cc=Rajeev.kumar@airoha.com \
--cc=Weifeng.xu@airoha.com \
--cc=ansuelsmth@gmail.com \
--cc=benjamin.larsson@genexis.eu \
--cc=brgl@kernel.org \
--cc=conor+dt@kernel.org \
--cc=devicetree@vger.kernel.org \
--cc=krzk+dt@kernel.org \
--cc=lee@kernel.org \
--cc=lei.dong@airoha.com \
--cc=linusw@kernel.org \
--cc=linux-gpio@vger.kernel.org \
--cc=linux-kernel@vger.kernel.org \
--cc=linux-mediatek@lists.infradead.org \
--cc=lorenzo@kernel.org \
--cc=mfd@lists.linux.dev \
--cc=mikhail.kshevetskiy@iopsys.eu \
--cc=naseefkm@gmail.com \
--cc=robh@kernel.org \
--cc=upstream@airoha.com \
--cc=zhengping.zhang@airoha.com \
/path/to/YOUR_REPLY
https://kernel.org/pub/software/scm/git/docs/git-send-email.html
* If your mail client supports setting the In-Reply-To header
via mailto: links, try the mailto: link
Be sure your reply has a Subject: header at the top and a blank line
before the message body.
This is an external index of several public inboxes,
see mirroring instructions on how to clone and mirror
all data and code used by this external index.