Re: [PATCH v2 18/19] riscv: errata: andes: limit the IOCP workaround to RZ/Five

From: Conor Dooley <conor@kernel.org>
To: Mina Hui-Min Chou <minachou@andestech.com>
Cc: pjw@kernel.org, palmer@dabbelt.com, aou@eecs.berkeley.edu,
	alex@ghiti.fr, jic23@kernel.org, robh@kernel.org,
	krzk+dt@kernel.org, conor+dt@kernel.org, geert+renesas@glider.be,
	magnus.damm@gmail.com, prabhakar.mahadev-lad.rj@bp.renesas.com,
	linux-riscv@lists.infradead.org, devicetree@vger.kernel.org,
	linux-renesas-soc@vger.kernel.org, linux-kernel@vger.kernel.org,
	randolph@andestech.com, cyyang772@andestech.com,
	tim609@andestech.com, az70021@gmail.com
Subject: Re: [PATCH v2 18/19] riscv: errata: andes: limit the IOCP workaround to RZ/Five
Date: Fri, 13 Nov 2026 13:53:29 +0000	[thread overview]
Message-ID: <20261113-helping-elsewhere-cbcf0c8f67ce@spud> (raw)
In-Reply-To: <20261113071143.1446167-19-minachou@andestech.com>

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On Fri, Nov 13, 2026 at 03:11:42PM +0800, Mina Hui-Min Chou wrote:
> The SBI-based IOCP check was added for Renesas RZ/Five (R9A07G043F),
> the only upstream-supported SoC whose AX45MP has no IOCP. It matches
> the AX45MP marchid and the mimpid of the RZ/Five core, but it is built
> into every kernel with ERRATA_ANDES_CMO, so the SBI call is issued even
> when the kernel does not support RZ/Five.
> 
> Move the match into soc_is_r9a07g043f() and make it also require
> ARCH_R9A07G043. Kernels without RZ/Five support then skip the SBI call
> and take the generic Andes cache errata path. No other upstream-
> supported SoC uses this AX45MP mimpid, so their behavior does not
> change.

But a device using this soc that doesn't have a dts in mainline won't
function properly, so this is fragile. Why not just do it properly and
check for RZ/Five specifically?
Can check for of_machine_is_compatible() probably?

> 
> While at it, rename ax45mp_iocp_sw_workaround() to
> r9a07g043f_iocp_sw_workaround(), as the check is only used for RZ/Five.
> 
> Signed-off-by: Mina Hui-Min Chou <minachou@andestech.com>
> ---
>  arch/riscv/errata/andes/errata.c | 13 ++++++++++---
>  1 file changed, 10 insertions(+), 3 deletions(-)
> 
> diff --git a/arch/riscv/errata/andes/errata.c b/arch/riscv/errata/andes/errata.c
> index 530d2df216e0..f2535a81b1e2 100644
> --- a/arch/riscv/errata/andes/errata.c
> +++ b/arch/riscv/errata/andes/errata.c
> @@ -25,7 +25,7 @@
>  
>  #define ANDES_SBI_EXT_IOCP_SW_WORKAROUND	1
>  
> -static long ax45mp_iocp_sw_workaround(void)
> +static long r9a07g043f_iocp_sw_workaround(void)
>  {
>  	struct sbiret ret;
>  
> @@ -39,6 +39,13 @@ static long ax45mp_iocp_sw_workaround(void)
>  	return ret.error ? 0 : ret.value;
>  }
>  
> +static bool soc_is_r9a07g043f(unsigned long arch_id, unsigned long impid)
> +{
> +	return IS_ENABLED(CONFIG_ARCH_R9A07G043) &&
> +	       arch_id == ANDES_AX45MP_MARCHID &&
> +	       impid == ANDES_AX45MP_MIMPID;
> +}
> +
>  static void errata_probe_andes_cache(unsigned int stage, unsigned long arch_id, unsigned long impid)
>  {
>  	static bool done;
> @@ -51,8 +58,8 @@ static void errata_probe_andes_cache(unsigned int stage, unsigned long arch_id,
>  
>  	done = true;
>  
> -	if (arch_id == ANDES_AX45MP_MARCHID && impid == ANDES_AX45MP_MIMPID) {
> -		if (!ax45mp_iocp_sw_workaround())
> +	if (soc_is_r9a07g043f(arch_id, impid)) {
> +		if (!r9a07g043f_iocp_sw_workaround())
>  			return;
>  	} else if (riscv_isa_extension_available(NULL, ZICBOM)) {
>  		return;
> -- 
> 2.34.1
> 

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