[PATCH 0/4] Update TSA mitigations for Zen3+

[Ben Cheatham <Benjamin.Cheatham@amd.com>]

This set adds new model versions for Zen3 (EPYC-Milan) through Zen5
(EPYC-Turin) to bring TSA mitigations up to date. This is done in two
parts:

	1. Add a definition for the new TSA-FILL variant (Patch 1)

		Only Zen5 is vulnerable to this TSA variant. QEMU invocations for 
		Zen3 and Zen4 may add "+tsa-fill-no" to the "-cpu" argument to
		set this feature bit.

		This bit is not set by default because it's not supported
		by SEV firmware on Zen3 and Zen4. If you try to start a SEV-SNP
		VM with this bit set the guest will fail to boot due to the
		firmware rejecting the modified CPUID page.

	2. Set the "verw-clear" feature bit for Zen3 through Zen5
	(Patches 2, 3, and 4)

		This bit is used to mitigate the TSA-L1 and TSA-SQ vectors on
		Zen3 and Zen4, and the TSA-FILL variant on Zen5. The definition
		for verw-clear was already in place, but unused. This set
		rectifies that by setting the verw-clear bit in an updated model
		for Zen3, 4, and 5.

		Updated microcode is required for Zen5. Any revision later than
		0xb002175 for Turin Classic or 0x0B101066 for Turin Dense will
		work. Updated microcode is available in the latest PI release
		or from linux-firmware.

		Updated microcode has been available for Zen3 & Zen4 for a
		while, but there is a revision check performed by the Linux
		kernel. If QEMU is complaining about the "verw-clear" bit being
		missing, please update to the latest PI release or microcode in
		linux-firmware.

Linux kernel support for these changes was just merged, see [1].

Quick note: This set conflicts with the Venice & Turin v3 model I sent out
a few weeks ago[2]. The only conflicting portion is the Turin model patch,
either that patch's number can be bumped to v4 or the two patches can be
merged if both sets are picked up at the same time.

[1]:
Link: https://git.kernel.org/pub/scm/linux/kernel/git/torvalds/linux.git/commit/?id=cf27412f19c9cc5909b9107cd1b3f4ab7608e362
[2]:
Link: https://lore.kernel.org/qemu-devel/20261029195623.2209-1-Benjamin.Cheatham@amd.com/

Thanks,
Ben

Ben Cheatham (4):
  target/i386: Add TSA attack variant TSA-FILL
  target/i386: Add EPYC-Milan-v5 Model
  target/i386: Add EPYC-Genoa-v4 Model
  target/i386: Add EPYC-Turin-v3 Model

 target/i386/cpu.c | 32 +++++++++++++++++++++++++++++++-
 target/i386/cpu.h |  2 ++
 2 files changed, 33 insertions(+), 1 deletion(-)

base-commit: fd7ab698c921

-- 
2.53.0