From: Ben Cheatham <Benjamin.Cheatham@amd.com>
To: <pbonzini@redhat.com>, <zhao1.liu@intel.com>
Cc: <qemu-devel@nongnu.org>, Ben Cheatham <Benjamin.Cheatham@amd.com>
Subject: [PATCH 3/4] target/i386: Add EPYC-Genoa-v4 Model
Date: Fri, 13 Nov 2026 11:49:25 -0600 [thread overview]
Message-ID: <20261113174926.1861-4-Benjamin.Cheatham@amd.com> (raw)
In-Reply-To: <20261113174926.1861-1-Benjamin.Cheatham@amd.com>
Add a new version of the EPYC-Genoa model with the verw-clear feature
set. This feature is used to mitigate the TSA L1, SQ, and FILL
variants.
Signed-off-by: Ben Cheatham <Benjamin.Cheatham@amd.com>
---
target/i386/cpu.c | 10 ++++++++++
1 file changed, 10 insertions(+)
diff --git a/target/i386/cpu.c b/target/i386/cpu.c
index 85745d5f907c..f80dd98d3ebd 100644
--- a/target/i386/cpu.c
+++ b/target/i386/cpu.c
@@ -7075,6 +7075,16 @@ static const X86CPUDefinition builtin_x86_defs[] = {
},
.cache_info = &epyc_genoa_v2_cache_info
},
+ {
+ .version = 4,
+ .props = (PropValue[]) {
+ { "verw-clear", "on" },
+ { "model-id",
+ "AMD EPYC-Genoa-v4 Processor" },
+ { /* end of list */ }
+ },
+ .cache_info = &epyc_genoa_v2_cache_info
+ },
{ /* end of list */ }
}
},
--
2.53.0
next prev parent reply other threads:[~2026-11-13 18:31 UTC|newest]
Thread overview: 5+ messages / expand[flat|nested] mbox.gz Atom feed top
2026-11-13 17:49 [PATCH 0/4] Update TSA mitigations for Zen3+ Ben Cheatham
2026-11-13 17:49 ` [PATCH 1/4] target/i386: Add TSA variant TSA-FILL Ben Cheatham
2026-11-13 17:49 ` [PATCH 2/4] target/i386: Add EPYC-Milan-v5 Model Ben Cheatham
2026-11-13 17:49 ` Ben Cheatham [this message]
2026-11-13 17:49 ` [PATCH 4/4] target/i386: Add EPYC-Turin-v3 Model Ben Cheatham
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