From: Gavin Shan <gshan@redhat.com>
To: Catalin Marinas <catalin.marinas@arm.com>
Cc: mark.rutland@arm.com, anshuman.khandual@arm.com,
robin.murphy@arm.com, linux-kernel@vger.kernel.org,
shan.gavin@gmail.com, will@kernel.org,
linux-arm-kernel@lists.infradead.org
Subject: Re: [PATCH v2 0/2] arm64/mm: Enable color zero pages
Date: Thu, 24 Sep 2020 08:47:09 +1000 [thread overview]
Message-ID: <2047fb91-da03-7774-ef5e-d194b92813c3@redhat.com> (raw)
In-Reply-To: <20200923084317.GA13434@gaia>
Hi Catalin,
On 9/23/20 6:43 PM, Catalin Marinas wrote:
> On Wed, Sep 23, 2020 at 03:37:19PM +1000, Gavin Shan wrote:
>> The feature of color zero pages isn't enabled on arm64, meaning all
>> read-only (anonymous) VM areas are backed up by same zero page. It
>> leads pressure to L1 (data) cache on reading data from them. This
>> tries to enable color zero pages.
>>
>> PATCH[1/2] decouples the zero PGD table from zero page
>> PATCH[2/2] allocates the needed zero pages according to L1 cache size
>
> To save you (and potential reviewers) some time, please include in the
> cover letter details of a realistic workload/benchmark that is improved
> by this patchset, backed by numbers. Just because it's doable and the
> patches aren't too complex is not a good enough reason for merging.
>
Sure, Please ignore this (v2) series for now. I'll try to provide
performance data in v3 even I'm not positive about that because
it depends on CPU's L1 dCache size :)
Cheers,
Gavin
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WARNING: multiple messages have this Message-ID (diff)
From: Gavin Shan <gshan@redhat.com>
To: Catalin Marinas <catalin.marinas@arm.com>
Cc: linux-arm-kernel@lists.infradead.org,
linux-kernel@vger.kernel.org, mark.rutland@arm.com,
anshuman.khandual@arm.com, robin.murphy@arm.com, will@kernel.org,
shan.gavin@gmail.com
Subject: Re: [PATCH v2 0/2] arm64/mm: Enable color zero pages
Date: Thu, 24 Sep 2020 08:47:09 +1000 [thread overview]
Message-ID: <2047fb91-da03-7774-ef5e-d194b92813c3@redhat.com> (raw)
In-Reply-To: <20200923084317.GA13434@gaia>
Hi Catalin,
On 9/23/20 6:43 PM, Catalin Marinas wrote:
> On Wed, Sep 23, 2020 at 03:37:19PM +1000, Gavin Shan wrote:
>> The feature of color zero pages isn't enabled on arm64, meaning all
>> read-only (anonymous) VM areas are backed up by same zero page. It
>> leads pressure to L1 (data) cache on reading data from them. This
>> tries to enable color zero pages.
>>
>> PATCH[1/2] decouples the zero PGD table from zero page
>> PATCH[2/2] allocates the needed zero pages according to L1 cache size
>
> To save you (and potential reviewers) some time, please include in the
> cover letter details of a realistic workload/benchmark that is improved
> by this patchset, backed by numbers. Just because it's doable and the
> patches aren't too complex is not a good enough reason for merging.
>
Sure, Please ignore this (v2) series for now. I'll try to provide
performance data in v3 even I'm not positive about that because
it depends on CPU's L1 dCache size :)
Cheers,
Gavin
next prev parent reply other threads:[~2020-09-23 22:48 UTC|newest]
Thread overview: 10+ messages / expand[flat|nested] mbox.gz Atom feed top
2020-09-23 5:37 [PATCH v2 0/2] arm64/mm: Enable color zero pages Gavin Shan
2020-09-23 5:37 ` Gavin Shan
2020-09-23 5:37 ` [PATCH v2 1/2] arm64/mm: Introduce zero PGD table Gavin Shan
2020-09-23 5:37 ` Gavin Shan
2020-09-23 5:37 ` [PATCH v2 2/2] arm64/mm: Enable color zero pages Gavin Shan
2020-09-23 5:37 ` Gavin Shan
2020-09-23 8:43 ` [PATCH v2 0/2] " Catalin Marinas
2020-09-23 8:43 ` Catalin Marinas
2020-09-23 22:47 ` Gavin Shan [this message]
2020-09-23 22:47 ` Gavin Shan
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