From: tomasz.figa@gmail.com
To: Prasanna Kumar <prasanna.ps@samsung.com>
Cc: kgene.kim@samsung.com, linux-samsung-soc@vger.kernel.org,
thomas.abraham@linaro.org, linux-arm-kernel@lists.infradead.org
Subject: Re: [PATCH v2 3/3] ARM: EXYNOS5: save CLK_TOP_SRC3 register before powergating
Date: Thu, 20 Dec 2012 22:06:27 +0100 [thread overview]
Message-ID: <21192551.mmsSZImfn7@flatron> (raw)
In-Reply-To: <1356006378-17441-4-git-send-email-prasanna.ps@samsung.com>
Hi Prasanna,
On Thursday 20 of December 2012 17:56:18 Prasanna Kumar wrote:
> This patch adds a software workaround to the hardware
> problem found in exynos5 while powergating.
>
> It is observed that CLK_TOP_SRC3 register gets modified if
> the G-Scaler/MFC devices are power gated. The clock for G-Scaler gets
> set to XXTI which results in the device running very slow .
> A big drop in performance is noticed whilerunning the video.
> This issue also occurs while powergating MFC.
>
> The value of clock source register is restored once the powergating
> operation is completed.
Is the problem really related to power gating at all? From what you
described in comment in the code, it seems like it's a problem with
suspend/resume, not power gating, so it should be rather saved on suspend
and restored on resume. Please recheck clock save/restore part of power
management code.
Altering clock configuration registers from power domain code looks really
ugly...
Best regards,
Tomasz Figa
WARNING: multiple messages have this Message-ID (diff)
From: tomasz.figa@gmail.com (tomasz.figa at gmail.com)
To: linux-arm-kernel@lists.infradead.org
Subject: [PATCH v2 3/3] ARM: EXYNOS5: save CLK_TOP_SRC3 register before powergating
Date: Thu, 20 Dec 2012 22:06:27 +0100 [thread overview]
Message-ID: <21192551.mmsSZImfn7@flatron> (raw)
In-Reply-To: <1356006378-17441-4-git-send-email-prasanna.ps@samsung.com>
Hi Prasanna,
On Thursday 20 of December 2012 17:56:18 Prasanna Kumar wrote:
> This patch adds a software workaround to the hardware
> problem found in exynos5 while powergating.
>
> It is observed that CLK_TOP_SRC3 register gets modified if
> the G-Scaler/MFC devices are power gated. The clock for G-Scaler gets
> set to XXTI which results in the device running very slow .
> A big drop in performance is noticed whilerunning the video.
> This issue also occurs while powergating MFC.
>
> The value of clock source register is restored once the powergating
> operation is completed.
Is the problem really related to power gating at all? From what you
described in comment in the code, it seems like it's a problem with
suspend/resume, not power gating, so it should be rather saved on suspend
and restored on resume. Please recheck clock save/restore part of power
management code.
Altering clock configuration registers from power domain code looks really
ugly...
Best regards,
Tomasz Figa
next prev parent reply other threads:[~2012-12-20 21:06 UTC|newest]
Thread overview: 40+ messages / expand[flat|nested] mbox.gz Atom feed top
2012-11-27 12:22 [PATCH 0/3]ARM: Exynos5 : Add Power domain device tree support and fix for hardware issue Prasanna Kumar
2012-11-27 12:22 ` Prasanna Kumar
2012-11-27 12:22 ` [PATCH 1/3] ARM: dts: exynos5: Set up power domain for MFC and G-scaler Prasanna Kumar
2012-11-27 12:22 ` Prasanna Kumar
2012-12-04 9:05 ` Thomas Abraham
2012-12-04 9:05 ` Thomas Abraham
2012-11-27 12:22 ` [PATCH 2/3] arm: exynos5: Enable PM generic domain support in Kconfig Prasanna Kumar
2012-11-27 12:22 ` Prasanna Kumar
2012-12-04 9:07 ` Thomas Abraham
2012-12-04 9:07 ` Thomas Abraham
2012-11-27 12:22 ` [PATCH 3/3] ARM: EXYNOS5: save CLK_TOP_SRC3 register before powergating Prasanna Kumar
2012-11-27 12:22 ` Prasanna Kumar
2012-12-04 8:59 ` Thomas Abraham
2012-12-04 8:59 ` Thomas Abraham
2012-12-07 12:49 ` Prasanna Kumar
2012-12-07 12:49 ` Prasanna Kumar
2012-12-20 12:26 ` [PATCH v2 0/3] ARM: Exynos5 : Add Power domain device tree support and fix for hardware issue Prasanna Kumar
2012-12-20 12:26 ` Prasanna Kumar
2012-12-20 12:26 ` [PATCH v2 1/3] ARM: dts: exynos5: Set up power domain for MFC,G-scaler,MAU and ISP Prasanna Kumar
2012-12-20 12:26 ` Prasanna Kumar
2012-12-27 4:58 ` Prasanna Kumar
2012-12-27 4:58 ` Prasanna Kumar
2012-12-20 12:26 ` [PATCH v2 2/3] arm: exynos5: Enable PM generic domain support in Kconfig Prasanna Kumar
2012-12-20 12:26 ` Prasanna Kumar
2012-12-20 12:26 ` [PATCH v2 3/3] ARM: EXYNOS5: save CLK_TOP_SRC3 register before powergating Prasanna Kumar
2012-12-20 12:26 ` Prasanna Kumar
2012-12-20 21:06 ` tomasz.figa [this message]
2012-12-20 21:06 ` tomasz.figa at gmail.com
2012-12-21 1:37 ` jonghwan Choi
2012-12-21 1:37 ` jonghwan Choi
2012-12-24 4:26 ` Prasanna Kumar
2012-12-24 4:26 ` Prasanna Kumar
2012-12-24 5:42 ` Prasanna Kumar
2012-12-24 5:42 ` Prasanna Kumar
2012-12-24 4:18 ` Prasanna Kumar
2012-12-24 4:18 ` Prasanna Kumar
2012-12-27 15:23 ` Tomasz Figa
2012-12-27 15:23 ` Tomasz Figa
2012-12-27 14:51 ` [PATCH " Tomasz Figa
2012-12-27 14:51 ` Tomasz Figa
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