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From: "Heiko Stübner" <heiko@sntech.de>
To: Chen-Yu Tsai <wens@csie.org>,
	Jernej Skrabec <jernej.skrabec@gmail.com>,
	linux-sunxi@lists.linux.dev, Palmer Dabbelt <palmer@dabbelt.com>,
	Conor Dooley <conor@kernel.org>,
	linux-riscv@lists.infradead.org,
	Samuel Holland <samuel@sholland.org>
Cc: Jisheng Zhang <jszhang@kernel.org>,
	linux-kernel@vger.kernel.org, devicetree@vger.kernel.org,
	Krzysztof Kozlowski <krzysztof.kozlowski+dt@linaro.org>,
	Rob Herring <robh+dt@kernel.org>,
	linux-arm-kernel@lists.infradead.org,
	Andre Przywara <andre.przywara@arm.com>,
	Samuel Holland <samuel@sholland.org>,
	Palmer Dabbelt <palmer@rivosinc.com>,
	Conor Dooley <conor.dooley@microchip.com>
Subject: Re: [PATCH v3 04/12] riscv: dts: allwinner: Add the D1/D1s SoC devicetree
Date: Mon, 19 Dec 2022 11:57:14 +0100	[thread overview]
Message-ID: <2133897.PYKUYFuaPT@diego> (raw)
In-Reply-To: <20221208090237.20572-5-samuel@sholland.org>

Am Donnerstag, 8. Dezember 2022, 10:02:29 CET schrieb Samuel Holland:
> D1 (aka D1-H), D1s (aka F133), R528, and T113 are a family of SoCs based
> on a single die, or at a pair of dies derived from the same design.
> 
> D1 and D1s contain a single T-HEAD Xuantie C906 CPU, whereas R528 and
> T113 contain a pair of Cortex-A7's. D1 and R528 are the full version of
> the chip with a BGA package, whereas D1s and T113 are low-pin-count QFP
> variants.
> 
> Because the original design supported both ARM and RISC-V CPUs, some
> peripherals are duplicated. In addition, all variants except D1s contain
> a HiFi 4 DSP with its own set of peripherals.
> 
> The devicetrees are organized to minimize duplication:
>  - Common perhiperals are described in sunxi-d1s-t113.dtsi
>  - DSP-related peripherals are described in sunxi-d1-t113.dtsi
>  - RISC-V specific hardware is described in sun20i-d1s.dtsi
>  - Functionality unique to the D1 variant is described in sun20i-d1.dtsi
> 
> The SOC_PERIPHERAL_IRQ macro handles the different #interrupt-cells
> values between the ARM (GIC) and RISC-V (PLIC) versions of the SoC.
> 
> Acked-by: Jernej Skrabec <jernej.skrabec@gmail.com>
> Acked-by: Palmer Dabbelt <palmer@rivosinc.com>
> Reviewed-by: Conor Dooley <conor.dooley@microchip.com>
> Tested-by: Heiko Stuebner <heiko.stuebner@vrull.eu>
> Signed-off-by: Samuel Holland <samuel@sholland.org>

after spending some more time looking at the devicetree, I'm pretty
confident that it looks ok, so also

Reviewed-by: Heiko Stuebner <heiko.stuebner@vrull.eu>



_______________________________________________
linux-riscv mailing list
linux-riscv@lists.infradead.org
http://lists.infradead.org/mailman/listinfo/linux-riscv

WARNING: multiple messages have this Message-ID (diff)
From: "Heiko Stübner" <heiko@sntech.de>
To: Chen-Yu Tsai <wens@csie.org>,
	Jernej Skrabec <jernej.skrabec@gmail.com>,
	linux-sunxi@lists.linux.dev, Palmer Dabbelt <palmer@dabbelt.com>,
	Conor Dooley <conor@kernel.org>,
	linux-riscv@lists.infradead.org,
	Samuel Holland <samuel@sholland.org>
Cc: Jisheng Zhang <jszhang@kernel.org>,
	linux-kernel@vger.kernel.org, devicetree@vger.kernel.org,
	Krzysztof Kozlowski <krzysztof.kozlowski+dt@linaro.org>,
	Rob Herring <robh+dt@kernel.org>,
	linux-arm-kernel@lists.infradead.org,
	Andre Przywara <andre.przywara@arm.com>,
	Samuel Holland <samuel@sholland.org>,
	Palmer Dabbelt <palmer@rivosinc.com>,
	Conor Dooley <conor.dooley@microchip.com>
Subject: Re: [PATCH v3 04/12] riscv: dts: allwinner: Add the D1/D1s SoC devicetree
Date: Mon, 19 Dec 2022 11:57:14 +0100	[thread overview]
Message-ID: <2133897.PYKUYFuaPT@diego> (raw)
In-Reply-To: <20221208090237.20572-5-samuel@sholland.org>

Am Donnerstag, 8. Dezember 2022, 10:02:29 CET schrieb Samuel Holland:
> D1 (aka D1-H), D1s (aka F133), R528, and T113 are a family of SoCs based
> on a single die, or at a pair of dies derived from the same design.
> 
> D1 and D1s contain a single T-HEAD Xuantie C906 CPU, whereas R528 and
> T113 contain a pair of Cortex-A7's. D1 and R528 are the full version of
> the chip with a BGA package, whereas D1s and T113 are low-pin-count QFP
> variants.
> 
> Because the original design supported both ARM and RISC-V CPUs, some
> peripherals are duplicated. In addition, all variants except D1s contain
> a HiFi 4 DSP with its own set of peripherals.
> 
> The devicetrees are organized to minimize duplication:
>  - Common perhiperals are described in sunxi-d1s-t113.dtsi
>  - DSP-related peripherals are described in sunxi-d1-t113.dtsi
>  - RISC-V specific hardware is described in sun20i-d1s.dtsi
>  - Functionality unique to the D1 variant is described in sun20i-d1.dtsi
> 
> The SOC_PERIPHERAL_IRQ macro handles the different #interrupt-cells
> values between the ARM (GIC) and RISC-V (PLIC) versions of the SoC.
> 
> Acked-by: Jernej Skrabec <jernej.skrabec@gmail.com>
> Acked-by: Palmer Dabbelt <palmer@rivosinc.com>
> Reviewed-by: Conor Dooley <conor.dooley@microchip.com>
> Tested-by: Heiko Stuebner <heiko.stuebner@vrull.eu>
> Signed-off-by: Samuel Holland <samuel@sholland.org>

after spending some more time looking at the devicetree, I'm pretty
confident that it looks ok, so also

Reviewed-by: Heiko Stuebner <heiko.stuebner@vrull.eu>



WARNING: multiple messages have this Message-ID (diff)
From: "Heiko Stübner" <heiko@sntech.de>
To: Chen-Yu Tsai <wens@csie.org>,
	Jernej Skrabec <jernej.skrabec@gmail.com>,
	linux-sunxi@lists.linux.dev, Palmer Dabbelt <palmer@dabbelt.com>,
	Conor Dooley <conor@kernel.org>,
	linux-riscv@lists.infradead.org,
	Samuel Holland <samuel@sholland.org>
Cc: Jisheng Zhang <jszhang@kernel.org>,
	linux-kernel@vger.kernel.org, devicetree@vger.kernel.org,
	Krzysztof Kozlowski <krzysztof.kozlowski+dt@linaro.org>,
	Rob Herring <robh+dt@kernel.org>,
	linux-arm-kernel@lists.infradead.org,
	Andre Przywara <andre.przywara@arm.com>,
	Samuel Holland <samuel@sholland.org>,
	Palmer Dabbelt <palmer@rivosinc.com>,
	Conor Dooley <conor.dooley@microchip.com>
Subject: Re: [PATCH v3 04/12] riscv: dts: allwinner: Add the D1/D1s SoC devicetree
Date: Mon, 19 Dec 2022 11:57:14 +0100	[thread overview]
Message-ID: <2133897.PYKUYFuaPT@diego> (raw)
In-Reply-To: <20221208090237.20572-5-samuel@sholland.org>

Am Donnerstag, 8. Dezember 2022, 10:02:29 CET schrieb Samuel Holland:
> D1 (aka D1-H), D1s (aka F133), R528, and T113 are a family of SoCs based
> on a single die, or at a pair of dies derived from the same design.
> 
> D1 and D1s contain a single T-HEAD Xuantie C906 CPU, whereas R528 and
> T113 contain a pair of Cortex-A7's. D1 and R528 are the full version of
> the chip with a BGA package, whereas D1s and T113 are low-pin-count QFP
> variants.
> 
> Because the original design supported both ARM and RISC-V CPUs, some
> peripherals are duplicated. In addition, all variants except D1s contain
> a HiFi 4 DSP with its own set of peripherals.
> 
> The devicetrees are organized to minimize duplication:
>  - Common perhiperals are described in sunxi-d1s-t113.dtsi
>  - DSP-related peripherals are described in sunxi-d1-t113.dtsi
>  - RISC-V specific hardware is described in sun20i-d1s.dtsi
>  - Functionality unique to the D1 variant is described in sun20i-d1.dtsi
> 
> The SOC_PERIPHERAL_IRQ macro handles the different #interrupt-cells
> values between the ARM (GIC) and RISC-V (PLIC) versions of the SoC.
> 
> Acked-by: Jernej Skrabec <jernej.skrabec@gmail.com>
> Acked-by: Palmer Dabbelt <palmer@rivosinc.com>
> Reviewed-by: Conor Dooley <conor.dooley@microchip.com>
> Tested-by: Heiko Stuebner <heiko.stuebner@vrull.eu>
> Signed-off-by: Samuel Holland <samuel@sholland.org>

after spending some more time looking at the devicetree, I'm pretty
confident that it looks ok, so also

Reviewed-by: Heiko Stuebner <heiko.stuebner@vrull.eu>



_______________________________________________
linux-arm-kernel mailing list
linux-arm-kernel@lists.infradead.org
http://lists.infradead.org/mailman/listinfo/linux-arm-kernel

  reply	other threads:[~2022-12-19 10:57 UTC|newest]

Thread overview: 63+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2022-12-08  9:02 [PATCH v3 00/12] riscv: Allwinner D1/D1s platform support Samuel Holland
2022-12-08  9:02 ` Samuel Holland
2022-12-08  9:02 ` Samuel Holland
2022-12-08  9:02 ` [PATCH v3 01/12] MAINTAINERS: Match the sun20i family of Allwinner SoCs Samuel Holland
2022-12-08  9:02   ` Samuel Holland
2022-12-08  9:02   ` Samuel Holland
2022-12-08  9:02 ` [PATCH v3 02/12] dt-bindings: vendor-prefixes: Add Allwinner D1/D1s board vendors Samuel Holland
2022-12-08  9:02   ` Samuel Holland
2022-12-08  9:02   ` Samuel Holland
2022-12-08  9:02 ` [PATCH v3 03/12] dt-bindings: riscv: Add Allwinner D1/D1s board compatibles Samuel Holland
2022-12-08  9:02   ` Samuel Holland
2022-12-08  9:02   ` Samuel Holland
2022-12-08  9:02 ` [PATCH v3 04/12] riscv: dts: allwinner: Add the D1/D1s SoC devicetree Samuel Holland
2022-12-08  9:02   ` Samuel Holland
2022-12-08  9:02   ` Samuel Holland
2022-12-19 10:57   ` Heiko Stübner [this message]
2022-12-19 10:57     ` Heiko Stübner
2022-12-19 10:57     ` Heiko Stübner
2022-12-08  9:02 ` [PATCH v3 05/12] riscv: dts: allwinner: Add MangoPi MQ devicetree Samuel Holland
2022-12-08  9:02   ` Samuel Holland
2022-12-08  9:02   ` Samuel Holland
2022-12-08  9:02 ` [PATCH v3 06/12] riscv: dts: allwinner: Add Allwinner D1 Nezha devicetree Samuel Holland
2022-12-08  9:02   ` Samuel Holland
2022-12-08  9:02   ` Samuel Holland
2022-12-08  9:02 ` [PATCH v3 07/12] riscv: dts: allwinner: Add Sipeed Lichee RV devicetrees Samuel Holland
2022-12-08  9:02   ` Samuel Holland
2022-12-08  9:02   ` Samuel Holland
2022-12-08  9:02 ` [PATCH v3 08/12] riscv: dts: allwinner: Add MangoPi MQ Pro devicetree Samuel Holland
2022-12-08  9:02   ` Samuel Holland
2022-12-08  9:02   ` Samuel Holland
2022-12-08  9:02 ` [PATCH v3 09/12] riscv: dts: allwinner: Add Dongshan Nezha STU devicetree Samuel Holland
2022-12-08  9:02   ` Samuel Holland
2022-12-08  9:02   ` Samuel Holland
2022-12-08  9:02 ` [PATCH v3 10/12] riscv: dts: allwinner: Add ClockworkPi and DevTerm devicetrees Samuel Holland
2022-12-08  9:02   ` Samuel Holland
2022-12-08  9:02   ` Samuel Holland
2022-12-08  9:02 ` [PATCH v3 11/12] riscv: Add the Allwinner SoC family Kconfig option Samuel Holland
2022-12-08  9:02   ` Samuel Holland
2022-12-08  9:02   ` Samuel Holland
2022-12-08  9:10   ` Conor Dooley
2022-12-08  9:10     ` Conor Dooley
2022-12-08  9:10     ` Conor Dooley
2022-12-08  9:02 ` [PATCH v3 12/12] riscv: defconfig: Enable the Allwinner D1 platform and drivers Samuel Holland
2022-12-08  9:02   ` Samuel Holland
2022-12-08  9:02   ` Samuel Holland
2022-12-08  9:09   ` Conor Dooley
2022-12-08  9:09     ` Conor Dooley
2022-12-08  9:09     ` Conor Dooley
2022-12-19 10:55   ` Heiko Stübner
2022-12-19 10:55     ` Heiko Stübner
2022-12-19 10:55     ` Heiko Stübner
2022-12-17 17:43 ` [PATCH v3 00/12] riscv: Allwinner D1/D1s platform support Conor Dooley
2022-12-17 17:43   ` Conor Dooley
2022-12-17 17:43   ` Conor Dooley
2022-12-19  9:43   ` Icenowy Zheng
2022-12-19  9:43     ` Icenowy Zheng
2022-12-19  9:43     ` Icenowy Zheng
2022-12-19 17:00     ` Conor Dooley
2022-12-19 17:00       ` Conor Dooley
2022-12-19 17:00       ` Conor Dooley
2022-12-19 11:13 ` Heiko Stübner
2022-12-19 11:13   ` Heiko Stübner
2022-12-19 11:13   ` Heiko Stübner

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