* [PATCH 1/5] dma/hisilicon: support Kunpeng930 DMA devices
2022-02-17 2:59 [PATCH 0/5] add Kunpeng930 DMA devices Chengwen Feng
@ 2022-02-17 2:59 ` Chengwen Feng
2022-02-17 2:59 ` [PATCH 2/5] dma/hisilicon: support handles errors with Kunpeng930 DMA Chengwen Feng
` (4 subsequent siblings)
5 siblings, 0 replies; 7+ messages in thread
From: Chengwen Feng @ 2022-02-17 2:59 UTC (permalink / raw)
To: thomas; +Cc: dev
The Kunpeng930 DMA devices have the same PCI device id with Kunpeng920,
but with different PCI revision and register layout. This patch
introduces the basic initialization for Kunpeng930 DMA devices.
Signed-off-by: Chengwen Feng <fengchengwen@huawei.com>
---
doc/guides/dmadevs/hisilicon.rst | 1 +
doc/guides/rel_notes/release_22_03.rst | 4 +++
drivers/dma/hisilicon/hisi_dmadev.c | 34 +++++++++++++++++++++++---
drivers/dma/hisilicon/hisi_dmadev.h | 28 ++++++++++++++++-----
4 files changed, 58 insertions(+), 9 deletions(-)
diff --git a/doc/guides/dmadevs/hisilicon.rst b/doc/guides/dmadevs/hisilicon.rst
index 191e56f2f7..81bf090311 100644
--- a/doc/guides/dmadevs/hisilicon.rst
+++ b/doc/guides/dmadevs/hisilicon.rst
@@ -13,6 +13,7 @@ Supported Kunpeng SoCs
----------------------
* Kunpeng 920
+* Kunpeng 930
Device Setup
diff --git a/doc/guides/rel_notes/release_22_03.rst b/doc/guides/rel_notes/release_22_03.rst
index ff3095d742..272f71af76 100644
--- a/doc/guides/rel_notes/release_22_03.rst
+++ b/doc/guides/rel_notes/release_22_03.rst
@@ -144,6 +144,10 @@ New Features
The new API ``rte_event_eth_rx_adapter_event_port_get()`` was added.
+* **Added support for Kunpeng930 DMA devices to HiSilicon DMA PMD.**
+
+ * Kunpeng930 DMA devices are now enabled for HiSilicon DMA PMD.
+
* **Updated testpmd.**
* Called ``rte_ipv4/6_udptcp_cksum_mbuf()`` functions in testpmd csum mode
diff --git a/drivers/dma/hisilicon/hisi_dmadev.c b/drivers/dma/hisilicon/hisi_dmadev.c
index 05066b4d0e..d4e08994a8 100644
--- a/drivers/dma/hisilicon/hisi_dmadev.c
+++ b/drivers/dma/hisilicon/hisi_dmadev.c
@@ -39,6 +39,8 @@ hisi_dma_queue_base(struct hisi_dma_dev *hw)
{
if (hw->reg_layout == HISI_DMA_REG_LAYOUT_HIP08)
return HISI_DMA_HIP08_QUEUE_BASE;
+ else if (hw->reg_layout == HISI_DMA_REG_LAYOUT_HIP09)
+ return HISI_DMA_HIP09_QUEUE_BASE;
else
return 0;
}
@@ -174,7 +176,7 @@ hisi_dma_reset_hw(struct hisi_dma_dev *hw)
}
static void
-hisi_dma_init_hw(struct hisi_dma_dev *hw)
+hisi_dma_init_common(struct hisi_dma_dev *hw)
{
hisi_dma_write_queue(hw, HISI_DMA_QUEUE_SQ_BASE_L_REG,
lower_32_bits(hw->sqe_iova));
@@ -192,6 +194,12 @@ hisi_dma_init_hw(struct hisi_dma_dev *hw)
hisi_dma_write_queue(hw, HISI_DMA_QUEUE_ERR_INT_NUM0_REG, 0);
hisi_dma_write_queue(hw, HISI_DMA_QUEUE_ERR_INT_NUM1_REG, 0);
hisi_dma_write_queue(hw, HISI_DMA_QUEUE_ERR_INT_NUM2_REG, 0);
+}
+
+static void
+hisi_dma_init_hw(struct hisi_dma_dev *hw)
+{
+ hisi_dma_init_common(hw);
if (hw->reg_layout == HISI_DMA_REG_LAYOUT_HIP08) {
hisi_dma_write_queue(hw, HISI_DMA_HIP08_QUEUE_ERR_INT_NUM3_REG,
@@ -206,9 +214,27 @@ hisi_dma_init_hw(struct hisi_dma_dev *hw)
HISI_DMA_HIP08_QUEUE_CTRL0_ERR_ABORT_B, false);
hisi_dma_update_queue_mbit(hw, HISI_DMA_QUEUE_INT_STATUS_REG,
HISI_DMA_HIP08_QUEUE_INT_MASK_M, true);
- hisi_dma_update_queue_mbit(hw,
- HISI_DMA_HIP08_QUEUE_INT_MASK_REG,
+ hisi_dma_update_queue_mbit(hw, HISI_DMA_QUEUE_INT_MASK_REG,
HISI_DMA_HIP08_QUEUE_INT_MASK_M, true);
+ } else if (hw->reg_layout == HISI_DMA_REG_LAYOUT_HIP09) {
+ hisi_dma_update_queue_mbit(hw, HISI_DMA_QUEUE_CTRL0_REG,
+ HISI_DMA_HIP09_QUEUE_CTRL0_ERR_ABORT_M, false);
+ hisi_dma_update_queue_mbit(hw, HISI_DMA_QUEUE_INT_STATUS_REG,
+ HISI_DMA_HIP09_QUEUE_INT_MASK_M, true);
+ hisi_dma_update_queue_mbit(hw, HISI_DMA_QUEUE_INT_MASK_REG,
+ HISI_DMA_HIP09_QUEUE_INT_MASK_M, true);
+ hisi_dma_update_queue_mbit(hw,
+ HISI_DMA_HIP09_QUEUE_ERR_INT_STATUS_REG,
+ HISI_DMA_HIP09_QUEUE_ERR_INT_MASK_M, true);
+ hisi_dma_update_queue_mbit(hw,
+ HISI_DMA_HIP09_QUEUE_ERR_INT_MASK_REG,
+ HISI_DMA_HIP09_QUEUE_ERR_INT_MASK_M, true);
+ hisi_dma_update_queue_bit(hw, HISI_DMA_QUEUE_CTRL1_REG,
+ HISI_DMA_HIP09_QUEUE_CTRL1_VA_ENABLE_B, true);
+ hisi_dma_update_bit(hw,
+ HISI_DMA_HIP09_QUEUE_CFG_REG(hw->queue_id),
+ HISI_DMA_HIP09_QUEUE_CFG_LINK_DOWN_MASK_B,
+ true);
}
}
@@ -230,6 +256,8 @@ hisi_dma_reg_layout(uint8_t revision)
{
if (revision == HISI_DMA_REVISION_HIP08B)
return HISI_DMA_REG_LAYOUT_HIP08;
+ else if (revision >= HISI_DMA_REVISION_HIP09A)
+ return HISI_DMA_REG_LAYOUT_HIP09;
else
return HISI_DMA_REG_LAYOUT_INVALID;
}
diff --git a/drivers/dma/hisilicon/hisi_dmadev.h b/drivers/dma/hisilicon/hisi_dmadev.h
index 12e209c86e..591aec0b32 100644
--- a/drivers/dma/hisilicon/hisi_dmadev.h
+++ b/drivers/dma/hisilicon/hisi_dmadev.h
@@ -23,20 +23,22 @@
#define HISI_DMA_DEVICE_ID 0xA122
#define HISI_DMA_PCI_REVISION_ID_REG 0x08
#define HISI_DMA_REVISION_HIP08B 0x21
+#define HISI_DMA_REVISION_HIP09A 0x30
#define HISI_DMA_MAX_HW_QUEUES 4
#define HISI_DMA_MAX_DESC_NUM 8192
#define HISI_DMA_MIN_DESC_NUM 32
/**
- * The HIP08B(HiSilicon IP08) and later Chip(e.g. HiSilicon IP09) are DMA iEPs,
- * they have the same pci device id but with different pci revision.
- * Unfortunately, they have different register layouts, so the layout
+ * The HIP08B(HiSilicon IP08) and HIP09B(HiSilicon IP09) are DMA iEPs, they
+ * have the same pci device id but different pci revision.
+ * Unfortunately, they have different register layouts, so two layout
* enumerations are defined.
*/
enum {
HISI_DMA_REG_LAYOUT_INVALID = 0,
- HISI_DMA_REG_LAYOUT_HIP08
+ HISI_DMA_REG_LAYOUT_HIP08,
+ HISI_DMA_REG_LAYOUT_HIP09
};
/**
@@ -66,7 +68,7 @@ enum {
* calculated by:
* offset = queue-base + (queue-id * queue-region) + reg-offset-in-region.
*
- * The first part of queue region is basically the same for HIP08 and later chip
+ * The first part of queue region is basically the same for HIP08 and HIP09
* register layouts, therefore, HISI_QUEUE_* registers are defined for it.
*/
#define HISI_DMA_QUEUE_SQ_BASE_L_REG 0x0
@@ -85,6 +87,7 @@ enum {
#define HISI_DMA_QUEUE_FSM_REG 0x30
#define HISI_DMA_QUEUE_FSM_STS_M GENMASK(3, 0)
#define HISI_DMA_QUEUE_INT_STATUS_REG 0x40
+#define HISI_DMA_QUEUE_INT_MASK_REG 0x44
#define HISI_DMA_QUEUE_ERR_INT_NUM0_REG 0x84
#define HISI_DMA_QUEUE_ERR_INT_NUM1_REG 0x88
#define HISI_DMA_QUEUE_ERR_INT_NUM2_REG 0x8C
@@ -95,7 +98,6 @@ enum {
*/
#define HISI_DMA_HIP08_QUEUE_BASE 0x0
#define HISI_DMA_HIP08_QUEUE_CTRL0_ERR_ABORT_B 2
-#define HISI_DMA_HIP08_QUEUE_INT_MASK_REG 0x44
#define HISI_DMA_HIP08_QUEUE_INT_MASK_M GENMASK(14, 0)
#define HISI_DMA_HIP08_QUEUE_ERR_INT_NUM3_REG 0x90
#define HISI_DMA_HIP08_QUEUE_ERR_INT_NUM4_REG 0x94
@@ -106,6 +108,20 @@ enum {
#define HISI_DMA_HIP08_DUMP_START_REG 0x2000
#define HISI_DMA_HIP08_DUMP_END_REG 0x2280
+/**
+ * HiSilicon IP09 DMA register and field define:
+ */
+#define HISI_DMA_HIP09_QUEUE_BASE 0x2000
+#define HISI_DMA_HIP09_QUEUE_CTRL0_ERR_ABORT_M GENMASK(31, 28)
+#define HISI_DMA_HIP09_QUEUE_CTRL1_VA_ENABLE_B 2
+#define HISI_DMA_HIP09_QUEUE_INT_MASK_M 0x1
+#define HISI_DMA_HIP09_QUEUE_ERR_INT_STATUS_REG 0x48
+#define HISI_DMA_HIP09_QUEUE_ERR_INT_MASK_REG 0x4C
+#define HISI_DMA_HIP09_QUEUE_ERR_INT_MASK_M GENMASK(18, 1)
+#define HISI_DMA_HIP09_QUEUE_CFG_REG(queue_id) (0x800 + \
+ (queue_id) * 0x20)
+#define HISI_DMA_HIP09_QUEUE_CFG_LINK_DOWN_MASK_B 16
+
/**
* In fact, there are multiple states, but it need to pay attention to
* the following two states for the driver:
--
2.33.0
^ permalink raw reply related [flat|nested] 7+ messages in thread* [PATCH 2/5] dma/hisilicon: support handles errors with Kunpeng930 DMA
2022-02-17 2:59 [PATCH 0/5] add Kunpeng930 DMA devices Chengwen Feng
2022-02-17 2:59 ` [PATCH 1/5] dma/hisilicon: support " Chengwen Feng
@ 2022-02-17 2:59 ` Chengwen Feng
2022-02-17 2:59 ` [PATCH 3/5] dma/hisilicon: support dump Kunpeng930 DMA registers Chengwen Feng
` (3 subsequent siblings)
5 siblings, 0 replies; 7+ messages in thread
From: Chengwen Feng @ 2022-02-17 2:59 UTC (permalink / raw)
To: thomas; +Cc: dev
The Kunpeng930 DMA supports the capability of handles errors.
Signed-off-by: Chengwen Feng <fengchengwen@huawei.com>
---
drivers/dma/hisilicon/hisi_dmadev.c | 5 ++++-
1 file changed, 4 insertions(+), 1 deletion(-)
diff --git a/drivers/dma/hisilicon/hisi_dmadev.c b/drivers/dma/hisilicon/hisi_dmadev.c
index d4e08994a8..b99a9bce6c 100644
--- a/drivers/dma/hisilicon/hisi_dmadev.c
+++ b/drivers/dma/hisilicon/hisi_dmadev.c
@@ -328,11 +328,14 @@ hisi_dma_info_get(const struct rte_dma_dev *dev,
struct rte_dma_info *dev_info,
uint32_t info_sz)
{
- RTE_SET_USED(dev);
+ struct hisi_dma_dev *hw = dev->data->dev_private;
RTE_SET_USED(info_sz);
dev_info->dev_capa = RTE_DMA_CAPA_MEM_TO_MEM |
RTE_DMA_CAPA_OPS_COPY;
+ if (hw->reg_layout == HISI_DMA_REG_LAYOUT_HIP09)
+ dev_info->dev_capa |= RTE_DMA_CAPA_HANDLES_ERRORS;
+
dev_info->max_vchans = 1;
dev_info->max_desc = HISI_DMA_MAX_DESC_NUM;
dev_info->min_desc = HISI_DMA_MIN_DESC_NUM;
--
2.33.0
^ permalink raw reply related [flat|nested] 7+ messages in thread* [PATCH 3/5] dma/hisilicon: support dump Kunpeng930 DMA registers
2022-02-17 2:59 [PATCH 0/5] add Kunpeng930 DMA devices Chengwen Feng
2022-02-17 2:59 ` [PATCH 1/5] dma/hisilicon: support " Chengwen Feng
2022-02-17 2:59 ` [PATCH 2/5] dma/hisilicon: support handles errors with Kunpeng930 DMA Chengwen Feng
@ 2022-02-17 2:59 ` Chengwen Feng
2022-02-17 2:59 ` [PATCH 4/5] dma/hisilicon: add queue full statistics Chengwen Feng
` (2 subsequent siblings)
5 siblings, 0 replies; 7+ messages in thread
From: Chengwen Feng @ 2022-02-17 2:59 UTC (permalink / raw)
To: thomas; +Cc: dev
This patch supports dump Kunpeng930 DMA registers.
Signed-off-by: Chengwen Feng <fengchengwen@huawei.com>
---
drivers/dma/hisilicon/hisi_dmadev.c | 54 +++++++++++++++++++----------
drivers/dma/hisilicon/hisi_dmadev.h | 8 +++++
2 files changed, 44 insertions(+), 18 deletions(-)
diff --git a/drivers/dma/hisilicon/hisi_dmadev.c b/drivers/dma/hisilicon/hisi_dmadev.c
index b99a9bce6c..3917db38b7 100644
--- a/drivers/dma/hisilicon/hisi_dmadev.c
+++ b/drivers/dma/hisilicon/hisi_dmadev.c
@@ -460,29 +460,13 @@ hisi_dma_stats_reset(struct rte_dma_dev *dev, uint16_t vchan)
}
static void
-hisi_dma_get_dump_range(struct hisi_dma_dev *hw, uint32_t *start, uint32_t *end)
-{
- if (hw->reg_layout == HISI_DMA_REG_LAYOUT_HIP08) {
- *start = HISI_DMA_HIP08_DUMP_START_REG;
- *end = HISI_DMA_HIP08_DUMP_END_REG;
- } else {
- *start = 0;
- *end = 0;
- }
-}
-
-static void
-hisi_dma_dump_common(struct hisi_dma_dev *hw, FILE *f)
+hisi_dma_dump_range(struct hisi_dma_dev *hw, FILE *f, uint32_t start,
+ uint32_t end)
{
#define DUMP_REGNUM_PER_LINE 4
- uint32_t start, end;
uint32_t cnt, i;
- hisi_dma_get_dump_range(hw, &start, &end);
-
- (void)fprintf(f, " common-register:\n");
-
cnt = 0;
for (i = start; i <= end; i += sizeof(uint32_t)) {
if (cnt % DUMP_REGNUM_PER_LINE == 0)
@@ -496,6 +480,40 @@ hisi_dma_dump_common(struct hisi_dma_dev *hw, FILE *f)
(void)fprintf(f, "\n");
}
+static void
+hisi_dma_dump_common(struct hisi_dma_dev *hw, FILE *f)
+{
+ struct {
+ uint8_t reg_layout;
+ uint32_t start;
+ uint32_t end;
+ } reg_info[] = {
+ { HISI_DMA_REG_LAYOUT_HIP08,
+ HISI_DMA_HIP08_DUMP_START_REG,
+ HISI_DMA_HIP08_DUMP_END_REG },
+ { HISI_DMA_REG_LAYOUT_HIP09,
+ HISI_DMA_HIP09_DUMP_REGION_A_START_REG,
+ HISI_DMA_HIP09_DUMP_REGION_A_END_REG },
+ { HISI_DMA_REG_LAYOUT_HIP09,
+ HISI_DMA_HIP09_DUMP_REGION_B_START_REG,
+ HISI_DMA_HIP09_DUMP_REGION_B_END_REG },
+ { HISI_DMA_REG_LAYOUT_HIP09,
+ HISI_DMA_HIP09_DUMP_REGION_C_START_REG,
+ HISI_DMA_HIP09_DUMP_REGION_C_END_REG },
+ { HISI_DMA_REG_LAYOUT_HIP09,
+ HISI_DMA_HIP09_DUMP_REGION_D_START_REG,
+ HISI_DMA_HIP09_DUMP_REGION_D_END_REG },
+ };
+ uint32_t i;
+
+ (void)fprintf(f, " common-register:\n");
+ for (i = 0; i < RTE_DIM(reg_info); i++) {
+ if (hw->reg_layout != reg_info[i].reg_layout)
+ continue;
+ hisi_dma_dump_range(hw, f, reg_info[i].start, reg_info[i].end);
+ }
+}
+
static void
hisi_dma_dump_read_queue(struct hisi_dma_dev *hw, uint32_t qoff,
char *buffer, int max_sz)
diff --git a/drivers/dma/hisilicon/hisi_dmadev.h b/drivers/dma/hisilicon/hisi_dmadev.h
index 591aec0b32..1eaa822db1 100644
--- a/drivers/dma/hisilicon/hisi_dmadev.h
+++ b/drivers/dma/hisilicon/hisi_dmadev.h
@@ -121,6 +121,14 @@ enum {
#define HISI_DMA_HIP09_QUEUE_CFG_REG(queue_id) (0x800 + \
(queue_id) * 0x20)
#define HISI_DMA_HIP09_QUEUE_CFG_LINK_DOWN_MASK_B 16
+#define HISI_DMA_HIP09_DUMP_REGION_A_START_REG 0x0
+#define HISI_DMA_HIP09_DUMP_REGION_A_END_REG 0x368
+#define HISI_DMA_HIP09_DUMP_REGION_B_START_REG 0x800
+#define HISI_DMA_HIP09_DUMP_REGION_B_END_REG 0xA08
+#define HISI_DMA_HIP09_DUMP_REGION_C_START_REG 0x1800
+#define HISI_DMA_HIP09_DUMP_REGION_C_END_REG 0x1A4C
+#define HISI_DMA_HIP09_DUMP_REGION_D_START_REG 0x1C00
+#define HISI_DMA_HIP09_DUMP_REGION_D_END_REG 0x1CC4
/**
* In fact, there are multiple states, but it need to pay attention to
--
2.33.0
^ permalink raw reply related [flat|nested] 7+ messages in thread* [PATCH 4/5] dma/hisilicon: add queue full statistics
2022-02-17 2:59 [PATCH 0/5] add Kunpeng930 DMA devices Chengwen Feng
` (2 preceding siblings ...)
2022-02-17 2:59 ` [PATCH 3/5] dma/hisilicon: support dump Kunpeng930 DMA registers Chengwen Feng
@ 2022-02-17 2:59 ` Chengwen Feng
2022-02-17 2:59 ` [PATCH 5/5] dma/hisilicon: use EAL API to generate dmadev name Chengwen Feng
2022-02-23 15:50 ` [PATCH 0/5] add Kunpeng930 DMA devices Thomas Monjalon
5 siblings, 0 replies; 7+ messages in thread
From: Chengwen Feng @ 2022-02-17 2:59 UTC (permalink / raw)
To: thomas; +Cc: dev
This patch adds queue full statistics for HiSilicon DMA PMD.
Signed-off-by: Chengwen Feng <fengchengwen@huawei.com>
---
drivers/dma/hisilicon/hisi_dmadev.c | 12 ++++++++----
drivers/dma/hisilicon/hisi_dmadev.h | 1 +
2 files changed, 9 insertions(+), 4 deletions(-)
diff --git a/drivers/dma/hisilicon/hisi_dmadev.c b/drivers/dma/hisilicon/hisi_dmadev.c
index 3917db38b7..c36acf01be 100644
--- a/drivers/dma/hisilicon/hisi_dmadev.c
+++ b/drivers/dma/hisilicon/hisi_dmadev.c
@@ -407,6 +407,7 @@ hisi_dma_start(struct rte_dma_dev *dev)
hw->submitted = 0;
hw->completed = 0;
hw->errors = 0;
+ hw->qfulls = 0;
hisi_dma_update_queue_bit(hw, HISI_DMA_QUEUE_CTRL0_REG,
HISI_DMA_QUEUE_CTRL0_EN_B, true);
@@ -455,6 +456,7 @@ hisi_dma_stats_reset(struct rte_dma_dev *dev, uint16_t vchan)
hw->submitted = 0;
hw->completed = 0;
hw->errors = 0;
+ hw->qfulls = 0;
return 0;
}
@@ -566,14 +568,14 @@ hisi_dma_dump(const struct rte_dma_dev *dev, FILE *f)
" ridx: %u cridx: %u\n"
" sq_head: %u sq_tail: %u cq_sq_head: %u\n"
" cq_head: %u cqs_completed: %u cqe_vld: %u\n"
- " submitted: %" PRIu64 " completed: %" PRIu64 " errors %"
- PRIu64"\n",
+ " submitted: %" PRIu64 " completed: %" PRIu64 " errors: %"
+ PRIu64 " qfulls: %" PRIu64 "\n",
hw->revision, hw->queue_id,
hw->sq_depth_mask > 0 ? hw->sq_depth_mask + 1 : 0,
hw->ridx, hw->cridx,
hw->sq_head, hw->sq_tail, hw->cq_sq_head,
hw->cq_head, hw->cqs_completed, hw->cqe_vld,
- hw->submitted, hw->completed, hw->errors);
+ hw->submitted, hw->completed, hw->errors, hw->qfulls);
hisi_dma_dump_queue(hw, f);
hisi_dma_dump_common(hw, f);
@@ -590,8 +592,10 @@ hisi_dma_copy(void *dev_private, uint16_t vchan,
RTE_SET_USED(vchan);
- if (((hw->sq_tail + 1) & hw->sq_depth_mask) == hw->sq_head)
+ if (((hw->sq_tail + 1) & hw->sq_depth_mask) == hw->sq_head) {
+ hw->qfulls++;
return -ENOSPC;
+ }
sqe->dw0 = rte_cpu_to_le_32(SQE_OPCODE_M2M);
sqe->dw1 = 0;
diff --git a/drivers/dma/hisilicon/hisi_dmadev.h b/drivers/dma/hisilicon/hisi_dmadev.h
index 1eaa822db1..90b85322ca 100644
--- a/drivers/dma/hisilicon/hisi_dmadev.h
+++ b/drivers/dma/hisilicon/hisi_dmadev.h
@@ -241,6 +241,7 @@ struct hisi_dma_dev {
uint64_t submitted;
uint64_t completed;
uint64_t errors;
+ uint64_t qfulls;
/**
* The following fields are not accessed in the I/O path, so they are
--
2.33.0
^ permalink raw reply related [flat|nested] 7+ messages in thread* [PATCH 5/5] dma/hisilicon: use EAL API to generate dmadev name
2022-02-17 2:59 [PATCH 0/5] add Kunpeng930 DMA devices Chengwen Feng
` (3 preceding siblings ...)
2022-02-17 2:59 ` [PATCH 4/5] dma/hisilicon: add queue full statistics Chengwen Feng
@ 2022-02-17 2:59 ` Chengwen Feng
2022-02-23 15:50 ` [PATCH 0/5] add Kunpeng930 DMA devices Thomas Monjalon
5 siblings, 0 replies; 7+ messages in thread
From: Chengwen Feng @ 2022-02-17 2:59 UTC (permalink / raw)
To: thomas; +Cc: dev
For DMA device 0000:7d:0.0, the original generated dmadev name starts
with the "7d:0.0", which is not expected.
This patch uses rte_pci_device_name API to generates the dmadev name.
Cc: stable@dpdk.org
Signed-off-by: Chengwen Feng <fengchengwen@huawei.com>
---
doc/guides/dmadevs/hisilicon.rst | 4 ++--
drivers/dma/hisilicon/hisi_dmadev.c | 23 +++++++----------------
2 files changed, 9 insertions(+), 18 deletions(-)
diff --git a/doc/guides/dmadevs/hisilicon.rst b/doc/guides/dmadevs/hisilicon.rst
index 81bf090311..8c1f0f8886 100644
--- a/doc/guides/dmadevs/hisilicon.rst
+++ b/doc/guides/dmadevs/hisilicon.rst
@@ -30,8 +30,8 @@ which can be accessed using API from the ``rte_dmadev`` library.
The name of the ``dmadev`` created is like "B:D.F-chX", e.g. DMA 0000:7b:00.0
will create four ``dmadev``,
-the 1st ``dmadev`` name is "7b:00.0-ch0",
-and the 2nd ``dmadev`` name is "7b:00.0-ch1".
+the 1st ``dmadev`` name is "0000:7b:00.0-ch0",
+and the 2nd ``dmadev`` name is "0000:7b:00.0-ch1".
Device Configuration
~~~~~~~~~~~~~~~~~~~~~
diff --git a/drivers/dma/hisilicon/hisi_dmadev.c b/drivers/dma/hisilicon/hisi_dmadev.c
index c36acf01be..9cef2cbfbe 100644
--- a/drivers/dma/hisilicon/hisi_dmadev.c
+++ b/drivers/dma/hisilicon/hisi_dmadev.c
@@ -784,24 +784,15 @@ hisi_dma_burst_capacity(const void *dev_private, uint16_t vchan)
sq_head - 1 - sq_tail;
}
-static void
-hisi_dma_gen_pci_device_name(const struct rte_pci_device *pci_dev,
- char *name, size_t size)
-{
- memset(name, 0, size);
- (void)snprintf(name, size, "%x:%x.%x",
- pci_dev->addr.bus, pci_dev->addr.devid,
- pci_dev->addr.function);
-}
-
static void
hisi_dma_gen_dev_name(const struct rte_pci_device *pci_dev,
- uint8_t queue_id, char *name, size_t size)
+ uint8_t queue_id, char *dev_name, size_t size)
{
- memset(name, 0, size);
- (void)snprintf(name, size, "%x:%x.%x-ch%u",
- pci_dev->addr.bus, pci_dev->addr.devid,
- pci_dev->addr.function, queue_id);
+ char name[RTE_DEV_NAME_MAX_LEN] = { 0 };
+
+ memset(dev_name, 0, size);
+ rte_pci_device_name(&pci_dev->addr, name, sizeof(name));
+ (void)snprintf(dev_name, size, "%s-ch%u", name, queue_id);
}
/**
@@ -917,7 +908,7 @@ hisi_dma_probe(struct rte_pci_driver *pci_drv __rte_unused,
uint8_t i;
int ret;
- hisi_dma_gen_pci_device_name(pci_dev, name, sizeof(name));
+ rte_pci_device_name(&pci_dev->addr, name, sizeof(name));
if (pci_dev->mem_resource[2].addr == NULL) {
HISI_DMA_LOG(ERR, "%s BAR2 is NULL!\n", name);
--
2.33.0
^ permalink raw reply related [flat|nested] 7+ messages in thread* Re: [PATCH 0/5] add Kunpeng930 DMA devices
2022-02-17 2:59 [PATCH 0/5] add Kunpeng930 DMA devices Chengwen Feng
` (4 preceding siblings ...)
2022-02-17 2:59 ` [PATCH 5/5] dma/hisilicon: use EAL API to generate dmadev name Chengwen Feng
@ 2022-02-23 15:50 ` Thomas Monjalon
5 siblings, 0 replies; 7+ messages in thread
From: Thomas Monjalon @ 2022-02-23 15:50 UTC (permalink / raw)
To: Chengwen Feng; +Cc: dev
17/02/2022 03:59, Chengwen Feng:
> This patchset add Kunpeng930 DMA devices, and also include two patch
> used to enhance HiSilicon DMA PMD.
>
> Chengwen Feng (5):
> dma/hisilicon: support Kunpeng930 DMA devices
> dma/hisilicon: support handles errors with Kunpeng930 DMA
> dma/hisilicon: support dump Kunpeng930 DMA registers
> dma/hisilicon: add queue full statistics
> dma/hisilicon: use EAL API to generate dmadev name
Applied, thanks.
^ permalink raw reply [flat|nested] 7+ messages in thread