From: Andrii Anisov <andrii.anisov@gmail.com>
To: Julien Grall <julien.grall@arm.com>,
Julien Grall <julien.grall@gmail.com>
Cc: "andre.przywara@arm.com" <andre.przywara@arm.com>,
Oleksandr Tyshchenko <Oleksandr_Tyshchenko@epam.com>,
"sstabellini@kernel.org" <sstabellini@kernel.org>,
Andrii Anisov <Andrii_Anisov@epam.com>,
"xen-devel@lists.xen.org" <xen-devel@lists.xen.org>
Subject: Re: [PATCH 1/4] xen/arm: gic: Ensure we have an ISB between ack and do_IRQ()
Date: Thu, 22 Nov 2018 18:51:13 +0200 [thread overview]
Message-ID: <2199be43-ef12-28c3-4dcb-cac404be1e4d@gmail.com> (raw)
In-Reply-To: <4ceea0f6-ede1-420a-d3b7-80c4584739ce@arm.com>
Hello Julien,
On 20.11.18 20:47, Julien Grall wrote:
>
>
> On 20/11/2018 18:10, Andrii Anisov wrote:
>> Hello Julien,
>>
>>
>> On 19.11.18 18:42, Julien Grall wrote:
>>> There are no issue about processing IRQs before the syncs. It is the
>>> same as if an IRQ was raised from ila different pCPUs.
>>> So why do you need that?
>>
>> From my understanding of gic-vgic code (old vgic), for the IRQs
>> targeting the `current` vcpu, it leads to a faster processing under
>> interrupts storm conditions. If it was all LRs set on previous switch
>> to a guest, a the IRQ will have a chance to go directly to LR instead
>> of setting on lr_pending queue. Also inflight_irqs queue have a chance
>> to be shorter to insert.
>
> Do you have actual numbers?
Unfortunately, my numbers are pretty indirect. I'm referring glmark2
benchmark results. With this and the rest of my changes (not yet
published), I can cut out another percent or two of performance drop due
to XEN existence in the system. BTW, that's why I recently asked Stefano
about his approach of interrupt latency measurement.
On my board that benchmark processing causes at least 4 different HW
interrupts issuing with different frequency. Adding the reschedule IRQ
makes the system tend to not fit all IRQs into 4 LRs available in my
GIC. Moreover, the benchmark does not emit a network traffic or disk
usage during the run. So real life cases will add more concurrent IRQs.
> Also to be on the same page, what is your
> definition of interrupts storm?
I mean the system takes different interrupts (more IRQ sources than LRs
available) with a relatively high rate. Let's say more than 7000
interrupts per second. It's not very big number, but close to what I see
on my desk.
> Bear in mind that the old vGIC will be phased out soon.
As I remember a new vgic experimental yet. Do not support GIC-v3 yet.
> If you are
> worried about performance, then I would recommend to try the new vGIC
> and see whether it improves.
You know, we are based on XEN 4.10. Initially, when a customer said
about their dissatisfaction about performance drop in benchmark due to
XEN existence, I tried 4.12-unstable, both an old and a new VGIC. So
performance with 4.12-unstable with the old VGIC was worse than 4.10,
and the new VGIC made things even much worse. I can't remember the exact
numbers or proportions, but that was the reason we do not offer
upgrading XEN yet.
> Well, if you re-enable the interrupts you give a chance for higher
> priority interrupts to come up. This will not happen if you have
> interrupts disabled.
I understand the theory, but can not match it with the current XEN code.
Guest interrupts prioritization within do_IRQ is pretty meaningless.
They will go through the same path. And an effect would not be seen
before exiting to a guest.
The PPI interrupts are reflected into the processing of soft IRQs or
injecting an IRQ into queues. So it does not matter much when exactly we
do read the IRQ from IAR in a gic_interrupt loop. I suppose it should be
faster to loop through gic_interrupt at once, collecting all interrupts,
without going through exception path, then switch to soft IRQs
processing in leave_hypervisor_tail.
The only thing which might get a noticeable effect here is serving
GIC_SGI_CALL_FUNCTION, which is executed right away from `gic_interrupt`.
> But you seem to base your assumption on interrupts storm (yet to be
> defined). If you have an interrupt storm, then you are already doomed as
> your guest/Xen will not have time to do any other work.
>
> In any case, you need to provide number to support your optimization.I'm moving all my patches to current staging and would send them as RFC
with a description of why is it done and how I measured results.
--
Sincerely,
Andrii Anisov.
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next prev parent reply other threads:[~2018-11-22 16:51 UTC|newest]
Thread overview: 59+ messages / expand[flat|nested] mbox.gz Atom feed top
2018-10-23 18:17 [PATCH 0/4] xen/arm: GIC fixes and improvement Julien Grall
2018-10-23 18:17 ` [PATCH 1/4] xen/arm: gic: Ensure we have an ISB between ack and do_IRQ() Julien Grall
2018-10-24 9:38 ` Andrii Anisov
2018-10-24 14:41 ` Julien Grall
2018-10-25 14:11 ` Andrii Anisov
2018-10-25 14:22 ` Julien Grall
2018-10-25 17:45 ` Andrii Anisov
2018-10-26 12:49 ` Andrii Anisov
2018-10-26 21:55 ` Julien Grall
2018-10-27 12:14 ` Andrii Anisov
2018-10-28 11:46 ` Julien Grall
2018-10-29 10:06 ` Andrii Anisov
2018-10-29 13:36 ` Julien Grall
2018-10-29 16:16 ` Andrii Anisov
2018-10-29 16:22 ` Julien Grall
2018-10-30 8:07 ` Andrii Anisov
2018-11-09 14:42 ` Andrii Anisov
2018-11-09 17:47 ` Julien Grall
2018-11-19 15:54 ` Andrii Anisov
2018-11-19 16:42 ` Julien Grall
2018-11-20 18:10 ` Andrii Anisov
2018-11-20 18:47 ` Julien Grall
2018-11-22 16:51 ` Andrii Anisov [this message]
2018-11-22 17:22 ` Julien Grall
2018-11-23 10:09 ` Andrii Anisov
2018-11-23 12:18 ` Andre Przywara
2018-11-23 13:04 ` Andrii Anisov
2018-11-30 19:52 ` Andrii Anisov
2018-12-03 13:46 ` Andre Przywara
2018-12-03 13:53 ` Juergen Gross
2018-12-03 14:36 ` Andrii Anisov
2018-12-04 17:16 ` Julien Grall
2018-12-03 15:28 ` Andrii Anisov
2018-11-28 0:30 ` Stefano Stabellini
2018-11-22 18:04 ` Andre Przywara
2018-11-23 12:58 ` Andrii Anisov
2018-11-23 13:27 ` Julien Grall
2018-11-27 13:30 ` Andrii Anisov
2018-11-27 15:13 ` Julien Grall
2018-12-03 12:08 ` Andrii Anisov
2018-12-03 12:17 ` Julien Grall
2018-12-03 12:58 ` Andrii Anisov
2018-12-03 13:10 ` Julien Grall
2018-10-25 17:46 ` Andrii Anisov
2018-11-09 23:02 ` Stefano Stabellini
2018-10-23 18:17 ` [PATCH 2/4] xen/arm: gic: Ensure ordering between read of INTACK and shared data Julien Grall
2018-10-24 15:40 ` Andrii Anisov
2018-11-09 23:02 ` Stefano Stabellini
2018-10-23 18:17 ` [PATCH 3/4] xen/arm: gic: Remove duplicated comment in do_sgi Julien Grall
2018-10-24 10:26 ` Andrii Anisov
2018-11-09 23:03 ` Stefano Stabellini
2018-10-23 18:17 ` [PATCH 4/4] xen/arm: gic: Relax barrier when sending an SGI Julien Grall
2018-10-24 13:32 ` Andrii Anisov
2018-10-24 14:46 ` Julien Grall
2018-10-24 15:40 ` Andrii Anisov
2018-10-24 15:44 ` Julien Grall
2018-11-09 23:14 ` Stefano Stabellini
2018-11-12 12:15 ` Julien Grall
-- strict thread matches above, loose matches on Subject: below --
2018-10-29 16:46 [PATCH 1/4] xen/arm: gic: Ensure we have an ISB between ack and do_IRQ() Andrii Anisov
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