Re: [PATCH v3] hw/ufs: Reset controller and MCQ state on HCE transition to 0

[Jeuk Kim <jeuk20.kim@gmail.com>]

On 9/2/2026 5:16 PM, Stanley Jhu wrote:
> According to the JEDEC Universal Flash Storage Host Controller Interface
> (UFSHCI) specification (Section 5.2.1 "Host Controller Enable"):
> when Host Controller Enable (HCE) transitions from 1 to 0, a host
> controller reset is initiated. The host controller shall abort all
> active transfers, return internal state machines to idle, and de-assert
> all interrupts.
>
> Currently, QEMU's UFS emulator only clears HCS and HCE registers upon
> HCE=0, leaving internal state active. Specifically:
> - Outstanding SCSI requests in the block layer are not purged.
> - Active bottom halves (doorbell_bh, complete_bh, and MCQ sq/cq BHs)
>    remain scheduled.
> - Allocated MCQ Submission and Completion Queues (sq and cq) are
>    not freed.
> - Dynamic MCQ queue registers, legacy UTRL request states, and status
>    registers (UTRLCNR, UTRLRSR) remain stale.
>
> Implement ufs_hce_reset() to:
> 1. Implement .cancel callback in ufs_scsi_info to properly unref
>     scsi_req and prevent reference leaks when SCSI requests are purged.
> 2. Cancel active bottom halves (doorbell_bh, complete_bh, and MCQ sq/cq
>     BHs) and guard them with a resetting flag before purging requests,
>     ensuring blk_drain() cannot run or reschedule request-producing BHs.
> 3. Purge outstanding SCSI requests for all logical units via
>     scsi_device_purge_requests().
> 4. Clear standard request list slots and release SGLs via
>     ufs_clear_req(), and clear doorbells and status registers (UTRLCNR,
>     UTRLRSR).
> 5. Free allocated MCQ queues and clear dynamic queue registers while
>     preserving static capability offsets.
> 6. De-assert interrupts via ufs_irq_check().
> 7. Add a trace_ufs_hce_reset() trace event.
>
> Signed-off-by: Stanley Jhu <stanleyjhu@google.com>
> ---


Thank you for your contribution.

Reviewed-by: Jeuk Kim <jeuk20.kim@samsung.com>