From: "Heiko Stübner" <heiko@sntech.de>
To: hl <hl@rock-chips.com>
Cc: Shawn Lin <shawn.lin@rock-chips.com>,
dbasehore@chromium.org, briannorris@chromium.org,
dianders@chromium.org, linux-rockchip@lists.infradead.org,
linux-clk@vger.kernel.org
Subject: Re: [PATCH v3 2/2] arm64: dts: rockchip: assign clock rate for some cpll child clock
Date: Tue, 20 Mar 2018 08:00:40 +0100 [thread overview]
Message-ID: <22053902.qFbnfPJqGC@diego> (raw)
In-Reply-To: <d92aa74d-7a49-8fbd-5efc-b931210ef0b7@rock-chips.com>
Am Dienstag, 20. März 2018, 03:23:41 CET schrieb hl:
> On Tuesday, March 20, 2018 10:12 AM, Shawn Lin wrote:
> > On 2018/3/20 10:06, Lin Huang wrote:
> >> These clocks do not assign default clock frequency, and use the
> >> default cru register value to get frequency, so if cpll increase
> >> frequency, these clocks also increase their frequency, that may
> >> exceed their signed off frequency. So assign default clock for
> >> them to avoid it.
> >>
> >> NOTE: on none of the boards currently in mainline do we expect
> >> CPLL to be anything other than 800 MHz, but some future boards
> >> might have it. It's still good to be explicit about the clock
> >> rates to make diffing against future boards easier and also to
> >> rely less on BIOS muxing.
> >>
> >> Change-Id: If79368aeda5c51dbf2a3b6659f17052a2ae4a401
> >
> > Should remove Change-Id for future patch(es), thought Heiko may help
> > do it when applied.
>
> Opp, sorry for that.
Yep, I can drop the changeId when applying
WARNING: multiple messages have this Message-ID (diff)
From: "Heiko Stübner" <heiko-4mtYJXux2i+zQB+pC5nmwQ@public.gmane.org>
To: hl <hl-TNX95d0MmH7DzftRWevZcw@public.gmane.org>
Cc: dbasehore-F7+t8E8rja9g9hUCZPvPmw@public.gmane.org,
Shawn Lin <shawn.lin-TNX95d0MmH7DzftRWevZcw@public.gmane.org>,
briannorris-F7+t8E8rja9g9hUCZPvPmw@public.gmane.org,
dianders-F7+t8E8rja9g9hUCZPvPmw@public.gmane.org,
linux-rockchip-IAPFreCvJWM7uuMidbF8XUB+6BGkLq7r@public.gmane.org,
linux-clk-u79uwXL29TY76Z2rM5mHXA@public.gmane.org
Subject: Re: [PATCH v3 2/2] arm64: dts: rockchip: assign clock rate for some cpll child clock
Date: Tue, 20 Mar 2018 08:00:40 +0100 [thread overview]
Message-ID: <22053902.qFbnfPJqGC@diego> (raw)
In-Reply-To: <d92aa74d-7a49-8fbd-5efc-b931210ef0b7-TNX95d0MmH7DzftRWevZcw@public.gmane.org>
Am Dienstag, 20. März 2018, 03:23:41 CET schrieb hl:
> On Tuesday, March 20, 2018 10:12 AM, Shawn Lin wrote:
> > On 2018/3/20 10:06, Lin Huang wrote:
> >> These clocks do not assign default clock frequency, and use the
> >> default cru register value to get frequency, so if cpll increase
> >> frequency, these clocks also increase their frequency, that may
> >> exceed their signed off frequency. So assign default clock for
> >> them to avoid it.
> >>
> >> NOTE: on none of the boards currently in mainline do we expect
> >> CPLL to be anything other than 800 MHz, but some future boards
> >> might have it. It's still good to be explicit about the clock
> >> rates to make diffing against future boards easier and also to
> >> rely less on BIOS muxing.
> >>
> >> Change-Id: If79368aeda5c51dbf2a3b6659f17052a2ae4a401
> >
> > Should remove Change-Id for future patch(es), thought Heiko may help
> > do it when applied.
>
> Opp, sorry for that.
Yep, I can drop the changeId when applying
next prev parent reply other threads:[~2018-03-20 7:00 UTC|newest]
Thread overview: 14+ messages / expand[flat|nested] mbox.gz Atom feed top
2018-03-20 2:06 [PATCH v3 1/2] clk: rockchip: assign correct id for pclk_ddr and hclk_sd in rk3399 Lin Huang
2018-03-20 2:06 ` Lin Huang
2018-03-20 2:06 ` [PATCH v3 2/2] arm64: dts: rockchip: assign clock rate for some cpll child clock Lin Huang
2018-03-20 2:06 ` Lin Huang
2018-03-20 2:12 ` Shawn Lin
2018-03-20 2:12 ` Shawn Lin
2018-03-20 2:23 ` hl
2018-03-20 2:23 ` hl
2018-03-20 7:00 ` Heiko Stübner [this message]
2018-03-20 7:00 ` Heiko Stübner
2018-03-23 8:45 ` Heiko Stuebner
2018-03-23 8:45 ` Heiko Stuebner
2018-03-23 8:26 ` [PATCH v3 1/2] clk: rockchip: assign correct id for pclk_ddr and hclk_sd in rk3399 Heiko Stuebner
2018-03-23 8:26 ` Heiko Stuebner
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