From: "Heiko Stübner" <heiko@sntech.de>
To: linux-riscv@lists.infradead.org, Andrew Jones <ajones@ventanamicro.com>
Cc: Palmer Dabbelt <palmer@dabbelt.com>,
Paul Walmsley <paul.walmsley@sifive.com>,
Albert Ou <aou@eecs.berkeley.edu>,
Conor Dooley <conor.dooley@microchip.com>,
Anup Patel <apatel@ventanamicro.com>,
Atish Patra <atishp@rivosinc.com>
Subject: Re: [PATCH v2 2/3] RISC-V: Introduce riscv_isa_extension_check
Date: Thu, 27 Oct 2022 15:08:28 +0200 [thread overview]
Message-ID: <2280350.irdbgypaU6@diego> (raw)
In-Reply-To: <20221024091309.406906-3-ajones@ventanamicro.com>
Am Montag, 24. Oktober 2022, 11:13:08 CEST schrieb Andrew Jones:
> Currently any isa extension found in the isa string is set in the
> isa bitmap. An isa extension set in the bitmap indicates that the
> extension is present and may be used (a.k.a is enabled). However,
> when an extension cannot be used due to missing dependencies or
> errata it should not be added to the bitmap. Introduce a function
> where additional checks may be placed in order to determine if an
> extension should be enabled or not.
>
> Note, the checks may simply indicate an issue with the DT, but,
> since extensions may be used in early boot, it's not always possible
> to simply produce an error at the point the issue is determined.
> It's best to keep the extension disabled and produce an error.
>
> No functional change intended, as the function is only introduced
> and always returns true. A later patch will provide checks for an
> isa extension.
>
> Signed-off-by: Andrew Jones <ajones@ventanamicro.com>
> Reviewed-by: Conor Dooley <conor.dooley@microchip.com>
Reviewed-by: Heiko Stuebner <heiko@sntech.de>
> ---
> arch/riscv/kernel/cpufeature.c | 14 +++++++++++---
> 1 file changed, 11 insertions(+), 3 deletions(-)
>
> diff --git a/arch/riscv/kernel/cpufeature.c b/arch/riscv/kernel/cpufeature.c
> index 4677320d7e31..220be7222129 100644
> --- a/arch/riscv/kernel/cpufeature.c
> +++ b/arch/riscv/kernel/cpufeature.c
> @@ -68,6 +68,11 @@ bool __riscv_isa_extension_available(const unsigned long *isa_bitmap, int bit)
> }
> EXPORT_SYMBOL_GPL(__riscv_isa_extension_available);
>
> +static bool riscv_isa_extension_check(int id)
> +{
> + return true;
> +}
> +
> void __init riscv_fill_hwcap(void)
> {
> struct device_node *node;
> @@ -189,7 +194,8 @@ void __init riscv_fill_hwcap(void)
> #define SET_ISA_EXT_MAP(name, bit) \
> do { \
> if ((ext_end - ext == sizeof(name) - 1) && \
> - !memcmp(ext, name, sizeof(name) - 1)) \
> + !memcmp(ext, name, sizeof(name) - 1) && \
> + riscv_isa_extension_check(bit)) \
> set_bit(bit, this_isa); \
> } while (false) \
>
> @@ -198,8 +204,10 @@ void __init riscv_fill_hwcap(void)
> if (!ext_long) {
> int nr = *ext - 'a';
>
> - this_hwcap |= isa2hwcap[nr];
> - set_bit(nr, this_isa);
> + if (riscv_isa_extension_check(nr)) {
> + this_hwcap |= isa2hwcap[nr];
> + set_bit(nr, this_isa);
> + }
> } else {
> SET_ISA_EXT_MAP("sscofpmf", RISCV_ISA_EXT_SSCOFPMF);
> SET_ISA_EXT_MAP("svpbmt", RISCV_ISA_EXT_SVPBMT);
>
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next prev parent reply other threads:[~2022-10-27 13:08 UTC|newest]
Thread overview: 9+ messages / expand[flat|nested] mbox.gz Atom feed top
2022-10-24 9:13 [PATCH v2 0/3] RISC-V: Ensure Zicbom has a valid block size Andrew Jones
2022-10-24 9:13 ` [PATCH v2 1/3] RISC-V: Improve use of isa2hwcap[] Andrew Jones
2022-10-27 13:05 ` Heiko Stübner
2022-10-24 9:13 ` [PATCH v2 2/3] RISC-V: Introduce riscv_isa_extension_check Andrew Jones
2022-10-27 13:08 ` Heiko Stübner [this message]
2022-10-24 9:13 ` [PATCH v2 3/3] RISC-V: Ensure Zicbom has a valid block size Andrew Jones
2022-10-24 9:33 ` Conor Dooley
2022-10-27 13:16 ` Heiko Stübner
2022-10-27 14:16 ` Andrew Jones
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