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From: "Heiko Stübner" <heiko@sntech.de>
To: linux-riscv@lists.infradead.org, Andrew Jones <ajones@ventanamicro.com>
Cc: Palmer Dabbelt <palmer@dabbelt.com>,
	Paul Walmsley <paul.walmsley@sifive.com>,
	Albert Ou <aou@eecs.berkeley.edu>,
	Conor Dooley <conor.dooley@microchip.com>,
	Anup Patel <apatel@ventanamicro.com>,
	Atish Patra <atishp@rivosinc.com>
Subject: Re: [PATCH v2 3/3] RISC-V: Ensure Zicbom has a valid block size
Date: Thu, 27 Oct 2022 15:16:48 +0200	[thread overview]
Message-ID: <3361717.44csPzL39Z@diego> (raw)
In-Reply-To: <20221024091309.406906-4-ajones@ventanamicro.com>

Hi,

Am Montag, 24. Oktober 2022, 11:13:09 CEST schrieb Andrew Jones:
> When a DT puts zicbom in the isa string, but does not provide a block
> size, ALT_CMO_OP() will attempt to do cache operations on address
> zero since the start address will be ANDed with zero. We can't simply
> BUG() in riscv_init_cbom_blocksize() when we fail to find a block
> size because the failure will happen before logging works, leaving
> users to scratch their heads as to why the boot hung. Instead, ensure
> Zicbom is disabled and output an error which will hopefully alert
> people that the DT needs to be fixed. While at it, add a check that
> the block size is a power-of-2 too.
> 
> Signed-off-by: Andrew Jones <ajones@ventanamicro.com>
> ---
>  arch/riscv/kernel/cpufeature.c | 13 +++++++++++++
>  1 file changed, 13 insertions(+)
> 
> diff --git a/arch/riscv/kernel/cpufeature.c b/arch/riscv/kernel/cpufeature.c
> index 220be7222129..93e45560af30 100644
> --- a/arch/riscv/kernel/cpufeature.c
> +++ b/arch/riscv/kernel/cpufeature.c
> @@ -9,6 +9,7 @@
>  #include <linux/bitmap.h>
>  #include <linux/ctype.h>
>  #include <linux/libfdt.h>
> +#include <linux/log2.h>
>  #include <linux/module.h>
>  #include <linux/of.h>
>  #include <asm/alternative.h>
> @@ -70,6 +71,18 @@ EXPORT_SYMBOL_GPL(__riscv_isa_extension_available);
>  
>  static bool riscv_isa_extension_check(int id)
>  {
> +	switch (id) {
> +	case RISCV_ISA_EXT_ZICBOM:
> +		if (!riscv_cbom_block_size) {
> +			pr_err("Zicbom detected in ISA string, but no cbom-block-size found\n");
> +			return false;
> +		} else if (!is_power_of_2(riscv_cbom_block_size)) {
> +			pr_err("cbom-block-size present, but is not a power-of-2\n");
> +			return false;

I guess this could use a comment where that rule stems from.

I.e. the cmo-spec only says
  "the size of a cache block are [...] implementation-specific"

So while requiring this to be a power-of-2 is abviously sane,
this looks like an additional requirement from the kernel side?

Otherwise
Reviewed-by: Heiko Stuebner <heiko@sntech.de>

Heiko


> +		}
> +		return true;
> +	}
> +
>  	return true;
>  }
>  
> 





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  parent reply	other threads:[~2022-10-27 13:32 UTC|newest]

Thread overview: 9+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2022-10-24  9:13 [PATCH v2 0/3] RISC-V: Ensure Zicbom has a valid block size Andrew Jones
2022-10-24  9:13 ` [PATCH v2 1/3] RISC-V: Improve use of isa2hwcap[] Andrew Jones
2022-10-27 13:05   ` Heiko Stübner
2022-10-24  9:13 ` [PATCH v2 2/3] RISC-V: Introduce riscv_isa_extension_check Andrew Jones
2022-10-27 13:08   ` Heiko Stübner
2022-10-24  9:13 ` [PATCH v2 3/3] RISC-V: Ensure Zicbom has a valid block size Andrew Jones
2022-10-24  9:33   ` Conor Dooley
2022-10-27 13:16   ` Heiko Stübner [this message]
2022-10-27 14:16     ` Andrew Jones

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