[PATCH v2] msr: Use defines for bits of MSR_IA32_DEBUGCTLMSR instead of numbers

[PATCH v2] msr: Use defines for bits of MSR_IA32_DEBUGCTLMSR instead of numbers

[Dietmar Hahn]

Changes to v1:
  As Jan suggested:
    - changed definitions of the bit fields
    - did the change more consistently across the source.

Dietmar.


# HG changeset patch
# Parent e2722b24dc0962de37215320b05d1bb7c4c42864

Use defines for bits of MSR_IA32_DEBUGCTLMSR instead of numbers.

Signed-off-by: Dietmar Hahn <dietmar.hahn@ts.fujitsu.com>

diff -r e2722b24dc09 xen/arch/x86/hvm/vmx/vmx.c
--- a/xen/arch/x86/hvm/vmx/vmx.c	Thu Jan 26 17:43:31 2012 +0000
+++ b/xen/arch/x86/hvm/vmx/vmx.c	Tue Jan 31 14:30:32 2012 +0100
@@ -1944,11 +1944,12 @@ static int vmx_msr_write_intercept(unsig
         break;
     case MSR_IA32_DEBUGCTLMSR: {
         int i, rc = 0;
-
-        if ( !msr_content || (msr_content & ~3) )
+        uint64_t supported = IA32_DEBUGCTLMSR_LBR | IA32_DEBUGCTLMSR_BTF;
+
+        if ( !msr_content || (msr_content & ~supported) )
             break;
 
-        if ( msr_content & 1 )
+        if ( msr_content & IA32_DEBUGCTLMSR_LBR )
         {
             const struct lbr_info *lbr = last_branch_msr_get();
             if ( lbr == NULL )
diff -r e2722b24dc09 xen/arch/x86/traps.c
--- a/xen/arch/x86/traps.c	Thu Jan 26 17:43:31 2012 +0000
+++ b/xen/arch/x86/traps.c	Tue Jan 31 14:30:32 2012 +0100
@@ -3376,12 +3376,12 @@ void write_efer(u64 val)
 static void ler_enable(void)
 {
     u64 debugctl;
-    
+
     if ( !this_cpu(ler_msr) )
         return;
 
     rdmsrl(MSR_IA32_DEBUGCTLMSR, debugctl);
-    wrmsrl(MSR_IA32_DEBUGCTLMSR, debugctl | 1);
+    wrmsrl(MSR_IA32_DEBUGCTLMSR, debugctl | IA32_DEBUGCTLMSR_LBR);
 }
 
 void do_debug(struct cpu_user_regs *regs)
diff -r e2722b24dc09 xen/include/asm-x86/msr-index.h
--- a/xen/include/asm-x86/msr-index.h	Thu Jan 26 17:43:31 2012 +0000
+++ b/xen/include/asm-x86/msr-index.h	Tue Jan 31 14:30:32 2012 +0100
@@ -65,11 +65,14 @@
 #define MSR_MTRRdefType			0x000002ff
 
 #define MSR_IA32_DEBUGCTLMSR		0x000001d9
+#define IA32_DEBUGCTLMSR_LBR		(1<<0) /* Last Branch Record */
+#define IA32_DEBUGCTLMSR_BTF		(1<<1) /* Single Step on Branches */
+
 #define MSR_IA32_LASTBRANCHFROMIP	0x000001db
 #define MSR_IA32_LASTBRANCHTOIP		0x000001dc
 #define MSR_IA32_LASTINTFROMIP		0x000001dd
 #define MSR_IA32_LASTINTTOIP		0x000001de
- 
+
 #define MSR_IA32_MTRR_PHYSBASE0     0x00000200
 #define MSR_IA32_MTRR_PHYSMASK0     0x00000201
 #define MSR_IA32_MTRR_PHYSBASE1     0x00000202


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