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From: Pierre-Louis Bossart <pierre-louis.bossart@linux.intel.com>
To: Cezary Rojewski <cezary.rojewski@intel.com>, alsa-devel@alsa-project.org
Cc: upstream@semihalf.com, harshapriya.n@intel.com, rad@semihalf.com,
	tiwai@suse.com, hdegoede@redhat.com, broonie@kernel.org,
	amadeuszx.slawinski@linux.intel.com, cujomalainey@chromium.org,
	lma@semihalf.com
Subject: Re: [PATCH 08/17] ASoC: Intel: avs: Add power management requests
Date: Thu, 24 Feb 2022 19:37:37 -0600	[thread overview]
Message-ID: <24125d33-bcb6-050b-88fb-6b2ef549fbad@linux.intel.com> (raw)
In-Reply-To: <20220207122108.3780926-9-cezary.rojewski@intel.com>



> Audio DSP supports low power states i.e.: transitions between D0 and D3
> and D0-substates in form of D0i3. That process is a combination of core

D0i0 and D0i3?

> and IPC operations. Here, Dx and D0ix IPC handlers are added.
> 
> Signed-off-by: Amadeusz Sławiński <amadeuszx.slawinski@linux.intel.com>
> Signed-off-by: Cezary Rojewski <cezary.rojewski@intel.com>
> ---
>  sound/soc/intel/avs/messages.c | 43 ++++++++++++++++++++++++++++++++++
>  sound/soc/intel/avs/messages.h | 16 +++++++++++++
>  2 files changed, 59 insertions(+)
> 
> diff --git a/sound/soc/intel/avs/messages.c b/sound/soc/intel/avs/messages.c
> index e870d5792a77..1b589689410f 100644
> --- a/sound/soc/intel/avs/messages.c
> +++ b/sound/soc/intel/avs/messages.c
> @@ -347,3 +347,46 @@ int avs_ipc_get_large_config(struct avs_dev *adev, u16 module_id, u8 instance_id
>  
>  	return 0;
>  }
> +
> +int avs_ipc_set_dx(struct avs_dev *adev, u32 core_mask, bool powerup)
> +{
> +	union avs_module_msg msg = AVS_MODULE_REQUEST(SET_DX);
> +	struct avs_ipc_msg request;
> +	struct avs_dxstate_info dx;
> +	int ret;
> +
> +	dx.core_mask = core_mask;
> +	dx.dx_mask = powerup ? core_mask : 0;
> +	request.header = msg.val;
> +	request.data = &dx;
> +	request.size = sizeof(dx);
> +
> +	/*
> +	 * SET_D0 is sent for non-main cores only while SET_D3 is used to
> +	 * suspend for all of them. Both cases prevent any D0I3 transitions.

The asymmetry in the comment isn't clear. Did you mean that the main
code is in D0 when powered?

> +	 */
> +	ret = avs_dsp_send_pm_msg(adev, &request, NULL, true);
> +	if (ret)
> +		avs_ipc_err(adev, &request, "set dx", ret);
> +
> +	return ret;
> +}
> +
> +int avs_ipc_set_d0ix(struct avs_dev *adev, bool enable_pg, bool streaming)
> +{
> +	union avs_module_msg msg = AVS_MODULE_REQUEST(SET_D0IX);
> +	struct avs_ipc_msg request = {0};
> +	int ret;
> +
> +	/* Wake & streaming for < cAVS 2.0 */

I don't how anyone outside of Intel could understand this comment.
Consider explaining what the two terms refer to.

> +	msg.ext.set_d0ix.wake = enable_pg;

simplify the argument? Not sure anyone could understand what wake and
enable_pg mean.

int avs_ipc_set_d0ix(struct avs_dev *adev, bool wake, bool streaming)

> +	msg.ext.set_d0ix.streaming = streaming;
> +
> +	request.header = msg.val;
> +
> +	ret = avs_dsp_send_pm_msg(adev, &request, NULL, false);
> +	if (ret)
> +		avs_ipc_err(adev, &request, "set d0ix", ret);
> +
> +	return ret;
> +}
> diff --git a/sound/soc/intel/avs/messages.h b/sound/soc/intel/avs/messages.h
> index 1dabd1005327..bbdba4631b1f 100644
> --- a/sound/soc/intel/avs/messages.h
> +++ b/sound/soc/intel/avs/messages.h
> @@ -101,6 +101,8 @@ enum avs_module_msg_type {
>  	AVS_MOD_LARGE_CONFIG_SET = 4,
>  	AVS_MOD_BIND = 5,
>  	AVS_MOD_UNBIND = 6,
> +	AVS_MOD_SET_DX = 7,
> +	AVS_MOD_SET_D0IX = 8,
>  	AVS_MOD_DELETE_INSTANCE = 11,
>  };
>  
> @@ -137,6 +139,11 @@ union avs_module_msg {
>  				u32 dst_queue:3;
>  				u32 src_queue:3;
>  			} bind_unbind;
> +			struct {
> +				/* cAVS < 2.0 */
> +				u32 wake:1;
> +				u32 streaming:1;

you probably want to explain how a 'streaming' flag is set at the module
level? One would think all modules connected in a pipeline would need to
use the same flag value.

> +			} set_d0ix;
>  		} ext;
>  	};
>  } __packed;
> @@ -298,4 +305,13 @@ int avs_ipc_get_large_config(struct avs_dev *adev, u16 module_id, u8 instance_id
>  			     u8 param_id, u8 *request_data, size_t request_size,
>  			     u8 **reply_data, size_t *reply_size);
>  
> +/* DSP cores and domains power management messages */
> +struct avs_dxstate_info {
> +	u32 core_mask;
> +	u32 dx_mask;

what is the convention for D0 and D3 in the mask ? which one is 0 or 1?

Is this also handled in a hierarchical way where only the bits set in
core_mask matter?

> +} __packed;
> +
> +int avs_ipc_set_dx(struct avs_dev *adev, u32 core_mask, bool powerup);
> +int avs_ipc_set_d0ix(struct avs_dev *adev, bool enable_pg, bool streaming);
> +
>  #endif /* __SOUND_SOC_INTEL_AVS_MSGS_H */

  reply	other threads:[~2022-02-25  2:42 UTC|newest]

Thread overview: 61+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2022-02-07 12:20 [PATCH 00/17] ASoC: Intel: AVS - Audio DSP for cAVS Cezary Rojewski
2022-02-07 12:20 ` [PATCH 01/17] ALSA: hda: Add helper macros for DSP capable devices Cezary Rojewski
2022-02-07 12:20 ` [PATCH 02/17] ASoC: Export DAI register and widget ctor and dctor functions Cezary Rojewski
2022-02-07 12:20 ` [PATCH 03/17] ASoC: Intel: Introduce AVS driver Cezary Rojewski
2022-02-24 23:55   ` Pierre-Louis Bossart
2022-02-25 16:56     ` Cezary Rojewski
2022-02-25 20:23       ` Pierre-Louis Bossart
2022-02-28 14:52         ` Cezary Rojewski
2022-02-07 12:20 ` [PATCH 04/17] ASoC: Intel: avs: Inter process communication Cezary Rojewski
2022-02-25  0:56   ` Pierre-Louis Bossart
2022-02-25 18:06     ` Cezary Rojewski
2022-02-25 20:37       ` Pierre-Louis Bossart
2022-02-28 15:19         ` Cezary Rojewski
2022-02-28 15:39           ` Cezary Rojewski
2022-02-07 12:20 ` [PATCH 05/17] ASoC: Intel: avs: Add code loading requests Cezary Rojewski
2022-02-25  1:02   ` Pierre-Louis Bossart
2022-02-25 18:08     ` Cezary Rojewski
2022-02-07 12:20 ` [PATCH 06/17] ASoC: Intel: avs: Add pipeline management requests Cezary Rojewski
2022-02-25  1:11   ` Pierre-Louis Bossart
2022-02-25 18:31     ` Cezary Rojewski
2022-02-25 20:42       ` Pierre-Louis Bossart
2022-02-28 15:25         ` Cezary Rojewski
2022-02-07 12:20 ` [PATCH 07/17] ASoC: Intel: avs: Add module " Cezary Rojewski
2022-02-25  1:27   ` Pierre-Louis Bossart
2022-02-25 18:50     ` Cezary Rojewski
2022-02-25 20:44       ` Pierre-Louis Bossart
2022-02-28 15:26         ` Cezary Rojewski
2022-02-07 12:20 ` [PATCH 08/17] ASoC: Intel: avs: Add power " Cezary Rojewski
2022-02-25  1:37   ` Pierre-Louis Bossart [this message]
2022-02-25 19:08     ` Cezary Rojewski
2022-02-25 20:46       ` Pierre-Louis Bossart
2022-02-28 15:28         ` Cezary Rojewski
2022-02-07 12:21 ` [PATCH 09/17] ASoC: Intel: avs: Add ROM requests Cezary Rojewski
2022-02-25  1:42   ` Pierre-Louis Bossart
2022-02-25 19:19     ` Cezary Rojewski
2022-02-07 12:21 ` [PATCH 10/17] ASoC: Intel: avs: Add basefw runtime-parameter requests Cezary Rojewski
2022-02-07 12:21 ` [PATCH 11/17] ASoC: Intel: avs: Firmware resources management utilities Cezary Rojewski
2022-02-25  1:53   ` Pierre-Louis Bossart
2022-02-25 19:20     ` Cezary Rojewski
2022-02-07 12:21 ` [PATCH 12/17] ASoC: Intel: avs: Declare module configuration types Cezary Rojewski
2022-02-07 12:21 ` [PATCH 13/17] ASoC: Intel: avs: Dynamic firmware resources management Cezary Rojewski
2022-02-25  2:02   ` Pierre-Louis Bossart
2022-02-25 19:27     ` Cezary Rojewski
2022-02-25 20:21       ` Pierre-Louis Bossart
2022-02-28 15:30         ` Cezary Rojewski
2022-02-28 17:20           ` Pierre-Louis Bossart
2022-02-07 12:21 ` [PATCH 14/17] ASoC: Intel: avs: General code loading flow Cezary Rojewski
2022-02-25  2:15   ` Pierre-Louis Bossart
2022-02-25 19:37     ` Cezary Rojewski
2022-02-07 12:21 ` [PATCH 15/17] ASoC: Intel: avs: Implement CLDMA transfer Cezary Rojewski
2022-02-25  2:18   ` Pierre-Louis Bossart
2022-02-25 19:38     ` Cezary Rojewski
2022-02-07 12:21 ` [PATCH 16/17] ASoC: Intel: avs: Code loading over CLDMA Cezary Rojewski
2022-02-25  2:21   ` Pierre-Louis Bossart
2022-02-25 19:38     ` Cezary Rojewski
2022-02-07 12:21 ` [PATCH 17/17] ASoC: Intel: avs: Code loading over HDA Cezary Rojewski
2022-02-21 11:51 ` [PATCH 00/17] ASoC: Intel: AVS - Audio DSP for cAVS Cezary Rojewski
2022-02-25  2:35 ` Pierre-Louis Bossart
2022-02-25 15:44   ` Cezary Rojewski
2022-02-25 16:33     ` Pierre-Louis Bossart
2022-02-25 18:07   ` Mark Brown

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