From: Heiko Stuebner <heiko@sntech.de>
To: Elaine Zhang <zhangqing@rock-chips.com>
Cc: mturquette@baylibre.com, sboyd@codeaurora.org, xf@rock-chips.com,
robh+dt@kernel.org, mark.rutland@arm.com,
linux-clk@vger.kernel.org, huangtao@rock-chips.com,
xxx@rock-chips.com, cl@rock-chips.com,
linux-rockchip@lists.infradead.org, linux-kernel@vger.kernel.org,
devicetree@vger.kernel.org, linux-arm-kernel@lists.infradead.org
Subject: Re: [PATCH v5 3/4] clk: rockchip: add new pll-type for rk3328
Date: Sat, 31 Dec 2016 13:53:51 +0100 [thread overview]
Message-ID: <2438805.XRRMBVrdEM@phil> (raw)
In-Reply-To: <1482979511-6847-4-git-send-email-zhangqing@rock-chips.com>
Am Donnerstag, 29. Dezember 2016, 10:45:10 CET schrieb Elaine Zhang:
> The rk3328's pll and clock are similar with rk3036's,
> it different with pll_mode_mask, the rk3328 soc
> pll mode only one bit(rk3036 soc have two bits)
> so these should be independent and separate from
> the series of rk3328s.
>
> Changes in v4:
> adjust the pacth 3 and 4 order.
> move pll_rk3328 to patch 3.
> Changes in v3:
> fix up the pll type pll_rk3328 description and use
>
> Signed-off-by: Elaine Zhang <zhangqing@rock-chips.com>
applied to my clk-branch for 4.11
The clock controller itself also looks good now, I'll just give Rob or someone
else a bit of time for eventual comments after new years :-)
Heiko
WARNING: multiple messages have this Message-ID (diff)
From: heiko@sntech.de (Heiko Stuebner)
To: linux-arm-kernel@lists.infradead.org
Subject: [PATCH v5 3/4] clk: rockchip: add new pll-type for rk3328
Date: Sat, 31 Dec 2016 13:53:51 +0100 [thread overview]
Message-ID: <2438805.XRRMBVrdEM@phil> (raw)
In-Reply-To: <1482979511-6847-4-git-send-email-zhangqing@rock-chips.com>
Am Donnerstag, 29. Dezember 2016, 10:45:10 CET schrieb Elaine Zhang:
> The rk3328's pll and clock are similar with rk3036's,
> it different with pll_mode_mask, the rk3328 soc
> pll mode only one bit(rk3036 soc have two bits)
> so these should be independent and separate from
> the series of rk3328s.
>
> Changes in v4:
> adjust the pacth 3 and 4 order.
> move pll_rk3328 to patch 3.
> Changes in v3:
> fix up the pll type pll_rk3328 description and use
>
> Signed-off-by: Elaine Zhang <zhangqing@rock-chips.com>
applied to my clk-branch for 4.11
The clock controller itself also looks good now, I'll just give Rob or someone
else a bit of time for eventual comments after new years :-)
Heiko
next prev parent reply other threads:[~2016-12-31 12:53 UTC|newest]
Thread overview: 26+ messages / expand[flat|nested] mbox.gz Atom feed top
2016-12-29 2:45 [PATCH v5 0/4] clk: rockchip: support clk controller for rk3328 SoC Elaine Zhang
2016-12-29 2:45 ` Elaine Zhang
2016-12-29 2:45 ` [PATCH v5 1/4] clk: rockchip: add dt-binding header for rk3328 Elaine Zhang
2016-12-29 2:45 ` Elaine Zhang
2016-12-29 2:45 ` Elaine Zhang
2017-01-05 12:39 ` Heiko Stuebner
2017-01-05 12:39 ` Heiko Stuebner
2017-01-05 12:39 ` Heiko Stuebner
2017-01-05 12:54 ` Heiko Stuebner
2017-01-05 12:54 ` Heiko Stuebner
2017-01-05 12:54 ` Heiko Stuebner
2016-12-29 2:45 ` [PATCH v5 2/4] dt-bindings: add bindings for rk3328 clock controller Elaine Zhang
2016-12-29 2:45 ` Elaine Zhang
2017-01-03 20:41 ` Rob Herring
2017-01-03 20:41 ` Rob Herring
2017-01-03 20:41 ` Rob Herring
2017-01-05 12:42 ` Heiko Stuebner
2017-01-05 12:42 ` Heiko Stuebner
2016-12-29 2:45 ` [PATCH v5 3/4] clk: rockchip: add new pll-type for rk3328 Elaine Zhang
2016-12-29 2:45 ` Elaine Zhang
2016-12-31 12:53 ` Heiko Stuebner [this message]
2016-12-31 12:53 ` Heiko Stuebner
2016-12-29 2:45 ` [PATCH v5 4/4] clk: rockchip: add clock controller " Elaine Zhang
2016-12-29 2:45 ` Elaine Zhang
2017-01-05 12:53 ` Heiko Stuebner
2017-01-05 12:53 ` Heiko Stuebner
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