From: Laurent Pinchart <laurent.pinchart@ideasonboard.com>
To: Geert Uytterhoeven <geert+renesas@glider.be>
Cc: Michael Turquette <mturquette@baylibre.com>,
Stephen Boyd <sboyd@codeaurora.org>,
Magnus Damm <damm+renesas@opensource.se>,
Simon Horman <horms+renesas@verge.net.au>,
Rob Herring <robh+dt@kernel.org>, Pawel Moll <pawel.moll@arm.com>,
Mark Rutland <mark.rutland@arm.com>,
Ian Campbell <ijc+devicetree@hellion.org.uk>,
Kumar Gala <galak@codeaurora.org>,
linux-clk@vger.kernel.org, devicetree@vger.kernel.org,
linux-sh@vger.kernel.org
Subject: Re: [PATCH v4 2/5] [RFC] clk: shmobile: Add r8a7795 CPG Core Clock Definitions
Date: Fri, 23 Oct 2015 14:21:04 +0300 [thread overview]
Message-ID: <2464036.AexIB1O0H1@avalon> (raw)
In-Reply-To: <1444999760-15750-3-git-send-email-geert+renesas@glider.be>
Hi Geert,
Thank you for the patch.
On Friday 16 October 2015 14:49:17 Geert Uytterhoeven wrote:
> Add all R-Car H3 CPG Core Clock Outputs defined in the datasheet.
>
> Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
> ---
> v4:
> - Add all clocks instead of just the ones used by the current DTS.
>
> v3:
> - New.
> ---
> include/dt-bindings/clock/r8a7795-cpg-mssr.h | 63 +++++++++++++++++++++++++
> 1 file changed, 63 insertions(+)
> create mode 100644 include/dt-bindings/clock/r8a7795-cpg-mssr.h
>
> diff --git a/include/dt-bindings/clock/r8a7795-cpg-mssr.h
> b/include/dt-bindings/clock/r8a7795-cpg-mssr.h new file mode 100644
> index 0000000000000000..e864aae0a2561c4b
> --- /dev/null
> +++ b/include/dt-bindings/clock/r8a7795-cpg-mssr.h
> @@ -0,0 +1,63 @@
> +/*
> + * Copyright (C) 2015 Renesas Electronics Corp.
> + *
> + * This program is free software; you can redistribute it and/or modify
> + * it under the terms of the GNU General Public License as published by
> + * the Free Software Foundation; either version 2 of the License, or
> + * (at your option) any later version.
> + */
> +#ifndef __DT_BINDINGS_CLOCK_R8A7795_CPG_MSSR_H__
> +#define __DT_BINDINGS_CLOCK_R8A7795_CPG_MSSR_H__
> +
> +#include <dt-bindings/clock/renesas-cpg-mssr.h>
> +
> +/* r8a7795 CPG Core Clocks */
> +#define R8A7795_CLK_Z 0
> +#define R8A7795_CLK_Z2 1
> +#define R8A7795_CLK_ZR 2
> +#define R8A7795_CLK_ZG 3
> +#define R8A7795_CLK_ZTR 4
> +#define R8A7795_CLK_ZTRD2 5
> +#define R8A7795_CLK_ZT 6
> +#define R8A7795_CLK_ZX 7
> +#define R8A7795_CLK_S0D1 8
> +#define R8A7795_CLK_S0D4 9
> +#define R8A7795_CLK_S1D1 10
> +#define R8A7795_CLK_S1D2 11
> +#define R8A7795_CLK_S1D4 12
> +#define R8A7795_CLK_S2D1 13
> +#define R8A7795_CLK_S2D2 14
> +#define R8A7795_CLK_S2D4 15
> +#define R8A7795_CLK_S3D1 16
> +#define R8A7795_CLK_S3D2 17
> +#define R8A7795_CLK_S3D4 18
> +#define R8A7795_CLK_LB 19
> +#define R8A7795_CLK_CL 20
> +#define R8A7795_CLK_ZB3 21
> +#define R8A7795_CLK_ZB3D2 22
> +#define R8A7795_CLK_CR 23
> +#define R8A7795_CLK_CRD2 24
> +#define R8A7795_CLK_SD0H 25
> +#define R8A7795_CLK_SD0 26
> +#define R8A7795_CLK_SD1H 27
> +#define R8A7795_CLK_SD1 28
> +#define R8A7795_CLK_SD2H 29
> +#define R8A7795_CLK_SD2 30
> +#define R8A7795_CLK_SD3H 31
> +#define R8A7795_CLK_SD3 32
> +#define R8A7795_CLK_SSP2 33
> +#define R8A7795_CLK_SSP1 34
> +#define R8A7795_CLK_SSPRS 35
> +#define R8A7795_CLK_RPC 36
> +#define R8A7795_CLK_RPCD2 37
> +#define R8A7795_CLK_MSO 38
> +#define R8A7795_CLK_CANFD 39
> +#define R8A7795_CLK_HDMI 40
> +#define R8A7795_CLK_CSI0 41
> +#define R8A7795_CLK_CSIREF 42
> +#define R8A7795_CLK_CP 43
> +#define R8A7795_CLK_CPEX 44
> +#define R8A7795_CLK_R 45
> +#define R8A7795_CLK_OSC 46
Those two clocks are called RCLK and OSCCLK in the datasheet, shouldn't we use
those names ?
Apart from that,
Reviewed-by: Laurent Pinchart <laurent.pinchart@ideasonboard.com>
> +#endif /* __DT_BINDINGS_CLOCK_R8A7795_CPG_MSSR_H__ */
--
Regards,
Laurent Pinchart
WARNING: multiple messages have this Message-ID (diff)
From: Laurent Pinchart <laurent.pinchart@ideasonboard.com>
To: Geert Uytterhoeven <geert+renesas@glider.be>
Cc: Michael Turquette <mturquette@baylibre.com>,
Stephen Boyd <sboyd@codeaurora.org>,
Magnus Damm <damm+renesas@opensource.se>,
Simon Horman <horms+renesas@verge.net.au>,
Rob Herring <robh+dt@kernel.org>, Pawel Moll <pawel.moll@arm.com>,
Mark Rutland <mark.rutland@arm.com>,
Ian Campbell <ijc+devicetree@hellion.org.uk>,
Kumar Gala <galak@codeaurora.org>,
linux-clk@vger.kernel.org, devicetree@vger.kernel.org,
linux-sh@vger.kernel.org
Subject: Re: [PATCH v4 2/5] [RFC] clk: shmobile: Add r8a7795 CPG Core Clock Definitions
Date: Fri, 23 Oct 2015 11:21:04 +0000 [thread overview]
Message-ID: <2464036.AexIB1O0H1@avalon> (raw)
In-Reply-To: <1444999760-15750-3-git-send-email-geert+renesas@glider.be>
Hi Geert,
Thank you for the patch.
On Friday 16 October 2015 14:49:17 Geert Uytterhoeven wrote:
> Add all R-Car H3 CPG Core Clock Outputs defined in the datasheet.
>
> Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
> ---
> v4:
> - Add all clocks instead of just the ones used by the current DTS.
>
> v3:
> - New.
> ---
> include/dt-bindings/clock/r8a7795-cpg-mssr.h | 63 +++++++++++++++++++++++++
> 1 file changed, 63 insertions(+)
> create mode 100644 include/dt-bindings/clock/r8a7795-cpg-mssr.h
>
> diff --git a/include/dt-bindings/clock/r8a7795-cpg-mssr.h
> b/include/dt-bindings/clock/r8a7795-cpg-mssr.h new file mode 100644
> index 0000000000000000..e864aae0a2561c4b
> --- /dev/null
> +++ b/include/dt-bindings/clock/r8a7795-cpg-mssr.h
> @@ -0,0 +1,63 @@
> +/*
> + * Copyright (C) 2015 Renesas Electronics Corp.
> + *
> + * This program is free software; you can redistribute it and/or modify
> + * it under the terms of the GNU General Public License as published by
> + * the Free Software Foundation; either version 2 of the License, or
> + * (at your option) any later version.
> + */
> +#ifndef __DT_BINDINGS_CLOCK_R8A7795_CPG_MSSR_H__
> +#define __DT_BINDINGS_CLOCK_R8A7795_CPG_MSSR_H__
> +
> +#include <dt-bindings/clock/renesas-cpg-mssr.h>
> +
> +/* r8a7795 CPG Core Clocks */
> +#define R8A7795_CLK_Z 0
> +#define R8A7795_CLK_Z2 1
> +#define R8A7795_CLK_ZR 2
> +#define R8A7795_CLK_ZG 3
> +#define R8A7795_CLK_ZTR 4
> +#define R8A7795_CLK_ZTRD2 5
> +#define R8A7795_CLK_ZT 6
> +#define R8A7795_CLK_ZX 7
> +#define R8A7795_CLK_S0D1 8
> +#define R8A7795_CLK_S0D4 9
> +#define R8A7795_CLK_S1D1 10
> +#define R8A7795_CLK_S1D2 11
> +#define R8A7795_CLK_S1D4 12
> +#define R8A7795_CLK_S2D1 13
> +#define R8A7795_CLK_S2D2 14
> +#define R8A7795_CLK_S2D4 15
> +#define R8A7795_CLK_S3D1 16
> +#define R8A7795_CLK_S3D2 17
> +#define R8A7795_CLK_S3D4 18
> +#define R8A7795_CLK_LB 19
> +#define R8A7795_CLK_CL 20
> +#define R8A7795_CLK_ZB3 21
> +#define R8A7795_CLK_ZB3D2 22
> +#define R8A7795_CLK_CR 23
> +#define R8A7795_CLK_CRD2 24
> +#define R8A7795_CLK_SD0H 25
> +#define R8A7795_CLK_SD0 26
> +#define R8A7795_CLK_SD1H 27
> +#define R8A7795_CLK_SD1 28
> +#define R8A7795_CLK_SD2H 29
> +#define R8A7795_CLK_SD2 30
> +#define R8A7795_CLK_SD3H 31
> +#define R8A7795_CLK_SD3 32
> +#define R8A7795_CLK_SSP2 33
> +#define R8A7795_CLK_SSP1 34
> +#define R8A7795_CLK_SSPRS 35
> +#define R8A7795_CLK_RPC 36
> +#define R8A7795_CLK_RPCD2 37
> +#define R8A7795_CLK_MSO 38
> +#define R8A7795_CLK_CANFD 39
> +#define R8A7795_CLK_HDMI 40
> +#define R8A7795_CLK_CSI0 41
> +#define R8A7795_CLK_CSIREF 42
> +#define R8A7795_CLK_CP 43
> +#define R8A7795_CLK_CPEX 44
> +#define R8A7795_CLK_R 45
> +#define R8A7795_CLK_OSC 46
Those two clocks are called RCLK and OSCCLK in the datasheet, shouldn't we use
those names ?
Apart from that,
Reviewed-by: Laurent Pinchart <laurent.pinchart@ideasonboard.com>
> +#endif /* __DT_BINDINGS_CLOCK_R8A7795_CPG_MSSR_H__ */
--
Regards,
Laurent Pinchart
next prev parent reply other threads:[~2015-10-23 11:21 UTC|newest]
Thread overview: 76+ messages / expand[flat|nested] mbox.gz Atom feed top
2015-10-16 12:49 [PATCH/RFC v4 0/5] clk: shmobile: Add new Renesas CPG/MSSR DT bindings Geert Uytterhoeven
2015-10-16 12:49 ` Geert Uytterhoeven
2015-10-16 12:49 ` [PATCH v4 1/5] [RFC] " Geert Uytterhoeven
2015-10-16 12:49 ` Geert Uytterhoeven
2015-10-20 10:15 ` Michael Turquette
2015-10-20 10:15 ` Michael Turquette
2015-10-20 10:15 ` Michael Turquette
2015-10-20 12:16 ` Geert Uytterhoeven
2015-10-20 12:16 ` Geert Uytterhoeven
2015-10-20 12:16 ` Geert Uytterhoeven
2015-10-20 16:01 ` Magnus Damm
2015-10-20 16:01 ` Magnus Damm
2015-10-20 16:01 ` Magnus Damm
2015-10-23 11:05 ` Laurent Pinchart
2015-10-23 11:05 ` Laurent Pinchart
2015-10-23 11:05 ` Laurent Pinchart
2015-10-23 11:09 ` Geert Uytterhoeven
2015-10-23 11:09 ` Geert Uytterhoeven
2015-10-23 11:09 ` Geert Uytterhoeven
2015-10-23 11:11 ` Laurent Pinchart
2015-10-23 11:11 ` Laurent Pinchart
2015-10-23 11:10 ` Laurent Pinchart
2015-10-23 11:10 ` Laurent Pinchart
2015-10-26 19:02 ` Geert Uytterhoeven
2015-10-26 19:02 ` Geert Uytterhoeven
2015-10-27 1:34 ` Laurent Pinchart
2015-10-27 1:34 ` Laurent Pinchart
2015-10-27 8:14 ` Geert Uytterhoeven
2015-10-27 8:14 ` Geert Uytterhoeven
2015-10-30 13:30 ` Laurent Pinchart
2015-10-30 13:30 ` Laurent Pinchart
2015-10-16 12:49 ` [PATCH v4 2/5] [RFC] clk: shmobile: Add r8a7795 CPG Core Clock Definitions Geert Uytterhoeven
2015-10-16 12:49 ` Geert Uytterhoeven
2015-10-20 10:09 ` Geert Uytterhoeven
2015-10-20 10:09 ` Geert Uytterhoeven
2015-10-20 16:21 ` Magnus Damm
2015-10-20 16:21 ` Magnus Damm
2015-10-23 11:21 ` Laurent Pinchart [this message]
2015-10-23 11:21 ` Laurent Pinchart
2015-10-23 11:25 ` Geert Uytterhoeven
2015-10-23 11:25 ` Geert Uytterhoeven
2015-10-23 11:25 ` Geert Uytterhoeven
2015-10-16 12:49 ` [PATCH v4 3/5] [RFC] clk: shmobile: div6: Extract cpg_div6_register() Geert Uytterhoeven
2015-10-16 12:49 ` Geert Uytterhoeven
2015-10-23 11:28 ` Laurent Pinchart
2015-10-23 11:28 ` Laurent Pinchart
2015-10-16 12:49 ` [PATCH v4 4/5] [RFC] clk: shmobile: cpg-mssr: Add new CPG/MSSR driver core Geert Uytterhoeven
2015-10-16 12:49 ` Geert Uytterhoeven
2015-10-16 12:49 ` [PATCH v4 5/5] [RFC] clk: shmobile: r8a7795: Add new CPG/MSSR driver Geert Uytterhoeven
2015-10-16 12:49 ` Geert Uytterhoeven
2015-10-20 12:24 ` Michael Turquette
2015-10-20 12:24 ` Michael Turquette
2015-10-20 12:24 ` Michael Turquette
2015-10-20 12:31 ` Geert Uytterhoeven
2015-10-20 12:31 ` Geert Uytterhoeven
2015-10-20 12:31 ` Geert Uytterhoeven
2015-10-20 13:00 ` Michael Turquette
2015-10-20 13:00 ` Michael Turquette
2015-10-20 13:07 ` Geert Uytterhoeven
2015-10-20 13:07 ` Geert Uytterhoeven
2015-10-20 13:07 ` Geert Uytterhoeven
2015-10-22 12:58 ` Geert Uytterhoeven
2015-10-22 12:58 ` Geert Uytterhoeven
2015-10-22 12:58 ` Geert Uytterhoeven
2015-10-24 1:10 ` Stephen Boyd
2015-10-24 1:10 ` Stephen Boyd
2015-10-24 17:34 ` Geert Uytterhoeven
2015-10-24 17:34 ` Geert Uytterhoeven
2015-10-26 2:25 ` Laurent Pinchart
2015-10-26 2:25 ` Laurent Pinchart
2015-10-26 8:03 ` Geert Uytterhoeven
2015-10-26 8:03 ` Geert Uytterhoeven
2015-10-30 13:12 ` Laurent Pinchart
2015-10-30 13:12 ` Laurent Pinchart
2015-10-29 14:03 ` Geert Uytterhoeven
2015-10-29 14:03 ` Geert Uytterhoeven
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