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From: Heiko Stuebner <heiko@sntech.de>
To: Geert Uytterhoeven <geert+renesas@glider.be>,
	Rob Herring <robh+dt@kernel.org>,
	Krzysztof Kozlowski <krzysztof.kozlowski+dt@linaro.org>,
	Paul Walmsley <paul.walmsley@sifive.com>,
	Palmer Dabbelt <palmer@dabbelt.com>,
	Albert Ou <aou@eecs.berkeley.edu>,
	Prabhakar <prabhakar.csengg@gmail.com>
Cc: Atish Patra <atishp@rivosinc.com>,
	Conor Dooley <conor.dooley@microchip.com>,
	devicetree@vger.kernel.org, linux-riscv@lists.infradead.org,
	linux-renesas-soc@vger.kernel.org, linux-kernel@vger.kernel.org,
	Prabhakar <prabhakar.csengg@gmail.com>,
	Biju Das <biju.das.jz@bp.renesas.com>,
	Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com>,
	Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org>
Subject: Re: [PATCH v3 02/10] dt-bindings: riscv: Sort the CPU core list alphabetically
Date: Thu, 15 Sep 2022 22:53:20 +0200	[thread overview]
Message-ID: <2526125.Lt9SDvczpP@phil> (raw)
In-Reply-To: <20220915181558.354737-3-prabhakar.mahadev-lad.rj@bp.renesas.com>

Am Donnerstag, 15. September 2022, 20:15:50 CEST schrieb Prabhakar:
> From: Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com>
> 
> Sort the CPU cores list alphabetically for maintenance.
> 
> Signed-off-by: Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com>
> Reviewed-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org>
> Reviewed-by: Geert Uytterhoeven <geert+renesas@glider.be>

That makes a lot of sense

Reviewed-by: Heiko Stuebner <heiko@sntech.de>

> ---
> v2->v3
> * included RB tag from Geert
> 
> v1->v2
> * Included RB tag from Krzysztof
> ---
>  Documentation/devicetree/bindings/riscv/cpus.yaml | 10 +++++-----
>  1 file changed, 5 insertions(+), 5 deletions(-)
> 
> diff --git a/Documentation/devicetree/bindings/riscv/cpus.yaml b/Documentation/devicetree/bindings/riscv/cpus.yaml
> index 873dd12f6e89..2a1c5ae5b0aa 100644
> --- a/Documentation/devicetree/bindings/riscv/cpus.yaml
> +++ b/Documentation/devicetree/bindings/riscv/cpus.yaml
> @@ -27,17 +27,17 @@ properties:
>      oneOf:
>        - items:
>            - enum:
> -              - sifive,rocket0
> +              - canaan,k210
>                - sifive,bullet0
>                - sifive,e5
>                - sifive,e7
>                - sifive,e71
> -              - sifive,u74-mc
> -              - sifive,u54
> -              - sifive,u74
> +              - sifive,rocket0
>                - sifive,u5
> +              - sifive,u54
>                - sifive,u7
> -              - canaan,k210
> +              - sifive,u74
> +              - sifive,u74-mc
>            - const: riscv
>        - items:
>            - enum:
> 





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WARNING: multiple messages have this Message-ID (diff)
From: Heiko Stuebner <heiko@sntech.de>
To: Geert Uytterhoeven <geert+renesas@glider.be>,
	Rob Herring <robh+dt@kernel.org>,
	Krzysztof Kozlowski <krzysztof.kozlowski+dt@linaro.org>,
	Paul Walmsley <paul.walmsley@sifive.com>,
	Palmer Dabbelt <palmer@dabbelt.com>,
	Albert Ou <aou@eecs.berkeley.edu>,
	Prabhakar <prabhakar.csengg@gmail.com>
Cc: Atish Patra <atishp@rivosinc.com>,
	Conor Dooley <conor.dooley@microchip.com>,
	devicetree@vger.kernel.org, linux-riscv@lists.infradead.org,
	linux-renesas-soc@vger.kernel.org, linux-kernel@vger.kernel.org,
	Prabhakar <prabhakar.csengg@gmail.com>,
	Biju Das <biju.das.jz@bp.renesas.com>,
	Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com>,
	Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org>
Subject: Re: [PATCH v3 02/10] dt-bindings: riscv: Sort the CPU core list alphabetically
Date: Thu, 15 Sep 2022 22:53:20 +0200	[thread overview]
Message-ID: <2526125.Lt9SDvczpP@phil> (raw)
In-Reply-To: <20220915181558.354737-3-prabhakar.mahadev-lad.rj@bp.renesas.com>

Am Donnerstag, 15. September 2022, 20:15:50 CEST schrieb Prabhakar:
> From: Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com>
> 
> Sort the CPU cores list alphabetically for maintenance.
> 
> Signed-off-by: Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com>
> Reviewed-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org>
> Reviewed-by: Geert Uytterhoeven <geert+renesas@glider.be>

That makes a lot of sense

Reviewed-by: Heiko Stuebner <heiko@sntech.de>

> ---
> v2->v3
> * included RB tag from Geert
> 
> v1->v2
> * Included RB tag from Krzysztof
> ---
>  Documentation/devicetree/bindings/riscv/cpus.yaml | 10 +++++-----
>  1 file changed, 5 insertions(+), 5 deletions(-)
> 
> diff --git a/Documentation/devicetree/bindings/riscv/cpus.yaml b/Documentation/devicetree/bindings/riscv/cpus.yaml
> index 873dd12f6e89..2a1c5ae5b0aa 100644
> --- a/Documentation/devicetree/bindings/riscv/cpus.yaml
> +++ b/Documentation/devicetree/bindings/riscv/cpus.yaml
> @@ -27,17 +27,17 @@ properties:
>      oneOf:
>        - items:
>            - enum:
> -              - sifive,rocket0
> +              - canaan,k210
>                - sifive,bullet0
>                - sifive,e5
>                - sifive,e7
>                - sifive,e71
> -              - sifive,u74-mc
> -              - sifive,u54
> -              - sifive,u74
> +              - sifive,rocket0
>                - sifive,u5
> +              - sifive,u54
>                - sifive,u7
> -              - canaan,k210
> +              - sifive,u74
> +              - sifive,u74-mc
>            - const: riscv
>        - items:
>            - enum:
> 





  reply	other threads:[~2022-09-15 20:53 UTC|newest]

Thread overview: 66+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2022-09-15 18:15 [PATCH v3 00/10] Add support for Renesas RZ/Five SoC Prabhakar
2022-09-15 18:15 ` Prabhakar
2022-09-15 18:15 ` [PATCH v3 01/10] dt-bindings: soc: renesas: Move renesas.yaml from arm to soc Prabhakar
2022-09-15 18:15   ` Prabhakar
2022-09-15 21:13   ` Conor.Dooley
2022-09-15 21:13     ` Conor.Dooley
2022-09-15 21:56     ` Lad, Prabhakar
2022-09-15 21:56       ` Lad, Prabhakar
2022-09-20 12:00   ` Geert Uytterhoeven
2022-09-20 12:00     ` Geert Uytterhoeven
2022-09-15 18:15 ` [PATCH v3 02/10] dt-bindings: riscv: Sort the CPU core list alphabetically Prabhakar
2022-09-15 18:15   ` Prabhakar
2022-09-15 20:53   ` Heiko Stuebner [this message]
2022-09-15 20:53     ` Heiko Stuebner
2022-09-15 18:15 ` [PATCH v3 03/10] dt-bindings: riscv: Add Andes AX45MP core to the list Prabhakar
2022-09-15 18:15   ` Prabhakar
2022-09-15 18:15 ` [PATCH v3 04/10] dt-bindings: soc: renesas: renesas.yaml: Document Renesas RZ/Five SoC Prabhakar
2022-09-15 18:15   ` Prabhakar
2022-09-15 18:15 ` [PATCH v3 05/10] RISC-V: Kconfig.socs: Add Renesas RZ/Five SoC kconfig option Prabhakar
2022-09-15 18:15   ` Prabhakar
2022-09-15 20:58   ` Conor.Dooley
2022-09-15 20:58     ` Conor.Dooley
2022-09-15 22:18     ` Lad, Prabhakar
2022-09-15 22:18       ` Lad, Prabhakar
2022-09-15 22:25       ` Conor.Dooley
2022-09-15 22:25         ` Conor.Dooley
2022-09-15 18:15 ` [PATCH v3 06/10] riscv: dts: renesas: Add initial devicetree for Renesas RZ/Five SoC Prabhakar
2022-09-15 18:15   ` Prabhakar
2022-09-15 18:15 ` [PATCH v3 07/10] riscv: boot: dts: r9a07g043: Add placeholder nodes Prabhakar
2022-09-15 18:15   ` Prabhakar
2022-09-15 21:36   ` Conor.Dooley
2022-09-15 21:36     ` Conor.Dooley
2022-09-15 22:26     ` Lad, Prabhakar
2022-09-15 22:26       ` Lad, Prabhakar
2022-09-15 22:40       ` Conor Dooley
2022-09-15 22:40         ` Conor Dooley
2022-09-20 12:17         ` Geert Uytterhoeven
2022-09-20 12:17           ` Geert Uytterhoeven
2022-09-20 12:31           ` Conor Dooley
2022-09-20 12:31             ` Conor Dooley
2022-09-20 13:46             ` Lad, Prabhakar
2022-09-20 13:46               ` Lad, Prabhakar
2022-09-15 18:15 ` [PATCH v3 08/10] riscv: dts: renesas: Add minimal DTS for Renesas RZ/Five SMARC EVK Prabhakar
2022-09-15 18:15   ` Prabhakar
2022-09-15 21:56   ` Conor.Dooley
2022-09-15 21:56     ` Conor.Dooley
2022-09-15 22:41     ` Lad, Prabhakar
2022-09-15 22:41       ` Lad, Prabhakar
2022-09-15 22:44       ` Conor.Dooley
2022-09-15 22:44         ` Conor.Dooley
2022-09-15 22:51         ` Lad, Prabhakar
2022-09-15 22:51           ` Lad, Prabhakar
2022-09-20 12:32   ` Geert Uytterhoeven
2022-09-20 12:32     ` Geert Uytterhoeven
2022-09-20 14:05     ` Lad, Prabhakar
2022-09-20 14:05       ` Lad, Prabhakar
2022-09-20 15:07       ` Geert Uytterhoeven
2022-09-20 15:07         ` Geert Uytterhoeven
2022-09-20 16:05         ` Lad, Prabhakar
2022-09-20 16:05           ` Lad, Prabhakar
2022-09-15 18:15 ` [PATCH v3 09/10] MAINTAINERS: Add entry for Renesas RISC-V architecture Prabhakar
2022-09-15 18:15   ` Prabhakar
2022-09-20 12:34   ` Geert Uytterhoeven
2022-09-20 12:34     ` Geert Uytterhoeven
2022-09-15 18:15 ` [PATCH v3 10/10] RISC-V: configs: defconfig: Enable Renesas RZ/Five SoC Prabhakar
2022-09-15 18:15   ` Prabhakar

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