From: Murray.Jensen at csiro.au <Murray.Jensen@csiro.au>
To: u-boot@lists.denx.de
Subject: [U-Boot-Users] [id]cache_status looks at wrong bit for MPC8560
Date: Fri, 15 Jul 2005 10:40:53 +1000 [thread overview]
Message-ID: <2574.1121388053@gerd> (raw)
Hi, the [id]cache_status functions in the MPC85xx start.S code look at
the wrong bit in the L1CSRn registers for the MPC8560. I have a patch
for it, but I was wondering if the code is wrong for all 85xx processors,
or just the 8560. Rather than me downloading all the 85xx user manuals
and checking the register bits (as I am only interested in 8560) I thought
I would post here instead. If anyone knows for certain the code is correct
or otherwise for other 85xx processors, please let me know. Cheers!
Murray...
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next reply other threads:[~2005-07-15 0:40 UTC|newest]
Thread overview: 4+ messages / expand[flat|nested] mbox.gz Atom feed top
2005-07-15 0:40 Murray.Jensen at csiro.au [this message]
2005-07-15 14:27 ` [U-Boot-Users] [id]cache_status looks at wrong bit for MPC8560 Kumar Gala
2005-07-15 15:36 ` Murray.Jensen at csiro.au
2005-07-18 12:42 ` Kumar Gala
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