From: Laurent Pinchart <laurent.pinchart@ideasonboard.com>
To: linux-arm-kernel@lists.infradead.org
Subject: Re: [PATCH RFC v2 04/17] ARM: shmobile: r8a7779: Add clocks
Date: Tue, 26 Nov 2013 14:48:45 +0000 [thread overview]
Message-ID: <2582481.JJAGzpNFcA@avalon> (raw)
In-Reply-To: <1385451139-29686-5-git-send-email-horms+renesas@verge.net.au>
Hi Simon,
Thanks for the patch.
On Tuesday 26 November 2013 16:32:06 Simon Horman wrote:
> Declare all core and MSTP clocks currently used by r8a7779-based boards.
>
> Based on work by Laurent Pinchart for the r8a7790 and r8a7791 SoCs.
>
> Cc: Laurent Pinchart <laurent.pinchart+renesas@ideasonboard.com>
> Signed-off-by: Simon Horman <horms@verge.net.au>
> ---
> arch/arm/boot/dts/r8a7779-marzen.dts | 1 +
> arch/arm/boot/dts/r8a7779.dtsi | 124 ++++++++++++++++++++++++++++++++
> 2 files changed, 125 insertions(+)
>
> diff --git a/arch/arm/boot/dts/r8a7779-marzen.dts
> b/arch/arm/boot/dts/r8a7779-marzen.dts index a7af2c2..ee3fb60 100644
> --- a/arch/arm/boot/dts/r8a7779-marzen.dts
> +++ b/arch/arm/boot/dts/r8a7779-marzen.dts
> @@ -11,6 +11,7 @@
>
> /dts-v1/;
> #include "r8a7779.dtsi"
> +#include <dt-bindings/gpio/gpio.h>
>
> / {
> model = "marzen";
> diff --git a/arch/arm/boot/dts/r8a7779.dtsi b/arch/arm/boot/dts/r8a7779.dtsi
> index b2b418a..d524b3f 100644
> --- a/arch/arm/boot/dts/r8a7779.dtsi
> +++ b/arch/arm/boot/dts/r8a7779.dtsi
> @@ -10,6 +10,7 @@
> */
>
> /include/ "skeleton.dtsi"
> +#include <dt-bindings/clock/r8a7779-clock.h>
>
> #include <dt-bindings/interrupt-controller/irq.h>
>
> @@ -248,4 +249,127 @@
> cap-sdio-irq;
> status = "disabled";
> };
> +
> + clocks {
> + #address-cells = <2>;
> + #size-cells = <2>;
> + ranges;
> +
> + /* Special CPG clocks */
> + cpg_clocks: cpg_clocks@0xe6150000 {
> + compatible = "renesas,r8a7779-cpg-clocks";
> + reg = <0 0xe6150000 0 0x1000>;
> + #clock-cells = <1>;
> + clock-output-names = "plla", "z", "zs", "s", "s1",
> + "p", "out";
> + };
> +
> + /* Fixed factor clocks */
> + i_clk: i_clk {
> + compatible = "fixed-factor-clock";
> + clocks = <&cpg_clocks R8A7779_CLK_PLLA>;
> + #clock-cells = <0>;
> + clock-div = <2>;
> + clock-mult = <1>;
> + clock-output-names = "i";
> + };
> + s3_clk: s3_clk {
> + compatible = "fixed-factor-clock";
> + clocks = <&cpg_clocks R8A7779_CLK_PLLA>;
> + #clock-cells = <0>;
> + clock-div = <8>;
> + clock-mult = <1>;
> + clock-output-names = "s3";
> + };
> + s4_clk: s4_clk {
> + compatible = "fixed-factor-clock";
> + clocks = <&cpg_clocks R8A7779_CLK_PLLA>;
> + #clock-cells = <0>;
> + clock-div = <16>;
> + clock-mult = <1>;
> + clock-output-names = "s4";
> + };
> + g_clk: g_clk {
> + compatible = "fixed-factor-clock";
> + clocks = <&cpg_clocks R8A7779_CLK_PLLA>;
> + #clock-cells = <0>;
> + clock-div = <24>;
> + clock-mult = <1>;
> + clock-output-names = "g";
> + };
clks2 is missing, either as a fixed-factor-clock in DT, or as a CPG special
clock.
> + /* Gate clocks */
> + mstp0_clks: mstp0_clks {
> + compatible = "renesas,r8a7779-mstp-clocks", "renesas,cpg-mstp-
clocks";
> + reg = <0 0xffc80030 0 4>, <0 0xffc80034 0 4>;
There's no status register for MSTP0.
> + clocks = <&cpg_clocks R8A7779_CLK_P>,
> <&cpg_clocks R8A7779_CLK_P>, <&cpg_clocks R8A7779_CLK_P>,
> + <&cpg_clocks R8A7779_CLK_P>, <&cpg_clocks R8A7779_CLK_P>,
> <&cpg_clocks R8A7779_CLK_P>,
> + <&cpg_clocks R8A7779_CLK_P>, <&cpg_clocks R8A7779_CLK_P>,
> <&cpg_clocks R8A7779_CLK_P>,
> + <&cpg_clocks R8A7779_CLK_P>, <&cpg_clocks R8A7779_CLK_P>,
> <&cpg_clocks R8A7779_CLK_P>,
> + <&cpg_clocks R8A7779_CLK_P>, <&cpg_clocks R8A7779_CLK_P>,
> <&cpg_clocks R8A7779_CLK_P>,
> + <&cpg_clocks R8A7779_CLK_P>;
> + #clock-cells = <1>;
> + renesas,clock-indices = <
> + R8A7779_CLK_HSPI0 R8A7779_CLK_HSPI1 R8A7779_CLK_HSPI2
> + R8A7779_CLK_TMU0 R8A7779_CLK_TMU1 R8A7779_CLK_TMU2
> + R8A7779_CLK_SCIF6 R8A7779_CLK_SCIF4 R8A7779_CLK_SCIF3
s/SCIF6/SCIF5/ (and in 04/17 as well) ?
> + R8A7779_CLK_SCIF2 R8A7779_CLK_SCIF1 R8A7779_CLK_SCIF0
> + R8A7779_CLK_I2C3 R8A7779_CLK_I2C2 R8A7779_CLK_I2C1
> + R8A7779_CLK_I2C0
> + >;
> + clock-output-names > + "hspi0", "hspi1", "hspi2",
> + "tmu0", "tmu1", "tmu2",
> + "scif6", "scif4", "scif3",
Here too.
> + "scif2", "scif1", "scif0",
> + "i2c3", "i2c2", "i2c1",
> + "i2c0";
> + };
> + mstp1_clks: mstp1_clks {
> + compatible = "renesas,r8a7779-mstp-clocks", "renesas,cpg-mstp-
clocks";
> + reg = <0 0xffc80034 0 4>, <0 0xffc80038 0 4>;
The status register is at 0xffc80044.
> + clocks = <&cpg_clocks R8A7779_CLK_P>, <&cpg_clocks
R8A7779_CLK_P>,
> + <&cpg_clocks R8A7779_CLK_P>, <&cpg_clocks R8A7779_CLK_P>,
> + <&cpg_clocks R8A7779_CLK_P>, <&cpg_clocks R8A7779_CLK_P>,
> + <&cpg_clocks R8A7779_CLK_P>, <&cpg_clocks R8A7779_CLK_P>,
> + <&cpg_clocks R8A7779_CLK_P>, <&cpg_clocks R8A7779_CLK_P>;
> + #clock-cells = <1>;
> + renesas,clock-indices = <
> + R8A7779_CLK_EHCI0 R8A7779_CLK_OHCI0
> + R8A7779_CLK_EHCI1 R8A7779_CLK_OHCI1
> + R8A7779_CLK_DU R8A7779_CLK_VIN2
> + R8A7779_CLK_VIN1 R8A7779_CLK_VIN0
> + R8A7779_CLK_SATA R8A7779_CLK_VIN3
> + >;
> + clock-output-names > + "ehci0", "ohci0",
> + "ehci1", "ohci1",
> + "du", "vin2",
> + "vin1", "vin0",
> + "sata", "vin3";
> + };
> + mstp3_clks: mstp3_clks {
> + compatible = "renesas,r8a7779-mstp-clocks", "renesas,cpg-mstp-
clocks";
> + reg = <0 0xffc8003c 0 4>, <0 0xffc80040 0 4>;
There's no status register for MSTP3.
> + clocks = <&cpg_clocks R8A7779_CLK_P>, <&cpg_clocks
R8A7779_CLK_P>,
> + <&cpg_clocks R8A7779_CLK_P>, <&cpg_clocks R8A7779_CLK_P>,
> + <&cpg_clocks R8A7779_CLK_P>, <&cpg_clocks R8A7779_CLK_P>,
> + <&cpg_clocks R8A7779_CLK_P>, <&cpg_clocks R8A7779_CLK_P>,
> + <&cpg_clocks R8A7779_CLK_P>, <&cpg_clocks R8A7779_CLK_P>;
> + #clock-cells = <1>;
> + renesas,clock-indices = <
> + R8A7779_CLK_EHCI0 R8A7779_CLK_OHCI0
> + R8A7779_CLK_EHCI1 R8A7779_CLK_OHCI1
> + R8A7779_CLK_DU R8A7779_CLK_VIN2
> + R8A7779_CLK_VIN1 R8A7779_CLK_VIN0
> + R8A7779_CLK_SATA R8A7779_CLK_VIN3
That's for MSTP1, not MSTP3.
> + >;
> + clock-output-names > + "ehci0", "ohci0",
> + "ehci1", "ohci1",
> + "du", "vin2",
> + "vin1", "vin0",
> + "sata", "vin3";
> + };
> + };
> };
--
Regards,
Laurent Pinchart
WARNING: multiple messages have this Message-ID (diff)
From: laurent.pinchart@ideasonboard.com (Laurent Pinchart)
To: linux-arm-kernel@lists.infradead.org
Subject: [PATCH RFC v2 04/17] ARM: shmobile: r8a7779: Add clocks
Date: Tue, 26 Nov 2013 15:48:45 +0100 [thread overview]
Message-ID: <2582481.JJAGzpNFcA@avalon> (raw)
In-Reply-To: <1385451139-29686-5-git-send-email-horms+renesas@verge.net.au>
Hi Simon,
Thanks for the patch.
On Tuesday 26 November 2013 16:32:06 Simon Horman wrote:
> Declare all core and MSTP clocks currently used by r8a7779-based boards.
>
> Based on work by Laurent Pinchart for the r8a7790 and r8a7791 SoCs.
>
> Cc: Laurent Pinchart <laurent.pinchart+renesas@ideasonboard.com>
> Signed-off-by: Simon Horman <horms@verge.net.au>
> ---
> arch/arm/boot/dts/r8a7779-marzen.dts | 1 +
> arch/arm/boot/dts/r8a7779.dtsi | 124 ++++++++++++++++++++++++++++++++
> 2 files changed, 125 insertions(+)
>
> diff --git a/arch/arm/boot/dts/r8a7779-marzen.dts
> b/arch/arm/boot/dts/r8a7779-marzen.dts index a7af2c2..ee3fb60 100644
> --- a/arch/arm/boot/dts/r8a7779-marzen.dts
> +++ b/arch/arm/boot/dts/r8a7779-marzen.dts
> @@ -11,6 +11,7 @@
>
> /dts-v1/;
> #include "r8a7779.dtsi"
> +#include <dt-bindings/gpio/gpio.h>
>
> / {
> model = "marzen";
> diff --git a/arch/arm/boot/dts/r8a7779.dtsi b/arch/arm/boot/dts/r8a7779.dtsi
> index b2b418a..d524b3f 100644
> --- a/arch/arm/boot/dts/r8a7779.dtsi
> +++ b/arch/arm/boot/dts/r8a7779.dtsi
> @@ -10,6 +10,7 @@
> */
>
> /include/ "skeleton.dtsi"
> +#include <dt-bindings/clock/r8a7779-clock.h>
>
> #include <dt-bindings/interrupt-controller/irq.h>
>
> @@ -248,4 +249,127 @@
> cap-sdio-irq;
> status = "disabled";
> };
> +
> + clocks {
> + #address-cells = <2>;
> + #size-cells = <2>;
> + ranges;
> +
> + /* Special CPG clocks */
> + cpg_clocks: cpg_clocks at 0xe6150000 {
> + compatible = "renesas,r8a7779-cpg-clocks";
> + reg = <0 0xe6150000 0 0x1000>;
> + #clock-cells = <1>;
> + clock-output-names = "plla", "z", "zs", "s", "s1",
> + "p", "out";
> + };
> +
> + /* Fixed factor clocks */
> + i_clk: i_clk {
> + compatible = "fixed-factor-clock";
> + clocks = <&cpg_clocks R8A7779_CLK_PLLA>;
> + #clock-cells = <0>;
> + clock-div = <2>;
> + clock-mult = <1>;
> + clock-output-names = "i";
> + };
> + s3_clk: s3_clk {
> + compatible = "fixed-factor-clock";
> + clocks = <&cpg_clocks R8A7779_CLK_PLLA>;
> + #clock-cells = <0>;
> + clock-div = <8>;
> + clock-mult = <1>;
> + clock-output-names = "s3";
> + };
> + s4_clk: s4_clk {
> + compatible = "fixed-factor-clock";
> + clocks = <&cpg_clocks R8A7779_CLK_PLLA>;
> + #clock-cells = <0>;
> + clock-div = <16>;
> + clock-mult = <1>;
> + clock-output-names = "s4";
> + };
> + g_clk: g_clk {
> + compatible = "fixed-factor-clock";
> + clocks = <&cpg_clocks R8A7779_CLK_PLLA>;
> + #clock-cells = <0>;
> + clock-div = <24>;
> + clock-mult = <1>;
> + clock-output-names = "g";
> + };
clks2 is missing, either as a fixed-factor-clock in DT, or as a CPG special
clock.
> + /* Gate clocks */
> + mstp0_clks: mstp0_clks {
> + compatible = "renesas,r8a7779-mstp-clocks", "renesas,cpg-mstp-
clocks";
> + reg = <0 0xffc80030 0 4>, <0 0xffc80034 0 4>;
There's no status register for MSTP0.
> + clocks = <&cpg_clocks R8A7779_CLK_P>,
> <&cpg_clocks R8A7779_CLK_P>, <&cpg_clocks R8A7779_CLK_P>,
> + <&cpg_clocks R8A7779_CLK_P>, <&cpg_clocks R8A7779_CLK_P>,
> <&cpg_clocks R8A7779_CLK_P>,
> + <&cpg_clocks R8A7779_CLK_P>, <&cpg_clocks R8A7779_CLK_P>,
> <&cpg_clocks R8A7779_CLK_P>,
> + <&cpg_clocks R8A7779_CLK_P>, <&cpg_clocks R8A7779_CLK_P>,
> <&cpg_clocks R8A7779_CLK_P>,
> + <&cpg_clocks R8A7779_CLK_P>, <&cpg_clocks R8A7779_CLK_P>,
> <&cpg_clocks R8A7779_CLK_P>,
> + <&cpg_clocks R8A7779_CLK_P>;
> + #clock-cells = <1>;
> + renesas,clock-indices = <
> + R8A7779_CLK_HSPI0 R8A7779_CLK_HSPI1 R8A7779_CLK_HSPI2
> + R8A7779_CLK_TMU0 R8A7779_CLK_TMU1 R8A7779_CLK_TMU2
> + R8A7779_CLK_SCIF6 R8A7779_CLK_SCIF4 R8A7779_CLK_SCIF3
s/SCIF6/SCIF5/ (and in 04/17 as well) ?
> + R8A7779_CLK_SCIF2 R8A7779_CLK_SCIF1 R8A7779_CLK_SCIF0
> + R8A7779_CLK_I2C3 R8A7779_CLK_I2C2 R8A7779_CLK_I2C1
> + R8A7779_CLK_I2C0
> + >;
> + clock-output-names =
> + "hspi0", "hspi1", "hspi2",
> + "tmu0", "tmu1", "tmu2",
> + "scif6", "scif4", "scif3",
Here too.
> + "scif2", "scif1", "scif0",
> + "i2c3", "i2c2", "i2c1",
> + "i2c0";
> + };
> + mstp1_clks: mstp1_clks {
> + compatible = "renesas,r8a7779-mstp-clocks", "renesas,cpg-mstp-
clocks";
> + reg = <0 0xffc80034 0 4>, <0 0xffc80038 0 4>;
The status register is at 0xffc80044.
> + clocks = <&cpg_clocks R8A7779_CLK_P>, <&cpg_clocks
R8A7779_CLK_P>,
> + <&cpg_clocks R8A7779_CLK_P>, <&cpg_clocks R8A7779_CLK_P>,
> + <&cpg_clocks R8A7779_CLK_P>, <&cpg_clocks R8A7779_CLK_P>,
> + <&cpg_clocks R8A7779_CLK_P>, <&cpg_clocks R8A7779_CLK_P>,
> + <&cpg_clocks R8A7779_CLK_P>, <&cpg_clocks R8A7779_CLK_P>;
> + #clock-cells = <1>;
> + renesas,clock-indices = <
> + R8A7779_CLK_EHCI0 R8A7779_CLK_OHCI0
> + R8A7779_CLK_EHCI1 R8A7779_CLK_OHCI1
> + R8A7779_CLK_DU R8A7779_CLK_VIN2
> + R8A7779_CLK_VIN1 R8A7779_CLK_VIN0
> + R8A7779_CLK_SATA R8A7779_CLK_VIN3
> + >;
> + clock-output-names =
> + "ehci0", "ohci0",
> + "ehci1", "ohci1",
> + "du", "vin2",
> + "vin1", "vin0",
> + "sata", "vin3";
> + };
> + mstp3_clks: mstp3_clks {
> + compatible = "renesas,r8a7779-mstp-clocks", "renesas,cpg-mstp-
clocks";
> + reg = <0 0xffc8003c 0 4>, <0 0xffc80040 0 4>;
There's no status register for MSTP3.
> + clocks = <&cpg_clocks R8A7779_CLK_P>, <&cpg_clocks
R8A7779_CLK_P>,
> + <&cpg_clocks R8A7779_CLK_P>, <&cpg_clocks R8A7779_CLK_P>,
> + <&cpg_clocks R8A7779_CLK_P>, <&cpg_clocks R8A7779_CLK_P>,
> + <&cpg_clocks R8A7779_CLK_P>, <&cpg_clocks R8A7779_CLK_P>,
> + <&cpg_clocks R8A7779_CLK_P>, <&cpg_clocks R8A7779_CLK_P>;
> + #clock-cells = <1>;
> + renesas,clock-indices = <
> + R8A7779_CLK_EHCI0 R8A7779_CLK_OHCI0
> + R8A7779_CLK_EHCI1 R8A7779_CLK_OHCI1
> + R8A7779_CLK_DU R8A7779_CLK_VIN2
> + R8A7779_CLK_VIN1 R8A7779_CLK_VIN0
> + R8A7779_CLK_SATA R8A7779_CLK_VIN3
That's for MSTP1, not MSTP3.
> + >;
> + clock-output-names =
> + "ehci0", "ohci0",
> + "ehci1", "ohci1",
> + "du", "vin2",
> + "vin1", "vin0",
> + "sata", "vin3";
> + };
> + };
> };
--
Regards,
Laurent Pinchart
next prev parent reply other threads:[~2013-11-26 14:48 UTC|newest]
Thread overview: 68+ messages / expand[flat|nested] mbox.gz Atom feed top
2013-11-26 7:32 [PATCH RFC v2 00/17] ARM: shmobile: r8a7779, marzen: multiplatform Simon Horman
2013-11-26 7:32 ` Simon Horman
2013-11-26 7:32 ` [PATCH RFC v2 01/17] clk: shmobile: r8a7779: Add clocks support Simon Horman
2013-11-26 7:32 ` Simon Horman
2013-11-26 14:35 ` Laurent Pinchart
2013-11-26 14:35 ` Laurent Pinchart
2013-11-26 7:32 ` [PATCH RFC v2 02/17] clk: shmobile: r8a7779: Add MSTP clock support Simon Horman
2013-11-26 7:32 ` Simon Horman
2013-11-26 14:36 ` Laurent Pinchart
2013-11-26 14:36 ` Laurent Pinchart
2013-11-27 5:13 ` Simon Horman
2013-11-27 5:13 ` Simon Horman
2013-11-26 7:32 ` [PATCH RFC v2 03/17] ARM: shmobile: r8a7779: Add clock index macros for DT sources Simon Horman
2013-11-26 7:32 ` Simon Horman
2013-11-26 14:43 ` Laurent Pinchart
2013-11-26 14:43 ` Laurent Pinchart
2013-11-27 5:16 ` Simon Horman
2013-11-27 5:16 ` Simon Horman
2013-11-26 7:32 ` [PATCH RFC v2 04/17] ARM: shmobile: r8a7779: Add clocks Simon Horman
2013-11-26 7:32 ` Simon Horman
2013-11-26 14:48 ` Laurent Pinchart [this message]
2013-11-26 14:48 ` Laurent Pinchart
2013-11-26 7:32 ` [PATCH RFC v2 05/17] ARM: shmobile: r8a7779: Reference clocks Simon Horman
2013-11-26 7:32 ` Simon Horman
2013-11-26 14:50 ` Laurent Pinchart
2013-11-26 14:50 ` Laurent Pinchart
2013-11-27 5:17 ` Simon Horman
2013-11-27 5:17 ` Simon Horman
2013-11-26 7:32 ` [PATCH RFC v2 06/17] ARM: shmobile: Sync Marzen DTS with Marzen reference DTS Simon Horman
2013-11-26 7:32 ` Simon Horman
2013-11-26 7:32 ` [PATCH RFC v2 07/17] ARM: shmobile: r8a7779: Sort headers alphabetically Simon Horman
2013-11-26 7:32 ` Simon Horman
2013-11-26 9:33 ` Sergei Shtylyov
2013-11-26 9:33 ` Sergei Shtylyov
2013-11-27 5:09 ` Simon Horman
2013-11-27 5:09 ` Simon Horman
2013-11-27 10:20 ` Laurent Pinchart
2013-11-27 10:20 ` Laurent Pinchart
2013-11-26 7:32 ` [PATCH RFC v2 08/17] ARM: shmobile: r8a7779: Add helper to read mode pins Simon Horman
2013-11-26 7:32 ` Simon Horman
2013-11-26 7:32 ` [PATCH RFC v2 09/17] ARM: shmobile: r8a7779: Move r8a7779_earlytimer_init to clock-r8a7779.c Simon Horman
2013-11-26 7:32 ` Simon Horman
2013-11-26 7:32 ` [PATCH RFC v2 10/17] ARM: shmobile: marzen-reference: Move clock and OF device initialisation into b Simon Horman
2013-11-26 7:32 ` [PATCH RFC v2 10/17] ARM: shmobile: marzen-reference: Move clock and OF device initialisation into board code Simon Horman
2013-11-26 7:32 ` [PATCH RFC v2 11/17] ARM: shmobile: r8a7779: Do not include sh_clk.h in r8a7779.h Simon Horman
2013-11-26 7:32 ` Simon Horman
2013-11-26 7:32 ` [PATCH RFC v2 12/17] ARM: shmobile: r8a7779: Initial multiplatform support Simon Horman
2013-11-26 7:32 ` Simon Horman
2013-11-26 7:32 ` [PATCH RFC v2 13/17] ARM: shmobile: marzen-reference: Initialize CPG device Simon Horman
2013-11-26 7:32 ` Simon Horman
2013-11-26 7:32 ` [PATCH RFC v2 14/17] ARM: shmobile: marzen-reference: Instantiate clkdevs for SCIF and CMT Simon Horman
2013-11-26 7:32 ` Simon Horman
2013-11-26 7:32 ` [PATCH RFC v2 15/17] ARM: shmobile: Remove non-multiplatform Marzen reference support Simon Horman
2013-11-26 7:32 ` Simon Horman
2013-11-26 14:52 ` Laurent Pinchart
2013-11-26 14:52 ` Laurent Pinchart
2013-11-27 5:17 ` Simon Horman
2013-11-27 5:17 ` Simon Horman
2013-11-27 8:51 ` Magnus Damm
2013-11-27 8:51 ` Magnus Damm
2013-11-27 11:29 ` Laurent Pinchart
2013-11-27 11:29 ` Laurent Pinchart
2013-11-28 2:41 ` Simon Horman
2013-11-28 2:41 ` Simon Horman
2013-11-26 7:32 ` [PATCH RFC v2 16/17] ARM: shmobile: Let Marzen multiplatform boot with Marzen DTB Simon Horman
2013-11-26 7:32 ` Simon Horman
2013-11-26 7:32 ` [PATCH RFC v2 17/17] ARM: shmobile: Remove Marzen reference DTS Simon Horman
2013-11-26 7:32 ` Simon Horman
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