From: "Heiko Stübner" <heiko@sntech.de>
To: Paul Walmsley <paul.walmsley@sifive.com>,
Palmer Dabbelt <palmer@dabbelt.com>,
Albert Ou <aou@eecs.berkeley.edu>, Guo Ren <guoren@kernel.org>,
Nathan Chancellor <nathan@kernel.org>,
Icenowy Zheng <uwu@icenowy.me>
Cc: Sergey Matyukevich <sergey.matyukevich@syntacore.com>,
linux-riscv@lists.infradead.org, linux-kernel@vger.kernel.org
Subject: Re: [PATCH RESEND 1/2] riscv: errata: fix T-Head dcache.cva encoding
Date: Tue, 03 Jan 2023 09:34:37 +0100 [thread overview]
Message-ID: <2668919.mvXUDI8C0e@diego> (raw)
In-Reply-To: <20230103062610.69704-1-uwu@icenowy.me>
Am Dienstag, 3. Januar 2023, 07:26:09 CET schrieb Icenowy Zheng:
> The dcache.cva encoding shown in the comments are wrong, it's for
> dcache.cval1 (which is restricted to L1) instead.
>
> Fix this in the comment and in the hardcoded instruction.
>
> Signed-off-by: Icenowy Zheng <uwu@icenowy.me>
> Tested-by: Sergey Matyukevich <sergey.matyukevich@syntacore.com>
Reviewed-by: Heiko Stuebner <heiko@sntech.de>
Original was on
https://lore.kernel.org/all/5894419.tdWV9SEqCh@phil/
> ---
> Included when resending:
> - Sergey's Tested-by tag.
>
> arch/riscv/include/asm/errata_list.h | 4 ++--
> 1 file changed, 2 insertions(+), 2 deletions(-)
>
> diff --git a/arch/riscv/include/asm/errata_list.h b/arch/riscv/include/asm/errata_list.h
> index 4180312d2a70..605800bd390e 100644
> --- a/arch/riscv/include/asm/errata_list.h
> +++ b/arch/riscv/include/asm/errata_list.h
> @@ -102,7 +102,7 @@ asm volatile(ALTERNATIVE( \
> * | 31 - 25 | 24 - 20 | 19 - 15 | 14 - 12 | 11 - 7 | 6 - 0 |
> * 0000001 01001 rs1 000 00000 0001011
> * dcache.cva rs1 (clean, virtual address)
> - * 0000001 00100 rs1 000 00000 0001011
> + * 0000001 00101 rs1 000 00000 0001011
> *
> * dcache.cipa rs1 (clean then invalidate, physical address)
> * | 31 - 25 | 24 - 20 | 19 - 15 | 14 - 12 | 11 - 7 | 6 - 0 |
> @@ -115,7 +115,7 @@ asm volatile(ALTERNATIVE( \
> * 0000000 11001 00000 000 00000 0001011
> */
> #define THEAD_inval_A0 ".long 0x0265000b"
> -#define THEAD_clean_A0 ".long 0x0245000b"
> +#define THEAD_clean_A0 ".long 0x0255000b"
> #define THEAD_flush_A0 ".long 0x0275000b"
> #define THEAD_SYNC_S ".long 0x0190000b"
>
>
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WARNING: multiple messages have this Message-ID (diff)
From: "Heiko Stübner" <heiko@sntech.de>
To: Paul Walmsley <paul.walmsley@sifive.com>,
Palmer Dabbelt <palmer@dabbelt.com>,
Albert Ou <aou@eecs.berkeley.edu>, Guo Ren <guoren@kernel.org>,
Nathan Chancellor <nathan@kernel.org>,
Icenowy Zheng <uwu@icenowy.me>
Cc: linux-riscv@lists.infradead.org, linux-kernel@vger.kernel.org,
Icenowy Zheng <uwu@icenowy.me>,
Sergey Matyukevich <sergey.matyukevich@syntacore.com>
Subject: Re: [PATCH RESEND 1/2] riscv: errata: fix T-Head dcache.cva encoding
Date: Tue, 03 Jan 2023 09:34:37 +0100 [thread overview]
Message-ID: <2668919.mvXUDI8C0e@diego> (raw)
In-Reply-To: <20230103062610.69704-1-uwu@icenowy.me>
Am Dienstag, 3. Januar 2023, 07:26:09 CET schrieb Icenowy Zheng:
> The dcache.cva encoding shown in the comments are wrong, it's for
> dcache.cval1 (which is restricted to L1) instead.
>
> Fix this in the comment and in the hardcoded instruction.
>
> Signed-off-by: Icenowy Zheng <uwu@icenowy.me>
> Tested-by: Sergey Matyukevich <sergey.matyukevich@syntacore.com>
Reviewed-by: Heiko Stuebner <heiko@sntech.de>
Original was on
https://lore.kernel.org/all/5894419.tdWV9SEqCh@phil/
> ---
> Included when resending:
> - Sergey's Tested-by tag.
>
> arch/riscv/include/asm/errata_list.h | 4 ++--
> 1 file changed, 2 insertions(+), 2 deletions(-)
>
> diff --git a/arch/riscv/include/asm/errata_list.h b/arch/riscv/include/asm/errata_list.h
> index 4180312d2a70..605800bd390e 100644
> --- a/arch/riscv/include/asm/errata_list.h
> +++ b/arch/riscv/include/asm/errata_list.h
> @@ -102,7 +102,7 @@ asm volatile(ALTERNATIVE( \
> * | 31 - 25 | 24 - 20 | 19 - 15 | 14 - 12 | 11 - 7 | 6 - 0 |
> * 0000001 01001 rs1 000 00000 0001011
> * dcache.cva rs1 (clean, virtual address)
> - * 0000001 00100 rs1 000 00000 0001011
> + * 0000001 00101 rs1 000 00000 0001011
> *
> * dcache.cipa rs1 (clean then invalidate, physical address)
> * | 31 - 25 | 24 - 20 | 19 - 15 | 14 - 12 | 11 - 7 | 6 - 0 |
> @@ -115,7 +115,7 @@ asm volatile(ALTERNATIVE( \
> * 0000000 11001 00000 000 00000 0001011
> */
> #define THEAD_inval_A0 ".long 0x0265000b"
> -#define THEAD_clean_A0 ".long 0x0245000b"
> +#define THEAD_clean_A0 ".long 0x0255000b"
> #define THEAD_flush_A0 ".long 0x0275000b"
> #define THEAD_SYNC_S ".long 0x0190000b"
>
>
next prev parent reply other threads:[~2023-01-03 8:39 UTC|newest]
Thread overview: 14+ messages / expand[flat|nested] mbox.gz Atom feed top
2023-01-03 6:26 [PATCH RESEND 1/2] riscv: errata: fix T-Head dcache.cva encoding Icenowy Zheng
2023-01-03 6:26 ` [PATCH RESEND 2/2] riscv: errata: prefix T-Head mnemonics with th Icenowy Zheng
2023-01-03 8:35 ` Heiko Stübner
2023-01-03 8:35 ` Heiko Stübner
2023-01-03 10:18 ` Conor Dooley
2023-01-03 10:18 ` Conor Dooley
2023-01-03 19:10 ` Conor Dooley
2023-01-03 19:10 ` Conor Dooley
2023-01-03 8:34 ` Heiko Stübner [this message]
2023-01-03 8:34 ` [PATCH RESEND 1/2] riscv: errata: fix T-Head dcache.cva encoding Heiko Stübner
2023-01-03 12:02 ` Guo Ren
2023-01-03 12:02 ` Guo Ren
2023-01-24 13:19 ` Icenowy Zheng
2023-01-24 13:19 ` Icenowy Zheng
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