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From: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org>
To: Peng Fan <peng.fan@oss.nxp.com>,
	robh+dt@kernel.org, krzysztof.kozlowski+dt@linaro.org,
	shawnguo@kernel.org, Fabio Estevam <festevam@denx.de>,
	Lucas Stach <l.stach@pengutronix.de>,
	Sascha Hauer <s.hauer@pengutronix.de>,
	kernel@pengutronix.de, linux-arm-kernel@lists.infradead.org,
	devicetree@vger.kernel.org, linux-imx@nxp.com,
	abelvesa@kernel.org, Marek Vasut <marex@denx.de>
Subject: Re: Align fsl,pins with dtschema
Date: Tue, 26 Jul 2022 11:35:52 +0200	[thread overview]
Message-ID: <26aa352e-d39c-1784-e5c3-9e90d25d8ab5@linaro.org> (raw)
In-Reply-To: <1c6c9750-571c-bfd9-8804-4f16d691c480@oss.nxp.com>

On 23/07/2022 14:15, Peng Fan wrote:
> All,
> 
> I am thinking whether we need to modify the fsl,pins as below. Because 
> fsl,pins use uint32-matrix, so just wanna know we should do this update.
> 
> Anyway there is NO dtbs check warning. If we update fsl,pins, there are 
> bunches of dts files need update. Do you think we need to update or not?
> 
>          pinctrl_ov5640: ov5640grp {
> -               fsl,pins = <
> -                       MX8MM_IOMUXC_GPIO1_IO07_GPIO1_IO7               0x19
> -                       MX8MM_IOMUXC_GPIO1_IO06_GPIO1_IO6               0x19
> -                       MX8MM_IOMUXC_GPIO1_IO14_CCMSRCGPCMIX_CLKO1      0x59
> -               >;
> +               fsl,pins =
> +                       <MX8MM_IOMUXC_GPIO1_IO07_GPIO1_IO7 
> 0x19>,
> +                       <MX8MM_IOMUXC_GPIO1_IO06_GPIO1_IO6 
> 0x19>,
> +                       <MX8MM_IOMUXC_GPIO1_IO14_CCMSRCGPCMIX_CLKO1 
> 0x59>;
>          };

I believe yes, but as Rob replied, the dtschema has trouble matching the
different fsl,pins, if I understood correctly.


Best regards,
Krzysztof

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WARNING: multiple messages have this Message-ID (diff)
From: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org>
To: Peng Fan <peng.fan@oss.nxp.com>,
	robh+dt@kernel.org, krzysztof.kozlowski+dt@linaro.org,
	shawnguo@kernel.org, Fabio Estevam <festevam@denx.de>,
	Lucas Stach <l.stach@pengutronix.de>,
	Sascha Hauer <s.hauer@pengutronix.de>,
	kernel@pengutronix.de, linux-arm-kernel@lists.infradead.org,
	devicetree@vger.kernel.org, linux-imx@nxp.com,
	abelvesa@kernel.org, Marek Vasut <marex@denx.de>
Subject: Re: Align fsl,pins with dtschema
Date: Tue, 26 Jul 2022 11:35:52 +0200	[thread overview]
Message-ID: <26aa352e-d39c-1784-e5c3-9e90d25d8ab5@linaro.org> (raw)
In-Reply-To: <1c6c9750-571c-bfd9-8804-4f16d691c480@oss.nxp.com>

On 23/07/2022 14:15, Peng Fan wrote:
> All,
> 
> I am thinking whether we need to modify the fsl,pins as below. Because 
> fsl,pins use uint32-matrix, so just wanna know we should do this update.
> 
> Anyway there is NO dtbs check warning. If we update fsl,pins, there are 
> bunches of dts files need update. Do you think we need to update or not?
> 
>          pinctrl_ov5640: ov5640grp {
> -               fsl,pins = <
> -                       MX8MM_IOMUXC_GPIO1_IO07_GPIO1_IO7               0x19
> -                       MX8MM_IOMUXC_GPIO1_IO06_GPIO1_IO6               0x19
> -                       MX8MM_IOMUXC_GPIO1_IO14_CCMSRCGPCMIX_CLKO1      0x59
> -               >;
> +               fsl,pins =
> +                       <MX8MM_IOMUXC_GPIO1_IO07_GPIO1_IO7 
> 0x19>,
> +                       <MX8MM_IOMUXC_GPIO1_IO06_GPIO1_IO6 
> 0x19>,
> +                       <MX8MM_IOMUXC_GPIO1_IO14_CCMSRCGPCMIX_CLKO1 
> 0x59>;
>          };

I believe yes, but as Rob replied, the dtschema has trouble matching the
different fsl,pins, if I understood correctly.


Best regards,
Krzysztof

  reply	other threads:[~2022-07-26  9:37 UTC|newest]

Thread overview: 6+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2022-07-23 12:15 Align fsl,pins with dtschema Peng Fan
2022-07-23 12:15 ` Peng Fan
2022-07-26  9:35 ` Krzysztof Kozlowski [this message]
2022-07-26  9:35   ` Krzysztof Kozlowski
2022-07-28  8:34   ` Alexander Stein
2022-07-28  8:34     ` Alexander Stein

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