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From: Christophe JAILLET <christophe.jaillet@wanadoo.fr>
To: lewis.hanly@microchip.com, linux-gpio@vger.kernel.org,
	linux-riscv@lists.infradead.org, linus.walleij@linaro.org,
	brgl@bgdev.pl, linux-kernel@vger.kernel.org, palmer@dabbelt.com,
	maz@kernel.org
Cc: conor.dooley@microchip.com, daire.mcnamara@microchip.com
Subject: Re: [PATCH v5 1/1] gpio: mpfs: add polarfire soc gpio support
Date: Mon, 15 Aug 2022 09:38:11 +0200	[thread overview]
Message-ID: <271c00a5-fb5d-ff9e-3c4d-ec2732b991ba@wanadoo.fr> (raw)
In-Reply-To: <20220815070606.1298421-2-lewis.hanly@microchip.com>

Le 15/08/2022 à 09:06, lewis.hanly@microchip.com a écrit :
> From: Lewis Hanly <lewis.hanly@microchip.com>
> 
> Add a driver to support the Polarfire SoC gpio controller
> 
> Signed-off-by: Lewis Hanly <lewis.hanly@microchip.com>
> ---
>   drivers/gpio/Kconfig     |   7 +
>   drivers/gpio/Makefile    |   1 +
>   drivers/gpio/gpio-mpfs.c | 318 +++++++++++++++++++++++++++++++++++++++
>   3 files changed, 326 insertions(+)
>   create mode 100644 drivers/gpio/gpio-mpfs.c
> 

> +static int mpfs_gpio_probe(struct platform_device *pdev)
> +{
> +	struct clk *clk;
> +	struct device *dev = &pdev->dev;
> +	struct device_node *node = pdev->dev.of_node;
> +	struct mpfs_gpio_chip *mpfs_gpio;
> +	struct gpio_irq_chip *girq;
> +	int i, ret, ngpios, nirqs;
> +
> +	mpfs_gpio = devm_kzalloc(dev, sizeof(*mpfs_gpio), GFP_KERNEL);
> +	if (!mpfs_gpio)
> +		return -ENOMEM;
> +
> +	mpfs_gpio->base = devm_platform_ioremap_resource(pdev, 0);
> +	if (IS_ERR(mpfs_gpio->base))
> +		return dev_err_probe(dev, PTR_ERR(mpfs_gpio->clk), "input clock not found.\n");

PTR_ERR(mpfs_gpio->base)?
"input clock not found" also looks odd after a 
devm_platform_ioremap_resource() call.

> +
> +	clk = devm_clk_get(dev, NULL);
> +	if (IS_ERR(clk))
> +		return dev_err_probe(dev, PTR_ERR(clk), "devm_clk_get failed\n");
> +

WARNING: multiple messages have this Message-ID (diff)
From: Christophe JAILLET <christophe.jaillet@wanadoo.fr>
To: lewis.hanly@microchip.com, linux-gpio@vger.kernel.org,
	linux-riscv@lists.infradead.org, linus.walleij@linaro.org,
	brgl@bgdev.pl, linux-kernel@vger.kernel.org, palmer@dabbelt.com,
	maz@kernel.org
Cc: conor.dooley@microchip.com, daire.mcnamara@microchip.com
Subject: Re: [PATCH v5 1/1] gpio: mpfs: add polarfire soc gpio support
Date: Mon, 15 Aug 2022 09:38:11 +0200	[thread overview]
Message-ID: <271c00a5-fb5d-ff9e-3c4d-ec2732b991ba@wanadoo.fr> (raw)
In-Reply-To: <20220815070606.1298421-2-lewis.hanly@microchip.com>

Le 15/08/2022 à 09:06, lewis.hanly@microchip.com a écrit :
> From: Lewis Hanly <lewis.hanly@microchip.com>
> 
> Add a driver to support the Polarfire SoC gpio controller
> 
> Signed-off-by: Lewis Hanly <lewis.hanly@microchip.com>
> ---
>   drivers/gpio/Kconfig     |   7 +
>   drivers/gpio/Makefile    |   1 +
>   drivers/gpio/gpio-mpfs.c | 318 +++++++++++++++++++++++++++++++++++++++
>   3 files changed, 326 insertions(+)
>   create mode 100644 drivers/gpio/gpio-mpfs.c
> 

> +static int mpfs_gpio_probe(struct platform_device *pdev)
> +{
> +	struct clk *clk;
> +	struct device *dev = &pdev->dev;
> +	struct device_node *node = pdev->dev.of_node;
> +	struct mpfs_gpio_chip *mpfs_gpio;
> +	struct gpio_irq_chip *girq;
> +	int i, ret, ngpios, nirqs;
> +
> +	mpfs_gpio = devm_kzalloc(dev, sizeof(*mpfs_gpio), GFP_KERNEL);
> +	if (!mpfs_gpio)
> +		return -ENOMEM;
> +
> +	mpfs_gpio->base = devm_platform_ioremap_resource(pdev, 0);
> +	if (IS_ERR(mpfs_gpio->base))
> +		return dev_err_probe(dev, PTR_ERR(mpfs_gpio->clk), "input clock not found.\n");

PTR_ERR(mpfs_gpio->base)?
"input clock not found" also looks odd after a 
devm_platform_ioremap_resource() call.

> +
> +	clk = devm_clk_get(dev, NULL);
> +	if (IS_ERR(clk))
> +		return dev_err_probe(dev, PTR_ERR(clk), "devm_clk_get failed\n");
> +

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  reply	other threads:[~2022-08-15  7:38 UTC|newest]

Thread overview: 10+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2022-08-15  7:06 [PATCH v5 0/1] Add Polarfire SoC GPIO support lewis.hanly
2022-08-15  7:06 ` lewis.hanly
2022-08-15  7:06 ` [PATCH v5 1/1] gpio: mpfs: add polarfire soc gpio support lewis.hanly
2022-08-15  7:06   ` lewis.hanly
2022-08-15  7:38   ` Christophe JAILLET [this message]
2022-08-15  7:38     ` Christophe JAILLET
2022-08-15 12:04     ` Lewis.Hanly
2022-08-15 12:04       ` Lewis.Hanly
2022-08-15 11:39   ` kernel test robot
2022-08-15 11:39     ` kernel test robot

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