From: James Hogan <james.hogan@imgtec.com>
To: qemu-devel@nongnu.org
Cc: Petar Jovanovic <petar.jovanovic@rt-rk.com>,
aurelien@aurel32.net, petar.jovanovic@imgtec.com
Subject: Re: [Qemu-devel] [PATCH 2/2] target-mips: implement UserLocal Register
Date: Thu, 22 May 2014 01:19:23 +0100 [thread overview]
Message-ID: <2733244.VTZ72pzX9G@radagast> (raw)
In-Reply-To: <1400264014-78911-3-git-send-email-petar.jovanovic@rt-rk.com>
On Friday 16 May 2014 20:13:34 Petar Jovanovic wrote:
> diff --git a/target-mips/cpu.h b/target-mips/cpu.h
> index 6c2014e..bb18fb8 100644
> --- a/target-mips/cpu.h
> +++ b/target-mips/cpu.h
> @@ -227,6 +227,7 @@ struct CPUMIPSState {
> target_ulong CP0_EntryLo0;
> target_ulong CP0_EntryLo1;
> target_ulong CP0_Context;
> + target_ulong CP0_UserLocal;
Also according to the MT ASE UserLocal is replicated for each TC, so this
should really go in struct TCState I think.
Cheers
James
prev parent reply other threads:[~2014-05-22 0:19 UTC|newest]
Thread overview: 7+ messages / expand[flat|nested] mbox.gz Atom feed top
2014-05-16 18:13 [Qemu-devel] [PATCH 0/2] implementation of UserLocal register for MIPS Petar Jovanovic
2014-05-16 18:13 ` [Qemu-devel] [PATCH 1/2] target-mips: pass CPUMIPSState to gen_mfc0/mtc0/dmfc0/dmtc0 Petar Jovanovic
2014-05-17 18:03 ` Richard Henderson
2014-05-16 18:13 ` [Qemu-devel] [PATCH 2/2] target-mips: implement UserLocal Register Petar Jovanovic
2014-05-17 18:11 ` Richard Henderson
2014-05-22 0:03 ` James Hogan
2014-05-22 0:19 ` James Hogan [this message]
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