From: Thomas Monjalon <thomas@monjalon.net>
To: Jerin Jacob <jerin.jacob@caviumnetworks.com>
Cc: dev@dpdk.org, Jianbo Liu <jianbo.liu@linaro.org>,
Hemant Agrawal <hemant.agrawal@nxp.com>,
christian.ehrhardt@canonical.com
Subject: Re: [PATCH] config: set cache line as 128B in the generic arm64 config
Date: Sun, 30 Apr 2017 23:10:16 +0200 [thread overview]
Message-ID: <2751948.JIQzdyJ0NR@xps> (raw)
In-Reply-To: <CAP4Qi39OGHq8fhmFDqQBsSuU8=w5Trsb0R-=tcJm2GNgKEGcig@mail.gmail.com>
28/04/2017 04:14, Jianbo Liu:
> On 27 April 2017 at 00:29, Jerin Jacob <jerin.jacob@caviumnetworks.com> wrote:
> > armv8 implementations may have 64B or 128B cache line.
> > Setting to the maximum available cache line size in generic config to
> > address minimum DMA alignment across all arm64 implementations.
> >
> > Increasing the cacheline size has no negative impact to cache invalidation
> > on systems with a smaller cache line.
> >
> > The need for the minimum DMA alignment has impact on functional aspects
> > of the platform so default config should cater the functional aspects.
> >
> > There is an impact on memory usage with this scheme, but that's not too
> > important for the single image arm64 distribution use case.
> >
> > The arm64 linux kernel followed the similar approach for single
> > arm64 image use case.
> > http://lxr.free-electrons.com/source/arch/arm64/include/asm/cache.h
> >
> > Signed-off-by: Jerin Jacob <jerin.jacob@caviumnetworks.com>
>
> Acked-by: Jianbo Liu <jianbo.liu@linaro.org>
Applied, thanks
next prev parent reply other threads:[~2017-04-30 21:10 UTC|newest]
Thread overview: 5+ messages / expand[flat|nested] mbox.gz Atom feed top
2017-04-26 16:29 [PATCH] config: set cache line as 128B in the generic arm64 config Jerin Jacob
2017-04-28 2:14 ` Jianbo Liu
2017-04-28 5:03 ` Jerin Jacob
2017-04-30 21:10 ` Thomas Monjalon [this message]
2017-04-28 3:59 ` santosh
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