From: Chris Wilson <chris@chris-wilson.co.uk>
To: Ben Widawsky <ben@bwidawsk.net>
Cc: intel-gfx@lists.freedesktop.org
Subject: Re: [PATCH] drm/i915: Fix pte updates in ggtt clear range
Date: Tue, 27 Nov 2012 16:42:30 +0000 [thread overview]
Message-ID: <275ffc$7ja45m@fmsmga002.fm.intel.com> (raw)
In-Reply-To: <20121127083257.00003a39@unknown>
On Tue, 27 Nov 2012 08:32:57 -0800, Ben Widawsky <ben@bwidawsk.net> wrote:
> On Tue, 27 Nov 2012 08:22:01 +0000
> Chris Wilson <chris@chris-wilson.co.uk> wrote:
>
> > On Mon, 26 Nov 2012 21:52:54 -0800, Ben Widawsky <ben@bwidawsk.net>
> > wrote:
> > > This bug was introduced by me:
> > > commit e76e9aebcdbfebae8f4cd147e3c0f800d36e97f3
> > > Author: Ben Widawsky <ben@bwidawsk.net>
> > > Date: Sun Nov 4 09:21:27 2012 -0800
> > >
> > > drm/i915: Stop using AGP layer for GEN6+
> > >
> > > The existing code uses memset_io which follows memset semantics in
> > > only guaranteeing a write of individual bytes. Since a PTE entry is
> > > 4 bytes, this can only be correct if the scratch page address is 0.
> >
> > Gah. Wasn't there an iowrite32_rep?
>
> And you would hope it does what you want... but it seems like just a
> memcpy of dword sized chunks.
I feel suitably embarassed at missing it the first time, especially as
we've had similar conversations in the past.
Reviewed-by: Chris Wilson <chris@chris-wilson.co.uk>
-Chris
--
Chris Wilson, Intel Open Source Technology Centre
next prev parent reply other threads:[~2012-11-27 16:42 UTC|newest]
Thread overview: 5+ messages / expand[flat|nested] mbox.gz Atom feed top
2012-11-27 5:52 [PATCH] drm/i915: Fix pte updates in ggtt clear range Ben Widawsky
2012-11-27 8:22 ` Chris Wilson
2012-11-27 16:32 ` Ben Widawsky
2012-11-27 16:42 ` Chris Wilson [this message]
2012-11-28 19:12 ` Ben Widawsky
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