From: Daniel Henrique Barboza <dbarboza@ventanamicro.com>
To: Richard Henderson <richard.henderson@linaro.org>, qemu-devel@nongnu.org
Subject: Re: [PATCH 06/11] tcg/riscv: Support rotates from Zbb
Date: Mon, 8 May 2023 09:44:27 -0300 [thread overview]
Message-ID: <27f0bafe-2a17-d64c-e749-047c0a12d083@ventanamicro.com> (raw)
In-Reply-To: <20230503085657.1814850-7-richard.henderson@linaro.org>
On 5/3/23 05:56, Richard Henderson wrote:
> Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
> ---
Reviewed-by: Daniel Henrique Barboza <dbarboza@ventanamicro.com>
> tcg/riscv/tcg-target.h | 4 ++--
> tcg/riscv/tcg-target.c.inc | 34 ++++++++++++++++++++++++++++++++++
> 2 files changed, 36 insertions(+), 2 deletions(-)
>
> diff --git a/tcg/riscv/tcg-target.h b/tcg/riscv/tcg-target.h
> index 9f58d46208..317d385924 100644
> --- a/tcg/riscv/tcg-target.h
> +++ b/tcg/riscv/tcg-target.h
> @@ -101,7 +101,7 @@ extern bool have_zbb;
> #define TCG_TARGET_HAS_div_i32 1
> #define TCG_TARGET_HAS_rem_i32 1
> #define TCG_TARGET_HAS_div2_i32 0
> -#define TCG_TARGET_HAS_rot_i32 0
> +#define TCG_TARGET_HAS_rot_i32 have_zbb
> #define TCG_TARGET_HAS_deposit_i32 0
> #define TCG_TARGET_HAS_extract_i32 0
> #define TCG_TARGET_HAS_sextract_i32 0
> @@ -136,7 +136,7 @@ extern bool have_zbb;
> #define TCG_TARGET_HAS_div_i64 1
> #define TCG_TARGET_HAS_rem_i64 1
> #define TCG_TARGET_HAS_div2_i64 0
> -#define TCG_TARGET_HAS_rot_i64 0
> +#define TCG_TARGET_HAS_rot_i64 have_zbb
> #define TCG_TARGET_HAS_deposit_i64 0
> #define TCG_TARGET_HAS_extract_i64 0
> #define TCG_TARGET_HAS_sextract_i64 0
> diff --git a/tcg/riscv/tcg-target.c.inc b/tcg/riscv/tcg-target.c.inc
> index f64eaa8515..58f969b4fe 100644
> --- a/tcg/riscv/tcg-target.c.inc
> +++ b/tcg/riscv/tcg-target.c.inc
> @@ -1458,6 +1458,36 @@ static void tcg_out_op(TCGContext *s, TCGOpcode opc,
> }
> break;
>
> + case INDEX_op_rotl_i32:
> + if (c2) {
> + tcg_out_opc_imm(s, OPC_RORIW, a0, a1, -a2 & 0x1f);
> + } else {
> + tcg_out_opc_reg(s, OPC_ROLW, a0, a1, a2);
> + }
> + break;
> + case INDEX_op_rotl_i64:
> + if (c2) {
> + tcg_out_opc_imm(s, OPC_RORI, a0, a1, -a2 & 0x3f);
> + } else {
> + tcg_out_opc_reg(s, OPC_ROL, a0, a1, a2);
> + }
> + break;
> +
> + case INDEX_op_rotr_i32:
> + if (c2) {
> + tcg_out_opc_imm(s, OPC_RORIW, a0, a1, a2 & 0x1f);
> + } else {
> + tcg_out_opc_reg(s, OPC_RORW, a0, a1, a2);
> + }
> + break;
> + case INDEX_op_rotr_i64:
> + if (c2) {
> + tcg_out_opc_imm(s, OPC_RORI, a0, a1, a2 & 0x3f);
> + } else {
> + tcg_out_opc_reg(s, OPC_ROR, a0, a1, a2);
> + }
> + break;
> +
> case INDEX_op_add2_i32:
> tcg_out_addsub2(s, a0, a1, a2, args[3], args[4], args[5],
> const_args[4], const_args[5], false, true);
> @@ -1629,9 +1659,13 @@ static TCGConstraintSetIndex tcg_target_op_def(TCGOpcode op)
> case INDEX_op_shl_i32:
> case INDEX_op_shr_i32:
> case INDEX_op_sar_i32:
> + case INDEX_op_rotl_i32:
> + case INDEX_op_rotr_i32:
> case INDEX_op_shl_i64:
> case INDEX_op_shr_i64:
> case INDEX_op_sar_i64:
> + case INDEX_op_rotl_i64:
> + case INDEX_op_rotr_i64:
> return C_O1_I2(r, r, ri);
>
> case INDEX_op_brcond_i32:
next prev parent reply other threads:[~2023-05-08 12:45 UTC|newest]
Thread overview: 35+ messages / expand[flat|nested] mbox.gz Atom feed top
2023-05-03 8:56 [PATCH 00/11] tcg/riscv: Support for Zba, Zbb, Zicond extensions Richard Henderson
2023-05-03 8:56 ` [PATCH 01/11] disas/riscv: Decode czero.{eqz,nez} Richard Henderson
2023-05-08 12:37 ` Daniel Henrique Barboza
2023-05-16 23:33 ` Alistair Francis
2023-05-03 8:56 ` [PATCH 02/11] tcg/riscv: Probe for Zba, Zbb, Zicond extensions Richard Henderson
2023-05-08 12:37 ` Daniel Henrique Barboza
2023-05-16 23:35 ` Alistair Francis
2023-05-03 8:56 ` [PATCH 03/11] tcg/riscv: Support ANDN, ORN, XNOR from Zbb Richard Henderson
2023-05-08 12:37 ` Daniel Henrique Barboza
2023-05-16 23:38 ` Alistair Francis
2023-05-03 8:56 ` [PATCH 04/11] tcg/riscv: Support ADD.UW, SEXT.B, SEXT.H, ZEXT.H from Zba+Zbb Richard Henderson
2023-05-08 12:39 ` Daniel Henrique Barboza
2023-05-16 23:40 ` Alistair Francis
2023-05-03 8:56 ` [PATCH 05/11] tcg/riscv: Use ADD.UW for guest address generation Richard Henderson
2023-05-08 12:43 ` Daniel Henrique Barboza
2023-05-16 23:43 ` Alistair Francis
2023-05-03 8:56 ` [PATCH 06/11] tcg/riscv: Support rotates from Zbb Richard Henderson
2023-05-08 12:44 ` Daniel Henrique Barboza [this message]
2023-05-16 23:48 ` Alistair Francis
2023-05-03 8:56 ` [PATCH 07/11] tcg/riscv: Support REV8 " Richard Henderson
2023-05-08 12:45 ` Daniel Henrique Barboza
2023-05-16 23:50 ` Alistair Francis
2023-05-03 8:56 ` [PATCH 08/11] tcg/riscv: Support CPOP " Richard Henderson
2023-05-08 12:45 ` Daniel Henrique Barboza
2023-05-16 23:50 ` Alistair Francis
2023-05-03 8:56 ` [PATCH 09/11] tcg/riscv: Improve setcond expansion Richard Henderson
2023-05-08 12:46 ` Daniel Henrique Barboza
2023-05-17 0:16 ` Alistair Francis
2023-05-03 8:56 ` [PATCH 10/11] tcg/riscv: Implement movcond Richard Henderson
2023-05-08 12:47 ` Daniel Henrique Barboza
2023-05-17 0:19 ` Alistair Francis
2023-05-03 8:56 ` [PATCH 11/11] tcg/riscv: Support CTZ, CLZ from Zbb Richard Henderson
2023-05-08 12:47 ` Daniel Henrique Barboza
2023-05-17 1:47 ` Alistair Francis
2023-05-08 12:53 ` [PATCH 00/11] tcg/riscv: Support for Zba, Zbb, Zicond extensions Daniel Henrique Barboza
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