From: Sven Eckelmann <sven@narfation.org>
To: Anilkumar Kolli <akolli@codeaurora.org>
Cc: ath11k@lists.infradead.org,
Manivannan Sadhasivam <manivannan.sadhasivam@linaro.org>,
linux-wireless@vger.kernel.org, devicetree@vger.kernel.org,
robh@kernel.org
Subject: Re: [PATCH v4 2/2] ath11k: Use reserved host DDR addresses from DT for PCI devices
Date: Mon, 22 Nov 2021 08:50:00 +0100 [thread overview]
Message-ID: <2802525.9g7TWp2vRq@ripper> (raw)
In-Reply-To: <a6f4fd77b1f8729368fee13a435fe652@codeaurora.org>
On Monday, 22 November 2021 07:12:27 CET Anilkumar Kolli wrote:
[...]
> >> + start = reg[0] + reg[1];
> >> + size = reg[2] + reg[3];
> >
> > See my messages for v2 [1] and v3 [2]
> >
> >
> Thanks for the review,
>
> Here addresses are always within 32-bit.
> so I will change the API to read only 2 integers and update start
> addresss and size.
The size of address and size depends on the reserved-memory node - not the
qcn9074 node. So please don't make such assumptions in your code.
Kind regards,
Sven
--
ath11k mailing list
ath11k@lists.infradead.org
http://lists.infradead.org/mailman/listinfo/ath11k
WARNING: multiple messages have this Message-ID (diff)
From: Sven Eckelmann <sven@narfation.org>
To: Anilkumar Kolli <akolli@codeaurora.org>
Cc: ath11k@lists.infradead.org,
Manivannan Sadhasivam <manivannan.sadhasivam@linaro.org>,
linux-wireless@vger.kernel.org, devicetree@vger.kernel.org,
robh@kernel.org
Subject: Re: [PATCH v4 2/2] ath11k: Use reserved host DDR addresses from DT for PCI devices
Date: Mon, 22 Nov 2021 08:50:00 +0100 [thread overview]
Message-ID: <2802525.9g7TWp2vRq@ripper> (raw)
In-Reply-To: <a6f4fd77b1f8729368fee13a435fe652@codeaurora.org>
On Monday, 22 November 2021 07:12:27 CET Anilkumar Kolli wrote:
[...]
> >> + start = reg[0] + reg[1];
> >> + size = reg[2] + reg[3];
> >
> > See my messages for v2 [1] and v3 [2]
> >
> >
> Thanks for the review,
>
> Here addresses are always within 32-bit.
> so I will change the API to read only 2 integers and update start
> addresss and size.
The size of address and size depends on the reserved-memory node - not the
qcn9074 node. So please don't make such assumptions in your code.
Kind regards,
Sven
next prev parent reply other threads:[~2021-11-22 7:58 UTC|newest]
Thread overview: 12+ messages / expand[flat|nested] mbox.gz Atom feed top
2021-11-21 14:22 [PATCH v4 1/2] dt: bindings: add new DT entry for ath11k PCI device support Anilkumar Kolli
2021-11-21 14:22 ` Anilkumar Kolli
2021-11-21 14:22 ` [PATCH v4 2/2] ath11k: Use reserved host DDR addresses from DT for PCI devices Anilkumar Kolli
2021-11-21 14:22 ` Anilkumar Kolli
2021-11-21 14:45 ` Sven Eckelmann
2021-11-21 14:45 ` Sven Eckelmann
2021-11-22 6:12 ` Anilkumar Kolli
2021-11-22 6:12 ` Anilkumar Kolli
2021-11-22 7:50 ` Sven Eckelmann [this message]
2021-11-22 7:50 ` Sven Eckelmann
2021-11-23 10:39 ` Anilkumar Kolli
2021-11-23 10:39 ` Anilkumar Kolli
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