[PATCH v2 0/6] improve FriendlyELEC NanoPC-T6 a bit

[PATCH v2 0/6] improve FriendlyELEC NanoPC-T6 a bit

[Marcin Juszkiewicz]

This series updates FriendlyELEC NanoPC-T6 DeviceTree a bit:

- enable USB 2.0 ports on NanoPC-T6 LTS
- enable USB-C port (one orientation only)
- enable Mali GPU
- enable IR receiver (not tested)
- enable SPI flash (present on LTS, optional on non-LTS)

Signed-off-by: Marcin Juszkiewicz <marcin.juszkiewicz@linaro.org>

---
Changes in v2:
- merged changes into NanoPC-T6 dts file
- add SPI flash pinctl for SPI M1
- enable SPI on NanoPC-T6 LTS
- enable USB-C port (one orientation only)
- enable Mali GPI
- enable IR receiver (not tested)
- Link to v1: https://lore.kernel.org/r/20240820-friendlyelec-nanopc-t6-lts-v1-1-da1273c3e08e@juszkiewicz.com.pl

---
Marcin Juszkiewicz (6):
      arm64: dts: rockchip: enable USB 2.0 on NanoPC-T6 LTS
      arm64: dts: rockchip: define pinctl for SPI M1
      arm64: dts: rockchip: enable SPI flash on NanoPC-T6 LTS
      arm64: dts: rockchip: add IR-receiver to NanoPC-T6
      arm64: dts: rockchip: enable GPU on NanoPC-T6
      arm64: dts: rockchip: enable USB-C on NanoPC-T6

 .../boot/dts/rockchip/rk3588-base-pinctrl.dtsi     |  17 +++
 arch/arm64/boot/dts/rockchip/rk3588-nanopc-t6.dts  | 139 ++++++++++++++++++++-
 2 files changed, 155 insertions(+), 1 deletion(-)
---
base-commit: 6e4436539ae182dc86d57d13849862bcafaa4709
change-id: 20240820-friendlyelec-nanopc-t6-lts-00c7678c3bd7

Best regards,
-- 
Marcin Juszkiewicz <marcin.juszkiewicz@linaro.org>


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[PATCH v2 1/6] arm64: dts: rockchip: enable USB 2.0 on NanoPC-T6 LTS

[Marcin Juszkiewicz]

FriendlyELEC introduced new version of NanoPC-T6 SBC.

MiniPCIe slot got removed and USB 2.0 configuration has changed.
There are two external accessible ports and two ports on internal
header.

There is on-board USB hub which provides:
- one external connector (bottom one)
- two internal ports on pin header
- m.2 E port

Top USB 2.0 connector comes directly from SoC.

Signed-off-by: Marcin Juszkiewicz <marcin.juszkiewicz@linaro.org>
---
 arch/arm64/boot/dts/rockchip/rk3588-nanopc-t6.dts | 35 +++++++++++++++++++++++
 1 file changed, 35 insertions(+)

diff --git a/arch/arm64/boot/dts/rockchip/rk3588-nanopc-t6.dts b/arch/arm64/boot/dts/rockchip/rk3588-nanopc-t6.dts
index ad8e36a339dc..bf2c4427ad74 100644
--- a/arch/arm64/boot/dts/rockchip/rk3588-nanopc-t6.dts
+++ b/arch/arm64/boot/dts/rockchip/rk3588-nanopc-t6.dts
@@ -182,6 +182,20 @@ vdd_4g_3v3: vdd-4g-3v3-regulator {
 		regulator-max-microvolt = <3300000>;
 		vin-supply = <&vcc5v0_sys>;
 	};
+
+	vcc5v0_usb20_host: vcc5v0-usb20-host-regulator {
+		compatible = "regulator-fixed";
+		enable-active-high;
+		gpio = <&gpio1 RK_PA4 GPIO_ACTIVE_HIGH>;
+		pinctrl-0 = <&usb20_host_pwren>;
+		pinctrl-names = "default";
+		regulator-always-on;
+		regulator-boot-on;
+		regulator-max-microvolt = <5000000>;
+		regulator-min-microvolt = <5000000>;
+		regulator-name = "vcc5v0_usb20_host";
+		vin-supply = <&vcc5v0_sys>;
+	};
 };
 
 &combphy0_ps {
@@ -535,6 +549,10 @@ typec5v_pwren: typec5v-pwren {
 			rockchip,pins = <1 RK_PD2 RK_FUNC_GPIO &pcfg_pull_none>;
 		};
 
+		usb20_host_pwren: usb20-host-pwren {
+			rockchip,pins = <1 RK_PA4 RK_FUNC_GPIO &pcfg_pull_none>;
+		};
+
 		usbc0_int: usbc0-int {
 			rockchip,pins = <0 RK_PD3 RK_FUNC_GPIO &pcfg_pull_up>;
 		};
@@ -911,6 +929,14 @@ &uart2 {
 	status = "okay";
 };
 
+&u2phy1 {
+	status = "okay";
+};
+
+&u2phy1_otg {
+	status = "okay";
+};
+
 &u2phy2_host {
 	phy-supply = <&vdd_4g_3v3>;
 	status = "okay";
@@ -928,6 +954,10 @@ &u2phy3 {
 	status = "okay";
 };
 
+&usbdp_phy1 {
+	status = "okay";
+};
+
 &usb_host0_ehci {
 	status = "okay";
 };
@@ -943,3 +973,8 @@ &usb_host1_ehci {
 &usb_host1_ohci {
 	status = "okay";
 };
+
+&usb_host1_xhci {
+	dr_mode = "host";
+	status = "okay";
+};

-- 
2.46.0


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Re: [PATCH v2 1/6] arm64: dts: rockchip: enable USB 2.0 on NanoPC-T6 LTS

[Heiko Stübner]

Am Mittwoch, 21. August 2024, 10:25:30 CEST schrieb Marcin Juszkiewicz:
> FriendlyELEC introduced new version of NanoPC-T6 SBC.

If this change is specific to the new "LTS" board variant, why is it in
the main board dts now?

I.e. with this change you enable it on _all_ NanoPC-T6 boards, even the
ones without those components?


Heiko


> MiniPCIe slot got removed and USB 2.0 configuration has changed.
> There are two external accessible ports and two ports on internal
> header.
> 
> There is on-board USB hub which provides:
> - one external connector (bottom one)
> - two internal ports on pin header
> - m.2 E port
> 
> Top USB 2.0 connector comes directly from SoC.
> 
> Signed-off-by: Marcin Juszkiewicz <marcin.juszkiewicz@linaro.org>
> ---
>  arch/arm64/boot/dts/rockchip/rk3588-nanopc-t6.dts | 35 +++++++++++++++++++++++
>  1 file changed, 35 insertions(+)
> 
> diff --git a/arch/arm64/boot/dts/rockchip/rk3588-nanopc-t6.dts b/arch/arm64/boot/dts/rockchip/rk3588-nanopc-t6.dts
> index ad8e36a339dc..bf2c4427ad74 100644
> --- a/arch/arm64/boot/dts/rockchip/rk3588-nanopc-t6.dts
> +++ b/arch/arm64/boot/dts/rockchip/rk3588-nanopc-t6.dts
> @@ -182,6 +182,20 @@ vdd_4g_3v3: vdd-4g-3v3-regulator {
>  		regulator-max-microvolt = <3300000>;
>  		vin-supply = <&vcc5v0_sys>;
>  	};
> +
> +	vcc5v0_usb20_host: vcc5v0-usb20-host-regulator {
> +		compatible = "regulator-fixed";
> +		enable-active-high;
> +		gpio = <&gpio1 RK_PA4 GPIO_ACTIVE_HIGH>;
> +		pinctrl-0 = <&usb20_host_pwren>;
> +		pinctrl-names = "default";
> +		regulator-always-on;
> +		regulator-boot-on;
> +		regulator-max-microvolt = <5000000>;
> +		regulator-min-microvolt = <5000000>;
> +		regulator-name = "vcc5v0_usb20_host";
> +		vin-supply = <&vcc5v0_sys>;
> +	};
>  };
>  
>  &combphy0_ps {
> @@ -535,6 +549,10 @@ typec5v_pwren: typec5v-pwren {
>  			rockchip,pins = <1 RK_PD2 RK_FUNC_GPIO &pcfg_pull_none>;
>  		};
>  
> +		usb20_host_pwren: usb20-host-pwren {
> +			rockchip,pins = <1 RK_PA4 RK_FUNC_GPIO &pcfg_pull_none>;
> +		};
> +
>  		usbc0_int: usbc0-int {
>  			rockchip,pins = <0 RK_PD3 RK_FUNC_GPIO &pcfg_pull_up>;
>  		};
> @@ -911,6 +929,14 @@ &uart2 {
>  	status = "okay";
>  };
>  
> +&u2phy1 {
> +	status = "okay";
> +};
> +
> +&u2phy1_otg {
> +	status = "okay";
> +};
> +
>  &u2phy2_host {
>  	phy-supply = <&vdd_4g_3v3>;
>  	status = "okay";
> @@ -928,6 +954,10 @@ &u2phy3 {
>  	status = "okay";
>  };
>  
> +&usbdp_phy1 {
> +	status = "okay";
> +};
> +
>  &usb_host0_ehci {
>  	status = "okay";
>  };
> @@ -943,3 +973,8 @@ &usb_host1_ehci {
>  &usb_host1_ohci {
>  	status = "okay";
>  };
> +
> +&usb_host1_xhci {
> +	dr_mode = "host";
> +	status = "okay";
> +};
> 
> 





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Re: [PATCH v2 1/6] arm64: dts: rockchip: enable USB 2.0 on NanoPC-T6 LTS

[Marcin Juszkiewicz]

On 21.08.2024 10:58, Heiko Stübner wrote:
> Am Mittwoch, 21. August 2024, 10:25:30 CEST schrieb Marcin Juszkiewicz:
>> FriendlyELEC introduced new version of NanoPC-T6 SBC.
> 
> If this change is specific to the new "LTS" board variant, why is it in
> the main board dts now?

I have not seen firmware builds which handle 'is it LTS or not' version 
of board.

> I.e. with this change you enable it on _all_ NanoPC-T6 boards, even the
> ones without those components?

The non-LTS version has usb20_host_pwren line not connected. So enabling 
it does not affect the board. Similar to 4g_lte_pwren line which is 
present on NanoPC-T6 non-LTS and not connected on LTS one.

Looks like vendor took care to keep both versions of board to work with 
one DT.

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Re: [PATCH v2 1/6] arm64: dts: rockchip: enable USB 2.0 on NanoPC-T6 LTS

[Dragan Simic]

Hello Marcin,

On 2024-08-21 11:14, Marcin Juszkiewicz wrote:
> On 21.08.2024 10:58, Heiko Stübner wrote:
>> Am Mittwoch, 21. August 2024, 10:25:30 CEST schrieb Marcin 
>> Juszkiewicz:
>>> FriendlyELEC introduced new version of NanoPC-T6 SBC.
>> 
>> If this change is specific to the new "LTS" board variant, why is it 
>> in
>> the main board dts now?
> 
> I have not seen firmware builds which handle 'is it LTS or not'
> version of board.
> 
>> I.e. with this change you enable it on _all_ NanoPC-T6 boards, even 
>> the
>> ones without those components?
> 
> The non-LTS version has usb20_host_pwren line not connected. So
> enabling it does not affect the board. Similar to 4g_lte_pwren line
> which is present on NanoPC-T6 non-LTS and not connected on LTS one.
> 
> Looks like vendor took care to keep both versions of board to work with 
> one DT.

I'd suggest that you introduce a new board dts file, specific to the LTS
version of this board.  The DT describes actual hardware, so it should 
be
as strict and as specific as possible.

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[PATCH v2 2/6] arm64: dts: rockchip: define pinctl for SPI M1

[Marcin Juszkiewicz]

FriendlyELEC NanoPC-T6 has 32MB of SPI flash connected to SPI M1 lines
(always present on LTS version, optional on non-LTS one).

Signed-off-by: Marcin Juszkiewicz <marcin.juszkiewicz@linaro.org>
---
 arch/arm64/boot/dts/rockchip/rk3588-base-pinctrl.dtsi | 17 +++++++++++++++++
 1 file changed, 17 insertions(+)

diff --git a/arch/arm64/boot/dts/rockchip/rk3588-base-pinctrl.dtsi b/arch/arm64/boot/dts/rockchip/rk3588-base-pinctrl.dtsi
index 30db12c4fc82..75d5816b6fa4 100644
--- a/arch/arm64/boot/dts/rockchip/rk3588-base-pinctrl.dtsi
+++ b/arch/arm64/boot/dts/rockchip/rk3588-base-pinctrl.dtsi
@@ -407,6 +407,23 @@ fspim0_cs1: fspim0-cs1 {
 				<2 RK_PD7 2 &pcfg_pull_up_drv_level_2>;
 		};
 
+		/omit-if-no-ref/
+		fspim1_pins: fspim1-pins {
+			rockchip,pins =
+				/* fspi_clk_m1 */
+				<2 RK_PB3 5 &pcfg_pull_up_drv_level_2>,
+				/* fspi_cs0n_m1 */
+				<2 RK_PB4 2 &pcfg_pull_up_drv_level_2>,
+				/* fspi_d0_m1 */
+				<2 RK_PA6 5 &pcfg_pull_up_drv_level_2>,
+				/* fspi_d1_m1 */
+				<2 RK_PA7 5 &pcfg_pull_up_drv_level_2>,
+				/* fspi_d2_m1 */
+				<2 RK_PB0 5 &pcfg_pull_up_drv_level_2>,
+				/* fspi_d3_m1 */
+				<2 RK_PB1 5 &pcfg_pull_up_drv_level_2>;
+		};
+
 		/omit-if-no-ref/
 		fspim2_pins: fspim2-pins {
 			rockchip,pins =

-- 
2.46.0


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[PATCH v2 3/6] arm64: dts: rockchip: enable SPI flash on NanoPC-T6 LTS

[Marcin Juszkiewicz]

FriendlyELEC NanoPC-T6 LTS has 32MB of SPI flash on-board. On non-LTS
boards this is optional chip.

Signed-off-by: Marcin Juszkiewicz <marcin.juszkiewicz@linaro.org>
---
 arch/arm64/boot/dts/rockchip/rk3588-nanopc-t6.dts | 14 ++++++++++++++
 1 file changed, 14 insertions(+)

diff --git a/arch/arm64/boot/dts/rockchip/rk3588-nanopc-t6.dts b/arch/arm64/boot/dts/rockchip/rk3588-nanopc-t6.dts
index bf2c4427ad74..0f9df64dc1b1 100644
--- a/arch/arm64/boot/dts/rockchip/rk3588-nanopc-t6.dts
+++ b/arch/arm64/boot/dts/rockchip/rk3588-nanopc-t6.dts
@@ -594,6 +594,20 @@ &sdmmc {
 	status = "okay";
 };
 
+&sfc {
+	pinctrl-names = "default";
+	pinctrl-0 = <&fspim1_pins>;
+	status = "okay";
+
+	flash@0 {
+		compatible = "jedec,spi-nor";
+		reg = <0>;
+		spi-max-frequency = <104000000>;
+		spi-rx-bus-width = <4>;
+		spi-tx-bus-width = <1>;
+	};
+};
+
 &spi2 {
 	status = "okay";
 	assigned-clocks = <&cru CLK_SPI2>;

-- 
2.46.0


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Re: [PATCH v2 3/6] arm64: dts: rockchip: enable SPI flash on NanoPC-T6 LTS

[Heiko Stübner]

Am Mittwoch, 21. August 2024, 10:25:32 CEST schrieb Marcin Juszkiewicz:
> FriendlyELEC NanoPC-T6 LTS has 32MB of SPI flash on-board. On non-LTS
> boards this is optional chip.
> 
> Signed-off-by: Marcin Juszkiewicz <marcin.juszkiewicz@linaro.org>
> ---
>  arch/arm64/boot/dts/rockchip/rk3588-nanopc-t6.dts | 14 ++++++++++++++
>  1 file changed, 14 insertions(+)
> 
> diff --git a/arch/arm64/boot/dts/rockchip/rk3588-nanopc-t6.dts b/arch/arm64/boot/dts/rockchip/rk3588-nanopc-t6.dts
> index bf2c4427ad74..0f9df64dc1b1 100644
> --- a/arch/arm64/boot/dts/rockchip/rk3588-nanopc-t6.dts
> +++ b/arch/arm64/boot/dts/rockchip/rk3588-nanopc-t6.dts
> @@ -594,6 +594,20 @@ &sdmmc {
>  	status = "okay";
>  };
>  
> +&sfc {
> +	pinctrl-names = "default";
> +	pinctrl-0 = <&fspim1_pins>;
> +	status = "okay";
> +
> +	flash@0 {
> +		compatible = "jedec,spi-nor";
> +		reg = <0>;
> +		spi-max-frequency = <104000000>;
> +		spi-rx-bus-width = <4>;
> +		spi-tx-bus-width = <1>;
> +	};
> +};
> +

same question as patch1. You enable this also on the non-LTS boards now
that don't have this flash chip?



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Re: [PATCH v2 3/6] arm64: dts: rockchip: enable SPI flash on NanoPC-T6 LTS

[Marcin Juszkiewicz]

On 21.08.2024 10:59, Heiko Stübner wrote:
> Am Mittwoch, 21. August 2024, 10:25:32 CEST schrieb Marcin Juszkiewicz:
>> FriendlyELEC NanoPC-T6 LTS has 32MB of SPI flash on-board. On non-LTS
>> boards this is optional chip.
>>
>> Signed-off-by: Marcin Juszkiewicz <marcin.juszkiewicz@linaro.org>
>> ---
>>   arch/arm64/boot/dts/rockchip/rk3588-nanopc-t6.dts | 14 ++++++++++++++
>>   1 file changed, 14 insertions(+)
>>
>> diff --git a/arch/arm64/boot/dts/rockchip/rk3588-nanopc-t6.dts b/arch/arm64/boot/dts/rockchip/rk3588-nanopc-t6.dts
>> index bf2c4427ad74..0f9df64dc1b1 100644
>> --- a/arch/arm64/boot/dts/rockchip/rk3588-nanopc-t6.dts
>> +++ b/arch/arm64/boot/dts/rockchip/rk3588-nanopc-t6.dts
>> @@ -594,6 +594,20 @@ &sdmmc {
>>   	status = "okay";
>>   };
>>   
>> +&sfc {
>> +	pinctrl-names = "default";
>> +	pinctrl-0 = <&fspim1_pins>;
>> +	status = "okay";
>> +
>> +	flash@0 {
>> +		compatible = "jedec,spi-nor";
>> +		reg = <0>;
>> +		spi-max-frequency = <104000000>;
>> +		spi-rx-bus-width = <4>;
>> +		spi-tx-bus-width = <1>;
>> +	};
>> +};
>> +
> 
> same question as patch1. You enable this also on the non-LTS boards now
> that don't have this flash chip?

non-LTS version of board has a space for this SPI chip so it can be 
populated either by vendor or by user. Any OS/firmware which touch SPI 
flash should (IMHO) check is chip present - DT tells where to look.




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Re: [PATCH v2 3/6] arm64: dts: rockchip: enable SPI flash on NanoPC-T6 LTS

[Dragan Simic]

On 2024-08-21 11:17, Marcin Juszkiewicz wrote:
> On 21.08.2024 10:59, Heiko Stübner wrote:
>> Am Mittwoch, 21. August 2024, 10:25:32 CEST schrieb Marcin 
>> Juszkiewicz:
>>> FriendlyELEC NanoPC-T6 LTS has 32MB of SPI flash on-board. On non-LTS
>>> boards this is optional chip.
>>> 
>>> Signed-off-by: Marcin Juszkiewicz <marcin.juszkiewicz@linaro.org>
>>> ---
>>>   arch/arm64/boot/dts/rockchip/rk3588-nanopc-t6.dts | 14 
>>> ++++++++++++++
>>>   1 file changed, 14 insertions(+)
>>> 
>>> diff --git a/arch/arm64/boot/dts/rockchip/rk3588-nanopc-t6.dts 
>>> b/arch/arm64/boot/dts/rockchip/rk3588-nanopc-t6.dts
>>> index bf2c4427ad74..0f9df64dc1b1 100644
>>> --- a/arch/arm64/boot/dts/rockchip/rk3588-nanopc-t6.dts
>>> +++ b/arch/arm64/boot/dts/rockchip/rk3588-nanopc-t6.dts
>>> @@ -594,6 +594,20 @@ &sdmmc {
>>>   	status = "okay";
>>>   };
>>>   +&sfc {
>>> +	pinctrl-names = "default";
>>> +	pinctrl-0 = <&fspim1_pins>;
>>> +	status = "okay";
>>> +
>>> +	flash@0 {
>>> +		compatible = "jedec,spi-nor";
>>> +		reg = <0>;
>>> +		spi-max-frequency = <104000000>;
>>> +		spi-rx-bus-width = <4>;
>>> +		spi-tx-bus-width = <1>;
>>> +	};
>>> +};
>>> +
>> 
>> same question as patch1. You enable this also on the non-LTS boards 
>> now
>> that don't have this flash chip?
> 
> non-LTS version of board has a space for this SPI chip so it can be
> populated either by vendor or by user. Any OS/firmware which touch SPI
> flash should (IMHO) check is chip present - DT tells where to look.

Ah, so it's like the Pine64 Rock64, for example, [1] which also comes
with unpopulated pads for the SPI chip.  In that case, I'd agree that
adding the definitions to the non-LTS DT is fine.

[1] 
https://git.kernel.org/pub/scm/linux/kernel/git/torvalds/linux.git/tree/arch/arm64/boot/dts/rockchip/rk3328-rock64.dts?h=v6.11-rc4#n338

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[PATCH v2 4/6] arm64: dts: rockchip: add IR-receiver to NanoPC-T6

[Marcin Juszkiewicz]

FriendlyELEC NanoPC-T6 has IR receiver connected to PWM3_IR_M0 line
which ends as GPIO0_D4.

Signed-off-by: Marcin Juszkiewicz <marcin.juszkiewicz@linaro.org>
---
 arch/arm64/boot/dts/rockchip/rk3588-nanopc-t6.dts | 14 +++++++++++++-
 1 file changed, 13 insertions(+), 1 deletion(-)

diff --git a/arch/arm64/boot/dts/rockchip/rk3588-nanopc-t6.dts b/arch/arm64/boot/dts/rockchip/rk3588-nanopc-t6.dts
index 0f9df64dc1b1..57a9cf3da178 100644
--- a/arch/arm64/boot/dts/rockchip/rk3588-nanopc-t6.dts
+++ b/arch/arm64/boot/dts/rockchip/rk3588-nanopc-t6.dts
@@ -25,6 +25,11 @@ chosen {
 		stdout-path = "serial2:1500000n8";
 	};
 
+	ir-receiver {
+		compatible = "gpio-ir-receiver";
+		gpios = <&gpio0 RK_PD4 GPIO_ACTIVE_LOW>;
+	};
+
 	leds {
 		compatible = "gpio-leds";
 
@@ -254,7 +259,7 @@ &gpio0 {
 			  "HEADER_10", "HEADER_08", "HEADER_32", "",
 			  /* GPIO0 D0-D7 */
 			  "", "", "", "",
-			  "", "", "", "";
+			  "IR receiver [PWM3_IR_M0]", "", "", "";
 };
 
 &gpio1 {
@@ -564,6 +569,13 @@ &pwm1 {
 	status = "okay";
 };
 
+/* Connected to IR Receiver */
+&pwm3 {
+	pinctrl-names = "default";
+	pinctrl-0 = <&pwm3m0_pins>;
+	status = "okay";
+};
+
 &saradc {
 	vref-supply = <&avcc_1v8_s0>;
 	status = "okay";

-- 
2.46.0


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[PATCH v2 5/6] arm64: dts: rockchip: enable GPU on NanoPC-T6

[Marcin Juszkiewicz]

Enable the Mali GPU on FriendlyELEC NanoPC-T6

Signed-off-by: Marcin Juszkiewicz <marcin.juszkiewicz@linaro.org>
---
 arch/arm64/boot/dts/rockchip/rk3588-nanopc-t6.dts | 5 +++++
 1 file changed, 5 insertions(+)

diff --git a/arch/arm64/boot/dts/rockchip/rk3588-nanopc-t6.dts b/arch/arm64/boot/dts/rockchip/rk3588-nanopc-t6.dts
index 57a9cf3da178..61b307371d4e 100644
--- a/arch/arm64/boot/dts/rockchip/rk3588-nanopc-t6.dts
+++ b/arch/arm64/boot/dts/rockchip/rk3588-nanopc-t6.dts
@@ -322,6 +322,11 @@ &gpio4 {
 			  "", "", "", "";
 };
 
+&gpu {
+	mali-supply = <&vdd_gpu_s0>;
+	status = "okay";
+};
+
 &i2c0 {
 	pinctrl-names = "default";
 	pinctrl-0 = <&i2c0m2_xfer>;

-- 
2.46.0


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[PATCH v2 6/6] arm64: dts: rockchip: enable USB-C on NanoPC-T6

[Marcin Juszkiewicz]

Enable the USB-C port on FriendlyELEC NanoPC-T6.

Works one way so far but still better than before.

Signed-off-by: Marcin Juszkiewicz <marcin.juszkiewicz@linaro.org>
---
 arch/arm64/boot/dts/rockchip/rk3588-nanopc-t6.dts | 71 +++++++++++++++++++++++
 1 file changed, 71 insertions(+)

diff --git a/arch/arm64/boot/dts/rockchip/rk3588-nanopc-t6.dts b/arch/arm64/boot/dts/rockchip/rk3588-nanopc-t6.dts
index 61b307371d4e..c0d498486657 100644
--- a/arch/arm64/boot/dts/rockchip/rk3588-nanopc-t6.dts
+++ b/arch/arm64/boot/dts/rockchip/rk3588-nanopc-t6.dts
@@ -135,6 +135,8 @@ vbus5v0_typec: vbus5v0-typec-regulator {
 		gpio = <&gpio1 RK_PD2 GPIO_ACTIVE_HIGH>;
 		pinctrl-names = "default";
 		pinctrl-0 = <&typec5v_pwren>;
+		regulator-always-on;
+		regulator-boot-on;
 		regulator-name = "vbus5v0_typec";
 		regulator-min-microvolt = <5000000>;
 		regulator-max-microvolt = <5000000>;
@@ -410,6 +412,32 @@ connector {
 			source-pdos = <PDO_FIXED(5000, 2000, PDO_FIXED_USB_COMM)>;
 			sink-pdos = <PDO_FIXED(5000, 3000, PDO_FIXED_USB_COMM)>;
 			op-sink-microwatt = <1000000>;
+
+			ports {
+				#address-cells = <1>;
+				#size-cells = <0>;
+
+				port@0 {
+					reg = <0>;
+					usbc0_hs: endpoint {
+						remote-endpoint = <&usb_host0_xhci_drd_sw>;
+					};
+				};
+
+				port@1 {
+					reg = <1>;
+					usbc0_ss: endpoint {
+						remote-endpoint = <&usbdp_phy0_typec_ss>;
+					};
+				};
+
+				port@2 {
+					reg = <2>;
+					usbc0_sbu: endpoint {
+						remote-endpoint = <&usbdp_phy0_typec_sbu>;
+					};
+				};
+			};
 		};
 	};
 
@@ -960,6 +988,14 @@ &uart2 {
 	status = "okay";
 };
 
+&u2phy0 {
+	status = "okay";
+};
+
+&u2phy0_otg {
+	status = "okay";
+};
+
 &u2phy1 {
 	status = "okay";
 };
@@ -985,6 +1021,29 @@ &u2phy3 {
 	status = "okay";
 };
 
+&usbdp_phy0 {
+	mode-switch;
+	orientation-switch;
+	sbu1-dc-gpios = <&gpio4 RK_PA6 GPIO_ACTIVE_HIGH>;
+	sbu2-dc-gpios = <&gpio4 RK_PA7 GPIO_ACTIVE_HIGH>;
+	status = "okay";
+
+	port {
+		#address-cells = <1>;
+		#size-cells = <0>;
+
+		usbdp_phy0_typec_ss: endpoint@0 {
+			reg = <0>;
+			remote-endpoint = <&usbc0_ss>;
+		};
+
+		usbdp_phy0_typec_sbu: endpoint@1 {
+			reg = <1>;
+			remote-endpoint = <&usbc0_sbu>;
+		};
+	};
+};
+
 &usbdp_phy1 {
 	status = "okay";
 };
@@ -997,6 +1056,18 @@ &usb_host0_ohci {
 	status = "okay";
 };
 
+&usb_host0_xhci {
+	dr_mode = "host";
+	status = "okay";
+	usb-role-switch;
+
+	port {
+		usb_host0_xhci_drd_sw: endpoint {
+			remote-endpoint = <&usbc0_hs>;
+		};
+	};
+};
+
 &usb_host1_ehci {
 	status = "okay";
 };

-- 
2.46.0


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