From: "Philippe Mathieu-Daudé" <philmd@linaro.org>
To: qemu-devel@nongnu.org
Cc: "Aleksandar Rikalo" <arikalo@gmail.com>,
"Jiaxun Yang" <jiaxun.yang@flygoat.com>,
"Aurelien Jarno" <aurelien@aurel32.net>,
"Philippe Mathieu-Daudé" <f4bug@amsat.org>,
"Richard Henderson" <richard.henderson@linaro.org>
Subject: Re: [PATCH v2 2/6] target/mips: Introduce decode tree bindings for nanoMIPS ISA
Date: Tue, 26 Nov 2024 14:20:43 +0100 [thread overview]
Message-ID: <2be6cd2d-44c6-45ab-bfce-c5ae31dc63ab@linaro.org> (raw)
In-Reply-To: <20241112172022.88348-3-philmd@linaro.org>
On 12/11/24 18:20, Philippe Mathieu-Daudé wrote:
> From: Philippe Mathieu-Daudé <f4bug@amsat.org>
>
> Introduce the nanoMIPS decodetree configs for the 16-bit
> and 32-bit instructions.
>
> Signed-off-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
> Reviewed-by: Aleksandar Rikalo <arikalo@gmail.com>
> Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
> Signed-off-by: Philippe Mathieu-Daudé <philmd@linaro.org>
> ---
> target/mips/tcg/translate.h | 2 ++
> target/mips/tcg/nanomips16.decode | 8 ++++++++
> target/mips/tcg/nanomips32.decode | 8 ++++++++
> target/mips/tcg/nanomips_translate.c | 14 ++++++++++++++
> target/mips/tcg/nanomips_translate.c.inc | 7 +++++++
> target/mips/tcg/meson.build | 3 +++
> 6 files changed, 42 insertions(+)
> create mode 100644 target/mips/tcg/nanomips16.decode
> create mode 100644 target/mips/tcg/nanomips32.decode
> create mode 100644 target/mips/tcg/nanomips_translate.c
> diff --git a/target/mips/tcg/nanomips_translate.c b/target/mips/tcg/nanomips_translate.c
> new file mode 100644
> index 0000000000..c148c13ed9
> --- /dev/null
> +++ b/target/mips/tcg/nanomips_translate.c
> @@ -0,0 +1,14 @@
> +/*
> + * MIPS emulation for QEMU - nanoMIPS translation routines
> + *
> + * Copyright (c) 2021 Philippe Mathieu-Daudé <f4bug@amsat.org>
> + *
> + * SPDX-License-Identifier: LGPL-2.1-or-later
> + */
> +
> +#include "qemu/osdep.h"
> +#include "translate.h"
> +
> +/* Include the auto-generated decoders. */
> +#include "decode-nanomips16.c.inc"
> +#include "decode-nanomips32.c.inc"
> diff --git a/target/mips/tcg/nanomips_translate.c.inc b/target/mips/tcg/nanomips_translate.c.inc
> index 1e274143bb..e401b92bfd 100644
> --- a/target/mips/tcg/nanomips_translate.c.inc
> +++ b/target/mips/tcg/nanomips_translate.c.inc
> @@ -4482,6 +4482,13 @@ static int decode_isa_nanomips(CPUMIPSState *env, DisasContext *ctx)
> return 2;
> }
>
> + if (decode_isa_nanomips16(ctx, ctx->opcode)) {
> + return 2;
> + }
> + if (decode_isa_nanomips32(ctx, ctx->opcode)) {
This call is incorrect, the caller previously called
translator_lduw() so ctx->opcode is incomplete.
> + return 4;
> + }
Discarding this series for now.
next prev parent reply other threads:[~2024-11-26 13:21 UTC|newest]
Thread overview: 15+ messages / expand[flat|nested] mbox.gz Atom feed top
2024-11-12 17:20 [PATCH v2 0/6] target/mips: Convert nanoMIPS LSA opcode to decodetree Philippe Mathieu-Daudé
2024-11-12 17:20 ` [PATCH v2 1/6] target/mips: Introduce decode tree bindings for microMIPS ISA Philippe Mathieu-Daudé
2024-11-12 18:14 ` Richard Henderson
2024-11-26 13:19 ` Philippe Mathieu-Daudé
2024-11-12 17:20 ` [PATCH v2 2/6] target/mips: Introduce decode tree bindings for nanoMIPS ISA Philippe Mathieu-Daudé
2024-11-26 13:20 ` Philippe Mathieu-Daudé [this message]
2024-11-12 17:20 ` [PATCH v2 3/6] target/mips: Have gen_[d]lsa() callers add 1 to shift amount argument Philippe Mathieu-Daudé
2024-11-12 18:16 ` Richard Henderson
2024-11-12 17:20 ` [PATCH v2 4/6] target/mips: Decode LSA shift amount using decodetree function Philippe Mathieu-Daudé
2024-11-12 18:16 ` Richard Henderson
2024-11-12 17:20 ` [PATCH v2 5/6] target/mips: Convert microMIPS LSA opcode to decodetree Philippe Mathieu-Daudé
2024-11-12 18:17 ` Richard Henderson
2024-11-12 17:20 ` [PATCH v2 6/6] target/mips: Convert nanoMIPS " Philippe Mathieu-Daudé
2024-11-12 18:18 ` Richard Henderson
2024-11-15 15:40 ` [PATCH v2 0/6] " Philippe Mathieu-Daudé
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