[PATCH v3 0/8] Enable CMRR in fixed-RR VRR path

[PATCH v3 0/8] Enable CMRR in fixed-RR VRR path

[Mitul Golani]

The existing CMRR fractional-timing code was permanently
disabled (if (!HAS_CMRR || true)), eDP-only, and relied
on a heuristic to guess when the fractional path was needed.
This series reworks it into a generic, debugfs-driven feature,
which later will be controlled via userspace when respective
uapi will be in-palce.

Mitul Golani (8):
  drm/i915/vrr: Add per-CRTC vrr/cmrr debugfs control
  drm/i915/display: Move CMRR crtc_state members under VRR
  drm/i915/vrr: Compute CMRR fractional timings generically
  drm/i915/vrr: Dump CMRR state in the crtc state dump
  drm/i915/vrr: Move CMRR hw registers to fix refresh rate path
  drm/i915/vrr: Program CMRR enable/disable from transcoder timings
  drm/i915/vrr: Return from CMRR compute config in case of PSR2 enabled
  drm/i915/vrr: Enable cmrr

 drivers/gpu/drm/i915/display/intel_cmtg.c     |   2 +-
 .../drm/i915/display/intel_crtc_state_dump.c  |   3 +
 drivers/gpu/drm/i915/display/intel_display.c  |  10 +-
 .../drm/i915/display/intel_display_debugfs.c  |   2 +
 .../drm/i915/display/intel_display_types.h    |  17 +-
 drivers/gpu/drm/i915/display/intel_dp.c       |   2 +-
 drivers/gpu/drm/i915/display/intel_vrr.c      | 315 +++++++++++++-----
 drivers/gpu/drm/i915/display/intel_vrr.h      |   2 +
 8 files changed, 253 insertions(+), 100 deletions(-)

-- 
2.48.1

[PATCH v3 1/8] drm/i915/vrr: Add per-CRTC vrr/cmrr debugfs control

[Mitul Golani]

Add a per-CRTC debugfs file 'intel_vrr_cmrr' that lets the user force a
CMRR target refresh rate and video-mode requirement.

The file uses a "numerator/denominator" format:
  - numerator:   requested refresh rate in milli-Hz
                 (refresh rate in Hz * 1000, e.g. 60000 for 60 Hz)
  - denominator: 1000 for a 1:1 ratio (no video timing) or
                 1001 for the 1000/1001 video timing

Reading the file reports the currently stored values; writing updates
them. The file is created only on platforms with VRR and CMRR support.

--v2:
- Drop the "vrr" debugfs subdirectory and expose a single flat,
  intel_-prefixed "intel_vrr_cmrr" file (Jani, Nikula)
- Rename struct intel_crtc.cmrr to force_cmrr to make its purpose
  explicit (Chaitanya)
- Fix parse comment: numerator unit is milli-Hz, not KHz (Chaitanya)
- Add debugfs/intel_ prefixes to the debugfs handler functions (Chaitanya)
- Expand commit message with debugfs entry semantics (Chaitanya)

Signed-off-by: Mitul Golani <mitulkumar.ajitkumar.golani@intel.com>
---
 .../drm/i915/display/intel_display_debugfs.c  |   2 +
 .../drm/i915/display/intel_display_types.h    |   5 +
 drivers/gpu/drm/i915/display/intel_vrr.c      | 103 ++++++++++++++++++
 drivers/gpu/drm/i915/display/intel_vrr.h      |   2 +
 4 files changed, 112 insertions(+)

diff --git a/drivers/gpu/drm/i915/display/intel_display_debugfs.c b/drivers/gpu/drm/i915/display/intel_display_debugfs.c
index 3f02868ef105..2bbf4760dc30 100644
--- a/drivers/gpu/drm/i915/display/intel_display_debugfs.c
+++ b/drivers/gpu/drm/i915/display/intel_display_debugfs.c
@@ -49,6 +49,7 @@
 #include "intel_psr.h"
 #include "intel_psr_regs.h"
 #include "intel_vdsc.h"
+#include "intel_vrr.h"
 #include "intel_wm.h"
 #include "intel_tc.h"
 
@@ -1395,6 +1396,7 @@ void intel_crtc_debugfs_add(struct intel_crtc *crtc)
 	intel_drrs_crtc_debugfs_add(crtc);
 	intel_fbc_crtc_debugfs_add(crtc);
 	hsw_ips_crtc_debugfs_add(crtc);
+	intel_vrr_crtc_debugfs_add(crtc);
 
 	debugfs_create_file("i915_current_bpc", 0444, root, crtc,
 			    &i915_current_bpc_fops);
diff --git a/drivers/gpu/drm/i915/display/intel_display_types.h b/drivers/gpu/drm/i915/display/intel_display_types.h
index c048da7d6fea..84a6d016e226 100644
--- a/drivers/gpu/drm/i915/display/intel_display_types.h
+++ b/drivers/gpu/drm/i915/display/intel_display_types.h
@@ -1546,6 +1546,11 @@ struct intel_crtc {
 		u64 flip_count;
 	} dc_balance;
 
+	struct {
+		u32 numerator;
+		u32 denominator;
+	} force_cmrr;
+
 	int scanline_offset;
 
 	struct {
diff --git a/drivers/gpu/drm/i915/display/intel_vrr.c b/drivers/gpu/drm/i915/display/intel_vrr.c
index 51e4f3309b8b..8b6e36ee9f55 100644
--- a/drivers/gpu/drm/i915/display/intel_vrr.c
+++ b/drivers/gpu/drm/i915/display/intel_vrr.c
@@ -4,6 +4,10 @@
  *
  */
 
+#include <linux/debugfs.h>
+#include <linux/seq_file.h>
+#include <linux/string.h>
+
 #include <drm/drm_print.h>
 #include <drm/intel/step.h>
 
@@ -1231,3 +1235,102 @@ int intel_vrr_dcb_vmax_vblank_start_final(const struct intel_crtc_state *crtc_st
 
 	return intel_vrr_vblank_start(crtc_state, VRR_DCB_VMAX(tmp) + 1);
 }
+
+static
+int intel_vrr_cmrr_parse_ratio(char *str, u32 *numerator, u32 *denominator)
+{
+	char *sep;
+	int ret;
+
+	/*
+	 * Parse a "numerator/denominator" CMRR ratio string. The numerator
+	 * is the requested refresh rate in milli-Hz (refresh rate in Hz * 1000)
+	 * and the denominator selects the timing: 1000 for a 1:1 ratio
+	 * (no video timing) or 1001 for the 1000/1001 video timing.
+	 */
+
+	sep = strchr(str, '/');
+	if (!sep)
+		return -EINVAL;
+
+	*sep = '\0';
+
+	ret = kstrtou32(strim(str), 10, numerator);
+	if (ret)
+		return ret;
+
+	ret = kstrtou32(strim(sep + 1), 10, denominator);
+	if (ret)
+		return ret;
+
+	if (*numerator == 0)
+		return -EINVAL;
+
+	if (*denominator != 1000 && *denominator != 1001)
+		return -EINVAL;
+
+	return 0;
+}
+
+static int intel_vrr_debugfs_cmrr_show(struct seq_file *m, void *data)
+{
+	struct intel_crtc *crtc = m->private;
+
+	seq_printf(m, "%u/%u\n", crtc->force_cmrr.numerator, crtc->force_cmrr.denominator);
+
+	return 0;
+}
+
+static int intel_vrr_debugfs_cmrr_open(struct inode *inode, struct file *file)
+{
+	return single_open(file, intel_vrr_debugfs_cmrr_show, inode->i_private);
+}
+
+static ssize_t intel_vrr_debugfs_cmrr_write(struct file *file, const char __user *ubuf,
+					    size_t len, loff_t *offp)
+{
+	struct seq_file *m = file->private_data;
+	struct intel_crtc *crtc = m->private;
+	u32 numerator, denominator;
+	char kbuf[32];
+	int ret;
+
+	if (len >= sizeof(kbuf))
+		return -EINVAL;
+
+	if (copy_from_user(kbuf, ubuf, len))
+		return -EFAULT;
+
+	kbuf[len] = '\0';
+
+	ret = intel_vrr_cmrr_parse_ratio(kbuf, &numerator, &denominator);
+	if (ret)
+		return ret;
+
+	crtc->force_cmrr.numerator = numerator;
+	crtc->force_cmrr.denominator = denominator;
+
+	return len;
+}
+
+static const struct file_operations intel_vrr_debugfs_cmrr_fops = {
+	.owner = THIS_MODULE,
+	.open = intel_vrr_debugfs_cmrr_open,
+	.read = seq_read,
+	.llseek = seq_lseek,
+	.release = single_release,
+	.write = intel_vrr_debugfs_cmrr_write,
+};
+
+void intel_vrr_crtc_debugfs_add(struct intel_crtc *crtc)
+{
+	struct intel_display *display = to_intel_display(crtc);
+
+	if (!HAS_VRR(display))
+		return;
+
+	if (HAS_CMRR(display))
+		debugfs_create_file("intel_vrr_cmrr", 0600, crtc->base.debugfs_entry,
+				    crtc, &intel_vrr_debugfs_cmrr_fops);
+}
+
diff --git a/drivers/gpu/drm/i915/display/intel_vrr.h b/drivers/gpu/drm/i915/display/intel_vrr.h
index 55e9c429f579..19c7990be1b2 100644
--- a/drivers/gpu/drm/i915/display/intel_vrr.h
+++ b/drivers/gpu/drm/i915/display/intel_vrr.h
@@ -56,4 +56,6 @@ int intel_vrr_dcb_vmax_vblank_start_next(const struct intel_crtc_state *crtc_sta
 int intel_vrr_dcb_vmin_vblank_start_final(const struct intel_crtc_state *crtc_state);
 int intel_vrr_dcb_vmax_vblank_start_final(const struct intel_crtc_state *crtc_state);
 
+void intel_vrr_crtc_debugfs_add(struct intel_crtc *crtc);
+
 #endif /* __INTEL_VRR_H__ */
-- 
2.48.1

Re: [PATCH v3 1/8] drm/i915/vrr: Add per-CRTC vrr/cmrr debugfs control

[Borah, Chaitanya Kumar]

On 7/14/2026 4:09 PM, Mitul Golani wrote:
> Add a per-CRTC debugfs file 'intel_vrr_cmrr' that lets the user force a
> CMRR target refresh rate and video-mode requirement.
> 
> The file uses a "numerator/denominator" format:
>    - numerator:   requested refresh rate in milli-Hz
>                   (refresh rate in Hz * 1000, e.g. 60000 for 60 Hz)
>    - denominator: 1000 for a 1:1 ratio (no video timing) or
>                   1001 for the 1000/1001 video timing
> 
> Reading the file reports the currently stored values; writing updates
> them. The file is created only on platforms with VRR and CMRR support.
> 
> --v2:
> - Drop the "vrr" debugfs subdirectory and expose a single flat,
>    intel_-prefixed "intel_vrr_cmrr" file (Jani, Nikula)
> - Rename struct intel_crtc.cmrr to force_cmrr to make its purpose
>    explicit (Chaitanya)
> - Fix parse comment: numerator unit is milli-Hz, not KHz (Chaitanya)
> - Add debugfs/intel_ prefixes to the debugfs handler functions (Chaitanya)
> - Expand commit message with debugfs entry semantics (Chaitanya)
> 
> Signed-off-by: Mitul Golani <mitulkumar.ajitkumar.golani@intel.com>
> ---
>   .../drm/i915/display/intel_display_debugfs.c  |   2 +
>   .../drm/i915/display/intel_display_types.h    |   5 +
>   drivers/gpu/drm/i915/display/intel_vrr.c      | 103 ++++++++++++++++++
>   drivers/gpu/drm/i915/display/intel_vrr.h      |   2 +
>   4 files changed, 112 insertions(+)
> 
> diff --git a/drivers/gpu/drm/i915/display/intel_display_debugfs.c b/drivers/gpu/drm/i915/display/intel_display_debugfs.c
> index 3f02868ef105..2bbf4760dc30 100644
> --- a/drivers/gpu/drm/i915/display/intel_display_debugfs.c
> +++ b/drivers/gpu/drm/i915/display/intel_display_debugfs.c
> @@ -49,6 +49,7 @@
>   #include "intel_psr.h"
>   #include "intel_psr_regs.h"
>   #include "intel_vdsc.h"
> +#include "intel_vrr.h"
>   #include "intel_wm.h"
>   #include "intel_tc.h"
>   
> @@ -1395,6 +1396,7 @@ void intel_crtc_debugfs_add(struct intel_crtc *crtc)
>   	intel_drrs_crtc_debugfs_add(crtc);
>   	intel_fbc_crtc_debugfs_add(crtc);
>   	hsw_ips_crtc_debugfs_add(crtc);
> +	intel_vrr_crtc_debugfs_add(crtc);
>   
>   	debugfs_create_file("i915_current_bpc", 0444, root, crtc,
>   			    &i915_current_bpc_fops);
> diff --git a/drivers/gpu/drm/i915/display/intel_display_types.h b/drivers/gpu/drm/i915/display/intel_display_types.h
> index c048da7d6fea..84a6d016e226 100644
> --- a/drivers/gpu/drm/i915/display/intel_display_types.h
> +++ b/drivers/gpu/drm/i915/display/intel_display_types.h
> @@ -1546,6 +1546,11 @@ struct intel_crtc {
>   		u64 flip_count;
>   	} dc_balance;
>   
> +	struct {
> +		u32 numerator;
> +		u32 denominator;
> +	} force_cmrr;
> +
>   	int scanline_offset;
>   
>   	struct {
> diff --git a/drivers/gpu/drm/i915/display/intel_vrr.c b/drivers/gpu/drm/i915/display/intel_vrr.c
> index 51e4f3309b8b..8b6e36ee9f55 100644
> --- a/drivers/gpu/drm/i915/display/intel_vrr.c
> +++ b/drivers/gpu/drm/i915/display/intel_vrr.c
> @@ -4,6 +4,10 @@
>    *
>    */
>   
> +#include <linux/debugfs.h>
> +#include <linux/seq_file.h>
> +#include <linux/string.h>
> +
>   #include <drm/drm_print.h>
>   #include <drm/intel/step.h>
>   
> @@ -1231,3 +1235,102 @@ int intel_vrr_dcb_vmax_vblank_start_final(const struct intel_crtc_state *crtc_st
>   
>   	return intel_vrr_vblank_start(crtc_state, VRR_DCB_VMAX(tmp) + 1);
>   }
> +
> +static
> +int intel_vrr_cmrr_parse_ratio(char *str, u32 *numerator, u32 *denominator)
> +{
> +	char *sep;
> +	int ret;
> +
> +	/*
> +	 * Parse a "numerator/denominator" CMRR ratio string. The numerator
> +	 * is the requested refresh rate in milli-Hz (refresh rate in Hz * 1000)
> +	 * and the denominator selects the timing: 1000 for a 1:1 ratio
> +	 * (no video timing) or 1001 for the 1000/1001 video timing.
> +	 */
> +
> +	sep = strchr(str, '/');
> +	if (!sep)
> +		return -EINVAL;
> +
> +	*sep = '\0';
> +
> +	ret = kstrtou32(strim(str), 10, numerator);
> +	if (ret)
> +		return ret;
> +
> +	ret = kstrtou32(strim(sep + 1), 10, denominator);
> +	if (ret)
> +		return ret;
> +
> +	if (*numerator == 0)
> +		return -EINVAL;
> +
> +	if (*denominator != 1000 && *denominator != 1001)
> +		return -EINVAL;
> +
> +	return 0;
> +}
> +
> +static int intel_vrr_debugfs_cmrr_show(struct seq_file *m, void *data)
> +{
> +	struct intel_crtc *crtc = m->private;
> +
> +	seq_printf(m, "%u/%u\n", crtc->force_cmrr.numerator, crtc->force_cmrr.denominator);
> +
> +	return 0;
> +}
> +
> +static int intel_vrr_debugfs_cmrr_open(struct inode *inode, struct file *file)
> +{
> +	return single_open(file, intel_vrr_debugfs_cmrr_show, inode->i_private);
> +}
> +
> +static ssize_t intel_vrr_debugfs_cmrr_write(struct file *file, const char __user *ubuf,
> +					    size_t len, loff_t *offp)
> +{
> +	struct seq_file *m = file->private_data;
> +	struct intel_crtc *crtc = m->private;
> +	u32 numerator, denominator;
> +	char kbuf[32];
> +	int ret;
> +
> +	if (len >= sizeof(kbuf))
> +		return -EINVAL;
> +
> +	if (copy_from_user(kbuf, ubuf, len))
> +		return -EFAULT;
> +
> +	kbuf[len] = '\0';
> +
> +	ret = intel_vrr_cmrr_parse_ratio(kbuf, &numerator, &denominator);
> +	if (ret)
> +		return ret;
> +
> +	crtc->force_cmrr.numerator = numerator;
> +	crtc->force_cmrr.denominator = denominator;
> +
> +	return len;
> +}
> +
> +static const struct file_operations intel_vrr_debugfs_cmrr_fops = {
> +	.owner = THIS_MODULE,
> +	.open = intel_vrr_debugfs_cmrr_open,
> +	.read = seq_read,
> +	.llseek = seq_lseek,
> +	.release = single_release,
> +	.write = intel_vrr_debugfs_cmrr_write,
> +};
> +
> +void intel_vrr_crtc_debugfs_add(struct intel_crtc *crtc)
> +{
> +	struct intel_display *display = to_intel_display(crtc);
> +
> +	if (!HAS_VRR(display))
> +		return;
> +
> +	if (HAS_CMRR(display))
> +		debugfs_create_file("intel_vrr_cmrr", 0600, crtc->base.debugfs_entry,

As discussed, please rename it to target_refresh_rate to cater to future 
use of the debugfs for other features.

Ideally rest of the function names should be changed accordingly but 
that can be handled later.

> +				    crtc, &intel_vrr_debugfs_cmrr_fops);
> +}
> +

trailing new line in EOF

With these fixed.

Reviewed-by: Chaitanya Kumar Borah <chaitanya.kumar.borah@intel.com>

> diff --git a/drivers/gpu/drm/i915/display/intel_vrr.h b/drivers/gpu/drm/i915/display/intel_vrr.h
> index 55e9c429f579..19c7990be1b2 100644
> --- a/drivers/gpu/drm/i915/display/intel_vrr.h
> +++ b/drivers/gpu/drm/i915/display/intel_vrr.h
> @@ -56,4 +56,6 @@ int intel_vrr_dcb_vmax_vblank_start_next(const struct intel_crtc_state *crtc_sta
>   int intel_vrr_dcb_vmin_vblank_start_final(const struct intel_crtc_state *crtc_state);
>   int intel_vrr_dcb_vmax_vblank_start_final(const struct intel_crtc_state *crtc_state);
>   
> +void intel_vrr_crtc_debugfs_add(struct intel_crtc *crtc);
> +
>   #endif /* __INTEL_VRR_H__ */

Re: [PATCH v3 1/8] drm/i915/vrr: Add per-CRTC vrr/cmrr debugfs control

[Naladala, Ramanaidu]

[-- Attachment #1: Type: text/plain, Size: 6590 bytes --]

Hi Mitul,

On 7/14/2026 4:09 PM, Mitul Golani wrote:
> Add a per-CRTC debugfs file 'intel_vrr_cmrr' that lets the user force a
> CMRR target refresh rate and video-mode requirement.
>
> The file uses a "numerator/denominator" format:
>    - numerator:   requested refresh rate in milli-Hz
>                   (refresh rate in Hz * 1000, e.g. 60000 for 60 Hz)
>    - denominator: 1000 for a 1:1 ratio (no video timing) or
>                   1001 for the 1000/1001 video timing
>
> Reading the file reports the currently stored values; writing updates
> them. The file is created only on platforms with VRR and CMRR support.
>
> --v2:
> - Drop the "vrr" debugfs subdirectory and expose a single flat,
>    intel_-prefixed "intel_vrr_cmrr" file (Jani, Nikula)
> - Rename struct intel_crtc.cmrr to force_cmrr to make its purpose
>    explicit (Chaitanya)
> - Fix parse comment: numerator unit is milli-Hz, not KHz (Chaitanya)
> - Add debugfs/intel_ prefixes to the debugfs handler functions (Chaitanya)
> - Expand commit message with debugfs entry semantics (Chaitanya)
>
> Signed-off-by: Mitul Golani<mitulkumar.ajitkumar.golani@intel.com>
> ---
>   .../drm/i915/display/intel_display_debugfs.c  |   2 +
>   .../drm/i915/display/intel_display_types.h    |   5 +
>   drivers/gpu/drm/i915/display/intel_vrr.c      | 103 ++++++++++++++++++
>   drivers/gpu/drm/i915/display/intel_vrr.h      |   2 +
>   4 files changed, 112 insertions(+)
>
> diff --git a/drivers/gpu/drm/i915/display/intel_display_debugfs.c b/drivers/gpu/drm/i915/display/intel_display_debugfs.c
> index 3f02868ef105..2bbf4760dc30 100644
> --- a/drivers/gpu/drm/i915/display/intel_display_debugfs.c
> +++ b/drivers/gpu/drm/i915/display/intel_display_debugfs.c
> @@ -49,6 +49,7 @@
>   #include "intel_psr.h"
>   #include "intel_psr_regs.h"
>   #include "intel_vdsc.h"
> +#include "intel_vrr.h"
>   #include "intel_wm.h"
>   #include "intel_tc.h"
>   
> @@ -1395,6 +1396,7 @@ void intel_crtc_debugfs_add(struct intel_crtc *crtc)
>   	intel_drrs_crtc_debugfs_add(crtc);
>   	intel_fbc_crtc_debugfs_add(crtc);
>   	hsw_ips_crtc_debugfs_add(crtc);
> +	intel_vrr_crtc_debugfs_add(crtc);
>   
>   	debugfs_create_file("i915_current_bpc", 0444, root, crtc,
>   			    &i915_current_bpc_fops);
> diff --git a/drivers/gpu/drm/i915/display/intel_display_types.h b/drivers/gpu/drm/i915/display/intel_display_types.h
> index c048da7d6fea..84a6d016e226 100644
> --- a/drivers/gpu/drm/i915/display/intel_display_types.h
> +++ b/drivers/gpu/drm/i915/display/intel_display_types.h
> @@ -1546,6 +1546,11 @@ struct intel_crtc {
>   		u64 flip_count;
>   	} dc_balance;
>   
> +	struct {
> +		u32 numerator;
> +		u32 denominator;
> +	} force_cmrr;
> +
>   	int scanline_offset;
>   
>   	struct {
> diff --git a/drivers/gpu/drm/i915/display/intel_vrr.c b/drivers/gpu/drm/i915/display/intel_vrr.c
> index 51e4f3309b8b..8b6e36ee9f55 100644
> --- a/drivers/gpu/drm/i915/display/intel_vrr.c
> +++ b/drivers/gpu/drm/i915/display/intel_vrr.c
> @@ -4,6 +4,10 @@
>    *
>    */
>   
> +#include <linux/debugfs.h>
> +#include <linux/seq_file.h>
> +#include <linux/string.h>
> +
>   #include <drm/drm_print.h>
>   #include <drm/intel/step.h>
>   
> @@ -1231,3 +1235,102 @@ int intel_vrr_dcb_vmax_vblank_start_final(const struct intel_crtc_state *crtc_st
>   
>   	return intel_vrr_vblank_start(crtc_state, VRR_DCB_VMAX(tmp) + 1);
>   }
> +
> +static
> +int intel_vrr_cmrr_parse_ratio(char *str, u32 *numerator, u32 *denominator)
> +{
> +	char *sep;
> +	int ret;
> +
> +	/*
> +	 * Parse a "numerator/denominator" CMRR ratio string. The numerator
> +	 * is the requested refresh rate in milli-Hz (refresh rate in Hz * 1000)
> +	 * and the denominator selects the timing: 1000 for a 1:1 ratio
> +	 * (no video timing) or 1001 for the 1000/1001 video timing.
> +	 */
> +
> +	sep = strchr(str, '/');
> +	if (!sep)
> +		return -EINVAL;
> +
> +	*sep = '\0';
> +
> +	ret = kstrtou32(strim(str), 10, numerator);
> +	if (ret)
> +		return ret;
> +
> +	ret = kstrtou32(strim(sep + 1), 10, denominator);
> +	if (ret)
> +		return ret;
> +
> +	if (*numerator == 0)
> +		return -EINVAL;
> +
> +	if (*denominator != 1000 && *denominator != 1001)
> +		return -EINVAL;
> +
> +	return 0;
> +}
> +
> +static int intel_vrr_debugfs_cmrr_show(struct seq_file *m, void *data)
> +{
> +	struct intel_crtc *crtc = m->private;
> +
> +	seq_printf(m, "%u/%u\n", crtc->force_cmrr.numerator, crtc->force_cmrr.denominator);
> +
> +	return 0;
> +}
> +
> +static int intel_vrr_debugfs_cmrr_open(struct inode *inode, struct file *file)
> +{
> +	return single_open(file, intel_vrr_debugfs_cmrr_show, inode->i_private);
> +}
> +
> +static ssize_t intel_vrr_debugfs_cmrr_write(struct file *file, const char __user *ubuf,
> +					    size_t len, loff_t *offp)
> +{
> +	struct seq_file *m = file->private_data;
> +	struct intel_crtc *crtc = m->private;
> +	u32 numerator, denominator;
> +	char kbuf[32];
> +	int ret;
> +
> +	if (len >= sizeof(kbuf))
> +		return -EINVAL;
> +
> +	if (copy_from_user(kbuf, ubuf, len))
> +		return -EFAULT;
> +
> +	kbuf[len] = '\0';
> +
> +	ret = intel_vrr_cmrr_parse_ratio(kbuf, &numerator, &denominator);
> +	if (ret)
> +		return ret;
> +
> +	crtc->force_cmrr.numerator = numerator;
> +	crtc->force_cmrr.denominator = denominator;
> +
> +	return len;
> +}
> +
> +static const struct file_operations intel_vrr_debugfs_cmrr_fops = {
> +	.owner = THIS_MODULE,
> +	.open = intel_vrr_debugfs_cmrr_open,
> +	.read = seq_read,
> +	.llseek = seq_lseek,
> +	.release = single_release,
> +	.write = intel_vrr_debugfs_cmrr_write,
> +};
> +
> +void intel_vrr_crtc_debugfs_add(struct intel_crtc *crtc)
> +{
> +	struct intel_display *display = to_intel_display(crtc);
> +
> +	if (!HAS_VRR(display))
> +		return;
> +
> +	if (HAS_CMRR(display))
> +		debugfs_create_file("intel_vrr_cmrr", 0600, crtc->base.debugfs_entry,
> +				    crtc, &intel_vrr_debugfs_cmrr_fops);
> +}
The debugfs interface accepts non-zero values, but fails to reset the 
value to zero.
> +
> diff --git a/drivers/gpu/drm/i915/display/intel_vrr.h b/drivers/gpu/drm/i915/display/intel_vrr.h
> index 55e9c429f579..19c7990be1b2 100644
> --- a/drivers/gpu/drm/i915/display/intel_vrr.h
> +++ b/drivers/gpu/drm/i915/display/intel_vrr.h
> @@ -56,4 +56,6 @@ int intel_vrr_dcb_vmax_vblank_start_next(const struct intel_crtc_state *crtc_sta
>   int intel_vrr_dcb_vmin_vblank_start_final(const struct intel_crtc_state *crtc_state);
>   int intel_vrr_dcb_vmax_vblank_start_final(const struct intel_crtc_state *crtc_state);
>   
> +void intel_vrr_crtc_debugfs_add(struct intel_crtc *crtc);
> +
>   #endif /* __INTEL_VRR_H__ */

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Re: [PATCH v3 1/8] drm/i915/vrr: Add per-CRTC vrr/cmrr debugfs control

[Naladala, Ramanaidu]

Hi Mitul,

Resending this, as it was previously sent only to i915 by mistake.

> Add a per-CRTC debugfs file 'intel_vrr_cmrr' that lets the user force a
> CMRR target refresh rate and video-mode requirement.
>
> The file uses a "numerator/denominator" format:
>    - numerator:   requested refresh rate in milli-Hz
>                   (refresh rate in Hz * 1000, e.g. 60000 for 60 Hz)
>    - denominator: 1000 for a 1:1 ratio (no video timing) or
>                   1001 for the 1000/1001 video timing
>
> Reading the file reports the currently stored values; writing updates
> them. The file is created only on platforms with VRR and CMRR support.
>
> --v2:
> - Drop the "vrr" debugfs subdirectory and expose a single flat,
>    intel_-prefixed "intel_vrr_cmrr" file (Jani, Nikula)
> - Rename struct intel_crtc.cmrr to force_cmrr to make its purpose
>    explicit (Chaitanya)
> - Fix parse comment: numerator unit is milli-Hz, not KHz (Chaitanya)
> - Add debugfs/intel_ prefixes to the debugfs handler functions (Chaitanya)
> - Expand commit message with debugfs entry semantics (Chaitanya)
>
> Signed-off-by: Mitul Golani <mitulkumar.ajitkumar.golani@intel.com>
> ---
>   .../drm/i915/display/intel_display_debugfs.c  |   2 +
>   .../drm/i915/display/intel_display_types.h    |   5 +
>   drivers/gpu/drm/i915/display/intel_vrr.c      | 103 ++++++++++++++++++
>   drivers/gpu/drm/i915/display/intel_vrr.h      |   2 +
>   4 files changed, 112 insertions(+)
>
> diff --git a/drivers/gpu/drm/i915/display/intel_display_debugfs.c b/drivers/gpu/drm/i915/display/intel_display_debugfs.c
> index 3f02868ef105..2bbf4760dc30 100644
> --- a/drivers/gpu/drm/i915/display/intel_display_debugfs.c
> +++ b/drivers/gpu/drm/i915/display/intel_display_debugfs.c
> @@ -49,6 +49,7 @@
>   #include "intel_psr.h"
>   #include "intel_psr_regs.h"
>   #include "intel_vdsc.h"
> +#include "intel_vrr.h"
>   #include "intel_wm.h"
>   #include "intel_tc.h"
>   
> @@ -1395,6 +1396,7 @@ void intel_crtc_debugfs_add(struct intel_crtc *crtc)
>   	intel_drrs_crtc_debugfs_add(crtc);
>   	intel_fbc_crtc_debugfs_add(crtc);
>   	hsw_ips_crtc_debugfs_add(crtc);
> +	intel_vrr_crtc_debugfs_add(crtc);
>   
>   	debugfs_create_file("i915_current_bpc", 0444, root, crtc,
>   			    &i915_current_bpc_fops);
> diff --git a/drivers/gpu/drm/i915/display/intel_display_types.h b/drivers/gpu/drm/i915/display/intel_display_types.h
> index c048da7d6fea..84a6d016e226 100644
> --- a/drivers/gpu/drm/i915/display/intel_display_types.h
> +++ b/drivers/gpu/drm/i915/display/intel_display_types.h
> @@ -1546,6 +1546,11 @@ struct intel_crtc {
>   		u64 flip_count;
>   	} dc_balance;
>   
> +	struct {
> +		u32 numerator;
> +		u32 denominator;
> +	} force_cmrr;
> +
>   	int scanline_offset;
>   
>   	struct {
> diff --git a/drivers/gpu/drm/i915/display/intel_vrr.c b/drivers/gpu/drm/i915/display/intel_vrr.c
> index 51e4f3309b8b..8b6e36ee9f55 100644
> --- a/drivers/gpu/drm/i915/display/intel_vrr.c
> +++ b/drivers/gpu/drm/i915/display/intel_vrr.c
> @@ -4,6 +4,10 @@
>    *
>    */
>   
> +#include <linux/debugfs.h>
> +#include <linux/seq_file.h>
> +#include <linux/string.h>
> +
>   #include <drm/drm_print.h>
>   #include <drm/intel/step.h>
>   
> @@ -1231,3 +1235,102 @@ int intel_vrr_dcb_vmax_vblank_start_final(const struct intel_crtc_state *crtc_st
>   
>   	return intel_vrr_vblank_start(crtc_state, VRR_DCB_VMAX(tmp) + 1);
>   }
> +
> +static
> +int intel_vrr_cmrr_parse_ratio(char *str, u32 *numerator, u32 *denominator)
> +{
> +	char *sep;
> +	int ret;
> +
> +	/*
> +	 * Parse a "numerator/denominator" CMRR ratio string. The numerator
> +	 * is the requested refresh rate in milli-Hz (refresh rate in Hz * 1000)
> +	 * and the denominator selects the timing: 1000 for a 1:1 ratio
> +	 * (no video timing) or 1001 for the 1000/1001 video timing.
> +	 */
> +
> +	sep = strchr(str, '/');
> +	if (!sep)
> +		return -EINVAL;
> +
> +	*sep = '\0';
> +
> +	ret = kstrtou32(strim(str), 10, numerator);
> +	if (ret)
> +		return ret;
> +
> +	ret = kstrtou32(strim(sep + 1), 10, denominator);
> +	if (ret)
> +		return ret;
> +
> +	if (*numerator == 0)
> +		return -EINVAL;
> +
> +	if (*denominator != 1000 && *denominator != 1001)
> +		return -EINVAL;
> +
> +	return 0;
> +}
> +
> +static int intel_vrr_debugfs_cmrr_show(struct seq_file *m, void *data)
> +{
> +	struct intel_crtc *crtc = m->private;
> +
> +	seq_printf(m, "%u/%u\n", crtc->force_cmrr.numerator, crtc->force_cmrr.denominator);
> +
> +	return 0;
> +}
> +
> +static int intel_vrr_debugfs_cmrr_open(struct inode *inode, struct file *file)
> +{
> +	return single_open(file, intel_vrr_debugfs_cmrr_show, inode->i_private);
> +}
> +
> +static ssize_t intel_vrr_debugfs_cmrr_write(struct file *file, const char __user *ubuf,
> +					    size_t len, loff_t *offp)
> +{
> +	struct seq_file *m = file->private_data;
> +	struct intel_crtc *crtc = m->private;
> +	u32 numerator, denominator;
> +	char kbuf[32];
> +	int ret;
> +
> +	if (len >= sizeof(kbuf))
> +		return -EINVAL;
> +
> +	if (copy_from_user(kbuf, ubuf, len))
> +		return -EFAULT;
> +
> +	kbuf[len] = '\0';
> +
> +	ret = intel_vrr_cmrr_parse_ratio(kbuf, &numerator, &denominator);
> +	if (ret)
> +		return ret;
> +
> +	crtc->force_cmrr.numerator = numerator;
> +	crtc->force_cmrr.denominator = denominator;
> +
> +	return len;
> +}
> +
> +static const struct file_operations intel_vrr_debugfs_cmrr_fops = {
> +	.owner = THIS_MODULE,
> +	.open = intel_vrr_debugfs_cmrr_open,
> +	.read = seq_read,
> +	.llseek = seq_lseek,
> +	.release = single_release,
> +	.write = intel_vrr_debugfs_cmrr_write,
> +};
> +
> +void intel_vrr_crtc_debugfs_add(struct intel_crtc *crtc)
> +{
> +	struct intel_display *display = to_intel_display(crtc);
> +
> +	if (!HAS_VRR(display))
> +		return;
> +
> +	if (HAS_CMRR(display))
> +		debugfs_create_file("intel_vrr_cmrr", 0600, crtc->base.debugfs_entry,
> +				    crtc, &intel_vrr_debugfs_cmrr_fops);
> +}

The debugfs interface accepts non-zero values, but fails to reset the 
value to zero.

> +
> diff --git a/drivers/gpu/drm/i915/display/intel_vrr.h b/drivers/gpu/drm/i915/display/intel_vrr.h
> index 55e9c429f579..19c7990be1b2 100644
> --- a/drivers/gpu/drm/i915/display/intel_vrr.h
> +++ b/drivers/gpu/drm/i915/display/intel_vrr.h
> @@ -56,4 +56,6 @@ int intel_vrr_dcb_vmax_vblank_start_next(const struct intel_crtc_state *crtc_sta
>   int intel_vrr_dcb_vmin_vblank_start_final(const struct intel_crtc_state *crtc_state);
>   int intel_vrr_dcb_vmax_vblank_start_final(const struct intel_crtc_state *crtc_state);
>   
> +void intel_vrr_crtc_debugfs_add(struct intel_crtc *crtc);
> +
>   #endif /* __INTEL_VRR_H__ */

Re: [PATCH v3 1/8] drm/i915/vrr: Add per-CRTC vrr/cmrr debugfs control

[Borah, Chaitanya Kumar]

On 7/16/2026 8:07 PM, Naladala, Ramanaidu wrote:
> Hi Mitul,
> 
> Resending this, as it was previously sent only to i915 by mistake.
> 
>> Add a per-CRTC debugfs file 'intel_vrr_cmrr' that lets the user force a
>> CMRR target refresh rate and video-mode requirement.
>>
>> The file uses a "numerator/denominator" format:
>>    - numerator:   requested refresh rate in milli-Hz
>>                   (refresh rate in Hz * 1000, e.g. 60000 for 60 Hz)
>>    - denominator: 1000 for a 1:1 ratio (no video timing) or
>>                   1001 for the 1000/1001 video timing
>>
>> Reading the file reports the currently stored values; writing updates
>> them. The file is created only on platforms with VRR and CMRR support.
>>
>> --v2:
>> - Drop the "vrr" debugfs subdirectory and expose a single flat,
>>    intel_-prefixed "intel_vrr_cmrr" file (Jani, Nikula)
>> - Rename struct intel_crtc.cmrr to force_cmrr to make its purpose
>>    explicit (Chaitanya)
>> - Fix parse comment: numerator unit is milli-Hz, not KHz (Chaitanya)
>> - Add debugfs/intel_ prefixes to the debugfs handler functions 
>> (Chaitanya)
>> - Expand commit message with debugfs entry semantics (Chaitanya)
>>
>> Signed-off-by: Mitul Golani <mitulkumar.ajitkumar.golani@intel.com>
>> ---
>>   .../drm/i915/display/intel_display_debugfs.c  |   2 +
>>   .../drm/i915/display/intel_display_types.h    |   5 +
>>   drivers/gpu/drm/i915/display/intel_vrr.c      | 103 ++++++++++++++++++
>>   drivers/gpu/drm/i915/display/intel_vrr.h      |   2 +
>>   4 files changed, 112 insertions(+)
>>
>> diff --git a/drivers/gpu/drm/i915/display/intel_display_debugfs.c b/ 
>> drivers/gpu/drm/i915/display/intel_display_debugfs.c
>> index 3f02868ef105..2bbf4760dc30 100644
>> --- a/drivers/gpu/drm/i915/display/intel_display_debugfs.c
>> +++ b/drivers/gpu/drm/i915/display/intel_display_debugfs.c
>> @@ -49,6 +49,7 @@
>>   #include "intel_psr.h"
>>   #include "intel_psr_regs.h"
>>   #include "intel_vdsc.h"
>> +#include "intel_vrr.h"
>>   #include "intel_wm.h"
>>   #include "intel_tc.h"
>> @@ -1395,6 +1396,7 @@ void intel_crtc_debugfs_add(struct intel_crtc 
>> *crtc)
>>       intel_drrs_crtc_debugfs_add(crtc);
>>       intel_fbc_crtc_debugfs_add(crtc);
>>       hsw_ips_crtc_debugfs_add(crtc);
>> +    intel_vrr_crtc_debugfs_add(crtc);
>>       debugfs_create_file("i915_current_bpc", 0444, root, crtc,
>>                   &i915_current_bpc_fops);
>> diff --git a/drivers/gpu/drm/i915/display/intel_display_types.h b/ 
>> drivers/gpu/drm/i915/display/intel_display_types.h
>> index c048da7d6fea..84a6d016e226 100644
>> --- a/drivers/gpu/drm/i915/display/intel_display_types.h
>> +++ b/drivers/gpu/drm/i915/display/intel_display_types.h
>> @@ -1546,6 +1546,11 @@ struct intel_crtc {
>>           u64 flip_count;
>>       } dc_balance;
>> +    struct {
>> +        u32 numerator;
>> +        u32 denominator;
>> +    } force_cmrr;
>> +
>>       int scanline_offset;
>>       struct {
>> diff --git a/drivers/gpu/drm/i915/display/intel_vrr.c b/drivers/gpu/ 
>> drm/i915/display/intel_vrr.c
>> index 51e4f3309b8b..8b6e36ee9f55 100644
>> --- a/drivers/gpu/drm/i915/display/intel_vrr.c
>> +++ b/drivers/gpu/drm/i915/display/intel_vrr.c
>> @@ -4,6 +4,10 @@
>>    *
>>    */
>> +#include <linux/debugfs.h>
>> +#include <linux/seq_file.h>
>> +#include <linux/string.h>
>> +
>>   #include <drm/drm_print.h>
>>   #include <drm/intel/step.h>
>> @@ -1231,3 +1235,102 @@ int 
>> intel_vrr_dcb_vmax_vblank_start_final(const struct intel_crtc_state 
>> *crtc_st
>>       return intel_vrr_vblank_start(crtc_state, VRR_DCB_VMAX(tmp) + 1);
>>   }
>> +
>> +static
>> +int intel_vrr_cmrr_parse_ratio(char *str, u32 *numerator, u32 
>> *denominator)
>> +{
>> +    char *sep;
>> +    int ret;
>> +
>> +    /*
>> +     * Parse a "numerator/denominator" CMRR ratio string. The numerator
>> +     * is the requested refresh rate in milli-Hz (refresh rate in Hz 
>> * 1000)
>> +     * and the denominator selects the timing: 1000 for a 1:1 ratio
>> +     * (no video timing) or 1001 for the 1000/1001 video timing.
>> +     */
>> +
>> +    sep = strchr(str, '/');
>> +    if (!sep)
>> +        return -EINVAL;
>> +
>> +    *sep = '\0';
>> +
>> +    ret = kstrtou32(strim(str), 10, numerator);
>> +    if (ret)
>> +        return ret;
>> +
>> +    ret = kstrtou32(strim(sep + 1), 10, denominator);
>> +    if (ret)
>> +        return ret;
>> +
>> +    if (*numerator == 0)
>> +        return -EINVAL;
>> +
>> +    if (*denominator != 1000 && *denominator != 1001)
>> +        return -EINVAL;
>> +
>> +    return 0;
>> +}
>> +
>> +static int intel_vrr_debugfs_cmrr_show(struct seq_file *m, void *data)
>> +{
>> +    struct intel_crtc *crtc = m->private;
>> +
>> +    seq_printf(m, "%u/%u\n", crtc->force_cmrr.numerator, crtc- 
>> >force_cmrr.denominator);
>> +
>> +    return 0;
>> +}
>> +
>> +static int intel_vrr_debugfs_cmrr_open(struct inode *inode, struct 
>> file *file)
>> +{
>> +    return single_open(file, intel_vrr_debugfs_cmrr_show, inode- 
>> >i_private);
>> +}
>> +
>> +static ssize_t intel_vrr_debugfs_cmrr_write(struct file *file, const 
>> char __user *ubuf,
>> +                        size_t len, loff_t *offp)
>> +{
>> +    struct seq_file *m = file->private_data;
>> +    struct intel_crtc *crtc = m->private;
>> +    u32 numerator, denominator;
>> +    char kbuf[32];
>> +    int ret;
>> +
>> +    if (len >= sizeof(kbuf))
>> +        return -EINVAL;
>> +
>> +    if (copy_from_user(kbuf, ubuf, len))
>> +        return -EFAULT;
>> +
>> +    kbuf[len] = '\0';
>> +
>> +    ret = intel_vrr_cmrr_parse_ratio(kbuf, &numerator, &denominator);
>> +    if (ret)
>> +        return ret;
>> +
>> +    crtc->force_cmrr.numerator = numerator;
>> +    crtc->force_cmrr.denominator = denominator;
>> +
>> +    return len;
>> +}
>> +
>> +static const struct file_operations intel_vrr_debugfs_cmrr_fops = {
>> +    .owner = THIS_MODULE,
>> +    .open = intel_vrr_debugfs_cmrr_open,
>> +    .read = seq_read,
>> +    .llseek = seq_lseek,
>> +    .release = single_release,
>> +    .write = intel_vrr_debugfs_cmrr_write,
>> +};
>> +
>> +void intel_vrr_crtc_debugfs_add(struct intel_crtc *crtc)
>> +{
>> +    struct intel_display *display = to_intel_display(crtc);
>> +
>> +    if (!HAS_VRR(display))
>> +        return;
>> +
>> +    if (HAS_CMRR(display))
>> +        debugfs_create_file("intel_vrr_cmrr", 0600, crtc- 
>> >base.debugfs_entry,
>> +                    crtc, &intel_vrr_debugfs_cmrr_fops);
>> +}
> 
> The debugfs interface accepts non-zero values, but fails to reset the 
> value to zero.
> 

Yeah I think we will also need some magic value to let the driver know 
to disable the feature. Since 0/0 is the default value shown by the 
debugfs entry that makes the most sense.

echo '0/0' > <file name>

to disable the CMRR. IGT can use it restore the state after testing is done.

>> +
>> diff --git a/drivers/gpu/drm/i915/display/intel_vrr.h b/drivers/gpu/ 
>> drm/i915/display/intel_vrr.h
>> index 55e9c429f579..19c7990be1b2 100644
>> --- a/drivers/gpu/drm/i915/display/intel_vrr.h
>> +++ b/drivers/gpu/drm/i915/display/intel_vrr.h
>> @@ -56,4 +56,6 @@ int intel_vrr_dcb_vmax_vblank_start_next(const 
>> struct intel_crtc_state *crtc_sta
>>   int intel_vrr_dcb_vmin_vblank_start_final(const struct 
>> intel_crtc_state *crtc_state);
>>   int intel_vrr_dcb_vmax_vblank_start_final(const struct 
>> intel_crtc_state *crtc_state);
>> +void intel_vrr_crtc_debugfs_add(struct intel_crtc *crtc);
>> +
>>   #endif /* __INTEL_VRR_H__ */

[PATCH v3 2/8] drm/i915/display: Move CMRR crtc_state members under VRR

[Mitul Golani]

Move CMRR crtc state members under VRR infrastructure as
it is enabled during fix refresh rate  VRR timing generator
is enabled.

--v2:
- Move cmrr structure under vrr umbrella.
- Remove dups. (Jani)

Signed-off-by: Mitul Golani <mitulkumar.ajitkumar.golani@intel.com>
---
 drivers/gpu/drm/i915/display/intel_cmtg.c     |  2 +-
 drivers/gpu/drm/i915/display/intel_display.c  | 10 +++----
 .../drm/i915/display/intel_display_types.h    | 12 ++++----
 drivers/gpu/drm/i915/display/intel_dp.c       |  2 +-
 drivers/gpu/drm/i915/display/intel_vrr.c      | 30 +++++++++----------
 5 files changed, 28 insertions(+), 28 deletions(-)

diff --git a/drivers/gpu/drm/i915/display/intel_cmtg.c b/drivers/gpu/drm/i915/display/intel_cmtg.c
index c8e0f90af910..3c0f5b2fb2e7 100644
--- a/drivers/gpu/drm/i915/display/intel_cmtg.c
+++ b/drivers/gpu/drm/i915/display/intel_cmtg.c
@@ -326,7 +326,7 @@ void intel_cmtg_set_vrr_ctl(const struct intel_crtc_state *crtc_state)
 		  XELPD_VRR_CTL_VRR_GUARDBAND(crtc_state->vrr.guardband);
 
 	/* TODO: The code below may need to be revisited once CMRR is enabled */
-	if (crtc_state->cmrr.enable)
+	if (crtc_state->vrr.cmrr.enable)
 		vrr_ctl |= VRR_CTL_CMRR_ENABLE;
 
 	intel_de_write(display, TRANS_VRR_CTL(display, cmtg_transcoder), vrr_ctl);
diff --git a/drivers/gpu/drm/i915/display/intel_display.c b/drivers/gpu/drm/i915/display/intel_display.c
index 214454f419e9..96e77e6a8725 100644
--- a/drivers/gpu/drm/i915/display/intel_display.c
+++ b/drivers/gpu/drm/i915/display/intel_display.c
@@ -950,8 +950,8 @@ static bool vrr_params_changed(const struct intel_crtc_state *old_crtc_state,
 static bool cmrr_params_changed(const struct intel_crtc_state *old_crtc_state,
 				const struct intel_crtc_state *new_crtc_state)
 {
-	return old_crtc_state->cmrr.cmrr_m != new_crtc_state->cmrr.cmrr_m ||
-		old_crtc_state->cmrr.cmrr_n != new_crtc_state->cmrr.cmrr_n;
+	return old_crtc_state->vrr.cmrr.cmrr_m != new_crtc_state->vrr.cmrr.cmrr_m ||
+		old_crtc_state->vrr.cmrr.cmrr_n != new_crtc_state->vrr.cmrr.cmrr_n;
 }
 
 static bool intel_crtc_vrr_enabling(struct intel_atomic_state *state,
@@ -5495,9 +5495,9 @@ intel_pipe_config_compare(const struct intel_crtc_state *current_config,
 		PIPE_CONF_CHECK_I(vrr.flipline);
 		PIPE_CONF_CHECK_I(vrr.vsync_start);
 		PIPE_CONF_CHECK_I(vrr.vsync_end);
-		PIPE_CONF_CHECK_LLI(cmrr.cmrr_m);
-		PIPE_CONF_CHECK_LLI(cmrr.cmrr_n);
-		PIPE_CONF_CHECK_BOOL(cmrr.enable);
+		PIPE_CONF_CHECK_LLI(vrr.cmrr.cmrr_m);
+		PIPE_CONF_CHECK_LLI(vrr.cmrr.cmrr_n);
+		PIPE_CONF_CHECK_BOOL(vrr.cmrr.enable);
 		PIPE_CONF_CHECK_I(vrr.dc_balance.vmin);
 		PIPE_CONF_CHECK_I(vrr.dc_balance.vmax);
 		PIPE_CONF_CHECK_I(vrr.dc_balance.guardband);
diff --git a/drivers/gpu/drm/i915/display/intel_display_types.h b/drivers/gpu/drm/i915/display/intel_display_types.h
index 84a6d016e226..644a3f32fb5f 100644
--- a/drivers/gpu/drm/i915/display/intel_display_types.h
+++ b/drivers/gpu/drm/i915/display/intel_display_types.h
@@ -1401,13 +1401,13 @@ struct intel_crtc_state {
 			u16 max_increase, max_decrease;
 			u16 vblank_target;
 		} dc_balance;
-	} vrr;
 
-	/* Content Match Refresh Rate state */
-	struct {
-		bool enable;
-		u64 cmrr_n, cmrr_m;
-	} cmrr;
+		/* Content Match Refresh Rate state */
+		struct {
+			bool enable;
+			u64 cmrr_n, cmrr_m;
+		} cmrr;
+	} vrr;
 
 	/* Stream Splitter for eDP MSO */
 	struct {
diff --git a/drivers/gpu/drm/i915/display/intel_dp.c b/drivers/gpu/drm/i915/display/intel_dp.c
index 0922d23b284c..01ef34d9d358 100644
--- a/drivers/gpu/drm/i915/display/intel_dp.c
+++ b/drivers/gpu/drm/i915/display/intel_dp.c
@@ -3090,7 +3090,7 @@ static void intel_dp_compute_as_sdp(struct intel_dp *intel_dp,
 	as_sdp->revision = 0x2;
 	as_sdp->vtotal = intel_vrr_vmin_vtotal(crtc_state);
 
-	if (crtc_state->cmrr.enable) {
+	if (crtc_state->vrr.cmrr.enable) {
 		as_sdp->mode = DP_AS_SDP_FAVT_TRR_REACHED;
 		as_sdp->target_rr = drm_mode_vrefresh(adjusted_mode);
 		as_sdp->target_rr_divider = true;
diff --git a/drivers/gpu/drm/i915/display/intel_vrr.c b/drivers/gpu/drm/i915/display/intel_vrr.c
index 8b6e36ee9f55..b36026183399 100644
--- a/drivers/gpu/drm/i915/display/intel_vrr.c
+++ b/drivers/gpu/drm/i915/display/intel_vrr.c
@@ -229,12 +229,12 @@ cmrr_get_vtotal(struct intel_crtc_state *crtc_state, bool video_mode_required)
 		multiplier_n = 1000;
 	}
 
-	crtc_state->cmrr.cmrr_n = mul_u32_u32(desired_refresh_rate * adjusted_mode->crtc_htotal,
-					      multiplier_n);
+	crtc_state->vrr.cmrr.cmrr_n = mul_u32_u32(desired_refresh_rate * adjusted_mode->crtc_htotal,
+						  multiplier_n);
 	vtotal = DIV_ROUND_UP_ULL(mul_u32_u32(adjusted_mode->crtc_clock * 1000, multiplier_n),
-				  crtc_state->cmrr.cmrr_n);
+				  crtc_state->vrr.cmrr.cmrr_n);
 	adjusted_pixel_rate = mul_u32_u32(adjusted_mode->crtc_clock * 1000, multiplier_m);
-	crtc_state->cmrr.cmrr_m = do_div(adjusted_pixel_rate, crtc_state->cmrr.cmrr_n);
+	crtc_state->vrr.cmrr.cmrr_m = do_div(adjusted_pixel_rate, crtc_state->vrr.cmrr.cmrr_n);
 
 	return vtotal;
 }
@@ -252,7 +252,7 @@ void intel_vrr_compute_cmrr_timings(struct intel_crtc_state *crtc_state)
 	crtc_state->vrr.vmin = crtc_state->vrr.vmax;
 	crtc_state->vrr.flipline = crtc_state->vrr.vmin;
 
-	crtc_state->cmrr.enable = true;
+	crtc_state->vrr.cmrr.enable = true;
 	crtc_state->mode_flags |= I915_MODE_FLAG_VRR;
 }
 
@@ -645,15 +645,15 @@ void intel_vrr_set_transcoder_timings(const struct intel_crtc_state *crtc_state)
 		return;
 	}
 
-	if (crtc_state->cmrr.enable) {
+	if (crtc_state->vrr.cmrr.enable) {
 		intel_de_write(display, TRANS_CMRR_M_HI(display, cpu_transcoder),
-			       upper_32_bits(crtc_state->cmrr.cmrr_m));
+			       upper_32_bits(crtc_state->vrr.cmrr.cmrr_m));
 		intel_de_write(display, TRANS_CMRR_M_LO(display, cpu_transcoder),
-			       lower_32_bits(crtc_state->cmrr.cmrr_m));
+			       lower_32_bits(crtc_state->vrr.cmrr.cmrr_m));
 		intel_de_write(display, TRANS_CMRR_N_HI(display, cpu_transcoder),
-			       upper_32_bits(crtc_state->cmrr.cmrr_n));
+			       upper_32_bits(crtc_state->vrr.cmrr.cmrr_n));
 		intel_de_write(display, TRANS_CMRR_N_LO(display, cpu_transcoder),
-			       lower_32_bits(crtc_state->cmrr.cmrr_n));
+			       lower_32_bits(crtc_state->vrr.cmrr.cmrr_n));
 	}
 
 	intel_vrr_set_fixed_rr_timings(crtc_state, cpu_transcoder);
@@ -974,7 +974,7 @@ void intel_vrr_enable(const struct intel_crtc_state *crtc_state)
 	intel_vrr_enable_dc_balancing(crtc_state);
 
 	if (!intel_vrr_always_use_vrr_tg(display))
-		intel_vrr_tg_enable(crtc_state, crtc_state->cmrr.enable);
+		intel_vrr_tg_enable(crtc_state, crtc_state->vrr.cmrr.enable);
 }
 
 void intel_vrr_disable(const struct intel_crtc_state *old_crtc_state)
@@ -1071,12 +1071,12 @@ void intel_vrr_get_config(struct intel_crtc_state *crtc_state)
 				      TRANS_VRR_CTL(display, cpu_transcoder));
 
 	if (HAS_CMRR(display))
-		crtc_state->cmrr.enable = (trans_vrr_ctl & VRR_CTL_CMRR_ENABLE);
+		crtc_state->vrr.cmrr.enable = (trans_vrr_ctl & VRR_CTL_CMRR_ENABLE);
 
-	if (crtc_state->cmrr.enable) {
-		crtc_state->cmrr.cmrr_n =
+	if (crtc_state->vrr.cmrr.enable) {
+		crtc_state->vrr.cmrr.cmrr_n =
 			intel_de_read64_2x32(display, TRANS_CMRR_N_LO(display, cpu_transcoder));
-		crtc_state->cmrr.cmrr_m =
+		crtc_state->vrr.cmrr.cmrr_m =
 			intel_de_read64_2x32(display, TRANS_CMRR_M_LO(display, cpu_transcoder));
 	}
 
-- 
2.48.1

Re: [PATCH v3 2/8] drm/i915/display: Move CMRR crtc_state members under VRR

[Borah, Chaitanya Kumar]

On 7/14/2026 4:09 PM, Mitul Golani wrote:
> Move CMRR crtc state members under VRR infrastructure as
> it is enabled during fix refresh rate  VRR timing generator
> is enabled.
> 

it is enabled when the fixed-refresh-rate VRR timing generator is enabled

with that,

Reviewed-by: Chaitanya Kumar Borah <chaitanya.kumar.borah@intel.com>

> --v2:
> - Move cmrr structure under vrr umbrella.
> - Remove dups. (Jani)
> 
> Signed-off-by: Mitul Golani <mitulkumar.ajitkumar.golani@intel.com>
> ---
>   drivers/gpu/drm/i915/display/intel_cmtg.c     |  2 +-
>   drivers/gpu/drm/i915/display/intel_display.c  | 10 +++----
>   .../drm/i915/display/intel_display_types.h    | 12 ++++----
>   drivers/gpu/drm/i915/display/intel_dp.c       |  2 +-
>   drivers/gpu/drm/i915/display/intel_vrr.c      | 30 +++++++++----------
>   5 files changed, 28 insertions(+), 28 deletions(-)
> 
> diff --git a/drivers/gpu/drm/i915/display/intel_cmtg.c b/drivers/gpu/drm/i915/display/intel_cmtg.c
> index c8e0f90af910..3c0f5b2fb2e7 100644
> --- a/drivers/gpu/drm/i915/display/intel_cmtg.c
> +++ b/drivers/gpu/drm/i915/display/intel_cmtg.c
> @@ -326,7 +326,7 @@ void intel_cmtg_set_vrr_ctl(const struct intel_crtc_state *crtc_state)
>   		  XELPD_VRR_CTL_VRR_GUARDBAND(crtc_state->vrr.guardband);
>   
>   	/* TODO: The code below may need to be revisited once CMRR is enabled */
> -	if (crtc_state->cmrr.enable)
> +	if (crtc_state->vrr.cmrr.enable)
>   		vrr_ctl |= VRR_CTL_CMRR_ENABLE;
>   
>   	intel_de_write(display, TRANS_VRR_CTL(display, cmtg_transcoder), vrr_ctl);
> diff --git a/drivers/gpu/drm/i915/display/intel_display.c b/drivers/gpu/drm/i915/display/intel_display.c
> index 214454f419e9..96e77e6a8725 100644
> --- a/drivers/gpu/drm/i915/display/intel_display.c
> +++ b/drivers/gpu/drm/i915/display/intel_display.c
> @@ -950,8 +950,8 @@ static bool vrr_params_changed(const struct intel_crtc_state *old_crtc_state,
>   static bool cmrr_params_changed(const struct intel_crtc_state *old_crtc_state,
>   				const struct intel_crtc_state *new_crtc_state)
>   {
> -	return old_crtc_state->cmrr.cmrr_m != new_crtc_state->cmrr.cmrr_m ||
> -		old_crtc_state->cmrr.cmrr_n != new_crtc_state->cmrr.cmrr_n;
> +	return old_crtc_state->vrr.cmrr.cmrr_m != new_crtc_state->vrr.cmrr.cmrr_m ||
> +		old_crtc_state->vrr.cmrr.cmrr_n != new_crtc_state->vrr.cmrr.cmrr_n;
>   }
>   
>   static bool intel_crtc_vrr_enabling(struct intel_atomic_state *state,
> @@ -5495,9 +5495,9 @@ intel_pipe_config_compare(const struct intel_crtc_state *current_config,
>   		PIPE_CONF_CHECK_I(vrr.flipline);
>   		PIPE_CONF_CHECK_I(vrr.vsync_start);
>   		PIPE_CONF_CHECK_I(vrr.vsync_end);
> -		PIPE_CONF_CHECK_LLI(cmrr.cmrr_m);
> -		PIPE_CONF_CHECK_LLI(cmrr.cmrr_n);
> -		PIPE_CONF_CHECK_BOOL(cmrr.enable);
> +		PIPE_CONF_CHECK_LLI(vrr.cmrr.cmrr_m);
> +		PIPE_CONF_CHECK_LLI(vrr.cmrr.cmrr_n);
> +		PIPE_CONF_CHECK_BOOL(vrr.cmrr.enable);
>   		PIPE_CONF_CHECK_I(vrr.dc_balance.vmin);
>   		PIPE_CONF_CHECK_I(vrr.dc_balance.vmax);
>   		PIPE_CONF_CHECK_I(vrr.dc_balance.guardband);
> diff --git a/drivers/gpu/drm/i915/display/intel_display_types.h b/drivers/gpu/drm/i915/display/intel_display_types.h
> index 84a6d016e226..644a3f32fb5f 100644
> --- a/drivers/gpu/drm/i915/display/intel_display_types.h
> +++ b/drivers/gpu/drm/i915/display/intel_display_types.h
> @@ -1401,13 +1401,13 @@ struct intel_crtc_state {
>   			u16 max_increase, max_decrease;
>   			u16 vblank_target;
>   		} dc_balance;
> -	} vrr;
>   
> -	/* Content Match Refresh Rate state */
> -	struct {
> -		bool enable;
> -		u64 cmrr_n, cmrr_m;
> -	} cmrr;
> +		/* Content Match Refresh Rate state */
> +		struct {
> +			bool enable;
> +			u64 cmrr_n, cmrr_m;
> +		} cmrr;
> +	} vrr;
>   
>   	/* Stream Splitter for eDP MSO */
>   	struct {
> diff --git a/drivers/gpu/drm/i915/display/intel_dp.c b/drivers/gpu/drm/i915/display/intel_dp.c
> index 0922d23b284c..01ef34d9d358 100644
> --- a/drivers/gpu/drm/i915/display/intel_dp.c
> +++ b/drivers/gpu/drm/i915/display/intel_dp.c
> @@ -3090,7 +3090,7 @@ static void intel_dp_compute_as_sdp(struct intel_dp *intel_dp,
>   	as_sdp->revision = 0x2;
>   	as_sdp->vtotal = intel_vrr_vmin_vtotal(crtc_state);
>   
> -	if (crtc_state->cmrr.enable) {
> +	if (crtc_state->vrr.cmrr.enable) {
>   		as_sdp->mode = DP_AS_SDP_FAVT_TRR_REACHED;
>   		as_sdp->target_rr = drm_mode_vrefresh(adjusted_mode);
>   		as_sdp->target_rr_divider = true;
> diff --git a/drivers/gpu/drm/i915/display/intel_vrr.c b/drivers/gpu/drm/i915/display/intel_vrr.c
> index 8b6e36ee9f55..b36026183399 100644
> --- a/drivers/gpu/drm/i915/display/intel_vrr.c
> +++ b/drivers/gpu/drm/i915/display/intel_vrr.c
> @@ -229,12 +229,12 @@ cmrr_get_vtotal(struct intel_crtc_state *crtc_state, bool video_mode_required)
>   		multiplier_n = 1000;
>   	}
>   
> -	crtc_state->cmrr.cmrr_n = mul_u32_u32(desired_refresh_rate * adjusted_mode->crtc_htotal,
> -					      multiplier_n);
> +	crtc_state->vrr.cmrr.cmrr_n = mul_u32_u32(desired_refresh_rate * adjusted_mode->crtc_htotal,
> +						  multiplier_n);
>   	vtotal = DIV_ROUND_UP_ULL(mul_u32_u32(adjusted_mode->crtc_clock * 1000, multiplier_n),
> -				  crtc_state->cmrr.cmrr_n);
> +				  crtc_state->vrr.cmrr.cmrr_n);
>   	adjusted_pixel_rate = mul_u32_u32(adjusted_mode->crtc_clock * 1000, multiplier_m);
> -	crtc_state->cmrr.cmrr_m = do_div(adjusted_pixel_rate, crtc_state->cmrr.cmrr_n);
> +	crtc_state->vrr.cmrr.cmrr_m = do_div(adjusted_pixel_rate, crtc_state->vrr.cmrr.cmrr_n);
>   
>   	return vtotal;
>   }
> @@ -252,7 +252,7 @@ void intel_vrr_compute_cmrr_timings(struct intel_crtc_state *crtc_state)
>   	crtc_state->vrr.vmin = crtc_state->vrr.vmax;
>   	crtc_state->vrr.flipline = crtc_state->vrr.vmin;
>   
> -	crtc_state->cmrr.enable = true;
> +	crtc_state->vrr.cmrr.enable = true;
>   	crtc_state->mode_flags |= I915_MODE_FLAG_VRR;
>   }
>   
> @@ -645,15 +645,15 @@ void intel_vrr_set_transcoder_timings(const struct intel_crtc_state *crtc_state)
>   		return;
>   	}
>   
> -	if (crtc_state->cmrr.enable) {
> +	if (crtc_state->vrr.cmrr.enable) {
>   		intel_de_write(display, TRANS_CMRR_M_HI(display, cpu_transcoder),
> -			       upper_32_bits(crtc_state->cmrr.cmrr_m));
> +			       upper_32_bits(crtc_state->vrr.cmrr.cmrr_m));
>   		intel_de_write(display, TRANS_CMRR_M_LO(display, cpu_transcoder),
> -			       lower_32_bits(crtc_state->cmrr.cmrr_m));
> +			       lower_32_bits(crtc_state->vrr.cmrr.cmrr_m));
>   		intel_de_write(display, TRANS_CMRR_N_HI(display, cpu_transcoder),
> -			       upper_32_bits(crtc_state->cmrr.cmrr_n));
> +			       upper_32_bits(crtc_state->vrr.cmrr.cmrr_n));
>   		intel_de_write(display, TRANS_CMRR_N_LO(display, cpu_transcoder),
> -			       lower_32_bits(crtc_state->cmrr.cmrr_n));
> +			       lower_32_bits(crtc_state->vrr.cmrr.cmrr_n));
>   	}
>   
>   	intel_vrr_set_fixed_rr_timings(crtc_state, cpu_transcoder);
> @@ -974,7 +974,7 @@ void intel_vrr_enable(const struct intel_crtc_state *crtc_state)
>   	intel_vrr_enable_dc_balancing(crtc_state);
>   
>   	if (!intel_vrr_always_use_vrr_tg(display))
> -		intel_vrr_tg_enable(crtc_state, crtc_state->cmrr.enable);
> +		intel_vrr_tg_enable(crtc_state, crtc_state->vrr.cmrr.enable);
>   }
>   
>   void intel_vrr_disable(const struct intel_crtc_state *old_crtc_state)
> @@ -1071,12 +1071,12 @@ void intel_vrr_get_config(struct intel_crtc_state *crtc_state)
>   				      TRANS_VRR_CTL(display, cpu_transcoder));
>   
>   	if (HAS_CMRR(display))
> -		crtc_state->cmrr.enable = (trans_vrr_ctl & VRR_CTL_CMRR_ENABLE);
> +		crtc_state->vrr.cmrr.enable = (trans_vrr_ctl & VRR_CTL_CMRR_ENABLE);
>   
> -	if (crtc_state->cmrr.enable) {
> -		crtc_state->cmrr.cmrr_n =
> +	if (crtc_state->vrr.cmrr.enable) {
> +		crtc_state->vrr.cmrr.cmrr_n =
>   			intel_de_read64_2x32(display, TRANS_CMRR_N_LO(display, cpu_transcoder));
> -		crtc_state->cmrr.cmrr_m =
> +		crtc_state->vrr.cmrr.cmrr_m =
>   			intel_de_read64_2x32(display, TRANS_CMRR_M_LO(display, cpu_transcoder));
>   	}
>   

[PATCH v3 3/8] drm/i915/vrr: Compute CMRR fractional timings generically

[Mitul Golani]

Rework the fractional-CMRR computation into a generic,
transcoder-agnostic helper driven by an explicit per-CRTC debugfs
target, replacing the previous disabled, eDP-only code path. Compute
CMRR_M and CMRR_N timings based on the video mode requirement. Note the
CMRR enable path is wired up separately; this patch only lays down the
generic computation.

--v2:
- Derive video_mode locally instead of caching it in persistent
  struct intel_crtc state (Jani, Chaitanya)
- Fix numerator unit in comment: milli-Hz, not kHz (Chaitanya)
- Fix "reqirement" typo and clarify CMRR is not yet enabled in the
  commit message (Chaitanya)
- Fix precision issue while computing M/N ration (Chaitanya)
- Multiplier_m and n naming update to increase readability. (Chaitanya)
- Compute vtotal as it is required to deither as per algo
implementation. (Chaitanya)
- Replace misleading adjusted_pixel_rate to dividend which is somewhat
relatable.

Signed-off-by: Mitul Golani <mitulkumar.ajitkumar.golani@intel.com>
---
 drivers/gpu/drm/i915/display/intel_vrr.c | 128 +++++++++++------------
 1 file changed, 63 insertions(+), 65 deletions(-)

diff --git a/drivers/gpu/drm/i915/display/intel_vrr.c b/drivers/gpu/drm/i915/display/intel_vrr.c
index b36026183399..25ce56d48bb1 100644
--- a/drivers/gpu/drm/i915/display/intel_vrr.c
+++ b/drivers/gpu/drm/i915/display/intel_vrr.c
@@ -27,9 +27,6 @@
 #include "skl_prefill.h"
 #include "skl_watermark.h"
 
-#define FIXED_POINT_PRECISION		100
-#define CMRR_PRECISION_TOLERANCE	10
-
 /*
  * Tunable parameters for DC Balance correction.
  * These are captured based on experimentations.
@@ -191,69 +188,72 @@ int intel_vrr_vmax_vblank_start(const struct intel_crtc_state *crtc_state)
 	return intel_vrr_vmax_vtotal(crtc_state) - crtc_state->vrr.guardband;
 }
 
-static bool
-is_cmrr_frac_required(struct intel_crtc_state *crtc_state)
+static void
+intel_vrr_cmrr_compute_config(struct intel_crtc_state *crtc_state)
 {
 	struct intel_display *display = to_intel_display(crtc_state);
-	int calculated_refresh_k, actual_refresh_k, pixel_clock_per_line;
+	struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc);
 	struct drm_display_mode *adjusted_mode = &crtc_state->hw.adjusted_mode;
+	u64 dividend;
+	int requested_refresh_rate, current_refresh_rate;
+	int rr_multiplier = 1, rr_divider = 1;
+	bool video_mode;
 
-	/* Avoid CMRR for now till we have VRR with fixed timings working */
-	if (!HAS_CMRR(display) || true)
-		return false;
-
-	actual_refresh_k =
-		drm_mode_vrefresh(adjusted_mode) * FIXED_POINT_PRECISION;
-	pixel_clock_per_line =
-		adjusted_mode->crtc_clock * 1000 / adjusted_mode->crtc_htotal;
-	calculated_refresh_k =
-		pixel_clock_per_line * FIXED_POINT_PRECISION / adjusted_mode->crtc_vtotal;
-
-	if ((actual_refresh_k - calculated_refresh_k) < CMRR_PRECISION_TOLERANCE)
-		return false;
-
-	return true;
-}
-
-static unsigned int
-cmrr_get_vtotal(struct intel_crtc_state *crtc_state, bool video_mode_required)
-{
-	int multiplier_m = 1, multiplier_n = 1, vtotal, desired_refresh_rate;
-	u64 adjusted_pixel_rate;
-	struct drm_display_mode *adjusted_mode = &crtc_state->hw.adjusted_mode;
+	if (!HAS_CMRR(display))
+		return;
 
-	desired_refresh_rate = drm_mode_vrefresh(adjusted_mode);
+	/* No CMRR ratio configured through debugfs */
+	if (!crtc->force_cmrr.numerator)
+		return;
 
-	if (video_mode_required) {
-		multiplier_m = 1001;
-		multiplier_n = 1000;
+	/*
+	 * The numerator encodes the requested refresh rate in milli-Hz, so the
+	 * requested refresh rate in Hz is numerator / 1000. It must match the
+	 * refresh rate of the current mode.
+	 */
+	requested_refresh_rate = crtc->force_cmrr.numerator / 1000;
+	current_refresh_rate = drm_mode_vrefresh(adjusted_mode);
+
+	if (requested_refresh_rate != current_refresh_rate) {
+		drm_dbg_kms(display->drm,
+			    "[CRTC:%d:%s] CMRR requested refresh rate %d Hz does not match current mode refresh rate %d Hz\n",
+				crtc->base.base.id, crtc->base.name,
+				requested_refresh_rate, current_refresh_rate);
+		return;
 	}
 
-	crtc_state->vrr.cmrr.cmrr_n = mul_u32_u32(desired_refresh_rate * adjusted_mode->crtc_htotal,
-						  multiplier_n);
-	vtotal = DIV_ROUND_UP_ULL(mul_u32_u32(adjusted_mode->crtc_clock * 1000, multiplier_n),
-				  crtc_state->vrr.cmrr.cmrr_n);
-	adjusted_pixel_rate = mul_u32_u32(adjusted_mode->crtc_clock * 1000, multiplier_m);
-	crtc_state->vrr.cmrr.cmrr_m = do_div(adjusted_pixel_rate, crtc_state->vrr.cmrr.cmrr_n);
-
-	return vtotal;
-}
+	/*
+	 * A 1:1 ratio (denominator == 1000) means no video timing is required
+	 * Any other ratio (e.g. 1000/1001) requires the video timing.
+	 */
+	video_mode = crtc->force_cmrr.denominator != 1000;
+	if (video_mode) {
+		rr_multiplier = 1000;
+		rr_divider = 1001;
+	}
 
-static
-void intel_vrr_compute_cmrr_timings(struct intel_crtc_state *crtc_state)
-{
 	/*
-	 * TODO: Compute precise target refresh rate to determine
-	 * if video_mode_required should be true. Currently set to
-	 * false due to uncertainty about the precise target
-	 * refresh Rate.
+	 * Let pixel_clock_hz = adjusted_mode->crtc_clock * 1000.
+	 *
+	 * cmrr_n = requested_refresh_rate x htotal x rr_multiplier
+	 * cmrr_m = (pixel_clock_hz x scale_m) % cmrr_n
+	 *
+	 * where rr_multiplier/rr_divider = 1000/1001 when the
+	 * video timing is required, else 1/1. The integer vtotal
+	 * term is tracked in SW (it is the programmed mode vtotal)
+	 * while the fractional part represented by cmrr_m/cmrr_n
+	 * is tracked in HW.
 	 */
-	crtc_state->vrr.vmax = cmrr_get_vtotal(crtc_state, false);
-	crtc_state->vrr.vmin = crtc_state->vrr.vmax;
-	crtc_state->vrr.flipline = crtc_state->vrr.vmin;
 
-	crtc_state->vrr.cmrr.enable = true;
-	crtc_state->mode_flags |= I915_MODE_FLAG_VRR;
+	crtc_state->vrr.cmrr.cmrr_n =
+		(mul_u32_u32(crtc->force_cmrr.numerator, adjusted_mode->crtc_htotal) *
+		rr_multiplier) / 1000;
+	dividend = mul_u32_u32(adjusted_mode->crtc_clock, 1000) * rr_divider;
+	adjusted_mode->crtc_vtotal = div64_u64_rem(dividend,
+						   crtc_state->vrr.cmrr.cmrr_n,
+						   &crtc_state->vrr.cmrr.cmrr_m);
+
+	return;
 }
 
 static
@@ -429,8 +429,6 @@ intel_vrr_compute_config(struct intel_crtc_state *crtc_state,
 	struct intel_display *display = to_intel_display(crtc_state);
 	struct intel_connector *connector =
 		to_intel_connector(conn_state->connector);
-	struct intel_dp *intel_dp = intel_attached_dp(connector);
-	bool is_edp = intel_dp_is_edp(intel_dp);
 	struct drm_display_mode *adjusted_mode = &crtc_state->hw.adjusted_mode;
 	int vmin, vmax;
 
@@ -464,12 +462,17 @@ intel_vrr_compute_config(struct intel_crtc_state *crtc_state,
 		vmax = vmin;
 	}
 
-	if (crtc_state->uapi.vrr_enabled && vmin < vmax)
+	if (crtc_state->uapi.vrr_enabled && vmin < vmax) {
 		intel_vrr_compute_vrr_timings(crtc_state, vmin, vmax);
-	else if (is_cmrr_frac_required(crtc_state) && is_edp)
-		intel_vrr_compute_cmrr_timings(crtc_state);
-	else
+	} else {
+		/*
+		 * CMRR is a fixed average Vtotal mode and is only computed on
+		 * the fixed refresh rate path. It is generic across transcoders
+		 * and gated on platform support and a valid debugfs ratio.
+		 */
+		intel_vrr_cmrr_compute_config(crtc_state);
 		intel_vrr_compute_fixed_rr_timings(crtc_state);
+	}
 
 	if (HAS_AS_SDP(display)) {
 		crtc_state->vrr.vsync_start =
@@ -1136,11 +1139,6 @@ void intel_vrr_get_config(struct intel_crtc_state *crtc_state)
 
 	intel_vrr_get_dc_balance_config(crtc_state);
 
-	/*
-	 * #TODO: For Both VRR and CMRR the flag I915_MODE_FLAG_VRR is set for mode_flags.
-	 * Since CMRR is currently disabled, set this flag for VRR for now.
-	 * Need to keep this in mind while re-enabling CMRR.
-	 */
 	if (crtc_state->vrr.enable)
 		crtc_state->mode_flags |= I915_MODE_FLAG_VRR;
 
-- 
2.48.1

Re: [PATCH v3 3/8] drm/i915/vrr: Compute CMRR fractional timings generically

[Borah, Chaitanya Kumar]

On 7/14/2026 4:09 PM, Mitul Golani wrote:
> Rework the fractional-CMRR computation into a generic,
> transcoder-agnostic helper driven by an explicit per-CRTC debugfs
> target, replacing the previous disabled, eDP-only code path. Compute
> CMRR_M and CMRR_N timings based on the video mode requirement. Note the
> CMRR enable path is wired up separately; this patch only lays down the
> generic computation.
> 

mention the logic behind removing the MODE_FLAG

> --v2:
> - Derive video_mode locally instead of caching it in persistent
>    struct intel_crtc state (Jani, Chaitanya)
> - Fix numerator unit in comment: milli-Hz, not kHz (Chaitanya)
> - Fix "reqirement" typo and clarify CMRR is not yet enabled in the
>    commit message (Chaitanya)
> - Fix precision issue while computing M/N ration (Chaitanya)
> - Multiplier_m and n naming update to increase readability. (Chaitanya)
> - Compute vtotal as it is required to deither as per algo
> implementation. (Chaitanya)
> - Replace misleading adjusted_pixel_rate to dividend which is somewhat
> relatable.
> 
> Signed-off-by: Mitul Golani <mitulkumar.ajitkumar.golani@intel.com>
> ---
>   drivers/gpu/drm/i915/display/intel_vrr.c | 128 +++++++++++------------
>   1 file changed, 63 insertions(+), 65 deletions(-)
> 
> diff --git a/drivers/gpu/drm/i915/display/intel_vrr.c b/drivers/gpu/drm/i915/display/intel_vrr.c
> index b36026183399..25ce56d48bb1 100644
> --- a/drivers/gpu/drm/i915/display/intel_vrr.c
> +++ b/drivers/gpu/drm/i915/display/intel_vrr.c
> @@ -27,9 +27,6 @@
>   #include "skl_prefill.h"
>   #include "skl_watermark.h"
>   
> -#define FIXED_POINT_PRECISION		100
> -#define CMRR_PRECISION_TOLERANCE	10
> -
>   /*
>    * Tunable parameters for DC Balance correction.
>    * These are captured based on experimentations.
> @@ -191,69 +188,72 @@ int intel_vrr_vmax_vblank_start(const struct intel_crtc_state *crtc_state)
>   	return intel_vrr_vmax_vtotal(crtc_state) - crtc_state->vrr.guardband;
>   }
>   
> -static bool
> -is_cmrr_frac_required(struct intel_crtc_state *crtc_state)
> +static void
> +intel_vrr_cmrr_compute_config(struct intel_crtc_state *crtc_state)
>   {
>   	struct intel_display *display = to_intel_display(crtc_state);
> -	int calculated_refresh_k, actual_refresh_k, pixel_clock_per_line;
> +	struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc);
>   	struct drm_display_mode *adjusted_mode = &crtc_state->hw.adjusted_mode;
> +	u64 dividend;
> +	int requested_refresh_rate, current_refresh_rate;
> +	int rr_multiplier = 1, rr_divider = 1;
> +	bool video_mode;
>   
> -	/* Avoid CMRR for now till we have VRR with fixed timings working */
> -	if (!HAS_CMRR(display) || true)
> -		return false;
> -
> -	actual_refresh_k =
> -		drm_mode_vrefresh(adjusted_mode) * FIXED_POINT_PRECISION;
> -	pixel_clock_per_line =
> -		adjusted_mode->crtc_clock * 1000 / adjusted_mode->crtc_htotal;
> -	calculated_refresh_k =
> -		pixel_clock_per_line * FIXED_POINT_PRECISION / adjusted_mode->crtc_vtotal;
> -
> -	if ((actual_refresh_k - calculated_refresh_k) < CMRR_PRECISION_TOLERANCE)
> -		return false;
> -
> -	return true;
> -}
> -
> -static unsigned int
> -cmrr_get_vtotal(struct intel_crtc_state *crtc_state, bool video_mode_required)
> -{
> -	int multiplier_m = 1, multiplier_n = 1, vtotal, desired_refresh_rate;
> -	u64 adjusted_pixel_rate;
> -	struct drm_display_mode *adjusted_mode = &crtc_state->hw.adjusted_mode;
> +	if (!HAS_CMRR(display))
> +		return;

We compute CMRR for DISPLAY_VER >= 20 (gated on HAS_CMRR), but looking 
at later patches in the series, CMRR only gets enabled when 
intel_vrr_always_use_vrr_tg() is true, which is DISPLAY_VER >= 30. On < 
30 the CMRR_ENABLE bit gets armed via the TRANS_CMRR_N_HI write but is 
then cleared by the subsequent TRANS_VRR_CTL write in 
intel_vrr_set_transcoder_timings() (it carries neither VRR_ENABLE nor 
CMRR_ENABLE), and intel_vrr_tg_enable() never runs to restore it since 
vrr.enable isn't set for CMRR. So CMRR ends up computed but inactive on 
< 30.

This needs a closer look.

>   
> -	desired_refresh_rate = drm_mode_vrefresh(adjusted_mode);
> +	/* No CMRR ratio configured through debugfs */
> +	if (!crtc->force_cmrr.numerator)
> +		return;
>   
> -	if (video_mode_required) {
> -		multiplier_m = 1001;
> -		multiplier_n = 1000;
> +	/*
> +	 * The numerator encodes the requested refresh rate in milli-Hz, so the
> +	 * requested refresh rate in Hz is numerator / 1000. It must match the
> +	 * refresh rate of the current mode.
> +	 */
> +	requested_refresh_rate = crtc->force_cmrr.numerator / 1000;
> +	current_refresh_rate = drm_mode_vrefresh(adjusted_mode);
> +
> +	if (requested_refresh_rate != current_refresh_rate) {
> +		drm_dbg_kms(display->drm,
> +			    "[CRTC:%d:%s] CMRR requested refresh rate %d Hz does not match current mode refresh rate %d Hz\n",
> +				crtc->base.base.id, crtc->base.name,
> +				requested_refresh_rate, current_refresh_rate);
> +		return;
>   	}
>   
> -	crtc_state->vrr.cmrr.cmrr_n = mul_u32_u32(desired_refresh_rate * adjusted_mode->crtc_htotal,
> -						  multiplier_n);
> -	vtotal = DIV_ROUND_UP_ULL(mul_u32_u32(adjusted_mode->crtc_clock * 1000, multiplier_n),
> -				  crtc_state->vrr.cmrr.cmrr_n);
> -	adjusted_pixel_rate = mul_u32_u32(adjusted_mode->crtc_clock * 1000, multiplier_m);
> -	crtc_state->vrr.cmrr.cmrr_m = do_div(adjusted_pixel_rate, crtc_state->vrr.cmrr.cmrr_n);
> -
> -	return vtotal;
> -}
> +	/*
> +	 * A 1:1 ratio (denominator == 1000) means no video timing is required
> +	 * Any other ratio (e.g. 1000/1001) requires the video timing.
> +	 */
> +	video_mode = crtc->force_cmrr.denominator != 1000;
> +	if (video_mode) {
> +		rr_multiplier = 1000;
> +		rr_divider = 1001;
> +	}
>   
> -static
> -void intel_vrr_compute_cmrr_timings(struct intel_crtc_state *crtc_state)
> -{
>   	/*
> -	 * TODO: Compute precise target refresh rate to determine
> -	 * if video_mode_required should be true. Currently set to
> -	 * false due to uncertainty about the precise target
> -	 * refresh Rate.
> +	 * Let pixel_clock_hz = adjusted_mode->crtc_clock * 1000.
> +	 *
> +	 * cmrr_n = requested_refresh_rate x htotal x rr_multiplier
> +	 * cmrr_m = (pixel_clock_hz x scale_m) % cmrr_n
> +	 *
> +	 * where rr_multiplier/rr_divider = 1000/1001 when the
> +	 * video timing is required, else 1/1. The integer vtotal
> +	 * term is tracked in SW (it is the programmed mode vtotal)
> +	 * while the fractional part represented by cmrr_m/cmrr_n
> +	 * is tracked in HW.
>   	 */
> -	crtc_state->vrr.vmax = cmrr_get_vtotal(crtc_state, false);
> -	crtc_state->vrr.vmin = crtc_state->vrr.vmax;
> -	crtc_state->vrr.flipline = crtc_state->vrr.vmin;
>   
> -	crtc_state->vrr.cmrr.enable = true;
> -	crtc_state->mode_flags |= I915_MODE_FLAG_VRR;
> +	crtc_state->vrr.cmrr.cmrr_n =
> +		(mul_u32_u32(crtc->force_cmrr.numerator, adjusted_mode->crtc_htotal) *
> +		rr_multiplier) / 1000;
> +	dividend = mul_u32_u32(adjusted_mode->crtc_clock, 1000) * rr_divider;

By only using the numerator here you are never calculating the desired 
refresh rate.

> +	adjusted_mode->crtc_vtotal = div64_u64_rem(dividend,
> +						   crtc_state->vrr.cmrr.cmrr_n,
> +						   &crtc_state->vrr.cmrr.cmrr_m);
> +
> +	return;

redundant

>   }
>   
>   static
> @@ -429,8 +429,6 @@ intel_vrr_compute_config(struct intel_crtc_state *crtc_state,
>   	struct intel_display *display = to_intel_display(crtc_state);
>   	struct intel_connector *connector =
>   		to_intel_connector(conn_state->connector);
> -	struct intel_dp *intel_dp = intel_attached_dp(connector);
> -	bool is_edp = intel_dp_is_edp(intel_dp);
>   	struct drm_display_mode *adjusted_mode = &crtc_state->hw.adjusted_mode;
>   	int vmin, vmax;
>   
> @@ -464,12 +462,17 @@ intel_vrr_compute_config(struct intel_crtc_state *crtc_state,
>   		vmax = vmin;
>   	}
>   
> -	if (crtc_state->uapi.vrr_enabled && vmin < vmax)
> +	if (crtc_state->uapi.vrr_enabled && vmin < vmax) {
>   		intel_vrr_compute_vrr_timings(crtc_state, vmin, vmax);
> -	else if (is_cmrr_frac_required(crtc_state) && is_edp)
> -		intel_vrr_compute_cmrr_timings(crtc_state);
> -	else
> +	} else {
> +		/*
> +		 * CMRR is a fixed average Vtotal mode and is only computed on
> +		 * the fixed refresh rate path. It is generic across transcoders
> +		 * and gated on platform support and a valid debugfs ratio.
> +		 */
> +		intel_vrr_cmrr_compute_config(crtc_state);
>   		intel_vrr_compute_fixed_rr_timings(crtc_state);
> +	}
>   
>   	if (HAS_AS_SDP(display)) {
>   		crtc_state->vrr.vsync_start =
> @@ -1136,11 +1139,6 @@ void intel_vrr_get_config(struct intel_crtc_state *crtc_state)
>   
>   	intel_vrr_get_dc_balance_config(crtc_state);
>   
> -	/*
> -	 * #TODO: For Both VRR and CMRR the flag I915_MODE_FLAG_VRR is set for mode_flags.
> -	 * Since CMRR is currently disabled, set this flag for VRR for now.
> -	 * Need to keep this in mind while re-enabling CMRR.
> -	 */
>   	if (crtc_state->vrr.enable)
>   		crtc_state->mode_flags |= I915_MODE_FLAG_VRR;
>   

RE: [PATCH v3 3/8] drm/i915/vrr: Compute CMRR fractional timings generically

[Golani, Mitulkumar Ajitkumar]

Thanks for the review Chaitanya,


> -----Original Message-----
> From: Borah, Chaitanya Kumar <chaitanya.kumar.borah@intel.com>
> Sent: 15 July 2026 18:44
> To: Golani, Mitulkumar Ajitkumar <mitulkumar.ajitkumar.golani@intel.com>;
> intel-gfx@lists.freedesktop.org
> Cc: intel-xe@lists.freedesktop.org; Shankar, Uma <uma.shankar@intel.com>;
> Nautiyal, Ankit K <ankit.k.nautiyal@intel.com>
> Subject: Re: [PATCH v3 3/8] drm/i915/vrr: Compute CMRR fractional timings
> generically
> 
> 
> 
> On 7/14/2026 4:09 PM, Mitul Golani wrote:
> > Rework the fractional-CMRR computation into a generic,
> > transcoder-agnostic helper driven by an explicit per-CRTC debugfs
> > target, replacing the previous disabled, eDP-only code path. Compute
> > CMRR_M and CMRR_N timings based on the video mode requirement.
> Note
> > the CMRR enable path is wired up separately; this patch only lays down
> > the generic computation.
> >
> 
> mention the logic behind removing the MODE_FLAG

Applied your suggestion. Will be addressed in v4

> 
> > --v2:
> > - Derive video_mode locally instead of caching it in persistent
> >    struct intel_crtc state (Jani, Chaitanya)
> > - Fix numerator unit in comment: milli-Hz, not kHz (Chaitanya)
> > - Fix "reqirement" typo and clarify CMRR is not yet enabled in the
> >    commit message (Chaitanya)
> > - Fix precision issue while computing M/N ration (Chaitanya)
> > - Multiplier_m and n naming update to increase readability.
> > (Chaitanya)
> > - Compute vtotal as it is required to deither as per algo
> > implementation. (Chaitanya)
> > - Replace misleading adjusted_pixel_rate to dividend which is somewhat
> > relatable.
> >
> > Signed-off-by: Mitul Golani <mitulkumar.ajitkumar.golani@intel.com>
> > ---
> >   drivers/gpu/drm/i915/display/intel_vrr.c | 128 +++++++++++------------
> >   1 file changed, 63 insertions(+), 65 deletions(-)
> >
> > diff --git a/drivers/gpu/drm/i915/display/intel_vrr.c
> > b/drivers/gpu/drm/i915/display/intel_vrr.c
> > index b36026183399..25ce56d48bb1 100644
> > --- a/drivers/gpu/drm/i915/display/intel_vrr.c
> > +++ b/drivers/gpu/drm/i915/display/intel_vrr.c
> > @@ -27,9 +27,6 @@
> >   #include "skl_prefill.h"
> >   #include "skl_watermark.h"
> >
> > -#define FIXED_POINT_PRECISION		100
> > -#define CMRR_PRECISION_TOLERANCE	10
> > -
> >   /*
> >    * Tunable parameters for DC Balance correction.
> >    * These are captured based on experimentations.
> > @@ -191,69 +188,72 @@ int intel_vrr_vmax_vblank_start(const struct
> intel_crtc_state *crtc_state)
> >   	return intel_vrr_vmax_vtotal(crtc_state) - crtc_state->vrr.guardband;
> >   }
> >
> > -static bool
> > -is_cmrr_frac_required(struct intel_crtc_state *crtc_state)
> > +static void
> > +intel_vrr_cmrr_compute_config(struct intel_crtc_state *crtc_state)
> >   {
> >   	struct intel_display *display = to_intel_display(crtc_state);
> > -	int calculated_refresh_k, actual_refresh_k, pixel_clock_per_line;
> > +	struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc);
> >   	struct drm_display_mode *adjusted_mode =
> > &crtc_state->hw.adjusted_mode;
> > +	u64 dividend;
> > +	int requested_refresh_rate, current_refresh_rate;
> > +	int rr_multiplier = 1, rr_divider = 1;
> > +	bool video_mode;
> >
> > -	/* Avoid CMRR for now till we have VRR with fixed timings working */
> > -	if (!HAS_CMRR(display) || true)
> > -		return false;
> > -
> > -	actual_refresh_k =
> > -		drm_mode_vrefresh(adjusted_mode) *
> FIXED_POINT_PRECISION;
> > -	pixel_clock_per_line =
> > -		adjusted_mode->crtc_clock * 1000 / adjusted_mode-
> >crtc_htotal;
> > -	calculated_refresh_k =
> > -		pixel_clock_per_line * FIXED_POINT_PRECISION /
> adjusted_mode->crtc_vtotal;
> > -
> > -	if ((actual_refresh_k - calculated_refresh_k) <
> CMRR_PRECISION_TOLERANCE)
> > -		return false;
> > -
> > -	return true;
> > -}
> > -
> > -static unsigned int
> > -cmrr_get_vtotal(struct intel_crtc_state *crtc_state, bool
> > video_mode_required) -{
> > -	int multiplier_m = 1, multiplier_n = 1, vtotal, desired_refresh_rate;
> > -	u64 adjusted_pixel_rate;
> > -	struct drm_display_mode *adjusted_mode = &crtc_state-
> >hw.adjusted_mode;
> > +	if (!HAS_CMRR(display))
> > +		return;
> 
> We compute CMRR for DISPLAY_VER >= 20 (gated on HAS_CMRR), but looking
> at later patches in the series, CMRR only gets enabled when
> intel_vrr_always_use_vrr_tg() is true, which is DISPLAY_VER >= 30. On <
> 30 the CMRR_ENABLE bit gets armed via the TRANS_CMRR_N_HI write but is
> then cleared by the subsequent TRANS_VRR_CTL write in
> intel_vrr_set_transcoder_timings() (it carries neither VRR_ENABLE nor
> CMRR_ENABLE), and intel_vrr_tg_enable() never runs to restore it since
> vrr.enable isn't set for CMRR. So CMRR ends up computed but inactive on <
> 30.
> 
> This needs a closer look.

As, had discussion offline, we will enable CMRR from the platform when VRR timing generator is also enabled.

So, will need to add additional check intel_vrr_always_use_vrr_tg. I will comment this into code as well so that can be documented in-place. 

So with this addition, patch #1 and #2 will also needs this check to make sure we have correct state programmed.

I will add this change with v4

Thanks

> 
> >
> > -	desired_refresh_rate = drm_mode_vrefresh(adjusted_mode);
> > +	/* No CMRR ratio configured through debugfs */
> > +	if (!crtc->force_cmrr.numerator)
> > +		return;
> >
> > -	if (video_mode_required) {
> > -		multiplier_m = 1001;
> > -		multiplier_n = 1000;
> > +	/*
> > +	 * The numerator encodes the requested refresh rate in milli-Hz, so
> the
> > +	 * requested refresh rate in Hz is numerator / 1000. It must match the
> > +	 * refresh rate of the current mode.
> > +	 */
> > +	requested_refresh_rate = crtc->force_cmrr.numerator / 1000;
> > +	current_refresh_rate = drm_mode_vrefresh(adjusted_mode);
> > +
> > +	if (requested_refresh_rate != current_refresh_rate) {
> > +		drm_dbg_kms(display->drm,
> > +			    "[CRTC:%d:%s] CMRR requested refresh rate %d Hz
> does not match current mode refresh rate %d Hz\n",
> > +				crtc->base.base.id, crtc->base.name,
> > +				requested_refresh_rate,
> current_refresh_rate);
> > +		return;
> >   	}
> >
> > -	crtc_state->vrr.cmrr.cmrr_n = mul_u32_u32(desired_refresh_rate *
> adjusted_mode->crtc_htotal,
> > -						  multiplier_n);
> > -	vtotal = DIV_ROUND_UP_ULL(mul_u32_u32(adjusted_mode-
> >crtc_clock * 1000, multiplier_n),
> > -				  crtc_state->vrr.cmrr.cmrr_n);
> > -	adjusted_pixel_rate = mul_u32_u32(adjusted_mode->crtc_clock *
> 1000, multiplier_m);
> > -	crtc_state->vrr.cmrr.cmrr_m = do_div(adjusted_pixel_rate, crtc_state-
> >vrr.cmrr.cmrr_n);
> > -
> > -	return vtotal;
> > -}
> > +	/*
> > +	 * A 1:1 ratio (denominator == 1000) means no video timing is
> required
> > +	 * Any other ratio (e.g. 1000/1001) requires the video timing.
> > +	 */
> > +	video_mode = crtc->force_cmrr.denominator != 1000;
> > +	if (video_mode) {
> > +		rr_multiplier = 1000;
> > +		rr_divider = 1001;
> > +	}
> >
> > -static
> > -void intel_vrr_compute_cmrr_timings(struct intel_crtc_state
> > *crtc_state) -{
> >   	/*
> > -	 * TODO: Compute precise target refresh rate to determine
> > -	 * if video_mode_required should be true. Currently set to
> > -	 * false due to uncertainty about the precise target
> > -	 * refresh Rate.
> > +	 * Let pixel_clock_hz = adjusted_mode->crtc_clock * 1000.
> > +	 *
> > +	 * cmrr_n = requested_refresh_rate x htotal x rr_multiplier
> > +	 * cmrr_m = (pixel_clock_hz x scale_m) % cmrr_n
> > +	 *
> > +	 * where rr_multiplier/rr_divider = 1000/1001 when the
> > +	 * video timing is required, else 1/1. The integer vtotal
> > +	 * term is tracked in SW (it is the programmed mode vtotal)
> > +	 * while the fractional part represented by cmrr_m/cmrr_n
> > +	 * is tracked in HW.
> >   	 */
> > -	crtc_state->vrr.vmax = cmrr_get_vtotal(crtc_state, false);
> > -	crtc_state->vrr.vmin = crtc_state->vrr.vmax;
> > -	crtc_state->vrr.flipline = crtc_state->vrr.vmin;
> >
> > -	crtc_state->vrr.cmrr.enable = true;
> > -	crtc_state->mode_flags |= I915_MODE_FLAG_VRR;
> > +	crtc_state->vrr.cmrr.cmrr_n =
> > +		(mul_u32_u32(crtc->force_cmrr.numerator, adjusted_mode-
> >crtc_htotal) *
> > +		rr_multiplier) / 1000;
> > +	dividend = mul_u32_u32(adjusted_mode->crtc_clock, 1000) *
> > +rr_divider;
> 
> By only using the numerator here you are never calculating the desired
> refresh rate.


Good point. I will address this in v4,

As we discussed, this basically we need to divide with denominator instead of hardcoded value, "1000"

Thanks


> 
> > +	adjusted_mode->crtc_vtotal = div64_u64_rem(dividend,
> > +						   crtc_state->vrr.cmrr.cmrr_n,
> > +						   &crtc_state-
> >vrr.cmrr.cmrr_m);
> > +
> > +	return;
> 
> redundant

Good point. I will address this in v4.

> 
> >   }
> >
> >   static
> > @@ -429,8 +429,6 @@ intel_vrr_compute_config(struct intel_crtc_state
> *crtc_state,
> >   	struct intel_display *display = to_intel_display(crtc_state);
> >   	struct intel_connector *connector =
> >   		to_intel_connector(conn_state->connector);
> > -	struct intel_dp *intel_dp = intel_attached_dp(connector);
> > -	bool is_edp = intel_dp_is_edp(intel_dp);
> >   	struct drm_display_mode *adjusted_mode = &crtc_state-
> >hw.adjusted_mode;
> >   	int vmin, vmax;
> >
> > @@ -464,12 +462,17 @@ intel_vrr_compute_config(struct intel_crtc_state
> *crtc_state,
> >   		vmax = vmin;
> >   	}
> >
> > -	if (crtc_state->uapi.vrr_enabled && vmin < vmax)
> > +	if (crtc_state->uapi.vrr_enabled && vmin < vmax) {
> >   		intel_vrr_compute_vrr_timings(crtc_state, vmin, vmax);
> > -	else if (is_cmrr_frac_required(crtc_state) && is_edp)
> > -		intel_vrr_compute_cmrr_timings(crtc_state);
> > -	else
> > +	} else {
> > +		/*
> > +		 * CMRR is a fixed average Vtotal mode and is only computed
> on
> > +		 * the fixed refresh rate path. It is generic across transcoders
> > +		 * and gated on platform support and a valid debugfs ratio.
> > +		 */
> > +		intel_vrr_cmrr_compute_config(crtc_state);
> >   		intel_vrr_compute_fixed_rr_timings(crtc_state);
> > +	}
> >
> >   	if (HAS_AS_SDP(display)) {
> >   		crtc_state->vrr.vsync_start =
> > @@ -1136,11 +1139,6 @@ void intel_vrr_get_config(struct
> > intel_crtc_state *crtc_state)
> >
> >   	intel_vrr_get_dc_balance_config(crtc_state);
> >
> > -	/*
> > -	 * #TODO: For Both VRR and CMRR the flag I915_MODE_FLAG_VRR is
> set for mode_flags.
> > -	 * Since CMRR is currently disabled, set this flag for VRR for now.
> > -	 * Need to keep this in mind while re-enabling CMRR.
> > -	 */
> >   	if (crtc_state->vrr.enable)
> >   		crtc_state->mode_flags |= I915_MODE_FLAG_VRR;
> >

[PATCH v3 4/8] drm/i915/vrr: Dump CMRR state in the crtc state dump

[Mitul Golani]

Add crtc state dump for CMRR.

--v2:
- Remove video mode state checker.

Signed-off-by: Mitul Golani <mitulkumar.ajitkumar.golani@intel.com>
---
 drivers/gpu/drm/i915/display/intel_crtc_state_dump.c | 3 +++
 1 file changed, 3 insertions(+)

diff --git a/drivers/gpu/drm/i915/display/intel_crtc_state_dump.c b/drivers/gpu/drm/i915/display/intel_crtc_state_dump.c
index 4493483f10a9..ad4f362e0c09 100644
--- a/drivers/gpu/drm/i915/display/intel_crtc_state_dump.c
+++ b/drivers/gpu/drm/i915/display/intel_crtc_state_dump.c
@@ -311,6 +311,9 @@ void intel_crtc_state_dump(const struct intel_crtc_state *pipe_config,
 		   pipe_config->vrr.dc_balance.max_increase,
 		   pipe_config->vrr.dc_balance.max_decrease,
 		   pipe_config->vrr.dc_balance.vblank_target);
+	drm_printf(&p, "cmrr: %s, cmrr_m: %llu, cmrr_n: %llu\n",
+		   str_yes_no(pipe_config->vrr.cmrr.enable),
+		   pipe_config->vrr.cmrr.cmrr_m, pipe_config->vrr.cmrr.cmrr_n);
 
 	drm_printf(&p, "requested mode: " DRM_MODE_FMT "\n",
 		   DRM_MODE_ARG(&pipe_config->hw.mode));
-- 
2.48.1

Re: [PATCH v3 4/8] drm/i915/vrr: Dump CMRR state in the crtc state dump

[Borah, Chaitanya Kumar]

On 7/14/2026 4:09 PM, Mitul Golani wrote:
> Add crtc state dump for CMRR.
> 
> --v2:
> - Remove video mode state checker.
> 

LGTM
Reviewed-by: Chaitanya Kumar Borah <chaitanya.kumar.borah@intel.com>

> Signed-off-by: Mitul Golani <mitulkumar.ajitkumar.golani@intel.com>
> ---
>   drivers/gpu/drm/i915/display/intel_crtc_state_dump.c | 3 +++
>   1 file changed, 3 insertions(+)
> 
> diff --git a/drivers/gpu/drm/i915/display/intel_crtc_state_dump.c b/drivers/gpu/drm/i915/display/intel_crtc_state_dump.c
> index 4493483f10a9..ad4f362e0c09 100644
> --- a/drivers/gpu/drm/i915/display/intel_crtc_state_dump.c
> +++ b/drivers/gpu/drm/i915/display/intel_crtc_state_dump.c
> @@ -311,6 +311,9 @@ void intel_crtc_state_dump(const struct intel_crtc_state *pipe_config,
>   		   pipe_config->vrr.dc_balance.max_increase,
>   		   pipe_config->vrr.dc_balance.max_decrease,
>   		   pipe_config->vrr.dc_balance.vblank_target);
> +	drm_printf(&p, "cmrr: %s, cmrr_m: %llu, cmrr_n: %llu\n",
> +		   str_yes_no(pipe_config->vrr.cmrr.enable),
> +		   pipe_config->vrr.cmrr.cmrr_m, pipe_config->vrr.cmrr.cmrr_n);
>   
>   	drm_printf(&p, "requested mode: " DRM_MODE_FMT "\n",
>   		   DRM_MODE_ARG(&pipe_config->hw.mode));

[PATCH v3 5/8] drm/i915/vrr: Move CMRR hw registers to fix refresh rate path

[Mitul Golani]

Move CMRR register writes to fix refresh rate register write path
to consolidate with fix refresh rate implementation.

Signed-off-by: Mitul Golani <mitulkumar.ajitkumar.golani@intel.com>
---
 drivers/gpu/drm/i915/display/intel_vrr.c | 22 +++++++++++-----------
 1 file changed, 11 insertions(+), 11 deletions(-)

diff --git a/drivers/gpu/drm/i915/display/intel_vrr.c b/drivers/gpu/drm/i915/display/intel_vrr.c
index 25ce56d48bb1..95c7b0c05ec3 100644
--- a/drivers/gpu/drm/i915/display/intel_vrr.c
+++ b/drivers/gpu/drm/i915/display/intel_vrr.c
@@ -337,6 +337,17 @@ void intel_vrr_set_fixed_rr_timings(const struct intel_crtc_state *crtc_state,
 	if (!intel_vrr_possible(crtc_state))
 		return;
 
+	if (crtc_state->vrr.cmrr.enable) {
+		intel_de_write(display, TRANS_CMRR_M_HI(display, transcoder),
+			       upper_32_bits(crtc_state->vrr.cmrr.cmrr_m));
+		intel_de_write(display, TRANS_CMRR_M_LO(display, transcoder),
+			       lower_32_bits(crtc_state->vrr.cmrr.cmrr_m));
+		intel_de_write(display, TRANS_CMRR_N_HI(display, transcoder),
+			       upper_32_bits(crtc_state->vrr.cmrr.cmrr_n));
+		intel_de_write(display, TRANS_CMRR_N_LO(display, transcoder),
+			       lower_32_bits(crtc_state->vrr.cmrr.cmrr_n));
+	}
+
 	intel_de_write(display, TRANS_VRR_VMIN(display, transcoder),
 		       intel_vrr_fixed_rr_hw_vmin(crtc_state) - 1);
 	intel_de_write(display, TRANS_VRR_VMAX(display, transcoder),
@@ -648,17 +659,6 @@ void intel_vrr_set_transcoder_timings(const struct intel_crtc_state *crtc_state)
 		return;
 	}
 
-	if (crtc_state->vrr.cmrr.enable) {
-		intel_de_write(display, TRANS_CMRR_M_HI(display, cpu_transcoder),
-			       upper_32_bits(crtc_state->vrr.cmrr.cmrr_m));
-		intel_de_write(display, TRANS_CMRR_M_LO(display, cpu_transcoder),
-			       lower_32_bits(crtc_state->vrr.cmrr.cmrr_m));
-		intel_de_write(display, TRANS_CMRR_N_HI(display, cpu_transcoder),
-			       upper_32_bits(crtc_state->vrr.cmrr.cmrr_n));
-		intel_de_write(display, TRANS_CMRR_N_LO(display, cpu_transcoder),
-			       lower_32_bits(crtc_state->vrr.cmrr.cmrr_n));
-	}
-
 	intel_vrr_set_fixed_rr_timings(crtc_state, cpu_transcoder);
 	intel_cmtg_set_vrr_timings(crtc_state);
 
-- 
2.48.1

Re: [PATCH v3 5/8] drm/i915/vrr: Move CMRR hw registers to fix refresh rate path

[Borah, Chaitanya Kumar]

On 7/14/2026 4:09 PM, Mitul Golani wrote:
> Move CMRR register writes to fix refresh rate register write path
> to consolidate with fix refresh rate implementation.
> 
> Signed-off-by: Mitul Golani <mitulkumar.ajitkumar.golani@intel.com>
> ---
>   drivers/gpu/drm/i915/display/intel_vrr.c | 22 +++++++++++-----------
>   1 file changed, 11 insertions(+), 11 deletions(-)
> 
> diff --git a/drivers/gpu/drm/i915/display/intel_vrr.c b/drivers/gpu/drm/i915/display/intel_vrr.c
> index 25ce56d48bb1..95c7b0c05ec3 100644
> --- a/drivers/gpu/drm/i915/display/intel_vrr.c
> +++ b/drivers/gpu/drm/i915/display/intel_vrr.c
> @@ -337,6 +337,17 @@ void intel_vrr_set_fixed_rr_timings(const struct intel_crtc_state *crtc_state,
>   	if (!intel_vrr_possible(crtc_state))
>   		return;
>   
> +	if (crtc_state->vrr.cmrr.enable) {
> +		intel_de_write(display, TRANS_CMRR_M_HI(display, transcoder),
> +			       upper_32_bits(crtc_state->vrr.cmrr.cmrr_m));
> +		intel_de_write(display, TRANS_CMRR_M_LO(display, transcoder),
> +			       lower_32_bits(crtc_state->vrr.cmrr.cmrr_m));
> +		intel_de_write(display, TRANS_CMRR_N_HI(display, transcoder),
> +			       upper_32_bits(crtc_state->vrr.cmrr.cmrr_n));
> +		intel_de_write(display, TRANS_CMRR_N_LO(display, transcoder),
> +			       lower_32_bits(crtc_state->vrr.cmrr.cmrr_n));

Shouldn't TRANS_CMRR_N_HI be the last register to be written.

> +	}
> +
>   	intel_de_write(display, TRANS_VRR_VMIN(display, transcoder),
>   		       intel_vrr_fixed_rr_hw_vmin(crtc_state) - 1);
>   	intel_de_write(display, TRANS_VRR_VMAX(display, transcoder),
> @@ -648,17 +659,6 @@ void intel_vrr_set_transcoder_timings(const struct intel_crtc_state *crtc_state)
>   		return;
>   	}
>   
> -	if (crtc_state->vrr.cmrr.enable) {
> -		intel_de_write(display, TRANS_CMRR_M_HI(display, cpu_transcoder),
> -			       upper_32_bits(crtc_state->vrr.cmrr.cmrr_m));
> -		intel_de_write(display, TRANS_CMRR_M_LO(display, cpu_transcoder),
> -			       lower_32_bits(crtc_state->vrr.cmrr.cmrr_m));
> -		intel_de_write(display, TRANS_CMRR_N_HI(display, cpu_transcoder),
> -			       upper_32_bits(crtc_state->vrr.cmrr.cmrr_n));
> -		intel_de_write(display, TRANS_CMRR_N_LO(display, cpu_transcoder),
> -			       lower_32_bits(crtc_state->vrr.cmrr.cmrr_n));
> -	}
> -
>   	intel_vrr_set_fixed_rr_timings(crtc_state, cpu_transcoder);
>   	intel_cmtg_set_vrr_timings(crtc_state);
>   

RE: [PATCH v3 5/8] drm/i915/vrr: Move CMRR hw registers to fix refresh rate path

[Golani, Mitulkumar Ajitkumar]

> -----Original Message-----
> From: Borah, Chaitanya Kumar <chaitanya.kumar.borah@intel.com>
> Sent: 15 July 2026 18:45
> To: Golani, Mitulkumar Ajitkumar <mitulkumar.ajitkumar.golani@intel.com>;
> intel-gfx@lists.freedesktop.org
> Cc: intel-xe@lists.freedesktop.org; Shankar, Uma <uma.shankar@intel.com>;
> Nautiyal, Ankit K <ankit.k.nautiyal@intel.com>
> Subject: Re: [PATCH v3 5/8] drm/i915/vrr: Move CMRR hw registers to fix
> refresh rate path
> 
> 
> 
> On 7/14/2026 4:09 PM, Mitul Golani wrote:
> > Move CMRR register writes to fix refresh rate register write path to
> > consolidate with fix refresh rate implementation.
> >
> > Signed-off-by: Mitul Golani <mitulkumar.ajitkumar.golani@intel.com>
> > ---
> >   drivers/gpu/drm/i915/display/intel_vrr.c | 22 +++++++++++-----------
> >   1 file changed, 11 insertions(+), 11 deletions(-)
> >
> > diff --git a/drivers/gpu/drm/i915/display/intel_vrr.c
> > b/drivers/gpu/drm/i915/display/intel_vrr.c
> > index 25ce56d48bb1..95c7b0c05ec3 100644
> > --- a/drivers/gpu/drm/i915/display/intel_vrr.c
> > +++ b/drivers/gpu/drm/i915/display/intel_vrr.c
> > @@ -337,6 +337,17 @@ void intel_vrr_set_fixed_rr_timings(const struct
> intel_crtc_state *crtc_state,
> >   	if (!intel_vrr_possible(crtc_state))
> >   		return;
> >
> > +	if (crtc_state->vrr.cmrr.enable) {
> > +		intel_de_write(display, TRANS_CMRR_M_HI(display,
> transcoder),
> > +			       upper_32_bits(crtc_state->vrr.cmrr.cmrr_m));
> > +		intel_de_write(display, TRANS_CMRR_M_LO(display,
> transcoder),
> > +			       lower_32_bits(crtc_state->vrr.cmrr.cmrr_m));
> > +		intel_de_write(display, TRANS_CMRR_N_HI(display,
> transcoder),
> > +			       upper_32_bits(crtc_state->vrr.cmrr.cmrr_n));
> > +		intel_de_write(display, TRANS_CMRR_N_LO(display,
> transcoder),
> > +			       lower_32_bits(crtc_state->vrr.cmrr.cmrr_n));
> 
> Shouldn't TRANS_CMRR_N_HI be the last register to be written.

No functional change has done, just moved to fix refresh rate path. 

In later patches when actual enable/disable sequence is computed, there suggested changes are applied.

Thanks

> 
> > +	}
> > +
> >   	intel_de_write(display, TRANS_VRR_VMIN(display, transcoder),
> >   		       intel_vrr_fixed_rr_hw_vmin(crtc_state) - 1);
> >   	intel_de_write(display, TRANS_VRR_VMAX(display, transcoder), @@
> > -648,17 +659,6 @@ void intel_vrr_set_transcoder_timings(const struct
> intel_crtc_state *crtc_state)
> >   		return;
> >   	}
> >
> > -	if (crtc_state->vrr.cmrr.enable) {
> > -		intel_de_write(display, TRANS_CMRR_M_HI(display,
> cpu_transcoder),
> > -			       upper_32_bits(crtc_state->vrr.cmrr.cmrr_m));
> > -		intel_de_write(display, TRANS_CMRR_M_LO(display,
> cpu_transcoder),
> > -			       lower_32_bits(crtc_state->vrr.cmrr.cmrr_m));
> > -		intel_de_write(display, TRANS_CMRR_N_HI(display,
> cpu_transcoder),
> > -			       upper_32_bits(crtc_state->vrr.cmrr.cmrr_n));
> > -		intel_de_write(display, TRANS_CMRR_N_LO(display,
> cpu_transcoder),
> > -			       lower_32_bits(crtc_state->vrr.cmrr.cmrr_n));
> > -	}
> > -
> >   	intel_vrr_set_fixed_rr_timings(crtc_state, cpu_transcoder);
> >   	intel_cmtg_set_vrr_timings(crtc_state);
> >

Re: [PATCH v3 5/8] drm/i915/vrr: Move CMRR hw registers to fix refresh rate path

[Borah, Chaitanya Kumar]

On 7/16/2026 5:32 PM, Golani, Mitulkumar Ajitkumar wrote:
> 
> 
>> -----Original Message-----
>> From: Borah, Chaitanya Kumar <chaitanya.kumar.borah@intel.com>
>> Sent: 15 July 2026 18:45
>> To: Golani, Mitulkumar Ajitkumar <mitulkumar.ajitkumar.golani@intel.com>;
>> intel-gfx@lists.freedesktop.org
>> Cc: intel-xe@lists.freedesktop.org; Shankar, Uma <uma.shankar@intel.com>;
>> Nautiyal, Ankit K <ankit.k.nautiyal@intel.com>
>> Subject: Re: [PATCH v3 5/8] drm/i915/vrr: Move CMRR hw registers to fix
>> refresh rate path
>>
>>
>>
>> On 7/14/2026 4:09 PM, Mitul Golani wrote:
>>> Move CMRR register writes to fix refresh rate register write path to
>>> consolidate with fix refresh rate implementation.
>>>
>>> Signed-off-by: Mitul Golani <mitulkumar.ajitkumar.golani@intel.com>
>>> ---
>>>    drivers/gpu/drm/i915/display/intel_vrr.c | 22 +++++++++++-----------
>>>    1 file changed, 11 insertions(+), 11 deletions(-)
>>>
>>> diff --git a/drivers/gpu/drm/i915/display/intel_vrr.c
>>> b/drivers/gpu/drm/i915/display/intel_vrr.c
>>> index 25ce56d48bb1..95c7b0c05ec3 100644
>>> --- a/drivers/gpu/drm/i915/display/intel_vrr.c
>>> +++ b/drivers/gpu/drm/i915/display/intel_vrr.c
>>> @@ -337,6 +337,17 @@ void intel_vrr_set_fixed_rr_timings(const struct
>> intel_crtc_state *crtc_state,
>>>    	if (!intel_vrr_possible(crtc_state))
>>>    		return;
>>>
>>> +	if (crtc_state->vrr.cmrr.enable) {
>>> +		intel_de_write(display, TRANS_CMRR_M_HI(display,
>> transcoder),
>>> +			       upper_32_bits(crtc_state->vrr.cmrr.cmrr_m));
>>> +		intel_de_write(display, TRANS_CMRR_M_LO(display,
>> transcoder),
>>> +			       lower_32_bits(crtc_state->vrr.cmrr.cmrr_m));
>>> +		intel_de_write(display, TRANS_CMRR_N_HI(display,
>> transcoder),
>>> +			       upper_32_bits(crtc_state->vrr.cmrr.cmrr_n));
>>> +		intel_de_write(display, TRANS_CMRR_N_LO(display,
>> transcoder),
>>> +			       lower_32_bits(crtc_state->vrr.cmrr.cmrr_n));
>>
>> Shouldn't TRANS_CMRR_N_HI be the last register to be written.
> 
> No functional change has done, just moved to fix refresh rate path.
> 
> In later patches when actual enable/disable sequence is computed, there suggested changes are applied.
> 

The function is never touched in the later patches.

> Thanks
> 
>>
>>> +	}
>>> +
>>>    	intel_de_write(display, TRANS_VRR_VMIN(display, transcoder),
>>>    		       intel_vrr_fixed_rr_hw_vmin(crtc_state) - 1);
>>>    	intel_de_write(display, TRANS_VRR_VMAX(display, transcoder), @@
>>> -648,17 +659,6 @@ void intel_vrr_set_transcoder_timings(const struct
>> intel_crtc_state *crtc_state)
>>>    		return;
>>>    	}
>>>
>>> -	if (crtc_state->vrr.cmrr.enable) {
>>> -		intel_de_write(display, TRANS_CMRR_M_HI(display,
>> cpu_transcoder),
>>> -			       upper_32_bits(crtc_state->vrr.cmrr.cmrr_m));
>>> -		intel_de_write(display, TRANS_CMRR_M_LO(display,
>> cpu_transcoder),
>>> -			       lower_32_bits(crtc_state->vrr.cmrr.cmrr_m));
>>> -		intel_de_write(display, TRANS_CMRR_N_HI(display,
>> cpu_transcoder),
>>> -			       upper_32_bits(crtc_state->vrr.cmrr.cmrr_n));
>>> -		intel_de_write(display, TRANS_CMRR_N_LO(display,
>> cpu_transcoder),
>>> -			       lower_32_bits(crtc_state->vrr.cmrr.cmrr_n));
>>> -	}
>>> -
>>>    	intel_vrr_set_fixed_rr_timings(crtc_state, cpu_transcoder);
>>>    	intel_cmtg_set_vrr_timings(crtc_state);
>>>
> 

RE: [PATCH v3 5/8] drm/i915/vrr: Move CMRR hw registers to fix refresh rate path

[Golani, Mitulkumar Ajitkumar]

> -----Original Message-----
> From: Borah, Chaitanya Kumar <chaitanya.kumar.borah@intel.com>
> Sent: 16 July 2026 18:58
> To: Golani, Mitulkumar Ajitkumar <mitulkumar.ajitkumar.golani@intel.com>;
> intel-gfx@lists.freedesktop.org
> Cc: intel-xe@lists.freedesktop.org; Shankar, Uma <uma.shankar@intel.com>;
> Nautiyal, Ankit K <ankit.k.nautiyal@intel.com>
> Subject: Re: [PATCH v3 5/8] drm/i915/vrr: Move CMRR hw registers to fix
> refresh rate path
> 
> 
> 
> On 7/16/2026 5:32 PM, Golani, Mitulkumar Ajitkumar wrote:
> >
> >
> >> -----Original Message-----
> >> From: Borah, Chaitanya Kumar <chaitanya.kumar.borah@intel.com>
> >> Sent: 15 July 2026 18:45
> >> To: Golani, Mitulkumar Ajitkumar
> >> <mitulkumar.ajitkumar.golani@intel.com>;
> >> intel-gfx@lists.freedesktop.org
> >> Cc: intel-xe@lists.freedesktop.org; Shankar, Uma
> >> <uma.shankar@intel.com>; Nautiyal, Ankit K
> >> <ankit.k.nautiyal@intel.com>
> >> Subject: Re: [PATCH v3 5/8] drm/i915/vrr: Move CMRR hw registers to
> >> fix refresh rate path
> >>
> >>
> >>
> >> On 7/14/2026 4:09 PM, Mitul Golani wrote:
> >>> Move CMRR register writes to fix refresh rate register write path to
> >>> consolidate with fix refresh rate implementation.
> >>>
> >>> Signed-off-by: Mitul Golani <mitulkumar.ajitkumar.golani@intel.com>
> >>> ---
> >>>    drivers/gpu/drm/i915/display/intel_vrr.c | 22 +++++++++++-----------
> >>>    1 file changed, 11 insertions(+), 11 deletions(-)
> >>>
> >>> diff --git a/drivers/gpu/drm/i915/display/intel_vrr.c
> >>> b/drivers/gpu/drm/i915/display/intel_vrr.c
> >>> index 25ce56d48bb1..95c7b0c05ec3 100644
> >>> --- a/drivers/gpu/drm/i915/display/intel_vrr.c
> >>> +++ b/drivers/gpu/drm/i915/display/intel_vrr.c
> >>> @@ -337,6 +337,17 @@ void intel_vrr_set_fixed_rr_timings(const
> >>> struct
> >> intel_crtc_state *crtc_state,
> >>>    	if (!intel_vrr_possible(crtc_state))
> >>>    		return;
> >>>
> >>> +	if (crtc_state->vrr.cmrr.enable) {
> >>> +		intel_de_write(display, TRANS_CMRR_M_HI(display,
> >> transcoder),
> >>> +			       upper_32_bits(crtc_state->vrr.cmrr.cmrr_m));
> >>> +		intel_de_write(display, TRANS_CMRR_M_LO(display,
> >> transcoder),
> >>> +			       lower_32_bits(crtc_state->vrr.cmrr.cmrr_m));
> >>> +		intel_de_write(display, TRANS_CMRR_N_HI(display,
> >> transcoder),
> >>> +			       upper_32_bits(crtc_state->vrr.cmrr.cmrr_n));
> >>> +		intel_de_write(display, TRANS_CMRR_N_LO(display,
> >> transcoder),
> >>> +			       lower_32_bits(crtc_state->vrr.cmrr.cmrr_n));
> >>
> >> Shouldn't TRANS_CMRR_N_HI be the last register to be written.
> >
> > No functional change has done, just moved to fix refresh rate path.
> >
> > In later patches when actual enable/disable sequence is computed, there
> suggested changes are applied.
> >
> 
> The function is never touched in the later patches.

Yeah I have already seen that, as said, I will be eliminating duplication in next revision. Good catch..

Thanks

> 
> > Thanks
> >
> >>
> >>> +	}
> >>> +
> >>>    	intel_de_write(display, TRANS_VRR_VMIN(display, transcoder),
> >>>    		       intel_vrr_fixed_rr_hw_vmin(crtc_state) - 1);
> >>>    	intel_de_write(display, TRANS_VRR_VMAX(display, transcoder), @@
> >>> -648,17 +659,6 @@ void intel_vrr_set_transcoder_timings(const struct
> >> intel_crtc_state *crtc_state)
> >>>    		return;
> >>>    	}
> >>>
> >>> -	if (crtc_state->vrr.cmrr.enable) {
> >>> -		intel_de_write(display, TRANS_CMRR_M_HI(display,
> >> cpu_transcoder),
> >>> -			       upper_32_bits(crtc_state->vrr.cmrr.cmrr_m));
> >>> -		intel_de_write(display, TRANS_CMRR_M_LO(display,
> >> cpu_transcoder),
> >>> -			       lower_32_bits(crtc_state->vrr.cmrr.cmrr_m));
> >>> -		intel_de_write(display, TRANS_CMRR_N_HI(display,
> >> cpu_transcoder),
> >>> -			       upper_32_bits(crtc_state->vrr.cmrr.cmrr_n));
> >>> -		intel_de_write(display, TRANS_CMRR_N_LO(display,
> >> cpu_transcoder),
> >>> -			       lower_32_bits(crtc_state->vrr.cmrr.cmrr_n));
> >>> -	}
> >>> -
> >>>    	intel_vrr_set_fixed_rr_timings(crtc_state, cpu_transcoder);
> >>>    	intel_cmtg_set_vrr_timings(crtc_state);
> >>>
> >

[PATCH v3 6/8] drm/i915/vrr: Program CMRR enable/disable from transcoder timings

[Mitul Golani]

Split the CMRR M/N register programming into intel_vrr_enable_cmrr()
and intel_vrr_disable_cmrr(), and drive them from
intel_vrr_set_transcoder_timings() based on crtc_state->cmrr.enable.

VRR_CTL_CMRR_ENABLE is not set explicitly, writing TRANS_CMRR_N_HI
arms CMRR in hardware. Drop the now-unused cmrr_enable
argument to intel_vrr_tg_enable().

No functional change intended for non-CMRR configurations.

--v2:
- Commit message changes.
- Added Simplified enable/disable sequence. (Chaitanya)

Signed-off-by: Mitul Golani <mitulkumar.ajitkumar.golani@intel.com>
Assisted-by: Claude:claude-opus-4-8
---
 drivers/gpu/drm/i915/display/intel_vrr.c | 51 ++++++++++++++++++++----
 1 file changed, 43 insertions(+), 8 deletions(-)

diff --git a/drivers/gpu/drm/i915/display/intel_vrr.c b/drivers/gpu/drm/i915/display/intel_vrr.c
index 95c7b0c05ec3..52fe40fdbdb3 100644
--- a/drivers/gpu/drm/i915/display/intel_vrr.c
+++ b/drivers/gpu/drm/i915/display/intel_vrr.c
@@ -624,6 +624,34 @@ static u32 trans_vrr_ctl(const struct intel_crtc_state *crtc_state)
 			VRR_CTL_PIPELINE_FULL_OVERRIDE;
 }
 
+static void
+intel_vrr_enable_cmrr(const struct intel_crtc_state *crtc_state)
+{
+	struct intel_display *display = to_intel_display(crtc_state);
+	enum transcoder cpu_transcoder = crtc_state->cpu_transcoder;
+
+	intel_de_write(display, TRANS_CMRR_M_HI(display, cpu_transcoder),
+		       upper_32_bits(crtc_state->vrr.cmrr.cmrr_m));
+	intel_de_write(display, TRANS_CMRR_M_LO(display, cpu_transcoder),
+		       lower_32_bits(crtc_state->vrr.cmrr.cmrr_m));
+	intel_de_write(display, TRANS_CMRR_N_LO(display, cpu_transcoder),
+		       lower_32_bits(crtc_state->vrr.cmrr.cmrr_n));
+	intel_de_write(display, TRANS_CMRR_N_HI(display, cpu_transcoder),
+		       upper_32_bits(crtc_state->vrr.cmrr.cmrr_n));
+}
+
+static void
+intel_vrr_disable_cmrr(const struct intel_crtc_state *crtc_state)
+{
+	struct intel_display *display = to_intel_display(crtc_state);
+	enum transcoder cpu_transcoder = crtc_state->cpu_transcoder;
+
+	intel_de_write(display, TRANS_CMRR_M_HI(display, cpu_transcoder), 0);
+	intel_de_write(display, TRANS_CMRR_M_LO(display, cpu_transcoder), 0);
+	intel_de_write(display, TRANS_CMRR_N_HI(display, cpu_transcoder), 0);
+	intel_de_write(display, TRANS_CMRR_N_LO(display, cpu_transcoder), 0);
+}
+
 void intel_vrr_set_transcoder_timings(const struct intel_crtc_state *crtc_state)
 {
 	struct intel_display *display = to_intel_display(crtc_state);
@@ -662,6 +690,13 @@ void intel_vrr_set_transcoder_timings(const struct intel_crtc_state *crtc_state)
 	intel_vrr_set_fixed_rr_timings(crtc_state, cpu_transcoder);
 	intel_cmtg_set_vrr_timings(crtc_state);
 
+	if (HAS_CMRR(display)) {
+		if (crtc_state->vrr.cmrr.enable)
+			intel_vrr_enable_cmrr(crtc_state);
+		else
+			intel_vrr_disable_cmrr(crtc_state);
+	}
+
 	if (!intel_vrr_always_use_vrr_tg(display))
 		intel_de_write(display, TRANS_VRR_CTL(display, cpu_transcoder),
 			       trans_vrr_ctl(crtc_state));
@@ -924,8 +959,7 @@ intel_vrr_disable_dc_balancing(const struct intel_crtc_state *old_crtc_state)
 	intel_de_write(display, TRANS_VRR_CTL(display, cpu_transcoder), vrr_ctl);
 }
 
-static void intel_vrr_tg_enable(const struct intel_crtc_state *crtc_state,
-				bool cmrr_enable)
+static void intel_vrr_tg_enable(const struct intel_crtc_state *crtc_state)
 {
 	struct intel_display *display = to_intel_display(crtc_state);
 	enum transcoder cpu_transcoder = crtc_state->cpu_transcoder;
@@ -937,11 +971,12 @@ static void intel_vrr_tg_enable(const struct intel_crtc_state *crtc_state,
 	vrr_ctl = VRR_CTL_VRR_ENABLE | trans_vrr_ctl(crtc_state);
 
 	/*
-	 * FIXME this might be broken as bspec seems to imply that
-	 * even VRR_CTL_CMRR_ENABLE is armed by TRANS_CMRR_N_HI
-	 * when enabling CMRR (but not when disabling CMRR?).
+	 * This full TRANS_VRR_CTL write is the authoritative one, so it must
+	 * carry VRR_CTL_CMRR_ENABLE when CMRR is in use. Writing TRANS_CMRR_N_HI
+	 * arms the bit in hardware, but this later write would otherwise clear
+	 * it again.
 	 */
-	if (cmrr_enable)
+	if (crtc_state->vrr.cmrr.enable)
 		vrr_ctl |= VRR_CTL_CMRR_ENABLE;
 
 	intel_de_write(display, TRANS_VRR_CTL(display, cpu_transcoder), vrr_ctl);
@@ -977,7 +1012,7 @@ void intel_vrr_enable(const struct intel_crtc_state *crtc_state)
 	intel_vrr_enable_dc_balancing(crtc_state);
 
 	if (!intel_vrr_always_use_vrr_tg(display))
-		intel_vrr_tg_enable(crtc_state, crtc_state->vrr.cmrr.enable);
+		intel_vrr_tg_enable(crtc_state);
 }
 
 void intel_vrr_disable(const struct intel_crtc_state *old_crtc_state)
@@ -1004,7 +1039,7 @@ void intel_vrr_transcoder_enable(const struct intel_crtc_state *crtc_state)
 		return;
 
 	if (intel_vrr_always_use_vrr_tg(display))
-		intel_vrr_tg_enable(crtc_state, false);
+		intel_vrr_tg_enable(crtc_state);
 }
 
 void intel_vrr_transcoder_disable(const struct intel_crtc_state *old_crtc_state)
-- 
2.48.1

Re: [PATCH v3 6/8] drm/i915/vrr: Program CMRR enable/disable from transcoder timings

[Borah, Chaitanya Kumar]

On 7/14/2026 4:09 PM, Mitul Golani wrote:
> Split the CMRR M/N register programming into intel_vrr_enable_cmrr()
> and intel_vrr_disable_cmrr(), and drive them from
> intel_vrr_set_transcoder_timings() based on crtc_state->cmrr.enable.

crtc_state->vrr.cmrr.enable

> 
> VRR_CTL_CMRR_ENABLE is not set explicitly, writing TRANS_CMRR_N_HI
> arms CMRR in hardware. Drop the now-unused cmrr_enable
> argument to intel_vrr_tg_enable().
> 
> No functional change intended for non-CMRR configurations.
> 
> --v2:
> - Commit message changes.
> - Added Simplified enable/disable sequence. (Chaitanya)
> 
> Signed-off-by: Mitul Golani <mitulkumar.ajitkumar.golani@intel.com>
> Assisted-by: Claude:claude-opus-4-8
> ---
>   drivers/gpu/drm/i915/display/intel_vrr.c | 51 ++++++++++++++++++++----
>   1 file changed, 43 insertions(+), 8 deletions(-)
> 
> diff --git a/drivers/gpu/drm/i915/display/intel_vrr.c b/drivers/gpu/drm/i915/display/intel_vrr.c
> index 95c7b0c05ec3..52fe40fdbdb3 100644
> --- a/drivers/gpu/drm/i915/display/intel_vrr.c
> +++ b/drivers/gpu/drm/i915/display/intel_vrr.c
> @@ -624,6 +624,34 @@ static u32 trans_vrr_ctl(const struct intel_crtc_state *crtc_state)
>   			VRR_CTL_PIPELINE_FULL_OVERRIDE;
>   }
>   
> +static void
> +intel_vrr_enable_cmrr(const struct intel_crtc_state *crtc_state)
> +{
> +	struct intel_display *display = to_intel_display(crtc_state);
> +	enum transcoder cpu_transcoder = crtc_state->cpu_transcoder;
> +
> +	intel_de_write(display, TRANS_CMRR_M_HI(display, cpu_transcoder),
> +		       upper_32_bits(crtc_state->vrr.cmrr.cmrr_m));
> +	intel_de_write(display, TRANS_CMRR_M_LO(display, cpu_transcoder),
> +		       lower_32_bits(crtc_state->vrr.cmrr.cmrr_m));
> +	intel_de_write(display, TRANS_CMRR_N_LO(display, cpu_transcoder),
> +		       lower_32_bits(crtc_state->vrr.cmrr.cmrr_n));
> +	intel_de_write(display, TRANS_CMRR_N_HI(display, cpu_transcoder),
> +		       upper_32_bits(crtc_state->vrr.cmrr.cmrr_n));
> +}
> +
> +static void
> +intel_vrr_disable_cmrr(const struct intel_crtc_state *crtc_state)
> +{
> +	struct intel_display *display = to_intel_display(crtc_state);
> +	enum transcoder cpu_transcoder = crtc_state->cpu_transcoder;
> +
> +	intel_de_write(display, TRANS_CMRR_M_HI(display, cpu_transcoder), 0);
> +	intel_de_write(display, TRANS_CMRR_M_LO(display, cpu_transcoder), 0);
> +	intel_de_write(display, TRANS_CMRR_N_HI(display, cpu_transcoder), 0);
> +	intel_de_write(display, TRANS_CMRR_N_LO(display, cpu_transcoder), 0);

TRANS_CMRR_N_HI should be the last register to be written.

> +}
> +
>   void intel_vrr_set_transcoder_timings(const struct intel_crtc_state *crtc_state)
>   {
>   	struct intel_display *display = to_intel_display(crtc_state);
> @@ -662,6 +690,13 @@ void intel_vrr_set_transcoder_timings(const struct intel_crtc_state *crtc_state)
>   	intel_vrr_set_fixed_rr_timings(crtc_state, cpu_transcoder);
>   	intel_cmtg_set_vrr_timings(crtc_state);
>   
> +	if (HAS_CMRR(display)) {
> +		if (crtc_state->vrr.cmrr.enable)
> +			intel_vrr_enable_cmrr(crtc_state);
> +		else
> +			intel_vrr_disable_cmrr(crtc_state);
> +	}
> +

CMRR M/N now gets written twice. intel_vrr_set_transcoder_timings() 
calls intel_vrr_set_fixed_rr_timings() and then also calls 
intel_vrr_enable_cmrr(). Same values, so no functional breakage, but 
it's redundant


>   	if (!intel_vrr_always_use_vrr_tg(display))
>   		intel_de_write(display, TRANS_VRR_CTL(display, cpu_transcoder),
>   			       trans_vrr_ctl(crtc_state));
> @@ -924,8 +959,7 @@ intel_vrr_disable_dc_balancing(const struct intel_crtc_state *old_crtc_state)
>   	intel_de_write(display, TRANS_VRR_CTL(display, cpu_transcoder), vrr_ctl);
>   }
>   
> -static void intel_vrr_tg_enable(const struct intel_crtc_state *crtc_state,
> -				bool cmrr_enable)
> +static void intel_vrr_tg_enable(const struct intel_crtc_state *crtc_state)
>   {
>   	struct intel_display *display = to_intel_display(crtc_state);
>   	enum transcoder cpu_transcoder = crtc_state->cpu_transcoder;
> @@ -937,11 +971,12 @@ static void intel_vrr_tg_enable(const struct intel_crtc_state *crtc_state,
>   	vrr_ctl = VRR_CTL_VRR_ENABLE | trans_vrr_ctl(crtc_state);
>   
>   	/*
> -	 * FIXME this might be broken as bspec seems to imply that
> -	 * even VRR_CTL_CMRR_ENABLE is armed by TRANS_CMRR_N_HI
> -	 * when enabling CMRR (but not when disabling CMRR?).
> +	 * This full TRANS_VRR_CTL write is the authoritative one, so it must
> +	 * carry VRR_CTL_CMRR_ENABLE when CMRR is in use. Writing TRANS_CMRR_N_HI
> +	 * arms the bit in hardware, but this later write would otherwise clear
> +	 * it again.
>   	 */
> -	if (cmrr_enable)
> +	if (crtc_state->vrr.cmrr.enable)
>   		vrr_ctl |= VRR_CTL_CMRR_ENABLE;
>   
>   	intel_de_write(display, TRANS_VRR_CTL(display, cpu_transcoder), vrr_ctl);
> @@ -977,7 +1012,7 @@ void intel_vrr_enable(const struct intel_crtc_state *crtc_state)
>   	intel_vrr_enable_dc_balancing(crtc_state);
>   
>   	if (!intel_vrr_always_use_vrr_tg(display))
> -		intel_vrr_tg_enable(crtc_state, crtc_state->vrr.cmrr.enable);
> +		intel_vrr_tg_enable(crtc_state);
>   }
>   
>   void intel_vrr_disable(const struct intel_crtc_state *old_crtc_state)
> @@ -1004,7 +1039,7 @@ void intel_vrr_transcoder_enable(const struct intel_crtc_state *crtc_state)
>   		return;
>   
>   	if (intel_vrr_always_use_vrr_tg(display))
> -		intel_vrr_tg_enable(crtc_state, false);
> +		intel_vrr_tg_enable(crtc_state);
>   }
>   
>   void intel_vrr_transcoder_disable(const struct intel_crtc_state *old_crtc_state)

[PATCH v3 7/8] drm/i915/vrr: Return from CMRR compute config in case of PSR2 enabled

[Mitul Golani]

CMRR is mutually exclusive to PSR2, hence return from CMRR if PSR2
is already computed.

Signed-off-by: Mitul Golani <mitulkumar.ajitkumar.golani@intel.com>
---
 drivers/gpu/drm/i915/display/intel_vrr.c | 3 +++
 1 file changed, 3 insertions(+)

diff --git a/drivers/gpu/drm/i915/display/intel_vrr.c b/drivers/gpu/drm/i915/display/intel_vrr.c
index 52fe40fdbdb3..ca3cac5aa6ab 100644
--- a/drivers/gpu/drm/i915/display/intel_vrr.c
+++ b/drivers/gpu/drm/i915/display/intel_vrr.c
@@ -202,6 +202,9 @@ intel_vrr_cmrr_compute_config(struct intel_crtc_state *crtc_state)
 	if (!HAS_CMRR(display))
 		return;
 
+	if (crtc_state->has_sel_update)
+		return;
+
 	/* No CMRR ratio configured through debugfs */
 	if (!crtc->force_cmrr.numerator)
 		return;
-- 
2.48.1

Re: [PATCH v3 7/8] drm/i915/vrr: Return from CMRR compute config in case of PSR2 enabled

[Borah, Chaitanya Kumar]

On 7/14/2026 4:09 PM, Mitul Golani wrote:
> CMRR is mutually exclusive to PSR2, hence return from CMRR if PSR2
> is already computed.
> 
> Signed-off-by: Mitul Golani <mitulkumar.ajitkumar.golani@intel.com>
> ---
>   drivers/gpu/drm/i915/display/intel_vrr.c | 3 +++
>   1 file changed, 3 insertions(+)
> 
> diff --git a/drivers/gpu/drm/i915/display/intel_vrr.c b/drivers/gpu/drm/i915/display/intel_vrr.c
> index 52fe40fdbdb3..ca3cac5aa6ab 100644
> --- a/drivers/gpu/drm/i915/display/intel_vrr.c
> +++ b/drivers/gpu/drm/i915/display/intel_vrr.c
> @@ -202,6 +202,9 @@ intel_vrr_cmrr_compute_config(struct intel_crtc_state *crtc_state)
>   	if (!HAS_CMRR(display))
>   		return;
>   
> +	if (crtc_state->has_sel_update)
> +		return;
> +

This won't work because psr_compute_config happens after vrr_compute_config.

Also is this the best flag to identify PSR2?

>   	/* No CMRR ratio configured through debugfs */
>   	if (!crtc->force_cmrr.numerator)
>   		return;

RE: [PATCH v3 7/8] drm/i915/vrr: Return from CMRR compute config in case of PSR2 enabled

[Golani, Mitulkumar Ajitkumar]

> -----Original Message-----
> From: Borah, Chaitanya Kumar <chaitanya.kumar.borah@intel.com>
> Sent: 15 July 2026 18:45
> To: Golani, Mitulkumar Ajitkumar <mitulkumar.ajitkumar.golani@intel.com>;
> intel-gfx@lists.freedesktop.org
> Cc: intel-xe@lists.freedesktop.org; Shankar, Uma <uma.shankar@intel.com>;
> Nautiyal, Ankit K <ankit.k.nautiyal@intel.com>
> Subject: Re: [PATCH v3 7/8] drm/i915/vrr: Return from CMRR compute config
> in case of PSR2 enabled
> 
> 
> 
> On 7/14/2026 4:09 PM, Mitul Golani wrote:
> > CMRR is mutually exclusive to PSR2, hence return from CMRR if PSR2 is
> > already computed.
> >
> > Signed-off-by: Mitul Golani <mitulkumar.ajitkumar.golani@intel.com>
> > ---
> >   drivers/gpu/drm/i915/display/intel_vrr.c | 3 +++
> >   1 file changed, 3 insertions(+)
> >
> > diff --git a/drivers/gpu/drm/i915/display/intel_vrr.c
> > b/drivers/gpu/drm/i915/display/intel_vrr.c
> > index 52fe40fdbdb3..ca3cac5aa6ab 100644
> > --- a/drivers/gpu/drm/i915/display/intel_vrr.c
> > +++ b/drivers/gpu/drm/i915/display/intel_vrr.c
> > @@ -202,6 +202,9 @@ intel_vrr_cmrr_compute_config(struct
> intel_crtc_state *crtc_state)
> >   	if (!HAS_CMRR(display))
> >   		return;
> >
> > +	if (crtc_state->has_sel_update)
> > +		return;
> > +
> 
> This won't work because psr_compute_config happens after
> vrr_compute_config.
> 
> Also is this the best flag to identify PSR2?

AFAIK, this is the suitable flag to guard PSR2. 

thanks for pointing out the other problem which is actually a chicken and egg problem, I will look into it and address in the next revision

Thanks

> 
> >   	/* No CMRR ratio configured through debugfs */
> >   	if (!crtc->force_cmrr.numerator)
> >   		return;

Re: [PATCH v3 7/8] drm/i915/vrr: Return from CMRR compute config in case of PSR2 enabled

[Borah, Chaitanya Kumar]

On 7/16/2026 5:59 PM, Golani, Mitulkumar Ajitkumar wrote:
> 
> 
>> -----Original Message-----
>> From: Borah, Chaitanya Kumar <chaitanya.kumar.borah@intel.com>
>> Sent: 15 July 2026 18:45
>> To: Golani, Mitulkumar Ajitkumar <mitulkumar.ajitkumar.golani@intel.com>;
>> intel-gfx@lists.freedesktop.org
>> Cc: intel-xe@lists.freedesktop.org; Shankar, Uma <uma.shankar@intel.com>;
>> Nautiyal, Ankit K <ankit.k.nautiyal@intel.com>
>> Subject: Re: [PATCH v3 7/8] drm/i915/vrr: Return from CMRR compute config
>> in case of PSR2 enabled
>>
>>
>>
>> On 7/14/2026 4:09 PM, Mitul Golani wrote:
>>> CMRR is mutually exclusive to PSR2, hence return from CMRR if PSR2 is
>>> already computed.
>>>
>>> Signed-off-by: Mitul Golani <mitulkumar.ajitkumar.golani@intel.com>
>>> ---
>>>    drivers/gpu/drm/i915/display/intel_vrr.c | 3 +++
>>>    1 file changed, 3 insertions(+)
>>>
>>> diff --git a/drivers/gpu/drm/i915/display/intel_vrr.c
>>> b/drivers/gpu/drm/i915/display/intel_vrr.c
>>> index 52fe40fdbdb3..ca3cac5aa6ab 100644
>>> --- a/drivers/gpu/drm/i915/display/intel_vrr.c
>>> +++ b/drivers/gpu/drm/i915/display/intel_vrr.c
>>> @@ -202,6 +202,9 @@ intel_vrr_cmrr_compute_config(struct
>> intel_crtc_state *crtc_state)
>>>    	if (!HAS_CMRR(display))
>>>    		return;
>>>
>>> +	if (crtc_state->has_sel_update)
>>> +		return;
>>> +
>>
>> This won't work because psr_compute_config happens after
>> vrr_compute_config.
>>
>> Also is this the best flag to identify PSR2?
> 
> AFAIK, this is the suitable flag to guard PSR2.
> 

crtc_state->has_sel_update is also set for Panel Replay.

So I think you would need something like

crtc_state->has_psr && crtc_state->has_sel_update &&
!crtc_state->has_panel_replay


Adding Jouni if he has something to add.


> thanks for pointing out the other problem which is actually a chicken and egg problem, I will look into it and address in the next revision
> 
> Thanks
> 
>>
>>>    	/* No CMRR ratio configured through debugfs */
>>>    	if (!crtc->force_cmrr.numerator)
>>>    		return;
> 

[PATCH v3 8/8] drm/i915/vrr: Enable cmrr

[Mitul Golani]

Enable CMRR during compute config and add related state
checker for the same.

--v2:
- Everything else except enable compute to handle before this patch
(Chaitanya)

Signed-off-by: Mitul Golani <mitulkumar.ajitkumar.golani@intel.com>
---
 drivers/gpu/drm/i915/display/intel_vrr.c | 2 ++
 1 file changed, 2 insertions(+)

diff --git a/drivers/gpu/drm/i915/display/intel_vrr.c b/drivers/gpu/drm/i915/display/intel_vrr.c
index ca3cac5aa6ab..ce4148fa1687 100644
--- a/drivers/gpu/drm/i915/display/intel_vrr.c
+++ b/drivers/gpu/drm/i915/display/intel_vrr.c
@@ -256,6 +256,8 @@ intel_vrr_cmrr_compute_config(struct intel_crtc_state *crtc_state)
 						   crtc_state->vrr.cmrr.cmrr_n,
 						   &crtc_state->vrr.cmrr.cmrr_m);
 
+	crtc_state->vrr.cmrr.enable = true;
+
 	return;
 }
 
-- 
2.48.1

Re: [PATCH v3 8/8] drm/i915/vrr: Enable cmrr

[Borah, Chaitanya Kumar]

On 7/14/2026 4:09 PM, Mitul Golani wrote:
> Enable CMRR during compute config and add related state
> checker for the same.
> 
> --v2:
> - Everything else except enable compute to handle before this patch
> (Chaitanya)
> 
> Signed-off-by: Mitul Golani <mitulkumar.ajitkumar.golani@intel.com>
> ---
>   drivers/gpu/drm/i915/display/intel_vrr.c | 2 ++
>   1 file changed, 2 insertions(+)
> 
> diff --git a/drivers/gpu/drm/i915/display/intel_vrr.c b/drivers/gpu/drm/i915/display/intel_vrr.c
> index ca3cac5aa6ab..ce4148fa1687 100644
> --- a/drivers/gpu/drm/i915/display/intel_vrr.c
> +++ b/drivers/gpu/drm/i915/display/intel_vrr.c
> @@ -256,6 +256,8 @@ intel_vrr_cmrr_compute_config(struct intel_crtc_state *crtc_state)
>   						   crtc_state->vrr.cmrr.cmrr_n,
>   						   &crtc_state->vrr.cmrr.cmrr_m);
>   
> +	crtc_state->vrr.cmrr.enable = true;
> +

Please enable it only when CMRR is actually needed.

This comment keeps getting ignored so I will mention it again.

The target rr divider bit is always set to true in
intel_dp_compute_as_sdp(). This is wrong for non-video mode refresh rates.

>   	return;
>   }
>   

✓ CI.KUnit: success for Enable CMRR in fixed-RR VRR path (rev2)

[Patchwork]

== Series Details ==

Series: Enable CMRR in fixed-RR VRR path (rev2)
URL   : https://patchwork.freedesktop.org/series/168613/
State : success

== Summary ==

+ trap cleanup EXIT
+ /kernel/tools/testing/kunit/kunit.py run --kunitconfig /kernel/drivers/gpu/drm/xe/.kunitconfig
[10:56:33] Configuring KUnit Kernel ...
Generating .config ...
Populating config with:
$ make ARCH=um O=.kunit olddefconfig
[10:56:37] Building KUnit Kernel ...
Populating config with:
$ make ARCH=um O=.kunit olddefconfig
Building with:
$ make all compile_commands.json scripts_gdb ARCH=um O=.kunit --jobs=48
[10:57:09] Starting KUnit Kernel (1/1)...
[10:57:09] ============================================================
Running tests with:
$ .kunit/linux kunit.enable=1 mem=1G console=tty kunit_shutdown=halt
[10:57:09] ================== guc_buf (11 subtests) ===================
[10:57:09] [PASSED] test_smallest
[10:57:09] [PASSED] test_largest
[10:57:09] [PASSED] test_granular
[10:57:09] [PASSED] test_unique
[10:57:09] [PASSED] test_overlap
[10:57:09] [PASSED] test_reusable
[10:57:09] [PASSED] test_too_big
[10:57:09] [PASSED] test_flush
[10:57:09] [PASSED] test_lookup
[10:57:09] [PASSED] test_data
[10:57:09] [PASSED] test_class
[10:57:09] ===================== [PASSED] guc_buf =====================
[10:57:09] =================== guc_dbm (7 subtests) ===================
[10:57:09] [PASSED] test_empty
[10:57:09] [PASSED] test_default
[10:57:09] ======================== test_size  ========================
[10:57:09] [PASSED] 4
[10:57:09] [PASSED] 8
[10:57:09] [PASSED] 32
[10:57:09] [PASSED] 256
[10:57:09] ==================== [PASSED] test_size ====================
[10:57:09] ======================= test_reuse  ========================
[10:57:09] [PASSED] 4
[10:57:09] [PASSED] 8
[10:57:09] [PASSED] 32
[10:57:09] [PASSED] 256
[10:57:09] =================== [PASSED] test_reuse ====================
[10:57:09] =================== test_range_overlap  ====================
[10:57:09] [PASSED] 4
[10:57:09] [PASSED] 8
[10:57:09] [PASSED] 32
[10:57:09] [PASSED] 256
[10:57:09] =============== [PASSED] test_range_overlap ================
[10:57:09] =================== test_range_compact  ====================
[10:57:09] [PASSED] 4
[10:57:09] [PASSED] 8
[10:57:09] [PASSED] 32
[10:57:09] [PASSED] 256
[10:57:09] =============== [PASSED] test_range_compact ================
[10:57:09] ==================== test_range_spare  =====================
[10:57:09] [PASSED] 4
[10:57:09] [PASSED] 8
[10:57:09] [PASSED] 32
[10:57:09] [PASSED] 256
[10:57:09] ================ [PASSED] test_range_spare =================
[10:57:09] ===================== [PASSED] guc_dbm =====================
[10:57:09] =================== guc_idm (6 subtests) ===================
[10:57:09] [PASSED] bad_init
[10:57:09] [PASSED] no_init
[10:57:09] [PASSED] init_fini
[10:57:09] [PASSED] check_used
[10:57:09] [PASSED] check_quota
[10:57:09] [PASSED] check_all
[10:57:09] ===================== [PASSED] guc_idm =====================
[10:57:09] =============== guc_klv_helpers (9 subtests) ===============
[10:57:09] [PASSED] test_count
[10:57:09] [PASSED] test_encode_u32
[10:57:09] [PASSED] test_encode_u64
[10:57:09] [PASSED] test_encode_string
[10:57:09] [PASSED] test_encode_object_raw
[10:57:09] [PASSED] test_encode_object_klv
[10:57:09] [PASSED] test_encode_object_nested
[10:57:09] [PASSED] test_encode_object_basic
[10:57:09] [PASSED] test_print
[10:57:09] ================= [PASSED] guc_klv_helpers =================
[10:57:09] ================== no_relay (3 subtests) ===================
[10:57:09] [PASSED] xe_drops_guc2pf_if_not_ready
[10:57:09] [PASSED] xe_drops_guc2vf_if_not_ready
[10:57:09] [PASSED] xe_rejects_send_if_not_ready
[10:57:09] ==================== [PASSED] no_relay =====================
[10:57:09] ================== pf_relay (14 subtests) ==================
[10:57:09] [PASSED] pf_rejects_guc2pf_too_short
[10:57:09] [PASSED] pf_rejects_guc2pf_too_long
[10:57:09] [PASSED] pf_rejects_guc2pf_no_payload
[10:57:09] [PASSED] pf_fails_no_payload
[10:57:09] [PASSED] pf_fails_bad_origin
[10:57:09] [PASSED] pf_fails_bad_type
[10:57:09] [PASSED] pf_txn_reports_error
[10:57:09] [PASSED] pf_txn_sends_pf2guc
[10:57:09] [PASSED] pf_sends_pf2guc
[10:57:09] [SKIPPED] pf_loopback_nop (requires CONFIG_DRM_XE_DEBUG_SRIOV)
[10:57:09] [SKIPPED] pf_loopback_echo (requires CONFIG_DRM_XE_DEBUG_SRIOV)
[10:57:09] [SKIPPED] pf_loopback_fail (requires CONFIG_DRM_XE_DEBUG_SRIOV)
[10:57:09] [SKIPPED] pf_loopback_busy (requires CONFIG_DRM_XE_DEBUG_SRIOV)
[10:57:09] [SKIPPED] pf_loopback_retry (requires CONFIG_DRM_XE_DEBUG_SRIOV)
[10:57:09] ==================== [PASSED] pf_relay =====================
[10:57:09] ================== vf_relay (3 subtests) ===================
[10:57:09] [PASSED] vf_rejects_guc2vf_too_short
[10:57:09] [PASSED] vf_rejects_guc2vf_too_long
[10:57:09] [PASSED] vf_rejects_guc2vf_no_payload
[10:57:09] ==================== [PASSED] vf_relay =====================
[10:57:09] ================ pf_gt_config (9 subtests) =================
[10:57:09] [PASSED] fair_contexts_1vf
[10:57:09] [PASSED] fair_doorbells_1vf
[10:57:09] [PASSED] fair_ggtt_1vf
[10:57:09] ====================== fair_vram_1vf  ======================
[10:57:09] [PASSED] 3.50 GiB
[10:57:09] [PASSED] 11.5 GiB
[10:57:09] [PASSED] 15.5 GiB
[10:57:09] [PASSED] 31.5 GiB
[10:57:09] [PASSED] 63.5 GiB
[10:57:09] [PASSED] 1.91 GiB
[10:57:09] ================== [PASSED] fair_vram_1vf ==================
[10:57:09] ================ fair_vram_1vf_admin_only  =================
[10:57:09] [PASSED] 3.50 GiB
[10:57:09] [PASSED] 11.5 GiB
[10:57:09] [PASSED] 15.5 GiB
[10:57:09] [PASSED] 31.5 GiB
[10:57:09] [PASSED] 63.5 GiB
[10:57:09] [PASSED] 1.91 GiB
[10:57:09] ============ [PASSED] fair_vram_1vf_admin_only =============
[10:57:09] ====================== fair_contexts  ======================
[10:57:09] [PASSED] 1 VF
[10:57:09] [PASSED] 2 VFs
[10:57:09] [PASSED] 3 VFs
[10:57:09] [PASSED] 4 VFs
[10:57:09] [PASSED] 5 VFs
[10:57:09] [PASSED] 6 VFs
[10:57:09] [PASSED] 7 VFs
[10:57:09] [PASSED] 8 VFs
[10:57:09] [PASSED] 9 VFs
[10:57:09] [PASSED] 10 VFs
[10:57:09] [PASSED] 11 VFs
[10:57:09] [PASSED] 12 VFs
[10:57:09] [PASSED] 13 VFs
[10:57:09] [PASSED] 14 VFs
[10:57:09] [PASSED] 15 VFs
[10:57:09] [PASSED] 16 VFs
[10:57:09] [PASSED] 17 VFs
[10:57:09] [PASSED] 18 VFs
[10:57:09] [PASSED] 19 VFs
[10:57:09] [PASSED] 20 VFs
[10:57:09] [PASSED] 21 VFs
[10:57:09] [PASSED] 22 VFs
[10:57:09] [PASSED] 23 VFs
[10:57:09] [PASSED] 24 VFs
[10:57:09] [PASSED] 25 VFs
[10:57:09] [PASSED] 26 VFs
[10:57:09] [PASSED] 27 VFs
[10:57:09] [PASSED] 28 VFs
[10:57:09] [PASSED] 29 VFs
[10:57:09] [PASSED] 30 VFs
[10:57:09] [PASSED] 31 VFs
[10:57:09] [PASSED] 32 VFs
[10:57:09] [PASSED] 33 VFs
[10:57:09] [PASSED] 34 VFs
[10:57:09] [PASSED] 35 VFs
[10:57:09] [PASSED] 36 VFs
[10:57:09] [PASSED] 37 VFs
[10:57:09] [PASSED] 38 VFs
[10:57:09] [PASSED] 39 VFs
[10:57:09] [PASSED] 40 VFs
[10:57:09] [PASSED] 41 VFs
[10:57:09] [PASSED] 42 VFs
[10:57:09] [PASSED] 43 VFs
[10:57:09] [PASSED] 44 VFs
[10:57:09] [PASSED] 45 VFs
[10:57:09] [PASSED] 46 VFs
[10:57:09] [PASSED] 47 VFs
[10:57:09] [PASSED] 48 VFs
[10:57:09] [PASSED] 49 VFs
[10:57:09] [PASSED] 50 VFs
[10:57:09] [PASSED] 51 VFs
[10:57:09] [PASSED] 52 VFs
[10:57:09] [PASSED] 53 VFs
[10:57:09] [PASSED] 54 VFs
[10:57:09] [PASSED] 55 VFs
[10:57:09] [PASSED] 56 VFs
[10:57:09] [PASSED] 57 VFs
[10:57:09] [PASSED] 58 VFs
[10:57:09] [PASSED] 59 VFs
[10:57:09] [PASSED] 60 VFs
[10:57:09] [PASSED] 61 VFs
[10:57:09] [PASSED] 62 VFs
[10:57:09] [PASSED] 63 VFs
[10:57:09] ================== [PASSED] fair_contexts ==================
[10:57:09] ===================== fair_doorbells  ======================
[10:57:09] [PASSED] 1 VF
[10:57:09] [PASSED] 2 VFs
[10:57:09] [PASSED] 3 VFs
[10:57:09] [PASSED] 4 VFs
[10:57:09] [PASSED] 5 VFs
[10:57:09] [PASSED] 6 VFs
[10:57:09] [PASSED] 7 VFs
[10:57:09] [PASSED] 8 VFs
[10:57:09] [PASSED] 9 VFs
[10:57:09] [PASSED] 10 VFs
[10:57:09] [PASSED] 11 VFs
[10:57:09] [PASSED] 12 VFs
[10:57:09] [PASSED] 13 VFs
[10:57:09] [PASSED] 14 VFs
[10:57:09] [PASSED] 15 VFs
[10:57:09] [PASSED] 16 VFs
[10:57:09] [PASSED] 17 VFs
[10:57:09] [PASSED] 18 VFs
[10:57:09] [PASSED] 19 VFs
[10:57:09] [PASSED] 20 VFs
[10:57:09] [PASSED] 21 VFs
[10:57:09] [PASSED] 22 VFs
[10:57:09] [PASSED] 23 VFs
[10:57:09] [PASSED] 24 VFs
[10:57:09] [PASSED] 25 VFs
[10:57:09] [PASSED] 26 VFs
[10:57:09] [PASSED] 27 VFs
[10:57:09] [PASSED] 28 VFs
[10:57:09] [PASSED] 29 VFs
[10:57:09] [PASSED] 30 VFs
[10:57:09] [PASSED] 31 VFs
[10:57:09] [PASSED] 32 VFs
[10:57:09] [PASSED] 33 VFs
[10:57:09] [PASSED] 34 VFs
[10:57:09] [PASSED] 35 VFs
[10:57:09] [PASSED] 36 VFs
[10:57:09] [PASSED] 37 VFs
[10:57:09] [PASSED] 38 VFs
[10:57:09] [PASSED] 39 VFs
[10:57:09] [PASSED] 40 VFs
[10:57:09] [PASSED] 41 VFs
[10:57:09] [PASSED] 42 VFs
[10:57:09] [PASSED] 43 VFs
[10:57:09] [PASSED] 44 VFs
[10:57:09] [PASSED] 45 VFs
[10:57:09] [PASSED] 46 VFs
[10:57:09] [PASSED] 47 VFs
[10:57:09] [PASSED] 48 VFs
[10:57:09] [PASSED] 49 VFs
[10:57:09] [PASSED] 50 VFs
[10:57:09] [PASSED] 51 VFs
[10:57:09] [PASSED] 52 VFs
[10:57:09] [PASSED] 53 VFs
[10:57:09] [PASSED] 54 VFs
[10:57:09] [PASSED] 55 VFs
[10:57:09] [PASSED] 56 VFs
[10:57:09] [PASSED] 57 VFs
[10:57:09] [PASSED] 58 VFs
[10:57:09] [PASSED] 59 VFs
[10:57:09] [PASSED] 60 VFs
[10:57:09] [PASSED] 61 VFs
[10:57:09] [PASSED] 62 VFs
[10:57:09] [PASSED] 63 VFs
[10:57:09] ================= [PASSED] fair_doorbells ==================
[10:57:09] ======================== fair_ggtt  ========================
[10:57:09] [PASSED] 1 VF
[10:57:09] [PASSED] 2 VFs
[10:57:09] [PASSED] 3 VFs
[10:57:09] [PASSED] 4 VFs
[10:57:09] [PASSED] 5 VFs
[10:57:09] [PASSED] 6 VFs
[10:57:09] [PASSED] 7 VFs
[10:57:09] [PASSED] 8 VFs
[10:57:09] [PASSED] 9 VFs
[10:57:09] [PASSED] 10 VFs
[10:57:09] [PASSED] 11 VFs
[10:57:09] [PASSED] 12 VFs
[10:57:09] [PASSED] 13 VFs
[10:57:09] [PASSED] 14 VFs
[10:57:09] [PASSED] 15 VFs
[10:57:09] [PASSED] 16 VFs
[10:57:09] [PASSED] 17 VFs
[10:57:09] [PASSED] 18 VFs
[10:57:09] [PASSED] 19 VFs
[10:57:09] [PASSED] 20 VFs
[10:57:09] [PASSED] 21 VFs
[10:57:09] [PASSED] 22 VFs
[10:57:09] [PASSED] 23 VFs
[10:57:09] [PASSED] 24 VFs
[10:57:09] [PASSED] 25 VFs
[10:57:09] [PASSED] 26 VFs
[10:57:09] [PASSED] 27 VFs
[10:57:09] [PASSED] 28 VFs
[10:57:09] [PASSED] 29 VFs
[10:57:09] [PASSED] 30 VFs
[10:57:09] [PASSED] 31 VFs
[10:57:09] [PASSED] 32 VFs
[10:57:09] [PASSED] 33 VFs
[10:57:09] [PASSED] 34 VFs
[10:57:09] [PASSED] 35 VFs
[10:57:09] [PASSED] 36 VFs
[10:57:09] [PASSED] 37 VFs
[10:57:09] [PASSED] 38 VFs
[10:57:09] [PASSED] 39 VFs
[10:57:09] [PASSED] 40 VFs
[10:57:09] [PASSED] 41 VFs
[10:57:09] [PASSED] 42 VFs
[10:57:09] [PASSED] 43 VFs
[10:57:09] [PASSED] 44 VFs
[10:57:09] [PASSED] 45 VFs
[10:57:09] [PASSED] 46 VFs
[10:57:09] [PASSED] 47 VFs
[10:57:09] [PASSED] 48 VFs
[10:57:09] [PASSED] 49 VFs
[10:57:09] [PASSED] 50 VFs
[10:57:09] [PASSED] 51 VFs
[10:57:09] [PASSED] 52 VFs
[10:57:09] [PASSED] 53 VFs
[10:57:09] [PASSED] 54 VFs
[10:57:09] [PASSED] 55 VFs
[10:57:09] [PASSED] 56 VFs
[10:57:09] [PASSED] 57 VFs
[10:57:09] [PASSED] 58 VFs
[10:57:09] [PASSED] 59 VFs
[10:57:09] [PASSED] 60 VFs
[10:57:09] [PASSED] 61 VFs
[10:57:09] [PASSED] 62 VFs
[10:57:09] [PASSED] 63 VFs
[10:57:09] ==================== [PASSED] fair_ggtt ====================
[10:57:09] ======================== fair_vram  ========================
[10:57:09] [PASSED] 1 VF
[10:57:09] [PASSED] 2 VFs
[10:57:09] [PASSED] 3 VFs
[10:57:09] [PASSED] 4 VFs
[10:57:09] [PASSED] 5 VFs
[10:57:09] [PASSED] 6 VFs
[10:57:09] [PASSED] 7 VFs
[10:57:09] [PASSED] 8 VFs
[10:57:09] [PASSED] 9 VFs
[10:57:09] [PASSED] 10 VFs
[10:57:09] [PASSED] 11 VFs
[10:57:09] [PASSED] 12 VFs
[10:57:09] [PASSED] 13 VFs
[10:57:09] [PASSED] 14 VFs
[10:57:09] [PASSED] 15 VFs
[10:57:09] [PASSED] 16 VFs
[10:57:09] [PASSED] 17 VFs
[10:57:09] [PASSED] 18 VFs
[10:57:09] [PASSED] 19 VFs
[10:57:09] [PASSED] 20 VFs
[10:57:09] [PASSED] 21 VFs
[10:57:09] [PASSED] 22 VFs
[10:57:09] [PASSED] 23 VFs
[10:57:09] [PASSED] 24 VFs
[10:57:09] [PASSED] 25 VFs
[10:57:09] [PASSED] 26 VFs
[10:57:09] [PASSED] 27 VFs
[10:57:10] [PASSED] 28 VFs
[10:57:10] [PASSED] 29 VFs
[10:57:10] [PASSED] 30 VFs
[10:57:10] [PASSED] 31 VFs
[10:57:10] [PASSED] 32 VFs
[10:57:10] [PASSED] 33 VFs
[10:57:10] [PASSED] 34 VFs
[10:57:10] [PASSED] 35 VFs
[10:57:10] [PASSED] 36 VFs
[10:57:10] [PASSED] 37 VFs
[10:57:10] [PASSED] 38 VFs
[10:57:10] [PASSED] 39 VFs
[10:57:10] [PASSED] 40 VFs
[10:57:10] [PASSED] 41 VFs
[10:57:10] [PASSED] 42 VFs
[10:57:10] [PASSED] 43 VFs
[10:57:10] [PASSED] 44 VFs
[10:57:10] [PASSED] 45 VFs
[10:57:10] [PASSED] 46 VFs
[10:57:10] [PASSED] 47 VFs
[10:57:10] [PASSED] 48 VFs
[10:57:10] [PASSED] 49 VFs
[10:57:10] [PASSED] 50 VFs
[10:57:10] [PASSED] 51 VFs
[10:57:10] [PASSED] 52 VFs
[10:57:10] [PASSED] 53 VFs
[10:57:10] [PASSED] 54 VFs
[10:57:10] [PASSED] 55 VFs
[10:57:10] [PASSED] 56 VFs
[10:57:10] [PASSED] 57 VFs
[10:57:10] [PASSED] 58 VFs
[10:57:10] [PASSED] 59 VFs
[10:57:10] [PASSED] 60 VFs
[10:57:10] [PASSED] 61 VFs
[10:57:10] [PASSED] 62 VFs
[10:57:10] [PASSED] 63 VFs
[10:57:10] ==================== [PASSED] fair_vram ====================
[10:57:10] ================== [PASSED] pf_gt_config ===================
[10:57:10] ===================== lmtt (1 subtest) =====================
[10:57:10] ======================== test_ops  =========================
[10:57:10] [PASSED] 2-level
[10:57:10] [PASSED] multi-level
[10:57:10] ==================== [PASSED] test_ops =====================
[10:57:10] ====================== [PASSED] lmtt =======================
[10:57:10] ================= sriov_packet (1 subtest) =================
[10:57:10] [PASSED] test_descriptor_init
[10:57:10] ================== [PASSED] sriov_packet ===================
[10:57:10] ================= pf_service (11 subtests) =================
[10:57:10] [PASSED] pf_negotiate_any
[10:57:10] [PASSED] pf_negotiate_base_match
[10:57:10] [PASSED] pf_negotiate_base_newer
[10:57:10] [PASSED] pf_negotiate_base_next
[10:57:10] [SKIPPED] pf_negotiate_base_older (no older minor)
[10:57:10] [PASSED] pf_negotiate_base_prev
[10:57:10] [PASSED] pf_negotiate_latest_match
[10:57:10] [PASSED] pf_negotiate_latest_newer
[10:57:10] [PASSED] pf_negotiate_latest_next
[10:57:10] [SKIPPED] pf_negotiate_latest_older (no older minor)
[10:57:10] [SKIPPED] pf_negotiate_latest_prev (no prev major)
[10:57:10] =================== [PASSED] pf_service ====================
[10:57:10] ================= xe_guc_g2g (2 subtests) ==================
[10:57:10] ============== xe_live_guc_g2g_kunit_default  ==============
[10:57:10] ========= [SKIPPED] xe_live_guc_g2g_kunit_default ==========
[10:57:10] ============== xe_live_guc_g2g_kunit_allmem  ===============
[10:57:10] ========== [SKIPPED] xe_live_guc_g2g_kunit_allmem ==========
[10:57:10] =================== [SKIPPED] xe_guc_g2g ===================
[10:57:10] =================== xe_mocs (2 subtests) ===================
[10:57:10] ================ xe_live_mocs_kernel_kunit  ================
[10:57:10] =========== [SKIPPED] xe_live_mocs_kernel_kunit ============
[10:57:10] ================ xe_live_mocs_reset_kunit  =================
[10:57:10] ============ [SKIPPED] xe_live_mocs_reset_kunit ============
[10:57:10] ==================== [SKIPPED] xe_mocs =====================
[10:57:10] ================= xe_migrate (2 subtests) ==================
[10:57:10] ================= xe_migrate_sanity_kunit  =================
[10:57:10] ============ [SKIPPED] xe_migrate_sanity_kunit =============
[10:57:10] ================== xe_validate_ccs_kunit  ==================
[10:57:10] ============= [SKIPPED] xe_validate_ccs_kunit ==============
[10:57:10] =================== [SKIPPED] xe_migrate ===================
[10:57:10] ================== xe_dma_buf (1 subtest) ==================
[10:57:10] ==================== xe_dma_buf_kunit  =====================
[10:57:10] ================ [SKIPPED] xe_dma_buf_kunit ================
[10:57:10] =================== [SKIPPED] xe_dma_buf ===================
[10:57:10] ================= xe_bo_shrink (1 subtest) =================
[10:57:10] =================== xe_bo_shrink_kunit  ====================
[10:57:10] =============== [SKIPPED] xe_bo_shrink_kunit ===============
[10:57:10] ================== [SKIPPED] xe_bo_shrink ==================
[10:57:10] ==================== xe_bo (2 subtests) ====================
[10:57:10] ================== xe_ccs_migrate_kunit  ===================
[10:57:10] ============== [SKIPPED] xe_ccs_migrate_kunit ==============
[10:57:10] ==================== xe_bo_evict_kunit  ====================
[10:57:10] =============== [SKIPPED] xe_bo_evict_kunit ================
[10:57:10] ===================== [SKIPPED] xe_bo ======================
[10:57:10] ==================== args (13 subtests) ====================
[10:57:10] [PASSED] count_args_test
[10:57:10] [PASSED] call_args_example
[10:57:10] [PASSED] call_args_test
[10:57:10] [PASSED] drop_first_arg_example
[10:57:10] [PASSED] drop_first_arg_test
[10:57:10] [PASSED] first_arg_example
[10:57:10] [PASSED] first_arg_test
[10:57:10] [PASSED] last_arg_example
[10:57:10] [PASSED] last_arg_test
[10:57:10] [PASSED] pick_arg_example
[10:57:10] [PASSED] if_args_example
[10:57:10] [PASSED] if_args_test
[10:57:10] [PASSED] sep_comma_example
[10:57:10] ====================== [PASSED] args =======================
[10:57:10] =================== xe_pci (3 subtests) ====================
[10:57:10] ==================== check_graphics_ip  ====================
[10:57:10] [PASSED] 12.00 Xe_LP
[10:57:10] [PASSED] 12.10 Xe_LP+
[10:57:10] [PASSED] 12.55 Xe_HPG
[10:57:10] [PASSED] 12.60 Xe_HPC
[10:57:10] [PASSED] 12.70 Xe_LPG
[10:57:10] [PASSED] 12.71 Xe_LPG
[10:57:10] [PASSED] 12.74 Xe_LPG+
[10:57:10] [PASSED] 20.01 Xe2_HPG
[10:57:10] [PASSED] 20.02 Xe2_HPG
[10:57:10] [PASSED] 20.04 Xe2_LPG
[10:57:10] [PASSED] 30.00 Xe3_LPG
[10:57:10] [PASSED] 30.01 Xe3_LPG
[10:57:10] [PASSED] 30.03 Xe3_LPG
[10:57:10] [PASSED] 30.04 Xe3_LPG
[10:57:10] [PASSED] 30.05 Xe3_LPG
[10:57:10] [PASSED] 35.10 Xe3p_LPG
[10:57:10] [PASSED] 35.11 Xe3p_XPC
[10:57:10] ================ [PASSED] check_graphics_ip ================
[10:57:10] ===================== check_media_ip  ======================
[10:57:10] [PASSED] 12.00 Xe_M
[10:57:10] [PASSED] 12.55 Xe_HPM
[10:57:10] [PASSED] 13.00 Xe_LPM+
[10:57:10] [PASSED] 13.01 Xe2_HPM
[10:57:10] [PASSED] 20.00 Xe2_LPM
[10:57:10] [PASSED] 30.00 Xe3_LPM
[10:57:10] [PASSED] 30.02 Xe3_LPM
[10:57:10] [PASSED] 35.00 Xe3p_LPM
[10:57:10] [PASSED] 35.03 Xe3p_HPM
[10:57:10] ================= [PASSED] check_media_ip ==================
[10:57:10] =================== check_platform_desc  ===================
[10:57:10] [PASSED] 0x9A60 (TIGERLAKE)
[10:57:10] [PASSED] 0x9A68 (TIGERLAKE)
[10:57:10] [PASSED] 0x9A70 (TIGERLAKE)
[10:57:10] [PASSED] 0x9A40 (TIGERLAKE)
[10:57:10] [PASSED] 0x9A49 (TIGERLAKE)
[10:57:10] [PASSED] 0x9A59 (TIGERLAKE)
[10:57:10] [PASSED] 0x9A78 (TIGERLAKE)
[10:57:10] [PASSED] 0x9AC0 (TIGERLAKE)
[10:57:10] [PASSED] 0x9AC9 (TIGERLAKE)
[10:57:10] [PASSED] 0x9AD9 (TIGERLAKE)
[10:57:10] [PASSED] 0x9AF8 (TIGERLAKE)
[10:57:10] [PASSED] 0x4C80 (ROCKETLAKE)
[10:57:10] [PASSED] 0x4C8A (ROCKETLAKE)
[10:57:10] [PASSED] 0x4C8B (ROCKETLAKE)
[10:57:10] [PASSED] 0x4C8C (ROCKETLAKE)
[10:57:10] [PASSED] 0x4C90 (ROCKETLAKE)
[10:57:10] [PASSED] 0x4C9A (ROCKETLAKE)
[10:57:10] [PASSED] 0x4680 (ALDERLAKE_S)
[10:57:10] [PASSED] 0x4682 (ALDERLAKE_S)
[10:57:10] [PASSED] 0x4688 (ALDERLAKE_S)
[10:57:10] [PASSED] 0x468A (ALDERLAKE_S)
[10:57:10] [PASSED] 0x468B (ALDERLAKE_S)
[10:57:10] [PASSED] 0x4690 (ALDERLAKE_S)
[10:57:10] [PASSED] 0x4692 (ALDERLAKE_S)
[10:57:10] [PASSED] 0x4693 (ALDERLAKE_S)
[10:57:10] [PASSED] 0x46A0 (ALDERLAKE_P)
[10:57:10] [PASSED] 0x46A1 (ALDERLAKE_P)
[10:57:10] [PASSED] 0x46A2 (ALDERLAKE_P)
[10:57:10] [PASSED] 0x46A3 (ALDERLAKE_P)
[10:57:10] [PASSED] 0x46A6 (ALDERLAKE_P)
[10:57:10] [PASSED] 0x46A8 (ALDERLAKE_P)
[10:57:10] [PASSED] 0x46AA (ALDERLAKE_P)
[10:57:10] [PASSED] 0x462A (ALDERLAKE_P)
[10:57:10] [PASSED] 0x4626 (ALDERLAKE_P)
[10:57:10] [PASSED] 0x4628 (ALDERLAKE_P)
[10:57:10] [PASSED] 0x46B0 (ALDERLAKE_P)
[10:57:10] [PASSED] 0x46B1 (ALDERLAKE_P)
[10:57:10] [PASSED] 0x46B2 (ALDERLAKE_P)
[10:57:10] [PASSED] 0x46B3 (ALDERLAKE_P)
[10:57:10] [PASSED] 0x46C0 (ALDERLAKE_P)
[10:57:10] [PASSED] 0x46C1 (ALDERLAKE_P)
[10:57:10] [PASSED] 0x46C2 (ALDERLAKE_P)
[10:57:10] [PASSED] 0x46C3 (ALDERLAKE_P)
[10:57:10] [PASSED] 0x46D0 (ALDERLAKE_N)
[10:57:10] [PASSED] 0x46D1 (ALDERLAKE_N)
[10:57:10] [PASSED] 0x46D2 (ALDERLAKE_N)
[10:57:10] [PASSED] 0x46D3 (ALDERLAKE_N)
[10:57:10] [PASSED] 0x46D4 (ALDERLAKE_N)
[10:57:10] [PASSED] 0xA721 (ALDERLAKE_P)
[10:57:10] [PASSED] 0xA7A1 (ALDERLAKE_P)
[10:57:10] [PASSED] 0xA7A9 (ALDERLAKE_P)
[10:57:10] [PASSED] 0xA7AC (ALDERLAKE_P)
[10:57:10] [PASSED] 0xA7AD (ALDERLAKE_P)
[10:57:10] [PASSED] 0xA720 (ALDERLAKE_P)
[10:57:10] [PASSED] 0xA7A0 (ALDERLAKE_P)
[10:57:10] [PASSED] 0xA7A8 (ALDERLAKE_P)
[10:57:10] [PASSED] 0xA7AA (ALDERLAKE_P)
[10:57:10] [PASSED] 0xA7AB (ALDERLAKE_P)
[10:57:10] [PASSED] 0xA780 (ALDERLAKE_S)
[10:57:10] [PASSED] 0xA781 (ALDERLAKE_S)
[10:57:10] [PASSED] 0xA782 (ALDERLAKE_S)
[10:57:10] [PASSED] 0xA783 (ALDERLAKE_S)
[10:57:10] [PASSED] 0xA788 (ALDERLAKE_S)
[10:57:10] [PASSED] 0xA789 (ALDERLAKE_S)
[10:57:10] [PASSED] 0xA78A (ALDERLAKE_S)
[10:57:10] [PASSED] 0xA78B (ALDERLAKE_S)
[10:57:10] [PASSED] 0x4905 (DG1)
[10:57:10] [PASSED] 0x4906 (DG1)
[10:57:10] [PASSED] 0x4907 (DG1)
[10:57:10] [PASSED] 0x4908 (DG1)
[10:57:10] [PASSED] 0x4909 (DG1)
[10:57:10] [PASSED] 0x56C0 (DG2)
[10:57:10] [PASSED] 0x56C2 (DG2)
[10:57:10] [PASSED] 0x56C1 (DG2)
[10:57:10] [PASSED] 0x7D51 (METEORLAKE)
[10:57:10] [PASSED] 0x7DD1 (METEORLAKE)
[10:57:10] [PASSED] 0x7D41 (METEORLAKE)
[10:57:10] [PASSED] 0x7D67 (METEORLAKE)
[10:57:10] [PASSED] 0xB640 (METEORLAKE)
[10:57:10] [PASSED] 0x56A0 (DG2)
[10:57:10] [PASSED] 0x56A1 (DG2)
[10:57:10] [PASSED] 0x56A2 (DG2)
[10:57:10] [PASSED] 0x56BE (DG2)
[10:57:10] [PASSED] 0x56BF (DG2)
[10:57:10] [PASSED] 0x5690 (DG2)
[10:57:10] [PASSED] 0x5691 (DG2)
[10:57:10] [PASSED] 0x5692 (DG2)
[10:57:10] [PASSED] 0x56A5 (DG2)
[10:57:10] [PASSED] 0x56A6 (DG2)
[10:57:10] [PASSED] 0x56B0 (DG2)
[10:57:10] [PASSED] 0x56B1 (DG2)
[10:57:10] [PASSED] 0x56BA (DG2)
[10:57:10] [PASSED] 0x56BB (DG2)
[10:57:10] [PASSED] 0x56BC (DG2)
[10:57:10] [PASSED] 0x56BD (DG2)
[10:57:10] [PASSED] 0x5693 (DG2)
[10:57:10] [PASSED] 0x5694 (DG2)
[10:57:10] [PASSED] 0x5695 (DG2)
[10:57:10] [PASSED] 0x56A3 (DG2)
[10:57:10] [PASSED] 0x56A4 (DG2)
[10:57:10] [PASSED] 0x56B2 (DG2)
[10:57:10] [PASSED] 0x56B3 (DG2)
[10:57:10] [PASSED] 0x5696 (DG2)
[10:57:10] [PASSED] 0x5697 (DG2)
[10:57:10] [PASSED] 0xB69 (PVC)
[10:57:10] [PASSED] 0xB6E (PVC)
[10:57:10] [PASSED] 0xBD4 (PVC)
[10:57:10] [PASSED] 0xBD5 (PVC)
[10:57:10] [PASSED] 0xBD6 (PVC)
[10:57:10] [PASSED] 0xBD7 (PVC)
[10:57:10] [PASSED] 0xBD8 (PVC)
[10:57:10] [PASSED] 0xBD9 (PVC)
[10:57:10] [PASSED] 0xBDA (PVC)
[10:57:10] [PASSED] 0xBDB (PVC)
[10:57:10] [PASSED] 0xBE0 (PVC)
[10:57:10] [PASSED] 0xBE1 (PVC)
[10:57:10] [PASSED] 0xBE5 (PVC)
[10:57:10] [PASSED] 0x7D40 (METEORLAKE)
[10:57:10] [PASSED] 0x7D45 (METEORLAKE)
[10:57:10] [PASSED] 0x7D55 (METEORLAKE)
[10:57:10] [PASSED] 0x7D60 (METEORLAKE)
[10:57:10] [PASSED] 0x7DD5 (METEORLAKE)
[10:57:10] [PASSED] 0x6420 (LUNARLAKE)
[10:57:10] [PASSED] 0x64A0 (LUNARLAKE)
[10:57:10] [PASSED] 0x64B0 (LUNARLAKE)
[10:57:10] [PASSED] 0xE202 (BATTLEMAGE)
[10:57:10] [PASSED] 0xE209 (BATTLEMAGE)
[10:57:10] [PASSED] 0xE20B (BATTLEMAGE)
[10:57:10] [PASSED] 0xE20C (BATTLEMAGE)
[10:57:10] [PASSED] 0xE20D (BATTLEMAGE)
[10:57:10] [PASSED] 0xE210 (BATTLEMAGE)
[10:57:10] [PASSED] 0xE211 (BATTLEMAGE)
[10:57:10] [PASSED] 0xE212 (BATTLEMAGE)
[10:57:10] [PASSED] 0xE216 (BATTLEMAGE)
[10:57:10] [PASSED] 0xE220 (BATTLEMAGE)
[10:57:10] [PASSED] 0xE221 (BATTLEMAGE)
[10:57:10] [PASSED] 0xE222 (BATTLEMAGE)
[10:57:10] [PASSED] 0xE223 (BATTLEMAGE)
[10:57:10] [PASSED] 0xB080 (PANTHERLAKE)
[10:57:10] [PASSED] 0xB081 (PANTHERLAKE)
[10:57:10] [PASSED] 0xB082 (PANTHERLAKE)
[10:57:10] [PASSED] 0xB083 (PANTHERLAKE)
[10:57:10] [PASSED] 0xB084 (PANTHERLAKE)
[10:57:10] [PASSED] 0xB085 (PANTHERLAKE)
[10:57:10] [PASSED] 0xB086 (PANTHERLAKE)
[10:57:10] [PASSED] 0xB087 (PANTHERLAKE)
[10:57:10] [PASSED] 0xB08F (PANTHERLAKE)
[10:57:10] [PASSED] 0xB090 (PANTHERLAKE)
[10:57:10] [PASSED] 0xB0A0 (PANTHERLAKE)
[10:57:10] [PASSED] 0xB0B0 (PANTHERLAKE)
[10:57:10] [PASSED] 0xFD80 (PANTHERLAKE)
[10:57:10] [PASSED] 0xFD81 (PANTHERLAKE)
[10:57:10] [PASSED] 0xD740 (NOVALAKE_S)
[10:57:10] [PASSED] 0xD741 (NOVALAKE_S)
[10:57:10] [PASSED] 0xD742 (NOVALAKE_S)
[10:57:10] [PASSED] 0xD743 (NOVALAKE_S)
[10:57:10] [PASSED] 0xD745 (NOVALAKE_S)
[10:57:10] [PASSED] 0xD74A (NOVALAKE_S)
[10:57:10] [PASSED] 0xD74B (NOVALAKE_S)
[10:57:10] [PASSED] 0x674C (CRESCENTISLAND)
[10:57:10] [PASSED] 0x674D (CRESCENTISLAND)
[10:57:10] [PASSED] 0x674E (CRESCENTISLAND)
[10:57:10] [PASSED] 0x674F (CRESCENTISLAND)
[10:57:10] [PASSED] 0x6750 (CRESCENTISLAND)
[10:57:10] [PASSED] 0xD750 (NOVALAKE_P)
[10:57:10] [PASSED] 0xD751 (NOVALAKE_P)
[10:57:10] [PASSED] 0xD752 (NOVALAKE_P)
[10:57:10] [PASSED] 0xD753 (NOVALAKE_P)
[10:57:10] [PASSED] 0xD754 (NOVALAKE_P)
[10:57:10] [PASSED] 0xD755 (NOVALAKE_P)
[10:57:10] [PASSED] 0xD756 (NOVALAKE_P)
[10:57:10] [PASSED] 0xD757 (NOVALAKE_P)
[10:57:10] [PASSED] 0xD75F (NOVALAKE_P)
[10:57:10] =============== [PASSED] check_platform_desc ===============
[10:57:10] ===================== [PASSED] xe_pci ======================
[10:57:10] ============= xe_rtp_tables_test (5 subtests) ==============
[10:57:10] ================== xe_rtp_table_gt_test  ===================
[10:57:10] [PASSED] gt_was/14011060649
[10:57:10] [PASSED] gt_was/14011059788
[10:57:10] [PASSED] gt_was/14015795083
[10:57:10] [PASSED] gt_was/16021867713
[10:57:10] [PASSED] gt_was/14019449301
[10:57:10] [PASSED] gt_was/16028005424
[10:57:10] [PASSED] gt_was/14026578760
[10:57:10] [PASSED] gt_was/1409420604
[10:57:10] [PASSED] gt_was/1408615072
[10:57:10] [PASSED] gt_was/22010523718
[10:57:10] [PASSED] gt_was/14011006942
[10:57:10] [PASSED] gt_was/14014830051
[10:57:10] [PASSED] gt_was/18018781329
[10:57:10] [PASSED] gt_was/1509235366
[10:57:10] [PASSED] gt_was/18018781329
[10:57:10] [PASSED] gt_was/16016694945
[10:57:10] [PASSED] gt_was/14018575942
[10:57:10] [PASSED] gt_was/22016670082
[10:57:10] [PASSED] gt_was/22016670082
[10:57:10] [PASSED] gt_was/14017421178
[10:57:10] [PASSED] gt_was/16025250150
[10:57:10] [PASSED] gt_was/14021871409
[10:57:10] [PASSED] gt_was/16021865536
[10:57:10] [PASSED] gt_was/14021486841
[10:57:10] [PASSED] gt_was/14025160223
[10:57:10] [PASSED] gt_was/14026144927, 16029437861, 14026127056
[10:57:10] [PASSED] gt_was/14025635424
[10:57:10] [PASSED] gt_was/16028005424
[10:57:10] ============== [PASSED] xe_rtp_table_gt_test ===============
[10:57:10] ================== xe_rtp_table_gt_test  ===================
[10:57:10] [PASSED] gt_tunings/Tuning: Blend Fill Caching Optimization Disable
[10:57:10] [PASSED] gt_tunings/Tuning: 32B Access Enable
[10:57:10] [PASSED] gt_tunings/Tuning: L3 cache
[10:57:10] [PASSED] gt_tunings/Tuning: L3 cache - media
[10:57:10] [PASSED] gt_tunings/Tuning: Compression Overfetch
[10:57:10] [PASSED] gt_tunings/Tuning: Compression Overfetch - media
[10:57:10] [PASSED] gt_tunings/Tuning: Enable compressible partial write overfetch in L3
[10:57:10] [PASSED] gt_tunings/Tuning: Enable compressible partial write overfetch in L3 - media
[10:57:10] [PASSED] gt_tunings/Tuning: L2 Overfetch Compressible Only
[10:57:10] [PASSED] gt_tunings/Tuning: L2 Overfetch Compressible Only - media
[10:57:10] [PASSED] gt_tunings/Tuning: Stateless compression control
[10:57:10] [PASSED] gt_tunings/Tuning: Stateless compression control - media
[10:57:10] [PASSED] gt_tunings/Tuning: L3 RW flush all Cache
[10:57:10] [PASSED] gt_tunings/Tuning: L3 RW flush all cache - media
[10:57:10] [PASSED] gt_tunings/Tuning: Set STLB Bank Hash Mode to 4KB
[10:57:10] ============== [PASSED] xe_rtp_table_gt_test ===============
[10:57:10] ================== xe_rtp_table_oob_test  ==================
[10:57:10] [PASSED] oob_was/1607983814
[10:57:10] [PASSED] oob_was/16010904313
[10:57:10] [PASSED] oob_was/18022495364
[10:57:10] [PASSED] oob_was/22012773006
[10:57:10] [PASSED] oob_was/14014475959
[10:57:10] [PASSED] oob_was/22011391025
[10:57:10] [PASSED] oob_was/22012727170
[10:57:10] [PASSED] oob_was/22012727685
[10:57:10] [PASSED] oob_was/22016596838
[10:57:10] [PASSED] oob_was/18020744125
[10:57:10] [PASSED] oob_was/1409600907
[10:57:10] [PASSED] oob_was/22014953428
[10:57:10] [PASSED] oob_was/16017236439
[10:57:10] [PASSED] oob_was/14019821291
[10:57:10] [PASSED] oob_was/14015076503
[10:57:10] [PASSED] oob_was/14018913170
[10:57:10] [PASSED] oob_was/14018094691
[10:57:10] [PASSED] oob_was/18024947630
[10:57:10] [PASSED] oob_was/16022287689
[10:57:10] [PASSED] oob_was/13011645652
[10:57:10] [PASSED] oob_was/14022293748
[10:57:10] [PASSED] oob_was/22019794406
[10:57:10] [PASSED] oob_was/22019338487
[10:57:10] [PASSED] oob_was/16023588340
[10:57:10] [PASSED] oob_was/14019789679
[10:57:10] [PASSED] oob_was/14022866841
[10:57:10] [PASSED] oob_was/16021333562
[10:57:10] [PASSED] oob_was/14016712196
[10:57:10] [PASSED] oob_was/14015568240
[10:57:10] [PASSED] oob_was/18013179988
[10:57:10] [PASSED] oob_was/1508761755
[10:57:10] [PASSED] oob_was/16023105232
[10:57:10] [PASSED] oob_was/16026508708
[10:57:10] [PASSED] oob_was/14020001231
[10:57:10] [PASSED] oob_was/16023683509
[10:57:10] [PASSED] oob_was/14025515070
[10:57:10] [PASSED] oob_was/15015404425_disable
[10:57:10] [PASSED] oob_was/16026007364
[10:57:10] [PASSED] oob_was/14020316580
[10:57:10] [PASSED] oob_was/14025883347
[10:57:10] [PASSED] oob_was/16029380221
[10:57:10] [PASSED] oob_was/22022079272
[10:57:10] [PASSED] oob_was/16029897822
[10:57:10] ============== [PASSED] xe_rtp_table_oob_test ==============
[10:57:10] ================ xe_rtp_table_dev_oob_test  ================
[10:57:10] [PASSED] device_oob_was/22010954014
[10:57:10] [PASSED] device_oob_was/15015404425
[10:57:10] [PASSED] device_oob_was/22019338487_display
[10:57:10] [PASSED] device_oob_was/14022085890
[10:57:10] [PASSED] device_oob_was/14026539277
[10:57:10] [PASSED] device_oob_was/14026633728
[10:57:10] [PASSED] device_oob_was/14026746987
[10:57:10] [PASSED] device_oob_was/14026779378
[10:57:10] ============ [PASSED] xe_rtp_table_dev_oob_test ============
[10:57:10] ========== xe_rtp_table_missing_upper_bound_test  ==========
[10:57:10] [PASSED] register_whitelist/WaAllowPMDepthAndInvocationCountAccessFromUMD, 1408556865
[10:57:10] [PASSED] register_whitelist/1508744258, 14012131227, 1808121037
[10:57:10] [PASSED] register_whitelist/1806527549
[10:57:10] [PASSED] register_whitelist/allow_read_ctx_timestamp
[10:57:10] [PASSED] register_whitelist/allow_read_queue_timestamp
[10:57:10] [PASSED] register_whitelist/16014440446
[10:57:10] [PASSED] register_whitelist/16017236439
[10:57:10] [PASSED] register_whitelist/16020183090
[10:57:10] [PASSED] register_whitelist/14024997852
[10:57:10] [PASSED] register_whitelist/14024997852
[10:57:10] ====== [PASSED] xe_rtp_table_missing_upper_bound_test ======
[10:57:10] =============== [PASSED] xe_rtp_tables_test ================
[10:57:10] =================== xe_rtp (3 subtests) ====================
[10:57:10] =================== xe_rtp_rules_tests  ====================
[10:57:10] [PASSED] no
[10:57:10] [PASSED] yes
[10:57:10] [PASSED] no-and-no
[10:57:10] [PASSED] no-and-yes
[10:57:10] [PASSED] yes-and-no
[10:57:10] [PASSED] yes-and-yes
[10:57:10] [PASSED] no-or-no
[10:57:10] [PASSED] no-or-yes
[10:57:10] [PASSED] yes-or-no
[10:57:10] [PASSED] yes-or-yes
[10:57:10] [PASSED] no-yes-or-yes-no
[10:57:10] [PASSED] no-yes-or-yes-yes
[10:57:10] [PASSED] yes-yes-or-no-yes
[10:57:10] [PASSED] yes-yes-or-yes-yes
[10:57:10] [PASSED] no-no-or-yes-or-no
[10:57:10] [PASSED] or
[10:57:10] [PASSED] or-yes
[10:57:10] [PASSED] or-no
[10:57:10] [PASSED] yes-or
[10:57:10] [PASSED] no-or
[10:57:10] [PASSED] no-or-or-yes
[10:57:10] [PASSED] yes-or-or-no
[10:57:10] [PASSED] no-or-or-no
[10:57:10] [PASSED] missing-context-engine-class
[10:57:10] [PASSED] missing-context-engine-class-or-yes
[10:57:10] [PASSED] missing-context-engine-class-or-or-yes
[10:57:10] =============== [PASSED] xe_rtp_rules_tests ================
[10:57:10] =============== xe_rtp_process_to_sr_tests  ================
[10:57:10] [PASSED] coalesce-same-reg
[10:57:10] [PASSED] coalesce-same-reg-literal-and-func
[10:57:10] [PASSED] no-match-no-add
[10:57:10] [PASSED] two-regs-two-entries
[10:57:10] [PASSED] clr-one-set-other
[10:57:10] [PASSED] set-field
[10:57:10] [PASSED] conflict-duplicate
[10:57:10] [PASSED] conflict-not-disjoint
[10:57:10] [PASSED] conflict-not-disjoint-literal-and-func
[10:57:10] [PASSED] conflict-reg-type
[10:57:10] [PASSED] bad-mcr-reg-forced-to-regular
[10:57:10] [PASSED] bad-regular-reg-forced-to-mcr
[10:57:10] =========== [PASSED] xe_rtp_process_to_sr_tests ============
[10:57:10] ================== xe_rtp_process_tests  ===================
[10:57:10] [PASSED] active1
[10:57:10] [PASSED] active2
[10:57:10] [PASSED] active-inactive
[10:57:10] [PASSED] inactive-active
[10:57:10] [PASSED] inactive-active-inactive
[10:57:10] [PASSED] inactive-inactive-inactive
[10:57:10] ============== [PASSED] xe_rtp_process_tests ===============
[10:57:10] ===================== [PASSED] xe_rtp ======================
[10:57:10] ==================== xe_wa (1 subtest) =====================
[10:57:10] ======================== xe_wa_gt  =========================
[10:57:10] [PASSED] TIGERLAKE B0
[10:57:10] [PASSED] DG1 A0
[10:57:10] [PASSED] DG1 B0
[10:57:10] [PASSED] ALDERLAKE_S A0
[10:57:10] [PASSED] ALDERLAKE_S B0
[10:57:10] [PASSED] ALDERLAKE_S C0
[10:57:10] [PASSED] ALDERLAKE_S D0
[10:57:10] [PASSED] ALDERLAKE_P A0
[10:57:10] [PASSED] ALDERLAKE_P B0
[10:57:10] [PASSED] ALDERLAKE_P C0
[10:57:10] [PASSED] ALDERLAKE_S RPLS D0
[10:57:10] [PASSED] ALDERLAKE_P RPLU E0
[10:57:10] [PASSED] DG2 G10 C0
[10:57:10] [PASSED] DG2 G11 B1
[10:57:10] [PASSED] DG2 G12 A1
[10:57:10] [PASSED] METEORLAKE 12.70(Xe_LPG) A0 13.00(Xe_LPM+) A0
[10:57:10] [PASSED] METEORLAKE 12.71(Xe_LPG) A0 13.00(Xe_LPM+) A0
[10:57:10] [PASSED] METEORLAKE 12.74(Xe_LPG+) A0 13.00(Xe_LPM+) A0
[10:57:10] [PASSED] LUNARLAKE 20.04(Xe2_LPG) A0 20.00(Xe2_LPM) A0
[10:57:10] [PASSED] LUNARLAKE 20.04(Xe2_LPG) B0 20.00(Xe2_LPM) A0
[10:57:10] [PASSED] BATTLEMAGE 20.01(Xe2_HPG) A0 13.01(Xe2_HPM) A1
[10:57:10] [PASSED] PANTHERLAKE 30.00(Xe3_LPG) A0 30.00(Xe3_LPM) A0
[10:57:10] ==================== [PASSED] xe_wa_gt =====================
[10:57:10] ====================== [PASSED] xe_wa ======================
[10:57:10] ============================================================
[10:57:10] Testing complete. Ran 741 tests: passed: 723, skipped: 18
[10:57:10] Elapsed time: 36.566s total, 4.367s configuring, 31.533s building, 0.655s running

+ /kernel/tools/testing/kunit/kunit.py run --kunitconfig /kernel/drivers/gpu/drm/tests/.kunitconfig
[10:57:10] Configuring KUnit Kernel ...
Regenerating .config ...
Populating config with:
$ make ARCH=um O=.kunit olddefconfig
[10:57:11] Building KUnit Kernel ...
Populating config with:
$ make ARCH=um O=.kunit olddefconfig
Building with:
$ make all compile_commands.json scripts_gdb ARCH=um O=.kunit --jobs=48
[10:57:36] Starting KUnit Kernel (1/1)...
[10:57:36] ============================================================
Running tests with:
$ .kunit/linux kunit.enable=1 mem=1G console=tty kunit_shutdown=halt
[10:57:36] ============ drm_test_pick_cmdline (2 subtests) ============
[10:57:36] [PASSED] drm_test_pick_cmdline_res_1920_1080_60
[10:57:36] =============== drm_test_pick_cmdline_named  ===============
[10:57:36] [PASSED] NTSC
[10:57:36] [PASSED] NTSC-J
[10:57:36] [PASSED] PAL
[10:57:36] [PASSED] PAL-M
[10:57:36] =========== [PASSED] drm_test_pick_cmdline_named ===========
[10:57:36] ============== [PASSED] drm_test_pick_cmdline ==============
[10:57:36] == drm_test_atomic_get_connector_for_encoder (1 subtest) ===
[10:57:36] [PASSED] drm_test_drm_atomic_get_connector_for_encoder
[10:57:36] ==== [PASSED] drm_test_atomic_get_connector_for_encoder ====
[10:57:36] =========== drm_validate_clone_mode (2 subtests) ===========
[10:57:36] ============== drm_test_check_in_clone_mode  ===============
[10:57:36] [PASSED] in_clone_mode
[10:57:36] [PASSED] not_in_clone_mode
[10:57:36] ========== [PASSED] drm_test_check_in_clone_mode ===========
[10:57:36] =============== drm_test_check_valid_clones  ===============
[10:57:36] [PASSED] not_in_clone_mode
[10:57:36] [PASSED] valid_clone
[10:57:36] [PASSED] invalid_clone
[10:57:36] =========== [PASSED] drm_test_check_valid_clones ===========
[10:57:36] ============= [PASSED] drm_validate_clone_mode =============
[10:57:36] ============= drm_validate_modeset (1 subtest) =============
[10:57:36] [PASSED] drm_test_check_connector_changed_modeset
[10:57:36] ============== [PASSED] drm_validate_modeset ===============
[10:57:36] ====== drm_test_bridge_get_current_state (2 subtests) ======
[10:57:36] [PASSED] drm_test_drm_bridge_get_current_state_atomic
[10:57:36] [PASSED] drm_test_drm_bridge_get_current_state_legacy
[10:57:36] ======== [PASSED] drm_test_bridge_get_current_state ========
[10:57:36] ====== drm_test_bridge_helper_reset_crtc (4 subtests) ======
[10:57:36] [PASSED] drm_test_drm_bridge_helper_reset_crtc_atomic
[10:57:36] [PASSED] drm_test_drm_bridge_helper_reset_crtc_atomic_disabled
[10:57:36] [PASSED] drm_test_drm_bridge_helper_reset_crtc_legacy
[10:57:36] [PASSED] drm_test_drm_bridge_helper_hdmi_output_bus_fmts
[10:57:36] ======== [PASSED] drm_test_bridge_helper_reset_crtc ========
[10:57:36] ============== drm_bridge_alloc (2 subtests) ===============
[10:57:36] [PASSED] drm_test_drm_bridge_alloc_basic
[10:57:36] [PASSED] drm_test_drm_bridge_alloc_get_put
[10:57:36] ================ [PASSED] drm_bridge_alloc =================
[10:57:36] ============= drm_bridge_bus_fmt (5 subtests) ==============
[10:57:36] [PASSED] drm_test_bridge_rgb_yuv_rgb
[10:57:36] [PASSED] drm_test_bridge_must_convert_to_yuv444
[10:57:36] [PASSED] drm_test_bridge_hdmi_auto_rgb
[10:57:36] [PASSED] drm_test_bridge_auto_first
[10:57:36] [PASSED] drm_test_bridge_rgb_yuv_no_path
[10:57:36] =============== [PASSED] drm_bridge_bus_fmt ================
[10:57:36] ============= drm_cmdline_parser (40 subtests) =============
[10:57:36] [PASSED] drm_test_cmdline_force_d_only
[10:57:36] [PASSED] drm_test_cmdline_force_D_only_dvi
[10:57:36] [PASSED] drm_test_cmdline_force_D_only_hdmi
[10:57:36] [PASSED] drm_test_cmdline_force_D_only_not_digital
[10:57:36] [PASSED] drm_test_cmdline_force_e_only
[10:57:36] [PASSED] drm_test_cmdline_res
[10:57:36] [PASSED] drm_test_cmdline_res_vesa
[10:57:36] [PASSED] drm_test_cmdline_res_vesa_rblank
[10:57:36] [PASSED] drm_test_cmdline_res_rblank
[10:57:36] [PASSED] drm_test_cmdline_res_bpp
[10:57:36] [PASSED] drm_test_cmdline_res_refresh
[10:57:36] [PASSED] drm_test_cmdline_res_bpp_refresh
[10:57:36] [PASSED] drm_test_cmdline_res_bpp_refresh_interlaced
[10:57:36] [PASSED] drm_test_cmdline_res_bpp_refresh_margins
[10:57:36] [PASSED] drm_test_cmdline_res_bpp_refresh_force_off
[10:57:36] [PASSED] drm_test_cmdline_res_bpp_refresh_force_on
[10:57:36] [PASSED] drm_test_cmdline_res_bpp_refresh_force_on_analog
[10:57:36] [PASSED] drm_test_cmdline_res_bpp_refresh_force_on_digital
[10:57:36] [PASSED] drm_test_cmdline_res_bpp_refresh_interlaced_margins_force_on
[10:57:36] [PASSED] drm_test_cmdline_res_margins_force_on
[10:57:36] [PASSED] drm_test_cmdline_res_vesa_margins
[10:57:36] [PASSED] drm_test_cmdline_name
[10:57:36] [PASSED] drm_test_cmdline_name_bpp
[10:57:36] [PASSED] drm_test_cmdline_name_option
[10:57:36] [PASSED] drm_test_cmdline_name_bpp_option
[10:57:36] [PASSED] drm_test_cmdline_rotate_0
[10:57:36] [PASSED] drm_test_cmdline_rotate_90
[10:57:36] [PASSED] drm_test_cmdline_rotate_180
[10:57:36] [PASSED] drm_test_cmdline_rotate_270
[10:57:36] [PASSED] drm_test_cmdline_hmirror
[10:57:36] [PASSED] drm_test_cmdline_vmirror
[10:57:36] [PASSED] drm_test_cmdline_margin_options
[10:57:36] [PASSED] drm_test_cmdline_multiple_options
[10:57:36] [PASSED] drm_test_cmdline_bpp_extra_and_option
[10:57:36] [PASSED] drm_test_cmdline_extra_and_option
[10:57:36] [PASSED] drm_test_cmdline_freestanding_options
[10:57:36] [PASSED] drm_test_cmdline_freestanding_force_e_and_options
[10:57:36] [PASSED] drm_test_cmdline_panel_orientation
[10:57:36] ================ drm_test_cmdline_invalid  =================
[10:57:36] [PASSED] margin_only
[10:57:36] [PASSED] interlace_only
[10:57:36] [PASSED] res_missing_x
[10:57:36] [PASSED] res_missing_y
[10:57:36] [PASSED] res_bad_y
[10:57:36] [PASSED] res_missing_y_bpp
[10:57:36] [PASSED] res_bad_bpp
[10:57:36] [PASSED] res_bad_refresh
[10:57:36] [PASSED] res_bpp_refresh_force_on_off
[10:57:36] [PASSED] res_invalid_mode
[10:57:36] [PASSED] res_bpp_wrong_place_mode
[10:57:36] [PASSED] name_bpp_refresh
[10:57:36] [PASSED] name_refresh
[10:57:36] [PASSED] name_refresh_wrong_mode
[10:57:36] [PASSED] name_refresh_invalid_mode
[10:57:36] [PASSED] rotate_multiple
[10:57:36] [PASSED] rotate_invalid_val
[10:57:36] [PASSED] rotate_truncated
[10:57:36] [PASSED] invalid_option
[10:57:36] [PASSED] invalid_tv_option
[10:57:36] [PASSED] truncated_tv_option
[10:57:36] ============ [PASSED] drm_test_cmdline_invalid =============
[10:57:36] =============== drm_test_cmdline_tv_options  ===============
[10:57:36] [PASSED] NTSC
[10:57:36] [PASSED] NTSC_443
[10:57:36] [PASSED] NTSC_J
[10:57:36] [PASSED] PAL
[10:57:36] [PASSED] PAL_M
[10:57:36] [PASSED] PAL_N
[10:57:36] [PASSED] SECAM
[10:57:36] [PASSED] MONO_525
[10:57:36] [PASSED] MONO_625
[10:57:36] =========== [PASSED] drm_test_cmdline_tv_options ===========
[10:57:36] =============== [PASSED] drm_cmdline_parser ================
[10:57:36] ========== drmm_connector_hdmi_init (20 subtests) ==========
[10:57:36] [PASSED] drm_test_connector_hdmi_init_valid
[10:57:36] [PASSED] drm_test_connector_hdmi_init_bpc_8
[10:57:36] [PASSED] drm_test_connector_hdmi_init_bpc_10
[10:57:36] [PASSED] drm_test_connector_hdmi_init_bpc_12
[10:57:36] [PASSED] drm_test_connector_hdmi_init_bpc_invalid
[10:57:36] [PASSED] drm_test_connector_hdmi_init_bpc_null
[10:57:36] [PASSED] drm_test_connector_hdmi_init_formats_empty
[10:57:36] [PASSED] drm_test_connector_hdmi_init_formats_no_rgb
[10:57:36] === drm_test_connector_hdmi_init_formats_yuv420_allowed  ===
[10:57:36] [PASSED] supported_formats=0x9 yuv420_allowed=1
[10:57:36] [PASSED] supported_formats=0x9 yuv420_allowed=0
[10:57:36] [PASSED] supported_formats=0x5 yuv420_allowed=1
[10:57:36] [PASSED] supported_formats=0x5 yuv420_allowed=0
[10:57:36] === [PASSED] drm_test_connector_hdmi_init_formats_yuv420_allowed ===
[10:57:36] [PASSED] drm_test_connector_hdmi_init_null_ddc
[10:57:36] [PASSED] drm_test_connector_hdmi_init_null_product
[10:57:36] [PASSED] drm_test_connector_hdmi_init_null_vendor
[10:57:36] [PASSED] drm_test_connector_hdmi_init_product_length_exact
[10:57:36] [PASSED] drm_test_connector_hdmi_init_product_length_too_long
[10:57:36] [PASSED] drm_test_connector_hdmi_init_product_valid
[10:57:36] [PASSED] drm_test_connector_hdmi_init_vendor_length_exact
[10:57:36] [PASSED] drm_test_connector_hdmi_init_vendor_length_too_long
[10:57:36] [PASSED] drm_test_connector_hdmi_init_vendor_valid
[10:57:36] ========= drm_test_connector_hdmi_init_type_valid  =========
[10:57:36] [PASSED] HDMI-A
[10:57:36] [PASSED] HDMI-B
[10:57:36] ===== [PASSED] drm_test_connector_hdmi_init_type_valid =====
[10:57:36] ======== drm_test_connector_hdmi_init_type_invalid  ========
[10:57:36] [PASSED] Unknown
[10:57:36] [PASSED] VGA
[10:57:36] [PASSED] DVI-I
[10:57:36] [PASSED] DVI-D
[10:57:36] [PASSED] DVI-A
[10:57:36] [PASSED] Composite
[10:57:36] [PASSED] SVIDEO
[10:57:36] [PASSED] LVDS
[10:57:36] [PASSED] Component
[10:57:36] [PASSED] DIN
[10:57:36] [PASSED] DP
[10:57:36] [PASSED] TV
[10:57:36] [PASSED] eDP
[10:57:36] [PASSED] Virtual
[10:57:36] [PASSED] DSI
[10:57:36] [PASSED] DPI
[10:57:36] [PASSED] Writeback
[10:57:36] [PASSED] SPI
[10:57:36] [PASSED] USB
[10:57:36] ==== [PASSED] drm_test_connector_hdmi_init_type_invalid ====
[10:57:36] ============ [PASSED] drmm_connector_hdmi_init =============
[10:57:36] ============= drmm_connector_init (3 subtests) =============
[10:57:36] [PASSED] drm_test_drmm_connector_init
[10:57:36] [PASSED] drm_test_drmm_connector_init_null_ddc
[10:57:36] ========= drm_test_drmm_connector_init_type_valid  =========
[10:57:36] [PASSED] Unknown
[10:57:36] [PASSED] VGA
[10:57:36] [PASSED] DVI-I
[10:57:36] [PASSED] DVI-D
[10:57:36] [PASSED] DVI-A
[10:57:36] [PASSED] Composite
[10:57:36] [PASSED] SVIDEO
[10:57:36] [PASSED] LVDS
[10:57:36] [PASSED] Component
[10:57:36] [PASSED] DIN
[10:57:36] [PASSED] DP
[10:57:36] [PASSED] HDMI-A
[10:57:36] [PASSED] HDMI-B
[10:57:36] [PASSED] TV
[10:57:36] [PASSED] eDP
[10:57:36] [PASSED] Virtual
[10:57:36] [PASSED] DSI
[10:57:36] [PASSED] DPI
[10:57:36] [PASSED] Writeback
[10:57:36] [PASSED] SPI
[10:57:36] [PASSED] USB
[10:57:36] ===== [PASSED] drm_test_drmm_connector_init_type_valid =====
[10:57:36] =============== [PASSED] drmm_connector_init ===============
[10:57:36] ========= drm_connector_dynamic_init (6 subtests) ==========
[10:57:36] [PASSED] drm_test_drm_connector_dynamic_init
[10:57:36] [PASSED] drm_test_drm_connector_dynamic_init_null_ddc
[10:57:36] [PASSED] drm_test_drm_connector_dynamic_init_not_added
[10:57:36] [PASSED] drm_test_drm_connector_dynamic_init_properties
[10:57:36] ===== drm_test_drm_connector_dynamic_init_type_valid  ======
[10:57:36] [PASSED] Unknown
[10:57:36] [PASSED] VGA
[10:57:36] [PASSED] DVI-I
[10:57:36] [PASSED] DVI-D
[10:57:36] [PASSED] DVI-A
[10:57:36] [PASSED] Composite
[10:57:36] [PASSED] SVIDEO
[10:57:36] [PASSED] LVDS
[10:57:36] [PASSED] Component
[10:57:36] [PASSED] DIN
[10:57:36] [PASSED] DP
[10:57:36] [PASSED] HDMI-A
[10:57:36] [PASSED] HDMI-B
[10:57:36] [PASSED] TV
[10:57:36] [PASSED] eDP
[10:57:36] [PASSED] Virtual
[10:57:36] [PASSED] DSI
[10:57:36] [PASSED] DPI
[10:57:36] [PASSED] Writeback
[10:57:36] [PASSED] SPI
[10:57:36] [PASSED] USB
[10:57:36] = [PASSED] drm_test_drm_connector_dynamic_init_type_valid ==
[10:57:36] ======== drm_test_drm_connector_dynamic_init_name  =========
[10:57:36] [PASSED] Unknown
[10:57:36] [PASSED] VGA
[10:57:36] [PASSED] DVI-I
[10:57:36] [PASSED] DVI-D
[10:57:36] [PASSED] DVI-A
[10:57:36] [PASSED] Composite
[10:57:36] [PASSED] SVIDEO
[10:57:36] [PASSED] LVDS
[10:57:36] [PASSED] Component
[10:57:36] [PASSED] DIN
[10:57:36] [PASSED] DP
[10:57:36] [PASSED] HDMI-A
[10:57:36] [PASSED] HDMI-B
[10:57:36] [PASSED] TV
[10:57:36] [PASSED] eDP
[10:57:36] [PASSED] Virtual
[10:57:36] [PASSED] DSI
[10:57:36] [PASSED] DPI
[10:57:36] [PASSED] Writeback
[10:57:36] [PASSED] SPI
[10:57:36] [PASSED] USB
[10:57:36] ==== [PASSED] drm_test_drm_connector_dynamic_init_name =====
[10:57:36] =========== [PASSED] drm_connector_dynamic_init ============
[10:57:36] ==== drm_connector_dynamic_register_early (4 subtests) =====
[10:57:36] [PASSED] drm_test_drm_connector_dynamic_register_early_on_list
[10:57:36] [PASSED] drm_test_drm_connector_dynamic_register_early_defer
[10:57:36] [PASSED] drm_test_drm_connector_dynamic_register_early_no_init
[10:57:36] [PASSED] drm_test_drm_connector_dynamic_register_early_no_mode_object
[10:57:36] ====== [PASSED] drm_connector_dynamic_register_early =======
[10:57:36] ======= drm_connector_dynamic_register (7 subtests) ========
[10:57:36] [PASSED] drm_test_drm_connector_dynamic_register_on_list
[10:57:36] [PASSED] drm_test_drm_connector_dynamic_register_no_defer
[10:57:36] [PASSED] drm_test_drm_connector_dynamic_register_no_init
[10:57:36] [PASSED] drm_test_drm_connector_dynamic_register_mode_object
[10:57:36] [PASSED] drm_test_drm_connector_dynamic_register_sysfs
[10:57:36] [PASSED] drm_test_drm_connector_dynamic_register_sysfs_name
[10:57:36] [PASSED] drm_test_drm_connector_dynamic_register_debugfs
[10:57:36] ========= [PASSED] drm_connector_dynamic_register ==========
[10:57:36] = drm_connector_attach_broadcast_rgb_property (2 subtests) =
[10:57:36] [PASSED] drm_test_drm_connector_attach_broadcast_rgb_property
[10:57:36] [PASSED] drm_test_drm_connector_attach_broadcast_rgb_property_hdmi_connector
[10:57:36] === [PASSED] drm_connector_attach_broadcast_rgb_property ===
[10:57:36] ========== drm_get_tv_mode_from_name (2 subtests) ==========
[10:57:36] ========== drm_test_get_tv_mode_from_name_valid  ===========
[10:57:36] [PASSED] NTSC
[10:57:36] [PASSED] NTSC-443
[10:57:36] [PASSED] NTSC-J
[10:57:36] [PASSED] PAL
[10:57:36] [PASSED] PAL-M
[10:57:36] [PASSED] PAL-N
[10:57:36] [PASSED] SECAM
[10:57:36] [PASSED] Mono
[10:57:36] ====== [PASSED] drm_test_get_tv_mode_from_name_valid =======
[10:57:36] [PASSED] drm_test_get_tv_mode_from_name_truncated
[10:57:36] ============ [PASSED] drm_get_tv_mode_from_name ============
[10:57:36] = drm_test_connector_hdmi_compute_mode_clock (12 subtests) =
[10:57:36] [PASSED] drm_test_drm_hdmi_compute_mode_clock_rgb
[10:57:36] [PASSED] drm_test_drm_hdmi_compute_mode_clock_rgb_10bpc
[10:57:36] [PASSED] drm_test_drm_hdmi_compute_mode_clock_rgb_10bpc_vic_1
[10:57:36] [PASSED] drm_test_drm_hdmi_compute_mode_clock_rgb_12bpc
[10:57:36] [PASSED] drm_test_drm_hdmi_compute_mode_clock_rgb_12bpc_vic_1
[10:57:36] [PASSED] drm_test_drm_hdmi_compute_mode_clock_rgb_double
[10:57:36] = drm_test_connector_hdmi_compute_mode_clock_yuv420_valid  =
[10:57:36] [PASSED] VIC 96
[10:57:36] [PASSED] VIC 97
[10:57:36] [PASSED] VIC 101
[10:57:36] [PASSED] VIC 102
[10:57:36] [PASSED] VIC 106
[10:57:36] [PASSED] VIC 107
[10:57:36] === [PASSED] drm_test_connector_hdmi_compute_mode_clock_yuv420_valid ===
[10:57:36] [PASSED] drm_test_connector_hdmi_compute_mode_clock_yuv420_10_bpc
[10:57:36] [PASSED] drm_test_connector_hdmi_compute_mode_clock_yuv420_12_bpc
[10:57:36] [PASSED] drm_test_connector_hdmi_compute_mode_clock_yuv422_8_bpc
[10:57:36] [PASSED] drm_test_connector_hdmi_compute_mode_clock_yuv422_10_bpc
[10:57:36] [PASSED] drm_test_connector_hdmi_compute_mode_clock_yuv422_12_bpc
[10:57:36] === [PASSED] drm_test_connector_hdmi_compute_mode_clock ====
[10:57:36] == drm_hdmi_connector_get_broadcast_rgb_name (2 subtests) ==
[10:57:36] === drm_test_drm_hdmi_connector_get_broadcast_rgb_name  ====
[10:57:36] [PASSED] Automatic
[10:57:36] [PASSED] Full
[10:57:36] [PASSED] Limited 16:235
[10:57:36] === [PASSED] drm_test_drm_hdmi_connector_get_broadcast_rgb_name ===
[10:57:36] [PASSED] drm_test_drm_hdmi_connector_get_broadcast_rgb_name_invalid
[10:57:36] ==== [PASSED] drm_hdmi_connector_get_broadcast_rgb_name ====
[10:57:36] == drm_hdmi_connector_get_output_format_name (2 subtests) ==
[10:57:36] === drm_test_drm_hdmi_connector_get_output_format_name  ====
[10:57:36] [PASSED] RGB
[10:57:36] [PASSED] YUV 4:2:0
[10:57:36] [PASSED] YUV 4:2:2
[10:57:36] [PASSED] YUV 4:4:4
[10:57:36] === [PASSED] drm_test_drm_hdmi_connector_get_output_format_name ===
[10:57:36] [PASSED] drm_test_drm_hdmi_connector_get_output_format_name_invalid
[10:57:36] ==== [PASSED] drm_hdmi_connector_get_output_format_name ====
[10:57:36] ============= drm_damage_helper (21 subtests) ==============
[10:57:36] [PASSED] drm_test_damage_iter_no_damage
[10:57:36] [PASSED] drm_test_damage_iter_no_damage_fractional_src
[10:57:36] [PASSED] drm_test_damage_iter_no_damage_src_moved
[10:57:36] [PASSED] drm_test_damage_iter_no_damage_fractional_src_moved
[10:57:36] [PASSED] drm_test_damage_iter_no_damage_not_visible
[10:57:36] [PASSED] drm_test_damage_iter_no_damage_no_crtc
[10:57:36] [PASSED] drm_test_damage_iter_no_damage_no_fb
[10:57:36] [PASSED] drm_test_damage_iter_simple_damage
[10:57:36] [PASSED] drm_test_damage_iter_single_damage
[10:57:36] [PASSED] drm_test_damage_iter_single_damage_intersect_src
[10:57:36] [PASSED] drm_test_damage_iter_single_damage_outside_src
[10:57:36] [PASSED] drm_test_damage_iter_single_damage_fractional_src
[10:57:36] [PASSED] drm_test_damage_iter_single_damage_intersect_fractional_src
[10:57:36] [PASSED] drm_test_damage_iter_single_damage_outside_fractional_src
[10:57:36] [PASSED] drm_test_damage_iter_single_damage_src_moved
[10:57:36] [PASSED] drm_test_damage_iter_single_damage_fractional_src_moved
[10:57:36] [PASSED] drm_test_damage_iter_damage
[10:57:36] [PASSED] drm_test_damage_iter_damage_one_intersect
[10:57:36] [PASSED] drm_test_damage_iter_damage_one_outside
[10:57:36] [PASSED] drm_test_damage_iter_damage_src_moved
[10:57:36] [PASSED] drm_test_damage_iter_damage_not_visible
[10:57:36] ================ [PASSED] drm_damage_helper ================
[10:57:36] ============== drm_dp_mst_helper (3 subtests) ==============
[10:57:36] ============== drm_test_dp_mst_calc_pbn_mode  ==============
[10:57:36] [PASSED] Clock 154000 BPP 30 DSC disabled
[10:57:36] [PASSED] Clock 234000 BPP 30 DSC disabled
[10:57:36] [PASSED] Clock 297000 BPP 24 DSC disabled
[10:57:36] [PASSED] Clock 332880 BPP 24 DSC enabled
[10:57:36] [PASSED] Clock 324540 BPP 24 DSC enabled
[10:57:36] ========== [PASSED] drm_test_dp_mst_calc_pbn_mode ==========
[10:57:36] ============== drm_test_dp_mst_calc_pbn_div  ===============
[10:57:36] [PASSED] Link rate 2000000 lane count 4
[10:57:36] [PASSED] Link rate 2000000 lane count 2
[10:57:36] [PASSED] Link rate 2000000 lane count 1
[10:57:36] [PASSED] Link rate 1350000 lane count 4
[10:57:36] [PASSED] Link rate 1350000 lane count 2
[10:57:36] [PASSED] Link rate 1350000 lane count 1
[10:57:36] [PASSED] Link rate 1000000 lane count 4
[10:57:36] [PASSED] Link rate 1000000 lane count 2
[10:57:36] [PASSED] Link rate 1000000 lane count 1
[10:57:36] [PASSED] Link rate 810000 lane count 4
[10:57:36] [PASSED] Link rate 810000 lane count 2
[10:57:36] [PASSED] Link rate 810000 lane count 1
[10:57:36] [PASSED] Link rate 540000 lane count 4
[10:57:36] [PASSED] Link rate 540000 lane count 2
[10:57:36] [PASSED] Link rate 540000 lane count 1
[10:57:36] [PASSED] Link rate 270000 lane count 4
[10:57:36] [PASSED] Link rate 270000 lane count 2
[10:57:36] [PASSED] Link rate 270000 lane count 1
[10:57:36] [PASSED] Link rate 162000 lane count 4
[10:57:36] [PASSED] Link rate 162000 lane count 2
[10:57:36] [PASSED] Link rate 162000 lane count 1
[10:57:36] ========== [PASSED] drm_test_dp_mst_calc_pbn_div ===========
[10:57:36] ========= drm_test_dp_mst_sideband_msg_req_decode  =========
[10:57:36] [PASSED] DP_ENUM_PATH_RESOURCES with port number
[10:57:36] [PASSED] DP_POWER_UP_PHY with port number
[10:57:36] [PASSED] DP_POWER_DOWN_PHY with port number
[10:57:36] [PASSED] DP_ALLOCATE_PAYLOAD with SDP stream sinks
[10:57:36] [PASSED] DP_ALLOCATE_PAYLOAD with port number
[10:57:36] [PASSED] DP_ALLOCATE_PAYLOAD with VCPI
[10:57:36] [PASSED] DP_ALLOCATE_PAYLOAD with PBN
[10:57:36] [PASSED] DP_QUERY_PAYLOAD with port number
[10:57:36] [PASSED] DP_QUERY_PAYLOAD with VCPI
[10:57:36] [PASSED] DP_REMOTE_DPCD_READ with port number
[10:57:36] [PASSED] DP_REMOTE_DPCD_READ with DPCD address
[10:57:36] [PASSED] DP_REMOTE_DPCD_READ with max number of bytes
[10:57:36] [PASSED] DP_REMOTE_DPCD_WRITE with port number
[10:57:36] [PASSED] DP_REMOTE_DPCD_WRITE with DPCD address
[10:57:36] [PASSED] DP_REMOTE_DPCD_WRITE with data array
[10:57:36] [PASSED] DP_REMOTE_I2C_READ with port number
[10:57:36] [PASSED] DP_REMOTE_I2C_READ with I2C device ID
[10:57:36] [PASSED] DP_REMOTE_I2C_READ with transactions array
[10:57:36] [PASSED] DP_REMOTE_I2C_WRITE with port number
[10:57:36] [PASSED] DP_REMOTE_I2C_WRITE with I2C device ID
[10:57:36] [PASSED] DP_REMOTE_I2C_WRITE with data array
[10:57:36] [PASSED] DP_QUERY_STREAM_ENC_STATUS with stream ID
[10:57:36] [PASSED] DP_QUERY_STREAM_ENC_STATUS with client ID
[10:57:36] [PASSED] DP_QUERY_STREAM_ENC_STATUS with stream event
[10:57:36] [PASSED] DP_QUERY_STREAM_ENC_STATUS with valid stream event
[10:57:36] [PASSED] DP_QUERY_STREAM_ENC_STATUS with stream behavior
[10:57:36] [PASSED] DP_QUERY_STREAM_ENC_STATUS with a valid stream behavior
[10:57:36] ===== [PASSED] drm_test_dp_mst_sideband_msg_req_decode =====
[10:57:36] ================ [PASSED] drm_dp_mst_helper ================
[10:57:36] ================== drm_exec (7 subtests) ===================
[10:57:36] [PASSED] sanitycheck
[10:57:36] [PASSED] test_lock
[10:57:36] [PASSED] test_lock_unlock
[10:57:36] [PASSED] test_duplicates
[10:57:36] [PASSED] test_prepare
[10:57:36] [PASSED] test_prepare_array
[10:57:36] [PASSED] test_multiple_loops
[10:57:36] ==================== [PASSED] drm_exec =====================
[10:57:36] =========== drm_format_helper_test (17 subtests) ===========
[10:57:36] ============== drm_test_fb_xrgb8888_to_gray8  ==============
[10:57:36] [PASSED] single_pixel_source_buffer
[10:57:36] [PASSED] single_pixel_clip_rectangle
[10:57:36] [PASSED] well_known_colors
[10:57:36] [PASSED] destination_pitch
[10:57:36] ========== [PASSED] drm_test_fb_xrgb8888_to_gray8 ==========
[10:57:36] ============= drm_test_fb_xrgb8888_to_rgb332  ==============
[10:57:36] [PASSED] single_pixel_source_buffer
[10:57:36] [PASSED] single_pixel_clip_rectangle
[10:57:36] [PASSED] well_known_colors
[10:57:36] [PASSED] destination_pitch
[10:57:36] ========= [PASSED] drm_test_fb_xrgb8888_to_rgb332 ==========
[10:57:36] ============= drm_test_fb_xrgb8888_to_rgb565  ==============
[10:57:36] [PASSED] single_pixel_source_buffer
[10:57:36] [PASSED] single_pixel_clip_rectangle
[10:57:36] [PASSED] well_known_colors
[10:57:36] [PASSED] destination_pitch
[10:57:36] ========= [PASSED] drm_test_fb_xrgb8888_to_rgb565 ==========
[10:57:36] ============ drm_test_fb_xrgb8888_to_xrgb1555  =============
[10:57:36] [PASSED] single_pixel_source_buffer
[10:57:36] [PASSED] single_pixel_clip_rectangle
[10:57:36] [PASSED] well_known_colors
[10:57:36] [PASSED] destination_pitch
[10:57:36] ======== [PASSED] drm_test_fb_xrgb8888_to_xrgb1555 =========
[10:57:36] ============ drm_test_fb_xrgb8888_to_argb1555  =============
[10:57:36] [PASSED] single_pixel_source_buffer
[10:57:36] [PASSED] single_pixel_clip_rectangle
[10:57:36] [PASSED] well_known_colors
[10:57:36] [PASSED] destination_pitch
[10:57:36] ======== [PASSED] drm_test_fb_xrgb8888_to_argb1555 =========
[10:57:36] ============ drm_test_fb_xrgb8888_to_rgba5551  =============
[10:57:36] [PASSED] single_pixel_source_buffer
[10:57:36] [PASSED] single_pixel_clip_rectangle
[10:57:36] [PASSED] well_known_colors
[10:57:36] [PASSED] destination_pitch
[10:57:36] ======== [PASSED] drm_test_fb_xrgb8888_to_rgba5551 =========
[10:57:36] ============= drm_test_fb_xrgb8888_to_rgb888  ==============
[10:57:36] [PASSED] single_pixel_source_buffer
[10:57:36] [PASSED] single_pixel_clip_rectangle
[10:57:36] [PASSED] well_known_colors
[10:57:36] [PASSED] destination_pitch
[10:57:36] ========= [PASSED] drm_test_fb_xrgb8888_to_rgb888 ==========
[10:57:36] ============= drm_test_fb_xrgb8888_to_bgr888  ==============
[10:57:36] [PASSED] single_pixel_source_buffer
[10:57:36] [PASSED] single_pixel_clip_rectangle
[10:57:36] [PASSED] well_known_colors
[10:57:36] [PASSED] destination_pitch
[10:57:36] ========= [PASSED] drm_test_fb_xrgb8888_to_bgr888 ==========
[10:57:36] ============ drm_test_fb_xrgb8888_to_argb8888  =============
[10:57:36] [PASSED] single_pixel_source_buffer
[10:57:36] [PASSED] single_pixel_clip_rectangle
[10:57:36] [PASSED] well_known_colors
[10:57:36] [PASSED] destination_pitch
[10:57:36] ======== [PASSED] drm_test_fb_xrgb8888_to_argb8888 =========
[10:57:36] =========== drm_test_fb_xrgb8888_to_xrgb2101010  ===========
[10:57:36] [PASSED] single_pixel_source_buffer
[10:57:36] [PASSED] single_pixel_clip_rectangle
[10:57:36] [PASSED] well_known_colors
[10:57:36] [PASSED] destination_pitch
[10:57:36] ======= [PASSED] drm_test_fb_xrgb8888_to_xrgb2101010 =======
[10:57:36] =========== drm_test_fb_xrgb8888_to_argb2101010  ===========
[10:57:36] [PASSED] single_pixel_source_buffer
[10:57:36] [PASSED] single_pixel_clip_rectangle
[10:57:36] [PASSED] well_known_colors
[10:57:36] [PASSED] destination_pitch
[10:57:36] ======= [PASSED] drm_test_fb_xrgb8888_to_argb2101010 =======
[10:57:36] ============== drm_test_fb_xrgb8888_to_mono  ===============
[10:57:36] [PASSED] single_pixel_source_buffer
[10:57:36] [PASSED] single_pixel_clip_rectangle
[10:57:36] [PASSED] well_known_colors
[10:57:36] [PASSED] destination_pitch
[10:57:36] ========== [PASSED] drm_test_fb_xrgb8888_to_mono ===========
[10:57:36] ==================== drm_test_fb_swab  =====================
[10:57:36] [PASSED] single_pixel_source_buffer
[10:57:36] [PASSED] single_pixel_clip_rectangle
[10:57:36] [PASSED] well_known_colors
[10:57:36] [PASSED] destination_pitch
[10:57:36] ================ [PASSED] drm_test_fb_swab =================
[10:57:36] ============ drm_test_fb_xrgb8888_to_xbgr8888  =============
[10:57:36] [PASSED] single_pixel_source_buffer
[10:57:36] [PASSED] single_pixel_clip_rectangle
[10:57:36] [PASSED] well_known_colors
[10:57:36] [PASSED] destination_pitch
[10:57:36] ======== [PASSED] drm_test_fb_xrgb8888_to_xbgr8888 =========
[10:57:36] ============ drm_test_fb_xrgb8888_to_abgr8888  =============
[10:57:36] [PASSED] single_pixel_source_buffer
[10:57:36] [PASSED] single_pixel_clip_rectangle
[10:57:36] [PASSED] well_known_colors
[10:57:36] [PASSED] destination_pitch
[10:57:36] ======== [PASSED] drm_test_fb_xrgb8888_to_abgr8888 =========
[10:57:36] ================= drm_test_fb_clip_offset  =================
[10:57:36] [PASSED] pass through
[10:57:36] [PASSED] horizontal offset
[10:57:36] [PASSED] vertical offset
[10:57:36] [PASSED] horizontal and vertical offset
[10:57:36] [PASSED] horizontal offset (custom pitch)
[10:57:36] [PASSED] vertical offset (custom pitch)
[10:57:36] [PASSED] horizontal and vertical offset (custom pitch)
[10:57:36] ============= [PASSED] drm_test_fb_clip_offset =============
[10:57:36] =================== drm_test_fb_memcpy  ====================
[10:57:36] [PASSED] single_pixel_source_buffer: XR24 little-endian (0x34325258)
[10:57:36] [PASSED] single_pixel_source_buffer: XRA8 little-endian (0x38415258)
[10:57:36] [PASSED] single_pixel_source_buffer: YU24 little-endian (0x34325559)
[10:57:36] [PASSED] single_pixel_clip_rectangle: XB24 little-endian (0x34324258)
[10:57:36] [PASSED] single_pixel_clip_rectangle: XRA8 little-endian (0x38415258)
[10:57:36] [PASSED] single_pixel_clip_rectangle: YU24 little-endian (0x34325559)
[10:57:36] [PASSED] well_known_colors: XB24 little-endian (0x34324258)
[10:57:36] [PASSED] well_known_colors: XRA8 little-endian (0x38415258)
[10:57:36] [PASSED] well_known_colors: YU24 little-endian (0x34325559)
[10:57:36] [PASSED] destination_pitch: XB24 little-endian (0x34324258)
[10:57:36] [PASSED] destination_pitch: XRA8 little-endian (0x38415258)
[10:57:36] [PASSED] destination_pitch: YU24 little-endian (0x34325559)
[10:57:36] =============== [PASSED] drm_test_fb_memcpy ================
[10:57:36] ============= [PASSED] drm_format_helper_test ==============
[10:57:36] ================= drm_format (18 subtests) =================
[10:57:36] [PASSED] drm_test_format_block_width_invalid
[10:57:36] [PASSED] drm_test_format_block_width_one_plane
[10:57:36] [PASSED] drm_test_format_block_width_two_plane
[10:57:36] [PASSED] drm_test_format_block_width_three_plane
[10:57:36] [PASSED] drm_test_format_block_width_tiled
[10:57:36] [PASSED] drm_test_format_block_height_invalid
[10:57:36] [PASSED] drm_test_format_block_height_one_plane
[10:57:36] [PASSED] drm_test_format_block_height_two_plane
[10:57:36] [PASSED] drm_test_format_block_height_three_plane
[10:57:36] [PASSED] drm_test_format_block_height_tiled
[10:57:36] [PASSED] drm_test_format_min_pitch_invalid
[10:57:36] [PASSED] drm_test_format_min_pitch_one_plane_8bpp
[10:57:36] [PASSED] drm_test_format_min_pitch_one_plane_16bpp
[10:57:36] [PASSED] drm_test_format_min_pitch_one_plane_24bpp
[10:57:36] [PASSED] drm_test_format_min_pitch_one_plane_32bpp
[10:57:36] [PASSED] drm_test_format_min_pitch_two_plane
[10:57:36] [PASSED] drm_test_format_min_pitch_three_plane_8bpp
[10:57:36] [PASSED] drm_test_format_min_pitch_tiled
[10:57:36] =================== [PASSED] drm_format ====================
[10:57:36] ============== drm_framebuffer (10 subtests) ===============
[10:57:36] ========== drm_test_framebuffer_check_src_coords  ==========
[10:57:36] [PASSED] Success: source fits into fb
[10:57:36] [PASSED] Fail: overflowing fb with x-axis coordinate
[10:57:36] [PASSED] Fail: overflowing fb with y-axis coordinate
[10:57:36] [PASSED] Fail: overflowing fb with source width
[10:57:36] [PASSED] Fail: overflowing fb with source height
[10:57:36] ====== [PASSED] drm_test_framebuffer_check_src_coords ======
[10:57:36] [PASSED] drm_test_framebuffer_cleanup
[10:57:36] =============== drm_test_framebuffer_create  ===============
[10:57:36] [PASSED] ABGR8888 normal sizes
[10:57:36] [PASSED] ABGR8888 max sizes
[10:57:36] [PASSED] ABGR8888 pitch greater than min required
[10:57:36] [PASSED] ABGR8888 pitch less than min required
[10:57:36] [PASSED] ABGR8888 Invalid width
[10:57:36] [PASSED] ABGR8888 Invalid buffer handle
[10:57:36] [PASSED] No pixel format
[10:57:36] [PASSED] ABGR8888 Width 0
[10:57:36] [PASSED] ABGR8888 Height 0
[10:57:36] [PASSED] ABGR8888 Out of bound height * pitch combination
[10:57:36] [PASSED] ABGR8888 Large buffer offset
[10:57:36] [PASSED] ABGR8888 Buffer offset for inexistent plane
[10:57:36] [PASSED] ABGR8888 Invalid flag
[10:57:36] [PASSED] ABGR8888 Set DRM_MODE_FB_MODIFIERS without modifiers
[10:57:36] [PASSED] ABGR8888 Valid buffer modifier
[10:57:36] [PASSED] ABGR8888 Invalid buffer modifier(DRM_FORMAT_MOD_SAMSUNG_64_32_TILE)
[10:57:36] [PASSED] ABGR8888 Extra pitches without DRM_MODE_FB_MODIFIERS
[10:57:36] [PASSED] ABGR8888 Extra pitches with DRM_MODE_FB_MODIFIERS
[10:57:36] [PASSED] NV12 Normal sizes
[10:57:36] [PASSED] NV12 Max sizes
[10:57:36] [PASSED] NV12 Invalid pitch
[10:57:36] [PASSED] NV12 Invalid modifier/missing DRM_MODE_FB_MODIFIERS flag
[10:57:36] [PASSED] NV12 different  modifier per-plane
[10:57:36] [PASSED] NV12 with DRM_FORMAT_MOD_SAMSUNG_64_32_TILE
[10:57:36] [PASSED] NV12 Valid modifiers without DRM_MODE_FB_MODIFIERS
[10:57:36] [PASSED] NV12 Modifier for inexistent plane
[10:57:36] [PASSED] NV12 Handle for inexistent plane
[10:57:36] [PASSED] NV12 Handle for inexistent plane without DRM_MODE_FB_MODIFIERS
[10:57:36] [PASSED] YVU420 DRM_MODE_FB_MODIFIERS set without modifier
[10:57:36] [PASSED] YVU420 Normal sizes
[10:57:36] [PASSED] YVU420 Max sizes
[10:57:36] [PASSED] YVU420 Invalid pitch
[10:57:36] [PASSED] YVU420 Different pitches
[10:57:36] [PASSED] YVU420 Different buffer offsets/pitches
[10:57:36] [PASSED] YVU420 Modifier set just for plane 0, without DRM_MODE_FB_MODIFIERS
[10:57:36] [PASSED] YVU420 Modifier set just for planes 0, 1, without DRM_MODE_FB_MODIFIERS
[10:57:36] [PASSED] YVU420 Modifier set just for plane 0, 1, with DRM_MODE_FB_MODIFIERS
[10:57:36] [PASSED] YVU420 Valid modifier
[10:57:36] [PASSED] YVU420 Different modifiers per plane
[10:57:36] [PASSED] YVU420 Modifier for inexistent plane
[10:57:36] [PASSED] YUV420_10BIT Invalid modifier(DRM_FORMAT_MOD_LINEAR)
[10:57:36] [PASSED] X0L2 Normal sizes
[10:57:36] [PASSED] X0L2 Max sizes
[10:57:36] [PASSED] X0L2 Invalid pitch
[10:57:36] [PASSED] X0L2 Pitch greater than minimum required
[10:57:36] [PASSED] X0L2 Handle for inexistent plane
[10:57:36] [PASSED] X0L2 Offset for inexistent plane, without DRM_MODE_FB_MODIFIERS set
[10:57:36] [PASSED] X0L2 Modifier without DRM_MODE_FB_MODIFIERS set
[10:57:36] [PASSED] X0L2 Valid modifier
[10:57:36] [PASSED] X0L2 Modifier for inexistent plane
[10:57:36] =========== [PASSED] drm_test_framebuffer_create ===========
[10:57:36] [PASSED] drm_test_framebuffer_free
[10:57:36] [PASSED] drm_test_framebuffer_init
[10:57:36] [PASSED] drm_test_framebuffer_init_bad_format
[10:57:36] [PASSED] drm_test_framebuffer_init_dev_mismatch
[10:57:36] [PASSED] drm_test_framebuffer_lookup
[10:57:36] [PASSED] drm_test_framebuffer_lookup_inexistent
[10:57:36] [PASSED] drm_test_framebuffer_modifiers_not_supported
[10:57:36] ================= [PASSED] drm_framebuffer =================
[10:57:36] ================ drm_gem_shmem (8 subtests) ================
[10:57:36] [PASSED] drm_gem_shmem_test_obj_create
[10:57:36] [PASSED] drm_gem_shmem_test_obj_create_private
[10:57:36] [PASSED] drm_gem_shmem_test_pin_pages
[10:57:36] [PASSED] drm_gem_shmem_test_vmap
[10:57:36] [PASSED] drm_gem_shmem_test_get_sg_table
[10:57:36] [PASSED] drm_gem_shmem_test_get_pages_sgt
[10:57:36] [PASSED] drm_gem_shmem_test_madvise
[10:57:36] [PASSED] drm_gem_shmem_test_purge
[10:57:36] ================== [PASSED] drm_gem_shmem ==================
[10:57:36] === drm_atomic_helper_connector_hdmi_check (29 subtests) ===
[10:57:36] [PASSED] drm_test_check_broadcast_rgb_auto_cea_mode
[10:57:36] [PASSED] drm_test_check_broadcast_rgb_auto_cea_mode_vic_1
[10:57:36] [PASSED] drm_test_check_broadcast_rgb_full_cea_mode
[10:57:36] [PASSED] drm_test_check_broadcast_rgb_full_cea_mode_vic_1
[10:57:36] [PASSED] drm_test_check_broadcast_rgb_limited_cea_mode
[10:57:36] [PASSED] drm_test_check_broadcast_rgb_limited_cea_mode_vic_1
[10:57:36] ====== drm_test_check_broadcast_rgb_cea_mode_yuv420  =======
[10:57:36] [PASSED] Automatic
[10:57:36] [PASSED] Full
[10:57:36] [PASSED] Limited 16:235
[10:57:36] == [PASSED] drm_test_check_broadcast_rgb_cea_mode_yuv420 ===
[10:57:36] [PASSED] drm_test_check_broadcast_rgb_crtc_mode_changed
[10:57:36] [PASSED] drm_test_check_broadcast_rgb_crtc_mode_not_changed
[10:57:36] [PASSED] drm_test_check_disable_connector
[10:57:36] [PASSED] drm_test_check_hdmi_funcs_reject_rate
[10:57:36] [PASSED] drm_test_check_max_tmds_rate_bpc_fallback_rgb
[10:57:36] [PASSED] drm_test_check_max_tmds_rate_bpc_fallback_yuv420
[10:57:36] [PASSED] drm_test_check_max_tmds_rate_bpc_fallback_ignore_yuv422
[10:57:36] [PASSED] drm_test_check_max_tmds_rate_bpc_fallback_ignore_yuv420
[10:57:36] [PASSED] drm_test_check_driver_unsupported_fallback_yuv420
[10:57:36] [PASSED] drm_test_check_output_bpc_crtc_mode_changed
[10:57:36] [PASSED] drm_test_check_output_bpc_crtc_mode_not_changed
[10:57:36] [PASSED] drm_test_check_output_bpc_dvi
[10:57:36] [PASSED] drm_test_check_output_bpc_format_vic_1
[10:57:36] [PASSED] drm_test_check_output_bpc_format_display_8bpc_only
[10:57:36] [PASSED] drm_test_check_output_bpc_format_display_rgb_only
[10:57:36] [PASSED] drm_test_check_output_bpc_format_driver_8bpc_only
[10:57:36] [PASSED] drm_test_check_output_bpc_format_driver_rgb_only
[10:57:36] [PASSED] drm_test_check_tmds_char_rate_rgb_8bpc
[10:57:36] [PASSED] drm_test_check_tmds_char_rate_rgb_10bpc
[10:57:36] [PASSED] drm_test_check_tmds_char_rate_rgb_12bpc
[10:57:36] ============ drm_test_check_hdmi_color_format  =============
[10:57:36] [PASSED] AUTO -> RGB
[10:57:36] [PASSED] YCBCR422 -> YUV422
[10:57:36] [PASSED] YCBCR420 -> YUV420
[10:57:36] [PASSED] YCBCR444 -> YUV444
[10:57:36] [PASSED] RGB -> RGB
[10:57:36] ======== [PASSED] drm_test_check_hdmi_color_format =========
[10:57:36] ======== drm_test_check_hdmi_color_format_420_only  ========
[10:57:36] [PASSED] RGB should fail
[10:57:36] [PASSED] YUV444 should fail
[10:57:36] [PASSED] YUV422 should fail
[10:57:36] [PASSED] YUV420 should work
[10:57:36] ==== [PASSED] drm_test_check_hdmi_color_format_420_only ====
[10:57:36] ===== [PASSED] drm_atomic_helper_connector_hdmi_check ======
[10:57:36] === drm_atomic_helper_connector_hdmi_reset (6 subtests) ====
[10:57:36] [PASSED] drm_test_check_broadcast_rgb_value
[10:57:36] [PASSED] drm_test_check_bpc_8_value
[10:57:36] [PASSED] drm_test_check_bpc_10_value
[10:57:36] [PASSED] drm_test_check_bpc_12_value
[10:57:36] [PASSED] drm_test_check_format_value
[10:57:36] [PASSED] drm_test_check_tmds_char_value
[10:57:36] ===== [PASSED] drm_atomic_helper_connector_hdmi_reset ======
[10:57:36] = drm_atomic_helper_connector_hdmi_mode_valid (7 subtests) =
[10:57:36] [PASSED] drm_test_check_mode_valid
[10:57:36] [PASSED] drm_test_check_mode_valid_reject
[10:57:36] [PASSED] drm_test_check_mode_valid_reject_rate
[10:57:36] [PASSED] drm_test_check_mode_valid_reject_max_clock
[10:57:36] [PASSED] drm_test_check_mode_valid_yuv420_only_max_clock
[10:57:36] [PASSED] drm_test_check_mode_valid_reject_yuv420_only_connector
[10:57:36] [PASSED] drm_test_check_mode_valid_accept_yuv420_also_connector_rgb
[10:57:36] === [PASSED] drm_atomic_helper_connector_hdmi_mode_valid ===
[10:57:36] = drm_atomic_helper_connector_hdmi_infoframes (5 subtests) =
[10:57:36] [PASSED] drm_test_check_infoframes
[10:57:36] [PASSED] drm_test_check_reject_avi_infoframe
[10:57:36] [PASSED] drm_test_check_reject_hdr_infoframe_bpc_8
[10:57:36] [PASSED] drm_test_check_reject_hdr_infoframe_bpc_10
[10:57:36] [PASSED] drm_test_check_reject_audio_infoframe
[10:57:36] === [PASSED] drm_atomic_helper_connector_hdmi_infoframes ===
[10:57:36] ================= drm_managed (2 subtests) =================
[10:57:36] [PASSED] drm_test_managed_release_action
[10:57:36] [PASSED] drm_test_managed_run_action
[10:57:36] =================== [PASSED] drm_managed ===================
[10:57:36] =================== drm_mm (6 subtests) ====================
[10:57:36] [PASSED] drm_test_mm_init
[10:57:36] [PASSED] drm_test_mm_debug
[10:57:36] [PASSED] drm_test_mm_align32
[10:57:36] [PASSED] drm_test_mm_align64
[10:57:36] [PASSED] drm_test_mm_lowest
[10:57:36] [PASSED] drm_test_mm_highest
[10:57:36] ===================== [PASSED] drm_mm ======================
[10:57:36] ============= drm_modes_analog_tv (5 subtests) =============
[10:57:36] [PASSED] drm_test_modes_analog_tv_mono_576i
[10:57:36] [PASSED] drm_test_modes_analog_tv_ntsc_480i
[10:57:36] [PASSED] drm_test_modes_analog_tv_ntsc_480i_inlined
[10:57:36] [PASSED] drm_test_modes_analog_tv_pal_576i
[10:57:36] [PASSED] drm_test_modes_analog_tv_pal_576i_inlined
[10:57:36] =============== [PASSED] drm_modes_analog_tv ===============
[10:57:36] ============== drm_plane_helper (2 subtests) ===============
[10:57:36] =============== drm_test_check_plane_state  ================
[10:57:36] [PASSED] clipping_simple
[10:57:36] [PASSED] clipping_rotate_reflect
[10:57:36] [PASSED] positioning_simple
[10:57:36] [PASSED] upscaling
[10:57:36] [PASSED] downscaling
[10:57:36] [PASSED] rounding1
[10:57:36] [PASSED] rounding2
[10:57:36] [PASSED] rounding3
[10:57:36] [PASSED] rounding4
[10:57:36] =========== [PASSED] drm_test_check_plane_state ============
[10:57:36] =========== drm_test_check_invalid_plane_state  ============
[10:57:36] [PASSED] positioning_invalid
[10:57:36] [PASSED] upscaling_invalid
[10:57:36] [PASSED] downscaling_invalid
[10:57:36] ======= [PASSED] drm_test_check_invalid_plane_state ========
[10:57:36] ================ [PASSED] drm_plane_helper =================
[10:57:36] ====== drm_connector_helper_tv_get_modes (1 subtest) =======
[10:57:36] ====== drm_test_connector_helper_tv_get_modes_check  =======
[10:57:36] [PASSED] None
[10:57:36] [PASSED] PAL
[10:57:36] [PASSED] NTSC
[10:57:36] [PASSED] Both, NTSC Default
[10:57:36] [PASSED] Both, PAL Default
[10:57:36] [PASSED] Both, NTSC Default, with PAL on command-line
[10:57:36] [PASSED] Both, PAL Default, with NTSC on command-line
[10:57:36] == [PASSED] drm_test_connector_helper_tv_get_modes_check ===
[10:57:36] ======== [PASSED] drm_connector_helper_tv_get_modes ========
[10:57:36] ================== drm_rect (9 subtests) ===================
[10:57:36] [PASSED] drm_test_rect_clip_scaled_div_by_zero
[10:57:36] [PASSED] drm_test_rect_clip_scaled_not_clipped
[10:57:36] [PASSED] drm_test_rect_clip_scaled_clipped
[10:57:36] [PASSED] drm_test_rect_clip_scaled_signed_vs_unsigned
[10:57:36] ================= drm_test_rect_intersect  =================
[10:57:36] [PASSED] top-left x bottom-right: 2x2+1+1 x 2x2+0+0
[10:57:36] [PASSED] top-right x bottom-left: 2x2+0+0 x 2x2+1-1
[10:57:36] [PASSED] bottom-left x top-right: 2x2+1-1 x 2x2+0+0
[10:57:36] [PASSED] bottom-right x top-left: 2x2+0+0 x 2x2+1+1
[10:57:36] [PASSED] right x left: 2x1+0+0 x 3x1+1+0
[10:57:36] [PASSED] left x right: 3x1+1+0 x 2x1+0+0
[10:57:36] [PASSED] up x bottom: 1x2+0+0 x 1x3+0-1
[10:57:36] [PASSED] bottom x up: 1x3+0-1 x 1x2+0+0
[10:57:36] [PASSED] touching corner: 1x1+0+0 x 2x2+1+1
[10:57:36] [PASSED] touching side: 1x1+0+0 x 1x1+1+0
[10:57:36] [PASSED] equal rects: 2x2+0+0 x 2x2+0+0
[10:57:36] [PASSED] inside another: 2x2+0+0 x 1x1+1+1
[10:57:36] [PASSED] far away: 1x1+0+0 x 1x1+3+6
[10:57:36] [PASSED] points intersecting: 0x0+5+10 x 0x0+5+10
[10:57:36] [PASSED] points not intersecting: 0x0+0+0 x 0x0+5+10
[10:57:36] ============= [PASSED] drm_test_rect_intersect =============
[10:57:36] ================ drm_test_rect_calc_hscale  ================
[10:57:36] [PASSED] normal use
[10:57:36] [PASSED] out of max range
[10:57:36] [PASSED] out of min range
[10:57:36] [PASSED] zero dst
[10:57:36] [PASSED] negative src
[10:57:36] [PASSED] negative dst
[10:57:36] ============ [PASSED] drm_test_rect_calc_hscale ============
[10:57:36] ================ drm_test_rect_calc_vscale  ================
[10:57:36] [PASSED] normal use
[10:57:36] [PASSED] out of max range
[10:57:36] [PASSED] out of min range
[10:57:36] [PASSED] zero dst
[10:57:36] [PASSED] negative src
[10:57:36] [PASSED] negative dst
[10:57:36] ============ [PASSED] drm_test_rect_calc_vscale ============
[10:57:36] ================== drm_test_rect_rotate  ===================
[10:57:36] [PASSED] reflect-x
[10:57:36] [PASSED] reflect-y
[10:57:36] [PASSED] rotate-0
[10:57:36] [PASSED] rotate-90
[10:57:36] [PASSED] rotate-180
[10:57:36] [PASSED] rotate-270
[10:57:36] ============== [PASSED] drm_test_rect_rotate ===============
[10:57:36] ================ drm_test_rect_rotate_inv  =================
[10:57:36] [PASSED] reflect-x
[10:57:36] [PASSED] reflect-y
[10:57:36] [PASSED] rotate-0
[10:57:36] [PASSED] rotate-90
[10:57:36] [PASSED] rotate-180
[10:57:36] [PASSED] rotate-270
[10:57:36] ============ [PASSED] drm_test_rect_rotate_inv =============
[10:57:36] ==================== [PASSED] drm_rect =====================
[10:57:36] ============ drm_sysfb_modeset_test (1 subtest) ============
[10:57:36] ============ drm_test_sysfb_build_fourcc_list  =============
[10:57:36] [PASSED] no native formats
[10:57:36] [PASSED] XRGB8888 as native format
[10:57:36] [PASSED] remove duplicates
[10:57:36] [PASSED] convert alpha formats
[10:57:36] [PASSED] random formats
[10:57:36] ======== [PASSED] drm_test_sysfb_build_fourcc_list =========
[10:57:36] ============= [PASSED] drm_sysfb_modeset_test ==============
[10:57:36] ================== drm_fixp (2 subtests) ===================
[10:57:36] [PASSED] drm_test_int2fixp
[10:57:36] [PASSED] drm_test_sm2fixp
[10:57:36] ==================== [PASSED] drm_fixp =====================
[10:57:36] ============================================================
[10:57:36] Testing complete. Ran 639 tests: passed: 639
[10:57:36] Elapsed time: 26.526s total, 1.712s configuring, 24.597s building, 0.181s running

+ /kernel/tools/testing/kunit/kunit.py run --kunitconfig /kernel/drivers/gpu/drm/ttm/tests/.kunitconfig
[10:57:36] Configuring KUnit Kernel ...
Regenerating .config ...
Populating config with:
$ make ARCH=um O=.kunit olddefconfig
[10:57:38] Building KUnit Kernel ...
Populating config with:
$ make ARCH=um O=.kunit olddefconfig
Building with:
$ make all compile_commands.json scripts_gdb ARCH=um O=.kunit --jobs=48
[10:57:48] Starting KUnit Kernel (1/1)...
[10:57:48] ============================================================
Running tests with:
$ .kunit/linux kunit.enable=1 mem=1G console=tty kunit_shutdown=halt
[10:57:48] ================= ttm_device (5 subtests) ==================
[10:57:48] [PASSED] ttm_device_init_basic
[10:57:48] [PASSED] ttm_device_init_multiple
[10:57:48] [PASSED] ttm_device_fini_basic
[10:57:48] [PASSED] ttm_device_init_no_vma_man
[10:57:48] ================== ttm_device_init_pools  ==================
[10:57:48] [PASSED] No DMA allocations, no DMA32 required
[10:57:48] [PASSED] DMA allocations, DMA32 required
[10:57:48] [PASSED] No DMA allocations, DMA32 required
[10:57:48] [PASSED] DMA allocations, no DMA32 required
[10:57:48] ============== [PASSED] ttm_device_init_pools ==============
[10:57:48] =================== [PASSED] ttm_device ====================
[10:57:48] ================== ttm_pool (8 subtests) ===================
[10:57:48] ================== ttm_pool_alloc_basic  ===================
[10:57:48] [PASSED] One page
[10:57:48] [PASSED] More than one page
[10:57:48] [PASSED] Above the allocation limit
[10:57:48] [PASSED] One page, with coherent DMA mappings enabled
[10:57:48] [PASSED] Above the allocation limit, with coherent DMA mappings enabled
[10:57:48] ============== [PASSED] ttm_pool_alloc_basic ===============
[10:57:48] ============== ttm_pool_alloc_basic_dma_addr  ==============
[10:57:48] [PASSED] One page
[10:57:48] [PASSED] More than one page
[10:57:48] [PASSED] Above the allocation limit
[10:57:48] [PASSED] One page, with coherent DMA mappings enabled
[10:57:48] [PASSED] Above the allocation limit, with coherent DMA mappings enabled
[10:57:48] ========== [PASSED] ttm_pool_alloc_basic_dma_addr ==========
[10:57:48] [PASSED] ttm_pool_alloc_order_caching_match
[10:57:48] [PASSED] ttm_pool_alloc_caching_mismatch
[10:57:48] [PASSED] ttm_pool_alloc_order_mismatch
[10:57:48] [PASSED] ttm_pool_free_dma_alloc
[10:57:48] [PASSED] ttm_pool_free_no_dma_alloc
[10:57:48] [PASSED] ttm_pool_fini_basic
[10:57:48] ==================== [PASSED] ttm_pool =====================
[10:57:48] ================ ttm_resource (8 subtests) =================
[10:57:48] ================= ttm_resource_init_basic  =================
[10:57:48] [PASSED] Init resource in TTM_PL_SYSTEM
[10:57:48] [PASSED] Init resource in TTM_PL_VRAM
[10:57:48] [PASSED] Init resource in a private placement
[10:57:48] [PASSED] Init resource in TTM_PL_SYSTEM, set placement flags
[10:57:48] ============= [PASSED] ttm_resource_init_basic =============
[10:57:48] [PASSED] ttm_resource_init_pinned
[10:57:48] [PASSED] ttm_resource_fini_basic
[10:57:48] [PASSED] ttm_resource_manager_init_basic
[10:57:48] [PASSED] ttm_resource_manager_usage_basic
[10:57:48] [PASSED] ttm_resource_manager_set_used_basic
[10:57:48] [PASSED] ttm_sys_man_alloc_basic
[10:57:48] [PASSED] ttm_sys_man_free_basic
[10:57:48] ================== [PASSED] ttm_resource ===================
[10:57:48] =================== ttm_tt (15 subtests) ===================
[10:57:48] ==================== ttm_tt_init_basic  ====================
[10:57:48] [PASSED] Page-aligned size
[10:57:48] [PASSED] Extra pages requested
[10:57:48] ================ [PASSED] ttm_tt_init_basic ================
[10:57:48] [PASSED] ttm_tt_init_misaligned
[10:57:48] [PASSED] ttm_tt_fini_basic
[10:57:48] [PASSED] ttm_tt_fini_sg
[10:57:48] [PASSED] ttm_tt_fini_shmem
[10:57:48] [PASSED] ttm_tt_create_basic
[10:57:48] [PASSED] ttm_tt_create_invalid_bo_type
[10:57:48] [PASSED] ttm_tt_create_ttm_exists
[10:57:48] [PASSED] ttm_tt_create_failed
[10:57:48] [PASSED] ttm_tt_destroy_basic
[10:57:48] [PASSED] ttm_tt_populate_null_ttm
[10:57:48] [PASSED] ttm_tt_populate_populated_ttm
[10:57:48] [PASSED] ttm_tt_unpopulate_basic
[10:57:48] [PASSED] ttm_tt_unpopulate_empty_ttm
[10:57:48] [PASSED] ttm_tt_swapin_basic
[10:57:48] ===================== [PASSED] ttm_tt ======================
[10:57:48] =================== ttm_bo (14 subtests) ===================
[10:57:48] =========== ttm_bo_reserve_optimistic_no_ticket  ===========
[10:57:48] [PASSED] Cannot be interrupted and sleeps
[10:57:48] [PASSED] Cannot be interrupted, locks straight away
[10:57:48] [PASSED] Can be interrupted, sleeps
[10:57:48] ======= [PASSED] ttm_bo_reserve_optimistic_no_ticket =======
[10:57:48] [PASSED] ttm_bo_reserve_locked_no_sleep
[10:57:48] [PASSED] ttm_bo_reserve_no_wait_ticket
[10:57:48] [PASSED] ttm_bo_reserve_double_resv
[10:57:48] [PASSED] ttm_bo_reserve_interrupted
[10:57:48] [PASSED] ttm_bo_reserve_deadlock
[10:57:48] [PASSED] ttm_bo_unreserve_basic
[10:57:48] [PASSED] ttm_bo_unreserve_pinned
[10:57:48] [PASSED] ttm_bo_unreserve_bulk
[10:57:48] [PASSED] ttm_bo_fini_basic
[10:57:48] [PASSED] ttm_bo_fini_shared_resv
[10:57:48] [PASSED] ttm_bo_pin_basic
[10:57:48] [PASSED] ttm_bo_pin_unpin_resource
[10:57:48] [PASSED] ttm_bo_multiple_pin_one_unpin
[10:57:48] ===================== [PASSED] ttm_bo ======================
[10:57:48] ============== ttm_bo_validate (22 subtests) ===============
[10:57:48] ============== ttm_bo_init_reserved_sys_man  ===============
[10:57:48] [PASSED] Buffer object for userspace
[10:57:48] [PASSED] Kernel buffer object
[10:57:48] [PASSED] Shared buffer object
[10:57:48] ========== [PASSED] ttm_bo_init_reserved_sys_man ===========
[10:57:48] ============== ttm_bo_init_reserved_mock_man  ==============
[10:57:48] [PASSED] Buffer object for userspace
[10:57:48] [PASSED] Kernel buffer object
[10:57:48] [PASSED] Shared buffer object
[10:57:48] ========== [PASSED] ttm_bo_init_reserved_mock_man ==========
[10:57:48] [PASSED] ttm_bo_init_reserved_resv
[10:57:48] ================== ttm_bo_validate_basic  ==================
[10:57:48] [PASSED] Buffer object for userspace
[10:57:48] [PASSED] Kernel buffer object
[10:57:48] [PASSED] Shared buffer object
[10:57:48] ============== [PASSED] ttm_bo_validate_basic ==============
[10:57:48] [PASSED] ttm_bo_validate_invalid_placement
[10:57:48] ============= ttm_bo_validate_same_placement  ==============
[10:57:48] [PASSED] System manager
[10:57:48] [PASSED] VRAM manager
[10:57:48] ========= [PASSED] ttm_bo_validate_same_placement ==========
[10:57:48] [PASSED] ttm_bo_validate_failed_alloc
[10:57:48] [PASSED] ttm_bo_validate_pinned
[10:57:48] [PASSED] ttm_bo_validate_busy_placement
[10:57:48] ================ ttm_bo_validate_multihop  =================
[10:57:48] [PASSED] Buffer object for userspace
[10:57:48] [PASSED] Kernel buffer object
[10:57:48] [PASSED] Shared buffer object
[10:57:48] ============ [PASSED] ttm_bo_validate_multihop =============
[10:57:48] ========== ttm_bo_validate_no_placement_signaled  ==========
[10:57:48] [PASSED] Buffer object in system domain, no page vector
[10:57:48] [PASSED] Buffer object in system domain with an existing page vector
[10:57:48] ====== [PASSED] ttm_bo_validate_no_placement_signaled ======
[10:57:48] ======== ttm_bo_validate_no_placement_not_signaled  ========
[10:57:48] [PASSED] Buffer object for userspace
[10:57:48] [PASSED] Kernel buffer object
[10:57:48] [PASSED] Shared buffer object
[10:57:48] ==== [PASSED] ttm_bo_validate_no_placement_not_signaled ====
[10:57:48] [PASSED] ttm_bo_validate_move_fence_signaled
[10:57:48] ========= ttm_bo_validate_move_fence_not_signaled  =========
[10:57:48] [PASSED] Waits for GPU
[10:57:48] [PASSED] Tries to lock straight away
[10:57:48] ===== [PASSED] ttm_bo_validate_move_fence_not_signaled =====
[10:57:48] [PASSED] ttm_bo_validate_swapout
[10:57:48] [PASSED] ttm_bo_validate_happy_evict
[10:57:48] [PASSED] ttm_bo_validate_all_pinned_evict
[10:57:48] [PASSED] ttm_bo_validate_allowed_only_evict
[10:57:48] [PASSED] ttm_bo_validate_deleted_evict
[10:57:48] [PASSED] ttm_bo_validate_busy_domain_evict
[10:57:48] [PASSED] ttm_bo_validate_evict_gutting
[10:57:48] [PASSED] ttm_bo_validate_recrusive_evict
[10:57:48] ================= [PASSED] ttm_bo_validate =================
[10:57:48] ============================================================
[10:57:48] Testing complete. Ran 102 tests: passed: 102
[10:57:48] Elapsed time: 11.933s total, 1.815s configuring, 9.902s building, 0.182s running

+ cleanup
++ stat -c %u:%g /kernel
+ chown -R 1003:1003 /kernel

✓ Xe.CI.BAT: success for Enable CMRR in fixed-RR VRR path (rev2)

[Patchwork]

[-- Attachment #1: Type: text/plain, Size: 953 bytes --]

== Series Details ==

Series: Enable CMRR in fixed-RR VRR path (rev2)
URL   : https://patchwork.freedesktop.org/series/168613/
State : success

== Summary ==

CI Bug Log - changes from xe-5398-d3709d2bd13debee032d55c0dd71f145e11ec366_BAT -> xe-pw-168613v2_BAT
====================================================

Summary
-------

  **SUCCESS**

  No regressions found.

  

Participating hosts (13 -> 13)
------------------------------

  No changes in participating hosts


Changes
-------

  No changes found


Build changes
-------------

  * Linux: xe-5398-d3709d2bd13debee032d55c0dd71f145e11ec366 -> xe-pw-168613v2

  IGT_9006: 6380a8af26359dd222e22679442272ded836c463 @ https://gitlab.freedesktop.org/drm/igt-gpu-tools.git
  xe-5398-d3709d2bd13debee032d55c0dd71f145e11ec366: d3709d2bd13debee032d55c0dd71f145e11ec366
  xe-pw-168613v2: 168613v2

== Logs ==

For more details see: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-168613v2/index.html

[-- Attachment #2: Type: text/html, Size: 1501 bytes --]

✓ i915.CI.BAT: success for Enable CMRR in fixed-RR VRR path (rev3)

[Patchwork]

[-- Attachment #1: Type: text/plain, Size: 1638 bytes --]

== Series Details ==

Series: Enable CMRR in fixed-RR VRR path (rev3)
URL   : https://patchwork.freedesktop.org/series/166819/
State : success

== Summary ==

CI Bug Log - changes from CI_DRM_18817 -> Patchwork_166819v3
====================================================

Summary
-------

  **SUCCESS**

  No regressions found.

  External URL: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_166819v3/index.html

Participating hosts (42 -> 38)
------------------------------

  Missing    (4): bat-dg2-13 fi-glk-j4005 fi-snb-2520m bat-adls-6 

Known issues
------------

  Here are the changes found in Patchwork_166819v3 that come from known issues:

### IGT changes ###

#### Issues hit ####

  * igt@i915_selftest@live:
    - bat-apl-1:          [PASS][1] -> [DMESG-FAIL][2] ([i915#14808]) +1 other test dmesg-fail
   [1]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_18817/bat-apl-1/igt@i915_selftest@live.html
   [2]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_166819v3/bat-apl-1/igt@i915_selftest@live.html

  
  [i915#14808]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/14808


Build changes
-------------

  * Linux: CI_DRM_18817 -> Patchwork_166819v3

  CI-20190529: 20190529
  CI_DRM_18817: d3709d2bd13debee032d55c0dd71f145e11ec366 @ git://anongit.freedesktop.org/gfx-ci/linux
  IGT_9006: 6380a8af26359dd222e22679442272ded836c463 @ https://gitlab.freedesktop.org/drm/igt-gpu-tools.git
  Patchwork_166819v3: d3709d2bd13debee032d55c0dd71f145e11ec366 @ git://anongit.freedesktop.org/gfx-ci/linux

== Logs ==

For more details see: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_166819v3/index.html

[-- Attachment #2: Type: text/html, Size: 2223 bytes --]

✓ Xe.CI.FULL: success for Enable CMRR in fixed-RR VRR path (rev2)

[Patchwork]

[-- Attachment #1: Type: text/plain, Size: 48731 bytes --]

== Series Details ==

Series: Enable CMRR in fixed-RR VRR path (rev2)
URL   : https://patchwork.freedesktop.org/series/168613/
State : success

== Summary ==

CI Bug Log - changes from xe-5398-d3709d2bd13debee032d55c0dd71f145e11ec366_FULL -> xe-pw-168613v2_FULL
====================================================

Summary
-------

  **SUCCESS**

  No regressions found.

  

Participating hosts (2 -> 2)
------------------------------

  No changes in participating hosts

Known issues
------------

  Here are the changes found in xe-pw-168613v2_FULL that come from known issues:

### IGT changes ###

#### Issues hit ####

  * igt@intel_hwmon@hwmon-write:
    - shard-lnl:          NOTRUN -> [SKIP][1] ([Intel XE#1125] / [Intel XE#7312])
   [1]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-168613v2/shard-lnl-5/igt@intel_hwmon@hwmon-write.html

  * igt@kms_big_fb@4-tiled-64bpp-rotate-270:
    - shard-lnl:          NOTRUN -> [SKIP][2] ([Intel XE#1407]) +1 other test skip
   [2]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-168613v2/shard-lnl-5/igt@kms_big_fb@4-tiled-64bpp-rotate-270.html

  * igt@kms_big_fb@4-tiled-max-hw-stride-64bpp-rotate-180-hflip-async-flip:
    - shard-lnl:          NOTRUN -> [SKIP][3] ([Intel XE#3658] / [Intel XE#7360])
   [3]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-168613v2/shard-lnl-5/igt@kms_big_fb@4-tiled-max-hw-stride-64bpp-rotate-180-hflip-async-flip.html

  * igt@kms_big_fb@linear-8bpp-rotate-270:
    - shard-bmg:          NOTRUN -> [SKIP][4] ([Intel XE#2327]) +1 other test skip
   [4]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-168613v2/shard-bmg-2/igt@kms_big_fb@linear-8bpp-rotate-270.html

  * igt@kms_big_fb@linear-max-hw-stride-32bpp-rotate-180-hflip:
    - shard-lnl:          NOTRUN -> [SKIP][5] ([Intel XE#7059] / [Intel XE#7085])
   [5]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-168613v2/shard-lnl-5/igt@kms_big_fb@linear-max-hw-stride-32bpp-rotate-180-hflip.html

  * igt@kms_big_fb@y-tiled-max-hw-stride-64bpp-rotate-0-async-flip:
    - shard-bmg:          NOTRUN -> [SKIP][6] ([Intel XE#1124]) +3 other tests skip
   [6]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-168613v2/shard-bmg-5/igt@kms_big_fb@y-tiled-max-hw-stride-64bpp-rotate-0-async-flip.html

  * igt@kms_big_fb@yf-tiled-max-hw-stride-64bpp-rotate-180-hflip-async-flip:
    - shard-lnl:          NOTRUN -> [SKIP][7] ([Intel XE#1124]) +4 other tests skip
   [7]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-168613v2/shard-lnl-2/igt@kms_big_fb@yf-tiled-max-hw-stride-64bpp-rotate-180-hflip-async-flip.html

  * igt@kms_bw@connected-linear-tiling-2-displays-target-2560x1440p:
    - shard-lnl:          NOTRUN -> [SKIP][8] ([Intel XE#7679])
   [8]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-168613v2/shard-lnl-5/igt@kms_bw@connected-linear-tiling-2-displays-target-2560x1440p.html

  * igt@kms_bw@connected-linear-tiling-3-displays-target-2160x1440p:
    - shard-bmg:          NOTRUN -> [SKIP][9] ([Intel XE#7679])
   [9]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-168613v2/shard-bmg-5/igt@kms_bw@connected-linear-tiling-3-displays-target-2160x1440p.html

  * igt@kms_bw@linear-tiling-1-displays-target-2560x1440p:
    - shard-bmg:          NOTRUN -> [SKIP][10] ([Intel XE#367])
   [10]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-168613v2/shard-bmg-2/igt@kms_bw@linear-tiling-1-displays-target-2560x1440p.html

  * igt@kms_ccs@crc-primary-suspend-4-tiled-bmg-ccs:
    - shard-bmg:          [PASS][11] -> [INCOMPLETE][12] ([Intel XE#7084] / [Intel XE#8150]) +1 other test incomplete
   [11]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-5398-d3709d2bd13debee032d55c0dd71f145e11ec366/shard-bmg-9/igt@kms_ccs@crc-primary-suspend-4-tiled-bmg-ccs.html
   [12]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-168613v2/shard-bmg-8/igt@kms_ccs@crc-primary-suspend-4-tiled-bmg-ccs.html

  * igt@kms_ccs@crc-primary-suspend-yf-tiled-ccs:
    - shard-bmg:          NOTRUN -> [SKIP][13] ([Intel XE#3432])
   [13]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-168613v2/shard-bmg-5/igt@kms_ccs@crc-primary-suspend-yf-tiled-ccs.html

  * igt@kms_ccs@crc-sprite-planes-basic-4-tiled-dg2-rc-ccs-cc:
    - shard-bmg:          NOTRUN -> [SKIP][14] ([Intel XE#2887]) +8 other tests skip
   [14]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-168613v2/shard-bmg-2/igt@kms_ccs@crc-sprite-planes-basic-4-tiled-dg2-rc-ccs-cc.html

  * igt@kms_ccs@crc-sprite-planes-basic-y-tiled-gen12-mc-ccs:
    - shard-lnl:          NOTRUN -> [SKIP][15] ([Intel XE#2887]) +3 other tests skip
   [15]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-168613v2/shard-lnl-5/igt@kms_ccs@crc-sprite-planes-basic-y-tiled-gen12-mc-ccs.html

  * igt@kms_chamelium_audio@dp-audio:
    - shard-lnl:          NOTRUN -> [SKIP][16] ([Intel XE#373]) +2 other tests skip
   [16]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-168613v2/shard-lnl-2/igt@kms_chamelium_audio@dp-audio.html

  * igt@kms_chamelium_color@ctm-red-to-blue:
    - shard-bmg:          NOTRUN -> [SKIP][17] ([Intel XE#2325] / [Intel XE#7358])
   [17]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-168613v2/shard-bmg-5/igt@kms_chamelium_color@ctm-red-to-blue.html

  * igt@kms_chamelium_color_pipeline@plane-ctm3x4:
    - shard-lnl:          NOTRUN -> [SKIP][18] ([Intel XE#7358])
   [18]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-168613v2/shard-lnl-5/igt@kms_chamelium_color_pipeline@plane-ctm3x4.html

  * igt@kms_chamelium_frames@hdmi-crc-multiple:
    - shard-bmg:          NOTRUN -> [SKIP][19] ([Intel XE#2252]) +2 other tests skip
   [19]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-168613v2/shard-bmg-5/igt@kms_chamelium_frames@hdmi-crc-multiple.html

  * igt@kms_content_protection@dp-mst-lic-type-1:
    - shard-bmg:          NOTRUN -> [SKIP][20] ([Intel XE#2390] / [Intel XE#6974])
   [20]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-168613v2/shard-bmg-8/igt@kms_content_protection@dp-mst-lic-type-1.html

  * igt@kms_content_protection@lic-type-0:
    - shard-lnl:          NOTRUN -> [SKIP][21] ([Intel XE#7642])
   [21]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-168613v2/shard-lnl-5/igt@kms_content_protection@lic-type-0.html

  * igt@kms_cursor_crc@cursor-offscreen-256x85:
    - shard-bmg:          NOTRUN -> [SKIP][22] ([Intel XE#2320]) +1 other test skip
   [22]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-168613v2/shard-bmg-5/igt@kms_cursor_crc@cursor-offscreen-256x85.html

  * igt@kms_cursor_crc@cursor-random-512x170:
    - shard-bmg:          NOTRUN -> [SKIP][23] ([Intel XE#2321] / [Intel XE#7355]) +1 other test skip
   [23]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-168613v2/shard-bmg-5/igt@kms_cursor_crc@cursor-random-512x170.html

  * igt@kms_cursor_crc@cursor-sliding-128x42:
    - shard-lnl:          NOTRUN -> [SKIP][24] ([Intel XE#1424]) +1 other test skip
   [24]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-168613v2/shard-lnl-5/igt@kms_cursor_crc@cursor-sliding-128x42.html

  * igt@kms_cursor_legacy@2x-long-flip-vs-cursor-legacy:
    - shard-lnl:          NOTRUN -> [SKIP][25] ([Intel XE#309] / [Intel XE#7343]) +1 other test skip
   [25]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-168613v2/shard-lnl-2/igt@kms_cursor_legacy@2x-long-flip-vs-cursor-legacy.html

  * igt@kms_dsc@dsc-with-formats-ultrajoiner:
    - shard-lnl:          NOTRUN -> [SKIP][26] ([Intel XE#8265]) +1 other test skip
   [26]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-168613v2/shard-lnl-5/igt@kms_dsc@dsc-with-formats-ultrajoiner.html

  * igt@kms_dsc@dsc-with-output-formats-bigjoiner:
    - shard-bmg:          NOTRUN -> [SKIP][27] ([Intel XE#8265]) +1 other test skip
   [27]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-168613v2/shard-bmg-5/igt@kms_dsc@dsc-with-output-formats-bigjoiner.html

  * igt@kms_fbc_dirty_rect@fbc-dirty-rectangle-different-formats:
    - shard-lnl:          NOTRUN -> [SKIP][28] ([Intel XE#4422] / [Intel XE#7442])
   [28]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-168613v2/shard-lnl-2/igt@kms_fbc_dirty_rect@fbc-dirty-rectangle-different-formats.html

  * igt@kms_flip@2x-plain-flip-ts-check:
    - shard-lnl:          NOTRUN -> [SKIP][29] ([Intel XE#1421]) +2 other tests skip
   [29]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-168613v2/shard-lnl-5/igt@kms_flip@2x-plain-flip-ts-check.html

  * igt@kms_flip@flip-vs-expired-vblank-interruptible@c-edp1:
    - shard-lnl:          [PASS][30] -> [FAIL][31] ([Intel XE#301] / [Intel XE#3149])
   [30]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-5398-d3709d2bd13debee032d55c0dd71f145e11ec366/shard-lnl-7/igt@kms_flip@flip-vs-expired-vblank-interruptible@c-edp1.html
   [31]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-168613v2/shard-lnl-3/igt@kms_flip@flip-vs-expired-vblank-interruptible@c-edp1.html

  * igt@kms_flip@flip-vs-expired-vblank-interruptible@d-hdmi-a3:
    - shard-bmg:          [PASS][32] -> [FAIL][33] ([Intel XE#3149] / [Intel XE#3321]) +1 other test fail
   [32]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-5398-d3709d2bd13debee032d55c0dd71f145e11ec366/shard-bmg-9/igt@kms_flip@flip-vs-expired-vblank-interruptible@d-hdmi-a3.html
   [33]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-168613v2/shard-bmg-2/igt@kms_flip@flip-vs-expired-vblank-interruptible@d-hdmi-a3.html

  * igt@kms_flip_scaled_crc@flip-64bpp-ytile-to-32bpp-ytile-downscaling:
    - shard-lnl:          NOTRUN -> [SKIP][34] ([Intel XE#7178] / [Intel XE#7351]) +1 other test skip
   [34]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-168613v2/shard-lnl-5/igt@kms_flip_scaled_crc@flip-64bpp-ytile-to-32bpp-ytile-downscaling.html

  * igt@kms_frontbuffer_tracking@drrs-1p-primscrn-spr-indfb-fullscreen:
    - shard-lnl:          NOTRUN -> [SKIP][35] ([Intel XE#6312] / [Intel XE#651]) +3 other tests skip
   [35]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-168613v2/shard-lnl-5/igt@kms_frontbuffer_tracking@drrs-1p-primscrn-spr-indfb-fullscreen.html

  * igt@kms_frontbuffer_tracking@drrs-2p-pri-indfb-multidraw:
    - shard-bmg:          NOTRUN -> [SKIP][36] ([Intel XE#2311]) +24 other tests skip
   [36]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-168613v2/shard-bmg-5/igt@kms_frontbuffer_tracking@drrs-2p-pri-indfb-multidraw.html

  * igt@kms_frontbuffer_tracking@drrs-argb161616f-draw-mmap-wc:
    - shard-lnl:          NOTRUN -> [SKIP][37] ([Intel XE#7061] / [Intel XE#7356]) +2 other tests skip
   [37]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-168613v2/shard-lnl-2/igt@kms_frontbuffer_tracking@drrs-argb161616f-draw-mmap-wc.html

  * igt@kms_frontbuffer_tracking@fbc-2p-scndscrn-pri-shrfb-draw-blt:
    - shard-lnl:          NOTRUN -> [SKIP][38] ([Intel XE#656] / [Intel XE#7905]) +16 other tests skip
   [38]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-168613v2/shard-lnl-5/igt@kms_frontbuffer_tracking@fbc-2p-scndscrn-pri-shrfb-draw-blt.html

  * igt@kms_frontbuffer_tracking@fbc-2p-scndscrn-spr-indfb-draw-render:
    - shard-bmg:          NOTRUN -> [SKIP][39] ([Intel XE#4141]) +7 other tests skip
   [39]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-168613v2/shard-bmg-2/igt@kms_frontbuffer_tracking@fbc-2p-scndscrn-spr-indfb-draw-render.html

  * igt@kms_frontbuffer_tracking@fbcdrrs-tiling-y:
    - shard-lnl:          NOTRUN -> [SKIP][40] ([Intel XE#1469] / [Intel XE#7399]) +1 other test skip
   [40]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-168613v2/shard-lnl-2/igt@kms_frontbuffer_tracking@fbcdrrs-tiling-y.html

  * igt@kms_frontbuffer_tracking@fbcdrrshdr-1p-primscrn-cur-indfb-move:
    - shard-lnl:          NOTRUN -> [SKIP][41] ([Intel XE#6312]) +5 other tests skip
   [41]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-168613v2/shard-lnl-5/igt@kms_frontbuffer_tracking@fbcdrrshdr-1p-primscrn-cur-indfb-move.html

  * igt@kms_frontbuffer_tracking@fbcpsr-abgr161616f-draw-render:
    - shard-bmg:          NOTRUN -> [SKIP][42] ([Intel XE#7061] / [Intel XE#7356]) +1 other test skip
   [42]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-168613v2/shard-bmg-2/igt@kms_frontbuffer_tracking@fbcpsr-abgr161616f-draw-render.html

  * igt@kms_frontbuffer_tracking@fbcpsrhdr-indfb-scaledprimary:
    - shard-lnl:          NOTRUN -> [SKIP][43] ([Intel XE#7865]) +10 other tests skip
   [43]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-168613v2/shard-lnl-2/igt@kms_frontbuffer_tracking@fbcpsrhdr-indfb-scaledprimary.html

  * igt@kms_frontbuffer_tracking@hdr-2p-primscrn-shrfb-plflip-blt:
    - shard-lnl:          NOTRUN -> [SKIP][44] ([Intel XE#7905]) +16 other tests skip
   [44]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-168613v2/shard-lnl-5/igt@kms_frontbuffer_tracking@hdr-2p-primscrn-shrfb-plflip-blt.html

  * igt@kms_frontbuffer_tracking@hdr-abgr161616f-draw-blt:
    - shard-lnl:          NOTRUN -> [SKIP][45] ([Intel XE#7061])
   [45]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-168613v2/shard-lnl-5/igt@kms_frontbuffer_tracking@hdr-abgr161616f-draw-blt.html

  * igt@kms_frontbuffer_tracking@psr-1p-primscrn-cur-indfb-draw-blt:
    - shard-bmg:          NOTRUN -> [SKIP][46] ([Intel XE#2313]) +24 other tests skip
   [46]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-168613v2/shard-bmg-2/igt@kms_frontbuffer_tracking@psr-1p-primscrn-cur-indfb-draw-blt.html

  * igt@kms_frontbuffer_tracking@psrhdr-argb161616f-draw-render:
    - shard-bmg:          NOTRUN -> [SKIP][47] ([Intel XE#7061]) +4 other tests skip
   [47]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-168613v2/shard-bmg-5/igt@kms_frontbuffer_tracking@psrhdr-argb161616f-draw-render.html

  * igt@kms_joiner@invalid-modeset-ultra-joiner:
    - shard-lnl:          NOTRUN -> [SKIP][48] ([Intel XE#6900] / [Intel XE#7362])
   [48]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-168613v2/shard-lnl-5/igt@kms_joiner@invalid-modeset-ultra-joiner.html

  * igt@kms_pipe_stress@stress-xrgb8888-yftiled:
    - shard-lnl:          NOTRUN -> [SKIP][49] ([Intel XE#6912] / [Intel XE#7375])
   [49]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-168613v2/shard-lnl-2/igt@kms_pipe_stress@stress-xrgb8888-yftiled.html

  * igt@kms_plane@pixel-format-4-tiled-mtl-mc-ccs-modifier:
    - shard-bmg:          NOTRUN -> [SKIP][50] ([Intel XE#7283]) +2 other tests skip
   [50]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-168613v2/shard-bmg-2/igt@kms_plane@pixel-format-4-tiled-mtl-mc-ccs-modifier.html

  * igt@kms_plane@pixel-format-x-tiled-modifier@pipe-b-plane-5:
    - shard-lnl:          NOTRUN -> [SKIP][51] ([Intel XE#8303]) +3 other tests skip
   [51]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-168613v2/shard-lnl-2/igt@kms_plane@pixel-format-x-tiled-modifier@pipe-b-plane-5.html

  * igt@kms_plane@pixel-format-yf-tiled-modifier-source-clamping:
    - shard-lnl:          NOTRUN -> [SKIP][52] ([Intel XE#7283]) +1 other test skip
   [52]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-168613v2/shard-lnl-2/igt@kms_plane@pixel-format-yf-tiled-modifier-source-clamping.html

  * igt@kms_plane_lowres@tiling-y:
    - shard-lnl:          NOTRUN -> [SKIP][53] ([Intel XE#599])
   [53]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-168613v2/shard-lnl-5/igt@kms_plane_lowres@tiling-y.html

  * igt@kms_plane_multiple@2x-tiling-y:
    - shard-bmg:          NOTRUN -> [SKIP][54] ([Intel XE#5021] / [Intel XE#7377])
   [54]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-168613v2/shard-bmg-2/igt@kms_plane_multiple@2x-tiling-y.html

  * igt@kms_plane_scaling@planes-downscale-factor-0-5-upscale-factor-0-25:
    - shard-lnl:          NOTRUN -> [SKIP][55] ([Intel XE#2763] / [Intel XE#6886]) +3 other tests skip
   [55]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-168613v2/shard-lnl-2/igt@kms_plane_scaling@planes-downscale-factor-0-5-upscale-factor-0-25.html

  * igt@kms_pm_backlight@bad-brightness:
    - shard-bmg:          NOTRUN -> [SKIP][56] ([Intel XE#7376] / [Intel XE#7760] / [Intel XE#870])
   [56]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-168613v2/shard-bmg-5/igt@kms_pm_backlight@bad-brightness.html

  * igt@kms_pm_rpm@dpms-mode-unset-lpsp:
    - shard-bmg:          NOTRUN -> [SKIP][57] ([Intel XE#1439] / [Intel XE#7402] / [Intel XE#836])
   [57]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-168613v2/shard-bmg-2/igt@kms_pm_rpm@dpms-mode-unset-lpsp.html

  * igt@kms_pm_rpm@modeset-non-lpsp:
    - shard-lnl:          NOTRUN -> [SKIP][58] ([Intel XE#1439] / [Intel XE#3141] / [Intel XE#7383])
   [58]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-168613v2/shard-lnl-5/igt@kms_pm_rpm@modeset-non-lpsp.html

  * igt@kms_psr2_sf@fbc-pr-plane-move-sf-dmg-area:
    - shard-lnl:          NOTRUN -> [SKIP][59] ([Intel XE#2893] / [Intel XE#7304]) +2 other tests skip
   [59]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-168613v2/shard-lnl-2/igt@kms_psr2_sf@fbc-pr-plane-move-sf-dmg-area.html

  * igt@kms_psr2_sf@psr2-overlay-plane-move-continuous-sf:
    - shard-bmg:          NOTRUN -> [SKIP][60] ([Intel XE#1489]) +3 other tests skip
   [60]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-168613v2/shard-bmg-5/igt@kms_psr2_sf@psr2-overlay-plane-move-continuous-sf.html

  * igt@kms_psr2_su@page_flip-xrgb8888:
    - shard-lnl:          NOTRUN -> [SKIP][61] ([Intel XE#1128] / [Intel XE#7413])
   [61]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-168613v2/shard-lnl-5/igt@kms_psr2_su@page_flip-xrgb8888.html

  * igt@kms_psr@fbc-psr2-sprite-plane-onoff:
    - shard-lnl:          NOTRUN -> [SKIP][62] ([Intel XE#1406] / [Intel XE#7345])
   [62]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-168613v2/shard-lnl-2/igt@kms_psr@fbc-psr2-sprite-plane-onoff.html

  * igt@kms_psr@fbc-psr2-sprite-plane-onoff@edp-1:
    - shard-lnl:          NOTRUN -> [SKIP][63] ([Intel XE#1406] / [Intel XE#4609])
   [63]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-168613v2/shard-lnl-2/igt@kms_psr@fbc-psr2-sprite-plane-onoff@edp-1.html

  * igt@kms_psr@psr2-suspend:
    - shard-bmg:          NOTRUN -> [SKIP][64] ([Intel XE#2234] / [Intel XE#2850]) +4 other tests skip
   [64]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-168613v2/shard-bmg-5/igt@kms_psr@psr2-suspend.html

  * igt@kms_rotation_crc@primary-4-tiled-reflect-x-180:
    - shard-bmg:          [PASS][65] -> [ABORT][66] ([Intel XE#7814] / [Intel XE#7893] / [Intel XE#8300])
   [65]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-5398-d3709d2bd13debee032d55c0dd71f145e11ec366/shard-bmg-5/igt@kms_rotation_crc@primary-4-tiled-reflect-x-180.html
   [66]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-168613v2/shard-bmg-9/igt@kms_rotation_crc@primary-4-tiled-reflect-x-180.html

  * igt@kms_rotation_crc@primary-y-tiled-reflect-x-270:
    - shard-lnl:          NOTRUN -> [SKIP][67] ([Intel XE#3414] / [Intel XE#3904] / [Intel XE#7342])
   [67]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-168613v2/shard-lnl-5/igt@kms_rotation_crc@primary-y-tiled-reflect-x-270.html

  * igt@kms_setmode@invalid-clone-exclusive-crtc:
    - shard-lnl:          NOTRUN -> [SKIP][68] ([Intel XE#1435])
   [68]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-168613v2/shard-lnl-5/igt@kms_setmode@invalid-clone-exclusive-crtc.html

  * igt@kms_sharpness_filter@invalid-filter-with-plane:
    - shard-bmg:          NOTRUN -> [SKIP][69] ([Intel XE#6503])
   [69]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-168613v2/shard-bmg-2/igt@kms_sharpness_filter@invalid-filter-with-plane.html

  * igt@kms_tiled_display@basic-test-pattern-with-chamelium:
    - shard-bmg:          NOTRUN -> [SKIP][70] ([Intel XE#2509] / [Intel XE#7437])
   [70]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-168613v2/shard-bmg-5/igt@kms_tiled_display@basic-test-pattern-with-chamelium.html

  * igt@kms_vrr@flip-dpms:
    - shard-bmg:          NOTRUN -> [SKIP][71] ([Intel XE#1499])
   [71]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-168613v2/shard-bmg-2/igt@kms_vrr@flip-dpms.html

  * igt@sriov_basic@enable-vfs-bind-unbind-each-numvfs-all:
    - shard-lnl:          NOTRUN -> [SKIP][72] ([Intel XE#1091] / [Intel XE#2849])
   [72]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-168613v2/shard-lnl-2/igt@sriov_basic@enable-vfs-bind-unbind-each-numvfs-all.html

  * igt@xe_compute@eu-busy-10s:
    - shard-lnl:          NOTRUN -> [SKIP][73] ([Intel XE#6592] / [Intel XE#6645] / [Intel XE#7391])
   [73]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-168613v2/shard-lnl-2/igt@xe_compute@eu-busy-10s.html

  * igt@xe_create@multigpu-create-massive-size:
    - shard-bmg:          NOTRUN -> [SKIP][74] ([Intel XE#2504] / [Intel XE#7319] / [Intel XE#7350])
   [74]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-168613v2/shard-bmg-5/igt@xe_create@multigpu-create-massive-size.html

  * igt@xe_evict@evict-threads-small-multi-queue:
    - shard-bmg:          NOTRUN -> [SKIP][75] ([Intel XE#8370])
   [75]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-168613v2/shard-bmg-2/igt@xe_evict@evict-threads-small-multi-queue.html

  * igt@xe_evict_ccs@evict-overcommit-parallel-instantfree-reopen:
    - shard-lnl:          NOTRUN -> [SKIP][76] ([Intel XE#6540] / [Intel XE#688]) +4 other tests skip
   [76]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-168613v2/shard-lnl-2/igt@xe_evict_ccs@evict-overcommit-parallel-instantfree-reopen.html

  * igt@xe_exec_balancer@twice-cm-parallel-userptr-rebind:
    - shard-lnl:          NOTRUN -> [SKIP][77] ([Intel XE#7482]) +7 other tests skip
   [77]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-168613v2/shard-lnl-5/igt@xe_exec_balancer@twice-cm-parallel-userptr-rebind.html

  * igt@xe_exec_basic@multigpu-no-exec-bindexecqueue:
    - shard-bmg:          NOTRUN -> [SKIP][78] ([Intel XE#2322] / [Intel XE#7372]) +3 other tests skip
   [78]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-168613v2/shard-bmg-5/igt@xe_exec_basic@multigpu-no-exec-bindexecqueue.html

  * igt@xe_exec_basic@multigpu-once-userptr-invalidate:
    - shard-lnl:          NOTRUN -> [SKIP][79] ([Intel XE#1392]) +2 other tests skip
   [79]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-168613v2/shard-lnl-5/igt@xe_exec_basic@multigpu-once-userptr-invalidate.html

  * igt@xe_exec_fault_mode@once-multi-queue-userptr-invalidate-imm:
    - shard-bmg:          NOTRUN -> [SKIP][80] ([Intel XE#8374]) +4 other tests skip
   [80]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-168613v2/shard-bmg-5/igt@xe_exec_fault_mode@once-multi-queue-userptr-invalidate-imm.html

  * igt@xe_exec_fault_mode@twice-multi-queue-userptr-invalidate-race:
    - shard-lnl:          NOTRUN -> [SKIP][81] ([Intel XE#8374]) +3 other tests skip
   [81]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-168613v2/shard-lnl-5/igt@xe_exec_fault_mode@twice-multi-queue-userptr-invalidate-race.html

  * igt@xe_exec_multi_queue@many-queues-preempt-mode-basic:
    - shard-lnl:          NOTRUN -> [SKIP][82] ([Intel XE#8364]) +8 other tests skip
   [82]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-168613v2/shard-lnl-5/igt@xe_exec_multi_queue@many-queues-preempt-mode-basic.html

  * igt@xe_exec_multi_queue@two-queues-basic-smem:
    - shard-bmg:          NOTRUN -> [SKIP][83] ([Intel XE#8364]) +12 other tests skip
   [83]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-168613v2/shard-bmg-5/igt@xe_exec_multi_queue@two-queues-basic-smem.html

  * igt@xe_exec_threads@threads-multi-queue-cm-fd-basic:
    - shard-lnl:          NOTRUN -> [SKIP][84] ([Intel XE#8378]) +4 other tests skip
   [84]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-168613v2/shard-lnl-2/igt@xe_exec_threads@threads-multi-queue-cm-fd-basic.html

  * igt@xe_exec_threads@threads-multi-queue-cm-fd-userptr-rebind:
    - shard-bmg:          NOTRUN -> [SKIP][85] ([Intel XE#8378]) +3 other tests skip
   [85]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-168613v2/shard-bmg-5/igt@xe_exec_threads@threads-multi-queue-cm-fd-userptr-rebind.html

  * igt@xe_gpgpu_fill@offset-4x4:
    - shard-bmg:          NOTRUN -> [SKIP][86] ([Intel XE#7954])
   [86]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-168613v2/shard-bmg-5/igt@xe_gpgpu_fill@offset-4x4.html

  * igt@xe_module_load@load:
    - shard-lnl:          ([PASS][87], [PASS][88], [PASS][89], [PASS][90], [PASS][91], [PASS][92], [PASS][93], [PASS][94], [PASS][95], [PASS][96], [PASS][97], [PASS][98], [PASS][99], [PASS][100], [PASS][101], [PASS][102], [PASS][103], [PASS][104], [PASS][105], [PASS][106], [PASS][107], [PASS][108], [PASS][109], [PASS][110], [PASS][111]) -> ([PASS][112], [PASS][113], [PASS][114], [PASS][115], [PASS][116], [PASS][117], [PASS][118], [PASS][119], [PASS][120], [PASS][121], [PASS][122], [PASS][123], [PASS][124], [PASS][125], [PASS][126], [PASS][127], [PASS][128], [PASS][129], [PASS][130], [PASS][131], [PASS][132], [PASS][133], [PASS][134], [SKIP][135], [PASS][136], [PASS][137]) ([Intel XE#378] / [Intel XE#7405])
   [87]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-5398-d3709d2bd13debee032d55c0dd71f145e11ec366/shard-lnl-3/igt@xe_module_load@load.html
   [88]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-5398-d3709d2bd13debee032d55c0dd71f145e11ec366/shard-lnl-6/igt@xe_module_load@load.html
   [89]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-5398-d3709d2bd13debee032d55c0dd71f145e11ec366/shard-lnl-6/igt@xe_module_load@load.html
   [90]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-5398-d3709d2bd13debee032d55c0dd71f145e11ec366/shard-lnl-7/igt@xe_module_load@load.html
   [91]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-5398-d3709d2bd13debee032d55c0dd71f145e11ec366/shard-lnl-7/igt@xe_module_load@load.html
   [92]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-5398-d3709d2bd13debee032d55c0dd71f145e11ec366/shard-lnl-1/igt@xe_module_load@load.html
   [93]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-5398-d3709d2bd13debee032d55c0dd71f145e11ec366/shard-lnl-1/igt@xe_module_load@load.html
   [94]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-5398-d3709d2bd13debee032d55c0dd71f145e11ec366/shard-lnl-1/igt@xe_module_load@load.html
   [95]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-5398-d3709d2bd13debee032d55c0dd71f145e11ec366/shard-lnl-2/igt@xe_module_load@load.html
   [96]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-5398-d3709d2bd13debee032d55c0dd71f145e11ec366/shard-lnl-3/igt@xe_module_load@load.html
   [97]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-5398-d3709d2bd13debee032d55c0dd71f145e11ec366/shard-lnl-5/igt@xe_module_load@load.html
   [98]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-5398-d3709d2bd13debee032d55c0dd71f145e11ec366/shard-lnl-3/igt@xe_module_load@load.html
   [99]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-5398-d3709d2bd13debee032d55c0dd71f145e11ec366/shard-lnl-7/igt@xe_module_load@load.html
   [100]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-5398-d3709d2bd13debee032d55c0dd71f145e11ec366/shard-lnl-4/igt@xe_module_load@load.html
   [101]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-5398-d3709d2bd13debee032d55c0dd71f145e11ec366/shard-lnl-8/igt@xe_module_load@load.html
   [102]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-5398-d3709d2bd13debee032d55c0dd71f145e11ec366/shard-lnl-8/igt@xe_module_load@load.html
   [103]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-5398-d3709d2bd13debee032d55c0dd71f145e11ec366/shard-lnl-8/igt@xe_module_load@load.html
   [104]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-5398-d3709d2bd13debee032d55c0dd71f145e11ec366/shard-lnl-4/igt@xe_module_load@load.html
   [105]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-5398-d3709d2bd13debee032d55c0dd71f145e11ec366/shard-lnl-4/igt@xe_module_load@load.html
   [106]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-5398-d3709d2bd13debee032d55c0dd71f145e11ec366/shard-lnl-5/igt@xe_module_load@load.html
   [107]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-5398-d3709d2bd13debee032d55c0dd71f145e11ec366/shard-lnl-5/igt@xe_module_load@load.html
   [108]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-5398-d3709d2bd13debee032d55c0dd71f145e11ec366/shard-lnl-2/igt@xe_module_load@load.html
   [109]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-5398-d3709d2bd13debee032d55c0dd71f145e11ec366/shard-lnl-2/igt@xe_module_load@load.html
   [110]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-5398-d3709d2bd13debee032d55c0dd71f145e11ec366/shard-lnl-4/igt@xe_module_load@load.html
   [111]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-5398-d3709d2bd13debee032d55c0dd71f145e11ec366/shard-lnl-6/igt@xe_module_load@load.html
   [112]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-168613v2/shard-lnl-6/igt@xe_module_load@load.html
   [113]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-168613v2/shard-lnl-8/igt@xe_module_load@load.html
   [114]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-168613v2/shard-lnl-6/igt@xe_module_load@load.html
   [115]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-168613v2/shard-lnl-8/igt@xe_module_load@load.html
   [116]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-168613v2/shard-lnl-8/igt@xe_module_load@load.html
   [117]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-168613v2/shard-lnl-7/igt@xe_module_load@load.html
   [118]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-168613v2/shard-lnl-7/igt@xe_module_load@load.html
   [119]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-168613v2/shard-lnl-7/igt@xe_module_load@load.html
   [120]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-168613v2/shard-lnl-5/igt@xe_module_load@load.html
   [121]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-168613v2/shard-lnl-3/igt@xe_module_load@load.html
   [122]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-168613v2/shard-lnl-2/igt@xe_module_load@load.html
   [123]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-168613v2/shard-lnl-2/igt@xe_module_load@load.html
   [124]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-168613v2/shard-lnl-5/igt@xe_module_load@load.html
   [125]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-168613v2/shard-lnl-5/igt@xe_module_load@load.html
   [126]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-168613v2/shard-lnl-3/igt@xe_module_load@load.html
   [127]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-168613v2/shard-lnl-3/igt@xe_module_load@load.html
   [128]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-168613v2/shard-lnl-6/igt@xe_module_load@load.html
   [129]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-168613v2/shard-lnl-1/igt@xe_module_load@load.html
   [130]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-168613v2/shard-lnl-6/igt@xe_module_load@load.html
   [131]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-168613v2/shard-lnl-1/igt@xe_module_load@load.html
   [132]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-168613v2/shard-lnl-1/igt@xe_module_load@load.html
   [133]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-168613v2/shard-lnl-4/igt@xe_module_load@load.html
   [134]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-168613v2/shard-lnl-2/igt@xe_module_load@load.html
   [135]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-168613v2/shard-lnl-2/igt@xe_module_load@load.html
   [136]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-168613v2/shard-lnl-4/igt@xe_module_load@load.html
   [137]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-168613v2/shard-lnl-4/igt@xe_module_load@load.html

  * igt@xe_multigpu_svm@mgpu-latency-basic:
    - shard-bmg:          NOTRUN -> [SKIP][138] ([Intel XE#6964]) +1 other test skip
   [138]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-168613v2/shard-bmg-2/igt@xe_multigpu_svm@mgpu-latency-basic.html

  * igt@xe_multigpu_svm@mgpu-latency-prefetch:
    - shard-lnl:          NOTRUN -> [SKIP][139] ([Intel XE#6964])
   [139]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-168613v2/shard-lnl-2/igt@xe_multigpu_svm@mgpu-latency-prefetch.html

  * igt@xe_page_reclaim@boundary-split:
    - shard-bmg:          NOTRUN -> [SKIP][140] ([Intel XE#7793])
   [140]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-168613v2/shard-bmg-2/igt@xe_page_reclaim@boundary-split.html

  * igt@xe_pat@xa-app-transient-media-off:
    - shard-lnl:          NOTRUN -> [SKIP][141] ([Intel XE#7590] / [Intel XE#7772])
   [141]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-168613v2/shard-lnl-5/igt@xe_pat@xa-app-transient-media-off.html

  * igt@xe_pm@d3cold-basic:
    - shard-bmg:          NOTRUN -> [SKIP][142] ([Intel XE#2284] / [Intel XE#7370])
   [142]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-168613v2/shard-bmg-5/igt@xe_pm@d3cold-basic.html

  * igt@xe_pm@d3hot-mmap-vram:
    - shard-lnl:          NOTRUN -> [SKIP][143] ([Intel XE#1948])
   [143]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-168613v2/shard-lnl-5/igt@xe_pm@d3hot-mmap-vram.html

  * igt@xe_pm@vram-d3cold-threshold:
    - shard-lnl:          NOTRUN -> [SKIP][144] ([Intel XE#579] / [Intel XE#7329] / [Intel XE#7456])
   [144]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-168613v2/shard-lnl-5/igt@xe_pm@vram-d3cold-threshold.html

  * igt@xe_prefetch_fault@prefetch-fault-svm:
    - shard-bmg:          NOTRUN -> [SKIP][145] ([Intel XE#7599])
   [145]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-168613v2/shard-bmg-5/igt@xe_prefetch_fault@prefetch-fault-svm.html

  * igt@xe_query@multigpu-query-invalid-query:
    - shard-bmg:          NOTRUN -> [SKIP][146] ([Intel XE#944]) +1 other test skip
   [146]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-168613v2/shard-bmg-5/igt@xe_query@multigpu-query-invalid-query.html

  * igt@xe_query@multigpu-query-uc-fw-version-guc:
    - shard-lnl:          NOTRUN -> [SKIP][147] ([Intel XE#944])
   [147]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-168613v2/shard-lnl-2/igt@xe_query@multigpu-query-uc-fw-version-guc.html

  * igt@xe_sriov_admin@exec-quantum-write-readback-vfs-disabled:
    - shard-lnl:          NOTRUN -> [SKIP][148] ([Intel XE#7174])
   [148]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-168613v2/shard-lnl-5/igt@xe_sriov_admin@exec-quantum-write-readback-vfs-disabled.html

  * igt@xe_sriov_flr@flr-vfs-parallel:
    - shard-lnl:          NOTRUN -> [SKIP][149] ([Intel XE#4273])
   [149]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-168613v2/shard-lnl-2/igt@xe_sriov_flr@flr-vfs-parallel.html

  
#### Possible fixes ####

  * igt@core_hotunplug@hotunbind-rebind:
    - shard-bmg:          [ABORT][150] ([Intel XE#8007]) -> [PASS][151] +1 other test pass
   [150]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-5398-d3709d2bd13debee032d55c0dd71f145e11ec366/shard-bmg-10/igt@core_hotunplug@hotunbind-rebind.html
   [151]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-168613v2/shard-bmg-5/igt@core_hotunplug@hotunbind-rebind.html

  * igt@kms_async_flips@alternate-sync-async-flip-atomic:
    - shard-lnl:          [FAIL][152] ([Intel XE#3718] / [Intel XE#7265]) -> [PASS][153]
   [152]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-5398-d3709d2bd13debee032d55c0dd71f145e11ec366/shard-lnl-3/igt@kms_async_flips@alternate-sync-async-flip-atomic.html
   [153]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-168613v2/shard-lnl-6/igt@kms_async_flips@alternate-sync-async-flip-atomic.html

  * igt@kms_async_flips@alternate-sync-async-flip-atomic@pipe-b-edp-1:
    - shard-lnl:          [FAIL][154] ([Intel XE#7265]) -> [PASS][155]
   [154]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-5398-d3709d2bd13debee032d55c0dd71f145e11ec366/shard-lnl-3/igt@kms_async_flips@alternate-sync-async-flip-atomic@pipe-b-edp-1.html
   [155]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-168613v2/shard-lnl-6/igt@kms_async_flips@alternate-sync-async-flip-atomic@pipe-b-edp-1.html

  * igt@kms_flip@flip-vs-expired-vblank@a-edp1:
    - shard-lnl:          [FAIL][156] ([Intel XE#301]) -> [PASS][157] +2 other tests pass
   [156]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-5398-d3709d2bd13debee032d55c0dd71f145e11ec366/shard-lnl-4/igt@kms_flip@flip-vs-expired-vblank@a-edp1.html
   [157]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-168613v2/shard-lnl-8/igt@kms_flip@flip-vs-expired-vblank@a-edp1.html

  * igt@kms_hdr@invalid-hdr:
    - shard-bmg:          [SKIP][158] ([Intel XE#1503]) -> [PASS][159]
   [158]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-5398-d3709d2bd13debee032d55c0dd71f145e11ec366/shard-bmg-10/igt@kms_hdr@invalid-hdr.html
   [159]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-168613v2/shard-bmg-6/igt@kms_hdr@invalid-hdr.html

  * igt@xe_evict@evict-mixed-many-threads-small:
    - shard-bmg:          [INCOMPLETE][160] ([Intel XE#6321] / [Intel XE#8355]) -> [PASS][161]
   [160]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-5398-d3709d2bd13debee032d55c0dd71f145e11ec366/shard-bmg-9/igt@xe_evict@evict-mixed-many-threads-small.html
   [161]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-168613v2/shard-bmg-4/igt@xe_evict@evict-mixed-many-threads-small.html

  * igt@xe_exec_reset@long-spin-reuse-many-preempt-media:
    - shard-bmg:          [FAIL][162] ([Intel XE#7850]) -> [PASS][163]
   [162]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-5398-d3709d2bd13debee032d55c0dd71f145e11ec366/shard-bmg-10/igt@xe_exec_reset@long-spin-reuse-many-preempt-media.html
   [163]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-168613v2/shard-bmg-6/igt@xe_exec_reset@long-spin-reuse-many-preempt-media.html

  * igt@xe_wedged@basic-wedged:
    - shard-lnl:          [ABORT][164] ([Intel XE#3119]) -> [PASS][165]
   [164]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-5398-d3709d2bd13debee032d55c0dd71f145e11ec366/shard-lnl-2/igt@xe_wedged@basic-wedged.html
   [165]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-168613v2/shard-lnl-2/igt@xe_wedged@basic-wedged.html

  
#### Warnings ####

  * igt@kms_flip@flip-vs-expired-vblank-interruptible:
    - shard-lnl:          [FAIL][166] ([Intel XE#301]) -> [FAIL][167] ([Intel XE#301] / [Intel XE#3149])
   [166]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-5398-d3709d2bd13debee032d55c0dd71f145e11ec366/shard-lnl-7/igt@kms_flip@flip-vs-expired-vblank-interruptible.html
   [167]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-168613v2/shard-lnl-3/igt@kms_flip@flip-vs-expired-vblank-interruptible.html

  * igt@kms_frontbuffer_tracking@fbcdrrshdr-2p-scndscrn-cur-indfb-draw-mmap-wc:
    - shard-lnl:          [ABORT][168] ([Intel XE#8007]) -> [SKIP][169] ([Intel XE#7905])
   [168]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-5398-d3709d2bd13debee032d55c0dd71f145e11ec366/shard-lnl-4/igt@kms_frontbuffer_tracking@fbcdrrshdr-2p-scndscrn-cur-indfb-draw-mmap-wc.html
   [169]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-168613v2/shard-lnl-5/igt@kms_frontbuffer_tracking@fbcdrrshdr-2p-scndscrn-cur-indfb-draw-mmap-wc.html

  
  [Intel XE#1091]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/1091
  [Intel XE#1124]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/1124
  [Intel XE#1125]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/1125
  [Intel XE#1128]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/1128
  [Intel XE#1392]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/1392
  [Intel XE#1406]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/1406
  [Intel XE#1407]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/1407
  [Intel XE#1421]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/1421
  [Intel XE#1424]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/1424
  [Intel XE#1435]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/1435
  [Intel XE#1439]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/1439
  [Intel XE#1469]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/1469
  [Intel XE#1489]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/1489
  [Intel XE#1499]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/1499
  [Intel XE#1503]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/1503
  [Intel XE#1948]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/1948
  [Intel XE#2234]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/2234
  [Intel XE#2252]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/2252
  [Intel XE#2284]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/2284
  [Intel XE#2311]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/2311
  [Intel XE#2313]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/2313
  [Intel XE#2320]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/2320
  [Intel XE#2321]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/2321
  [Intel XE#2322]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/2322
  [Intel XE#2325]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/2325
  [Intel XE#2327]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/2327
  [Intel XE#2390]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/2390
  [Intel XE#2504]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/2504
  [Intel XE#2509]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/2509
  [Intel XE#2763]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/2763
  [Intel XE#2849]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/2849
  [Intel XE#2850]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/2850
  [Intel XE#2887]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/2887
  [Intel XE#2893]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/2893
  [Intel XE#301]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/301
  [Intel XE#309]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/309
  [Intel XE#3119]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/3119
  [Intel XE#3141]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/3141
  [Intel XE#3149]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/3149
  [Intel XE#3321]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/3321
  [Intel XE#3414]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/3414
  [Intel XE#3432]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/3432
  [Intel XE#3658]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/3658
  [Intel XE#367]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/367
  [Intel XE#3718]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/3718
  [Intel XE#373]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/373
  [Intel XE#378]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/378
  [Intel XE#3904]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/3904
  [Intel XE#4141]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/4141
  [Intel XE#4273]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/4273
  [Intel XE#4422]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/4422
  [Intel XE#4609]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/4609
  [Intel XE#5021]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/5021
  [Intel XE#579]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/579
  [Intel XE#599]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/599
  [Intel XE#6312]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/6312
  [Intel XE#6321]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/6321
  [Intel XE#6503]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/6503
  [Intel XE#651]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/651
  [Intel XE#6540]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/6540
  [Intel XE#656]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/656
  [Intel XE#6592]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/6592
  [Intel XE#6645]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/6645
  [Intel XE#688]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/688
  [Intel XE#6886]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/6886
  [Intel XE#6900]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/6900
  [Intel XE#6912]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/6912
  [Intel XE#6964]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/6964
  [Intel XE#6974]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/6974
  [Intel XE#7059]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/7059
  [Intel XE#7061]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/7061
  [Intel XE#7084]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/7084
  [Intel XE#7085]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/7085
  [Intel XE#7174]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/7174
  [Intel XE#7178]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/7178
  [Intel XE#7265]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/7265
  [Intel XE#7283]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/7283
  [Intel XE#7304]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/7304
  [Intel XE#7312]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/7312
  [Intel XE#7319]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/7319
  [Intel XE#7329]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/7329
  [Intel XE#7342]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/7342
  [Intel XE#7343]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/7343
  [Intel XE#7345]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/7345
  [Intel XE#7350]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/7350
  [Intel XE#7351]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/7351
  [Intel XE#7355]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/7355
  [Intel XE#7356]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/7356
  [Intel XE#7358]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/7358
  [Intel XE#7360]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/7360
  [Intel XE#7362]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/7362
  [Intel XE#7370]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/7370
  [Intel XE#7372]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/7372
  [Intel XE#7375]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/7375
  [Intel XE#7376]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/7376
  [Intel XE#7377]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/7377
  [Intel XE#7383]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/7383
  [Intel XE#7391]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/7391
  [Intel XE#7399]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/7399
  [Intel XE#7402]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/7402
  [Intel XE#7405]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/7405
  [Intel XE#7413]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/7413
  [Intel XE#7437]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/7437
  [Intel XE#7442]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/7442
  [Intel XE#7456]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/7456
  [Intel XE#7482]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/7482
  [Intel XE#7590]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/7590
  [Intel XE#7599]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/7599
  [Intel XE#7642]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/7642
  [Intel XE#7679]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/7679
  [Intel XE#7760]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/7760
  [Intel XE#7772]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/7772
  [Intel XE#7793]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/7793
  [Intel XE#7814]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/7814
  [Intel XE#7850]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/7850
  [Intel XE#7865]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/7865
  [Intel XE#7893]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/7893
  [Intel XE#7905]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/7905
  [Intel XE#7954]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/7954
  [Intel XE#8007]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/8007
  [Intel XE#8150]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/8150
  [Intel XE#8265]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/8265
  [Intel XE#8300]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/8300
  [Intel XE#8303]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/8303
  [Intel XE#8355]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/8355
  [Intel XE#836]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/836
  [Intel XE#8364]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/8364
  [Intel XE#8370]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/8370
  [Intel XE#8374]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/8374
  [Intel XE#8378]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/8378
  [Intel XE#870]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/870
  [Intel XE#944]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/944


Build changes
-------------

  * Linux: xe-5398-d3709d2bd13debee032d55c0dd71f145e11ec366 -> xe-pw-168613v2

  IGT_9006: 6380a8af26359dd222e22679442272ded836c463 @ https://gitlab.freedesktop.org/drm/igt-gpu-tools.git
  xe-5398-d3709d2bd13debee032d55c0dd71f145e11ec366: d3709d2bd13debee032d55c0dd71f145e11ec366
  xe-pw-168613v2: 168613v2

== Logs ==

For more details see: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-168613v2/index.html

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