From: "Cheatham, Benjamin" <benjamin.cheatham@amd.com>
To: Terry Bowman <terry.bowman@amd.com>,
Jonathan Cameron <jic23@kernel.org>,
Dave Jiang <dave.jiang@intel.com>,
Alison Schofield <alison.schofield@intel.com>,
Vishal Verma <vishal.l.verma@intel.com>,
Davidlohr Bueso <dave@stgolabs.net>,
Bjorn Helgaas <bhelgaas@google.com>,
"Dan Williams" <djbw@kernel.org>,
"Rafael J . Wysocki" <rafael@kernel.org>,
Jonathan Corbet <corbet@lwn.net>, <linux-cxl@vger.kernel.org>
Cc: Tony Luck <tony.luck@intel.com>, Borislav Petkov <bp@alien8.de>,
"Hanjun Guo" <guohanjun@huawei.com>,
Mauro Carvalho Chehab <mchehab@kernel.org>,
"Shuai Xue" <xueshuai@linux.alibaba.com>,
Len Brown <lenb@kernel.org>, Ira Weiny <iweiny@kernel.org>,
Li Ming <ming.li@zohomail.com>,
Shuah Khan <skhan@linuxfoundation.org>,
Richard Cheng <icheng@nvidia.com>,
"Robert Richter" <rrichter@amd.com>,
Lukas Wunner <lukas@wunner.de>, <linux-pci@vger.kernel.org>,
<linux-acpi@vger.kernel.org>, <linux-doc@vger.kernel.org>,
<linux-kernel@vger.kernel.org>
Subject: Re: [PATCH v20 8/9] PCI/CXL: Mask/Unmask CXL protocol errors
Date: Wed, 2 Sep 2026 15:57:37 -0500 [thread overview]
Message-ID: <2df10ab6-5bb9-461e-8aab-c53daf11368e@amd.com> (raw)
In-Reply-To: <20260902133933.2992457-9-terry.bowman@amd.com>
On 9/2/2026 8:39 AM, Terry Bowman wrote:
> CXL protocol errors must be unmasked to be reported. Add
> pci_aer_mask_internal_errors() as the symmetric counterpart to
> pci_aer_unmask_internal_errors() and export both for cxl_core.
>
> Unmask CXL internal errors in cxl_dport_map_ras() and
> devm_cxl_port_ras_setup() after the RAS register block is
> successfully mapped. Register a devm action to restore the mask
> on teardown. The unmask/mask helpers gate on dev_is_pci() and
> pcie_aer_is_native() internally so callers need no special-casing.
>
> Remove the dev_is_pci(dport->dport_dev) guard in
> devm_cxl_dport_rch_ras_setup(). On RCH systems dport->dport_dev
> is the pci_host_bridge device which is not on pci_bus_type, so
> this guard blocked real hardware. The caller already gates on
> dport->rch.
>
> Co-developed-by: Dan Williams <djbw@kernel.org>
> Signed-off-by: Dan Williams <djbw@kernel.org>
> Signed-off-by: Terry Bowman <terry.bowman@amd.com>
> Reviewed-by: Dave Jiang <dave.jiang@intel.com>
> Reviewed-by: Jonathan Cameron <jonathan.cameron@oss.qualcomm.com>
> Reviewed-by: Alison Schofield <alison.schofield@intel.com>
>
> ---
Reviewed-by: Ben Cheatham <benjamin.cheatham@amd.com>
Thanks,
Ben
next prev parent reply other threads:[~2026-09-02 20:57 UTC|newest]
Thread overview: 45+ messages / expand[flat|nested] mbox.gz Atom feed top
2026-09-02 13:39 [PATCH v20 0/9] Enable CXL PCIe Port Protocol Error handling and logging Terry Bowman
2026-09-02 13:39 ` [PATCH v20 1/9] PCI/AER: Introduce AER-CXL protocol error kfifo Terry Bowman
2026-09-02 13:48 ` sashiko-bot
2026-09-02 20:57 ` Cheatham, Benjamin
2026-09-08 0:51 ` Jonathan Cameron
2026-09-09 15:38 ` Bowman, Terry
2026-09-09 22:02 ` Jonathan Cameron
2026-09-10 14:57 ` Bowman, Terry
2026-09-02 13:39 ` [PATCH v20 2/9] PCI: Establish common CXL Port protocol error flow Terry Bowman
2026-09-02 13:57 ` sashiko-bot
2026-09-02 16:11 ` Bowman, Terry
2026-09-02 20:57 ` Cheatham, Benjamin
2026-09-10 16:55 ` Bowman, Terry
2026-09-08 0:57 ` Jonathan Cameron
2026-09-02 13:39 ` [PATCH v20 3/9] cxl/ras: Handle RCH correctable and uncorrectable errors in one pass Terry Bowman
2026-09-02 13:50 ` sashiko-bot
2026-09-02 20:57 ` Cheatham, Benjamin
2026-09-08 1:06 ` Jonathan Cameron
2026-09-02 13:39 ` [PATCH v20 4/9] cxl/pci: Thread port and dport through RAS handling helpers Terry Bowman
2026-09-02 13:51 ` sashiko-bot
2026-09-02 20:57 ` Cheatham, Benjamin
2026-09-09 14:42 ` Bowman, Terry
2026-09-09 15:21 ` Bowman, Terry
2026-09-08 17:47 ` Jonathan Cameron
2026-09-02 13:39 ` [PATCH v20 5/9] cxl: Update CXL Endpoint AER handler Terry Bowman
2026-09-02 14:05 ` sashiko-bot
2026-09-02 18:19 ` Bowman, Terry
2026-09-02 20:57 ` Cheatham, Benjamin
2026-09-02 13:39 ` [PATCH v20 6/9] PCI: Cache PCI DSN into pci_dev->dsn during probe Terry Bowman
2026-09-02 13:47 ` sashiko-bot
2026-09-02 20:57 ` Cheatham, Benjamin
2026-09-09 15:16 ` Lukas Wunner
2026-09-02 13:39 ` [PATCH v20 7/9] cxl: Add port and dport identifiers to CXL AER trace events Terry Bowman
2026-09-02 13:50 ` sashiko-bot
2026-09-08 18:13 ` Jonathan Cameron
2026-09-02 13:39 ` [PATCH v20 8/9] PCI/CXL: Mask/Unmask CXL protocol errors Terry Bowman
2026-09-02 14:03 ` sashiko-bot
2026-09-02 15:49 ` Bowman, Terry
2026-09-02 20:57 ` Cheatham, Benjamin [this message]
2026-09-02 13:39 ` [PATCH v20 9/9] Documentation: cxl: Document CXL protocol error handling Terry Bowman
2026-09-02 13:50 ` sashiko-bot
2026-09-08 18:39 ` Jonathan Cameron
2026-09-10 15:19 ` Bowman, Terry
2026-09-09 16:03 ` [PATCH v20 0/9] Enable CXL PCIe Port Protocol Error handling and logging Lukas Wunner
2026-09-09 20:31 ` Bowman, Terry
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