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From: "Heiko Stübner" <heiko@sntech.de>
To: Cunhao Lu <1579567540@qq.com>, Krzysztof Kozlowski <krzk@kernel.org>
Cc: Stephen Boyd <sboyd@kernel.org>,
	Brian Masney <bmasney+clk@redhat.com>,
	Jerome Brunet <jbrunet+clk@baylibre.com>,
	Rob Herring <robh@kernel.org>,
	Krzysztof Kozlowski <krzk+dt@kernel.org>,
	Conor Dooley <conor+dt@kernel.org>,
	Philipp Zabel <p.zabel@pengutronix.de>,
	Elaine Zhang <zhangqing@rock-chips.com>,
	Richard Cochran <richardcochran@gmail.com>,
	linux-clk@vger.kernel.org, devicetree@vger.kernel.org,
	linux-arm-kernel@lists.infradead.org,
	linux-rockchip@lists.infradead.org, linux-kernel@vger.kernel.org,
	netdev@vger.kernel.org
Subject: Re: [PATCH v3 1/3] dt-bindings: clock: rockchip: Add RK3572 CRU
Date: Tue, 27 Oct 2026 11:43:56 +0100	[thread overview]
Message-ID: <3011736.yaVYbkx8dN@diego> (raw)
In-Reply-To: <20261027-vagabond-gabby-caracara-4edabe@quoll>

Am Dienstag, 27. Oktober 2026, 11:17:08 Mitteleuropäische Normalzeit schrieb Krzysztof Kozlowski:
> On Mon, Oct 26, 2026 at 02:56:47PM +0800, Cunhao Lu wrote:
> > From: Elaine Zhang <zhangqing@rock-chips.com>
> > 
> > The RK3572 CRU uses the PMU0 GRF for the AUPLL reference mux.
> > Describe the controller and define its clock and reset IDs.
> > 
> > Signed-off-by: Elaine Zhang <zhangqing@rock-chips.com>
> > 
> > - Documented the xin24m input.
> > - Made the PMU0 GRF phandle required.
> > - Updated the example.
> > - Closed the reset ID gap while preserving each named reset's register
> >   mapping.
> > - Removed CLK_NR_CLKS from the clock binding.
> > 
> 
> All your patches seems to have odd commit msg.
> 
> > Signed-off-by: Cunhao Lu <1579567540@qq.com>

With code originating in the vendor kernel, it is nice to know what changed,
but I guess there is a tradeoff between brevity and more details.

I guess this could be shorted to something less verbose, like

+++++++++++++
Signed-off-by: Elaine Zhang <zhangqing@rock-chips.com>
[adapted to mainline rockchip clock and reset handling (xin24m input,
  don't introduce CLK_NR_CLKS, etc ]
Signed-off-by: Cunhao Lu <1579567540@qq.com>
+++++++++++++





WARNING: multiple messages have this Message-ID (diff)
From: "Heiko Stübner" <heiko@sntech.de>
To: Cunhao Lu <1579567540@qq.com>, Krzysztof Kozlowski <krzk@kernel.org>
Cc: Stephen Boyd <sboyd@kernel.org>,
	Brian Masney <bmasney+clk@redhat.com>,
	Jerome Brunet <jbrunet+clk@baylibre.com>,
	Rob Herring <robh@kernel.org>,
	Krzysztof Kozlowski <krzk+dt@kernel.org>,
	Conor Dooley <conor+dt@kernel.org>,
	Philipp Zabel <p.zabel@pengutronix.de>,
	Elaine Zhang <zhangqing@rock-chips.com>,
	Richard Cochran <richardcochran@gmail.com>,
	linux-clk@vger.kernel.org, devicetree@vger.kernel.org,
	linux-arm-kernel@lists.infradead.org,
	linux-rockchip@lists.infradead.org, linux-kernel@vger.kernel.org,
	netdev@vger.kernel.org
Subject: Re: [PATCH v3 1/3] dt-bindings: clock: rockchip: Add RK3572 CRU
Date: Tue, 27 Oct 2026 11:43:56 +0100	[thread overview]
Message-ID: <3011736.yaVYbkx8dN@diego> (raw)
In-Reply-To: <20261027-vagabond-gabby-caracara-4edabe@quoll>

Am Dienstag, 27. Oktober 2026, 11:17:08 Mitteleuropäische Normalzeit schrieb Krzysztof Kozlowski:
> On Mon, Oct 26, 2026 at 02:56:47PM +0800, Cunhao Lu wrote:
> > From: Elaine Zhang <zhangqing@rock-chips.com>
> > 
> > The RK3572 CRU uses the PMU0 GRF for the AUPLL reference mux.
> > Describe the controller and define its clock and reset IDs.
> > 
> > Signed-off-by: Elaine Zhang <zhangqing@rock-chips.com>
> > 
> > - Documented the xin24m input.
> > - Made the PMU0 GRF phandle required.
> > - Updated the example.
> > - Closed the reset ID gap while preserving each named reset's register
> >   mapping.
> > - Removed CLK_NR_CLKS from the clock binding.
> > 
> 
> All your patches seems to have odd commit msg.
> 
> > Signed-off-by: Cunhao Lu <1579567540@qq.com>

With code originating in the vendor kernel, it is nice to know what changed,
but I guess there is a tradeoff between brevity and more details.

I guess this could be shorted to something less verbose, like

+++++++++++++
Signed-off-by: Elaine Zhang <zhangqing@rock-chips.com>
[adapted to mainline rockchip clock and reset handling (xin24m input,
  don't introduce CLK_NR_CLKS, etc ]
Signed-off-by: Cunhao Lu <1579567540@qq.com>
+++++++++++++





_______________________________________________
Linux-rockchip mailing list
Linux-rockchip@lists.infradead.org
http://lists.infradead.org/mailman/listinfo/linux-rockchip

  reply	other threads:[~2026-10-27 10:44 UTC|newest]

Thread overview: 30+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2026-10-26  6:56 [PATCH v3 0/3] clk: rockchip: Add RK3572 clock and reset support Cunhao Lu via B4 Relay
2026-10-26  6:56 ` Cunhao Lu via B4 Relay
2026-10-26  6:56 ` Cunhao Lu
2026-10-26  6:56 ` [PATCH v3 1/3] dt-bindings: clock: rockchip: Add RK3572 CRU Cunhao Lu via B4 Relay
2026-10-26  6:56   ` Cunhao Lu via B4 Relay
2026-10-26  6:56   ` Cunhao Lu
2026-10-27 10:17   ` Krzysztof Kozlowski
2026-10-27 10:17     ` Krzysztof Kozlowski
2026-10-27 10:43     ` Heiko Stübner [this message]
2026-10-27 10:43       ` Heiko Stübner
2026-10-27 11:06       ` Cunhao Lu
2026-10-27 11:06         ` Cunhao Lu
2026-10-27 11:07       ` Krzysztof Kozlowski
2026-10-27 11:07         ` Krzysztof Kozlowski
2026-10-27 12:53         ` Heiko Stübner
2026-10-27 12:53           ` Heiko Stübner
2026-10-26  6:56 ` [PATCH v3 2/3] clk: rockchip: Add internal support for 24-bit fractional dividers Cunhao Lu via B4 Relay
2026-10-26  6:56   ` Cunhao Lu via B4 Relay
2026-10-26  6:56   ` Cunhao Lu
2026-10-27  6:57   ` sashiko-bot
2026-10-27  9:27     ` Cunhao Lu
2026-10-26  6:56 ` [PATCH v3 3/3] clk: rockchip: Add RK3572 clock and reset support Cunhao Lu via B4 Relay
2026-10-26  6:56   ` Cunhao Lu via B4 Relay
2026-10-26  6:56   ` Cunhao Lu
     [not found]   ` <0d5de6fd-3150-4898-a652-7f5b64dcaf07@rock-chips.com>
2026-10-26 14:56     ` Cunhao Lu
2026-10-26 14:56       ` Cunhao Lu
2026-10-26 17:25       ` Heiko Stübner
2026-10-26 17:25         ` Heiko Stübner
2026-10-27  0:57       ` 张晴
2026-10-27  0:57         ` 张晴

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