* [v2 PATCH 1/3] clk: rockchip: Fractional dividers can't set parent rates @ 2016-09-02 3:26 ` Chris Zhong 0 siblings, 0 replies; 16+ messages in thread From: Chris Zhong @ 2016-09-02 3:26 UTC (permalink / raw) To: heiko, dianders Cc: linux-rockchip, zhengxing, ykk, Chris Zhong, Michael Turquette, Stephen Boyd, linux-kernel, linux-clk, linux-arm-kernel From: Douglas Anderson <dianders@chromium.org> Currently the fractional divider clock time can't handle the CLK_SET_RATE_PARENT flag. This is because, unlike normal dividers, there is no clk_divider_bestdiv() function to try speeding up the parent to see if it helps things. Eventually someone could try to figure out how to make fractional dividers able to use CLK_SET_RATE_PARENT, but until they do let's not confuse the common clock framework (and anyone using it) by setting the flag. Signed-off-by: Douglas Anderson <dianders@chromium.org> Signed-off-by: Chris Zhong <zyw@rock-chips.com> --- drivers/clk/rockchip/clk-rk3399.c | 26 +++++++++++++------------- 1 file changed, 13 insertions(+), 13 deletions(-) diff --git a/drivers/clk/rockchip/clk-rk3399.c b/drivers/clk/rockchip/clk-rk3399.c index ea32b7e..59417c5 100644 --- a/drivers/clk/rockchip/clk-rk3399.c +++ b/drivers/clk/rockchip/clk-rk3399.c @@ -585,7 +585,7 @@ static struct rockchip_clk_branch rk3399_clk_branches[] __initdata = { COMPOSITE(0, "clk_spdif_div", mux_pll_src_cpll_gpll_p, 0, RK3399_CLKSEL_CON(32), 7, 1, MFLAGS, 0, 7, DFLAGS, RK3399_CLKGATE_CON(8), 13, GFLAGS), - COMPOSITE_FRACMUX(0, "clk_spdif_frac", "clk_spdif_div", CLK_SET_RATE_PARENT, + COMPOSITE_FRACMUX(0, "clk_spdif_frac", "clk_spdif_div", 0, RK3399_CLKSEL_CON(99), 0, RK3399_CLKGATE_CON(8), 14, GFLAGS, &rk3399_spdif_fracmux), @@ -599,7 +599,7 @@ static struct rockchip_clk_branch rk3399_clk_branches[] __initdata = { COMPOSITE(0, "clk_i2s0_div", mux_pll_src_cpll_gpll_p, 0, RK3399_CLKSEL_CON(28), 7, 1, MFLAGS, 0, 7, DFLAGS, RK3399_CLKGATE_CON(8), 3, GFLAGS), - COMPOSITE_FRACMUX(0, "clk_i2s0_frac", "clk_i2s0_div", CLK_SET_RATE_PARENT, + COMPOSITE_FRACMUX(0, "clk_i2s0_frac", "clk_i2s0_div", 0, RK3399_CLKSEL_CON(96), 0, RK3399_CLKGATE_CON(8), 4, GFLAGS, &rk3399_i2s0_fracmux), @@ -609,7 +609,7 @@ static struct rockchip_clk_branch rk3399_clk_branches[] __initdata = { COMPOSITE(0, "clk_i2s1_div", mux_pll_src_cpll_gpll_p, 0, RK3399_CLKSEL_CON(29), 7, 1, MFLAGS, 0, 7, DFLAGS, RK3399_CLKGATE_CON(8), 6, GFLAGS), - COMPOSITE_FRACMUX(0, "clk_i2s1_frac", "clk_i2s1_div", CLK_SET_RATE_PARENT, + COMPOSITE_FRACMUX(0, "clk_i2s1_frac", "clk_i2s1_div", 0, RK3399_CLKSEL_CON(97), 0, RK3399_CLKGATE_CON(8), 7, GFLAGS, &rk3399_i2s1_fracmux), @@ -619,7 +619,7 @@ static struct rockchip_clk_branch rk3399_clk_branches[] __initdata = { COMPOSITE(0, "clk_i2s2_div", mux_pll_src_cpll_gpll_p, 0, RK3399_CLKSEL_CON(30), 7, 1, MFLAGS, 0, 7, DFLAGS, RK3399_CLKGATE_CON(8), 9, GFLAGS), - COMPOSITE_FRACMUX(0, "clk_i2s2_frac", "clk_i2s2_div", CLK_SET_RATE_PARENT, + COMPOSITE_FRACMUX(0, "clk_i2s2_frac", "clk_i2s2_div", 0, RK3399_CLKSEL_CON(98), 0, RK3399_CLKGATE_CON(8), 10, GFLAGS, &rk3399_i2s2_fracmux), @@ -638,7 +638,7 @@ static struct rockchip_clk_branch rk3399_clk_branches[] __initdata = { COMPOSITE_NOMUX(0, "clk_uart0_div", "clk_uart0_src", 0, RK3399_CLKSEL_CON(33), 0, 7, DFLAGS, RK3399_CLKGATE_CON(9), 0, GFLAGS), - COMPOSITE_FRACMUX(0, "clk_uart0_frac", "clk_uart0_div", CLK_SET_RATE_PARENT, + COMPOSITE_FRACMUX(0, "clk_uart0_frac", "clk_uart0_div", 0, RK3399_CLKSEL_CON(100), 0, RK3399_CLKGATE_CON(9), 1, GFLAGS, &rk3399_uart0_fracmux), @@ -648,7 +648,7 @@ static struct rockchip_clk_branch rk3399_clk_branches[] __initdata = { COMPOSITE_NOMUX(0, "clk_uart1_div", "clk_uart_src", 0, RK3399_CLKSEL_CON(34), 0, 7, DFLAGS, RK3399_CLKGATE_CON(9), 2, GFLAGS), - COMPOSITE_FRACMUX(0, "clk_uart1_frac", "clk_uart1_div", CLK_SET_RATE_PARENT, + COMPOSITE_FRACMUX(0, "clk_uart1_frac", "clk_uart1_div", 0, RK3399_CLKSEL_CON(101), 0, RK3399_CLKGATE_CON(9), 3, GFLAGS, &rk3399_uart1_fracmux), @@ -656,7 +656,7 @@ static struct rockchip_clk_branch rk3399_clk_branches[] __initdata = { COMPOSITE_NOMUX(0, "clk_uart2_div", "clk_uart_src", 0, RK3399_CLKSEL_CON(35), 0, 7, DFLAGS, RK3399_CLKGATE_CON(9), 4, GFLAGS), - COMPOSITE_FRACMUX(0, "clk_uart2_frac", "clk_uart2_div", CLK_SET_RATE_PARENT, + COMPOSITE_FRACMUX(0, "clk_uart2_frac", "clk_uart2_div", 0, RK3399_CLKSEL_CON(102), 0, RK3399_CLKGATE_CON(9), 5, GFLAGS, &rk3399_uart2_fracmux), @@ -664,7 +664,7 @@ static struct rockchip_clk_branch rk3399_clk_branches[] __initdata = { COMPOSITE_NOMUX(0, "clk_uart3_div", "clk_uart_src", 0, RK3399_CLKSEL_CON(36), 0, 7, DFLAGS, RK3399_CLKGATE_CON(9), 6, GFLAGS), - COMPOSITE_FRACMUX(0, "clk_uart3_frac", "clk_uart3_div", CLK_SET_RATE_PARENT, + COMPOSITE_FRACMUX(0, "clk_uart3_frac", "clk_uart3_div", 0, RK3399_CLKSEL_CON(103), 0, RK3399_CLKGATE_CON(9), 7, GFLAGS, &rk3399_uart3_fracmux), @@ -1168,7 +1168,7 @@ static struct rockchip_clk_branch rk3399_clk_branches[] __initdata = { RK3399_CLKSEL_CON(49), 8, 2, MFLAGS, 0, 8, DFLAGS, RK3399_CLKGATE_CON(10), 12, GFLAGS), - COMPOSITE_FRACMUX_NOGATE(0, "dclk_vop0_frac", "dclk_vop0_div", CLK_SET_RATE_PARENT, + COMPOSITE_FRACMUX_NOGATE(0, "dclk_vop0_frac", "dclk_vop0_div", 0, RK3399_CLKSEL_CON(106), 0, &rk3399_dclk_vop0_fracmux), @@ -1198,7 +1198,7 @@ static struct rockchip_clk_branch rk3399_clk_branches[] __initdata = { RK3399_CLKSEL_CON(50), 8, 2, MFLAGS, 0, 8, DFLAGS, RK3399_CLKGATE_CON(10), 13, GFLAGS), - COMPOSITE_FRACMUX_NOGATE(0, "dclk_vop1_frac", "dclk_vop1_div", CLK_SET_RATE_PARENT, + COMPOSITE_FRACMUX_NOGATE(0, "dclk_vop1_frac", "dclk_vop1_div", 0, RK3399_CLKSEL_CON(107), 0, &rk3399_dclk_vop1_fracmux), @@ -1312,7 +1312,7 @@ static struct rockchip_clk_branch rk3399_clk_branches[] __initdata = { /* testout */ MUX(0, "clk_test_pre", mux_pll_src_cpll_gpll_p, CLK_SET_RATE_PARENT, RK3399_CLKSEL_CON(58), 7, 1, MFLAGS), - COMPOSITE_FRAC(0, "clk_test_frac", "clk_test_pre", CLK_SET_RATE_PARENT, + COMPOSITE_FRAC(0, "clk_test_frac", "clk_test_pre", 0, RK3399_CLKSEL_CON(105), 0, RK3399_CLKGATE_CON(13), 9, GFLAGS), @@ -1417,7 +1417,7 @@ static struct rockchip_clk_branch rk3399_clk_pmu_branches[] __initdata = { RK3399_PMU_CLKSEL_CON(1), 13, 1, MFLAGS, 8, 5, DFLAGS, RK3399_PMU_CLKGATE_CON(0), 8, GFLAGS), - COMPOSITE_FRACMUX_NOGATE(0, "clk_wifi_frac", "clk_wifi_div", CLK_SET_RATE_PARENT, + COMPOSITE_FRACMUX_NOGATE(0, "clk_wifi_frac", "clk_wifi_div", 0, RK3399_PMU_CLKSEL_CON(7), 0, &rk3399_pmuclk_wifi_fracmux), @@ -1445,7 +1445,7 @@ static struct rockchip_clk_branch rk3399_clk_pmu_branches[] __initdata = { RK3399_PMU_CLKSEL_CON(5), 10, 1, MFLAGS, 0, 7, DFLAGS, RK3399_PMU_CLKGATE_CON(0), 5, GFLAGS), - COMPOSITE_FRACMUX(0, "clk_uart4_frac", "clk_uart4_div", CLK_SET_RATE_PARENT, + COMPOSITE_FRACMUX(0, "clk_uart4_frac", "clk_uart4_div", 0, RK3399_PMU_CLKSEL_CON(6), 0, RK3399_PMU_CLKGATE_CON(0), 6, GFLAGS, &rk3399_uart4_pmu_fracmux), -- 1.9.1 ^ permalink raw reply related [flat|nested] 16+ messages in thread
* [v2 PATCH 1/3] clk: rockchip: Fractional dividers can't set parent rates @ 2016-09-02 3:26 ` Chris Zhong 0 siblings, 0 replies; 16+ messages in thread From: Chris Zhong @ 2016-09-02 3:26 UTC (permalink / raw) To: linux-arm-kernel From: Douglas Anderson <dianders@chromium.org> Currently the fractional divider clock time can't handle the CLK_SET_RATE_PARENT flag. This is because, unlike normal dividers, there is no clk_divider_bestdiv() function to try speeding up the parent to see if it helps things. Eventually someone could try to figure out how to make fractional dividers able to use CLK_SET_RATE_PARENT, but until they do let's not confuse the common clock framework (and anyone using it) by setting the flag. Signed-off-by: Douglas Anderson <dianders@chromium.org> Signed-off-by: Chris Zhong <zyw@rock-chips.com> --- drivers/clk/rockchip/clk-rk3399.c | 26 +++++++++++++------------- 1 file changed, 13 insertions(+), 13 deletions(-) diff --git a/drivers/clk/rockchip/clk-rk3399.c b/drivers/clk/rockchip/clk-rk3399.c index ea32b7e..59417c5 100644 --- a/drivers/clk/rockchip/clk-rk3399.c +++ b/drivers/clk/rockchip/clk-rk3399.c @@ -585,7 +585,7 @@ static struct rockchip_clk_branch rk3399_clk_branches[] __initdata = { COMPOSITE(0, "clk_spdif_div", mux_pll_src_cpll_gpll_p, 0, RK3399_CLKSEL_CON(32), 7, 1, MFLAGS, 0, 7, DFLAGS, RK3399_CLKGATE_CON(8), 13, GFLAGS), - COMPOSITE_FRACMUX(0, "clk_spdif_frac", "clk_spdif_div", CLK_SET_RATE_PARENT, + COMPOSITE_FRACMUX(0, "clk_spdif_frac", "clk_spdif_div", 0, RK3399_CLKSEL_CON(99), 0, RK3399_CLKGATE_CON(8), 14, GFLAGS, &rk3399_spdif_fracmux), @@ -599,7 +599,7 @@ static struct rockchip_clk_branch rk3399_clk_branches[] __initdata = { COMPOSITE(0, "clk_i2s0_div", mux_pll_src_cpll_gpll_p, 0, RK3399_CLKSEL_CON(28), 7, 1, MFLAGS, 0, 7, DFLAGS, RK3399_CLKGATE_CON(8), 3, GFLAGS), - COMPOSITE_FRACMUX(0, "clk_i2s0_frac", "clk_i2s0_div", CLK_SET_RATE_PARENT, + COMPOSITE_FRACMUX(0, "clk_i2s0_frac", "clk_i2s0_div", 0, RK3399_CLKSEL_CON(96), 0, RK3399_CLKGATE_CON(8), 4, GFLAGS, &rk3399_i2s0_fracmux), @@ -609,7 +609,7 @@ static struct rockchip_clk_branch rk3399_clk_branches[] __initdata = { COMPOSITE(0, "clk_i2s1_div", mux_pll_src_cpll_gpll_p, 0, RK3399_CLKSEL_CON(29), 7, 1, MFLAGS, 0, 7, DFLAGS, RK3399_CLKGATE_CON(8), 6, GFLAGS), - COMPOSITE_FRACMUX(0, "clk_i2s1_frac", "clk_i2s1_div", CLK_SET_RATE_PARENT, + COMPOSITE_FRACMUX(0, "clk_i2s1_frac", "clk_i2s1_div", 0, RK3399_CLKSEL_CON(97), 0, RK3399_CLKGATE_CON(8), 7, GFLAGS, &rk3399_i2s1_fracmux), @@ -619,7 +619,7 @@ static struct rockchip_clk_branch rk3399_clk_branches[] __initdata = { COMPOSITE(0, "clk_i2s2_div", mux_pll_src_cpll_gpll_p, 0, RK3399_CLKSEL_CON(30), 7, 1, MFLAGS, 0, 7, DFLAGS, RK3399_CLKGATE_CON(8), 9, GFLAGS), - COMPOSITE_FRACMUX(0, "clk_i2s2_frac", "clk_i2s2_div", CLK_SET_RATE_PARENT, + COMPOSITE_FRACMUX(0, "clk_i2s2_frac", "clk_i2s2_div", 0, RK3399_CLKSEL_CON(98), 0, RK3399_CLKGATE_CON(8), 10, GFLAGS, &rk3399_i2s2_fracmux), @@ -638,7 +638,7 @@ static struct rockchip_clk_branch rk3399_clk_branches[] __initdata = { COMPOSITE_NOMUX(0, "clk_uart0_div", "clk_uart0_src", 0, RK3399_CLKSEL_CON(33), 0, 7, DFLAGS, RK3399_CLKGATE_CON(9), 0, GFLAGS), - COMPOSITE_FRACMUX(0, "clk_uart0_frac", "clk_uart0_div", CLK_SET_RATE_PARENT, + COMPOSITE_FRACMUX(0, "clk_uart0_frac", "clk_uart0_div", 0, RK3399_CLKSEL_CON(100), 0, RK3399_CLKGATE_CON(9), 1, GFLAGS, &rk3399_uart0_fracmux), @@ -648,7 +648,7 @@ static struct rockchip_clk_branch rk3399_clk_branches[] __initdata = { COMPOSITE_NOMUX(0, "clk_uart1_div", "clk_uart_src", 0, RK3399_CLKSEL_CON(34), 0, 7, DFLAGS, RK3399_CLKGATE_CON(9), 2, GFLAGS), - COMPOSITE_FRACMUX(0, "clk_uart1_frac", "clk_uart1_div", CLK_SET_RATE_PARENT, + COMPOSITE_FRACMUX(0, "clk_uart1_frac", "clk_uart1_div", 0, RK3399_CLKSEL_CON(101), 0, RK3399_CLKGATE_CON(9), 3, GFLAGS, &rk3399_uart1_fracmux), @@ -656,7 +656,7 @@ static struct rockchip_clk_branch rk3399_clk_branches[] __initdata = { COMPOSITE_NOMUX(0, "clk_uart2_div", "clk_uart_src", 0, RK3399_CLKSEL_CON(35), 0, 7, DFLAGS, RK3399_CLKGATE_CON(9), 4, GFLAGS), - COMPOSITE_FRACMUX(0, "clk_uart2_frac", "clk_uart2_div", CLK_SET_RATE_PARENT, + COMPOSITE_FRACMUX(0, "clk_uart2_frac", "clk_uart2_div", 0, RK3399_CLKSEL_CON(102), 0, RK3399_CLKGATE_CON(9), 5, GFLAGS, &rk3399_uart2_fracmux), @@ -664,7 +664,7 @@ static struct rockchip_clk_branch rk3399_clk_branches[] __initdata = { COMPOSITE_NOMUX(0, "clk_uart3_div", "clk_uart_src", 0, RK3399_CLKSEL_CON(36), 0, 7, DFLAGS, RK3399_CLKGATE_CON(9), 6, GFLAGS), - COMPOSITE_FRACMUX(0, "clk_uart3_frac", "clk_uart3_div", CLK_SET_RATE_PARENT, + COMPOSITE_FRACMUX(0, "clk_uart3_frac", "clk_uart3_div", 0, RK3399_CLKSEL_CON(103), 0, RK3399_CLKGATE_CON(9), 7, GFLAGS, &rk3399_uart3_fracmux), @@ -1168,7 +1168,7 @@ static struct rockchip_clk_branch rk3399_clk_branches[] __initdata = { RK3399_CLKSEL_CON(49), 8, 2, MFLAGS, 0, 8, DFLAGS, RK3399_CLKGATE_CON(10), 12, GFLAGS), - COMPOSITE_FRACMUX_NOGATE(0, "dclk_vop0_frac", "dclk_vop0_div", CLK_SET_RATE_PARENT, + COMPOSITE_FRACMUX_NOGATE(0, "dclk_vop0_frac", "dclk_vop0_div", 0, RK3399_CLKSEL_CON(106), 0, &rk3399_dclk_vop0_fracmux), @@ -1198,7 +1198,7 @@ static struct rockchip_clk_branch rk3399_clk_branches[] __initdata = { RK3399_CLKSEL_CON(50), 8, 2, MFLAGS, 0, 8, DFLAGS, RK3399_CLKGATE_CON(10), 13, GFLAGS), - COMPOSITE_FRACMUX_NOGATE(0, "dclk_vop1_frac", "dclk_vop1_div", CLK_SET_RATE_PARENT, + COMPOSITE_FRACMUX_NOGATE(0, "dclk_vop1_frac", "dclk_vop1_div", 0, RK3399_CLKSEL_CON(107), 0, &rk3399_dclk_vop1_fracmux), @@ -1312,7 +1312,7 @@ static struct rockchip_clk_branch rk3399_clk_branches[] __initdata = { /* testout */ MUX(0, "clk_test_pre", mux_pll_src_cpll_gpll_p, CLK_SET_RATE_PARENT, RK3399_CLKSEL_CON(58), 7, 1, MFLAGS), - COMPOSITE_FRAC(0, "clk_test_frac", "clk_test_pre", CLK_SET_RATE_PARENT, + COMPOSITE_FRAC(0, "clk_test_frac", "clk_test_pre", 0, RK3399_CLKSEL_CON(105), 0, RK3399_CLKGATE_CON(13), 9, GFLAGS), @@ -1417,7 +1417,7 @@ static struct rockchip_clk_branch rk3399_clk_pmu_branches[] __initdata = { RK3399_PMU_CLKSEL_CON(1), 13, 1, MFLAGS, 8, 5, DFLAGS, RK3399_PMU_CLKGATE_CON(0), 8, GFLAGS), - COMPOSITE_FRACMUX_NOGATE(0, "clk_wifi_frac", "clk_wifi_div", CLK_SET_RATE_PARENT, + COMPOSITE_FRACMUX_NOGATE(0, "clk_wifi_frac", "clk_wifi_div", 0, RK3399_PMU_CLKSEL_CON(7), 0, &rk3399_pmuclk_wifi_fracmux), @@ -1445,7 +1445,7 @@ static struct rockchip_clk_branch rk3399_clk_pmu_branches[] __initdata = { RK3399_PMU_CLKSEL_CON(5), 10, 1, MFLAGS, 0, 7, DFLAGS, RK3399_PMU_CLKGATE_CON(0), 5, GFLAGS), - COMPOSITE_FRACMUX(0, "clk_uart4_frac", "clk_uart4_div", CLK_SET_RATE_PARENT, + COMPOSITE_FRACMUX(0, "clk_uart4_frac", "clk_uart4_div", 0, RK3399_PMU_CLKSEL_CON(6), 0, RK3399_PMU_CLKGATE_CON(0), 6, GFLAGS, &rk3399_uart4_pmu_fracmux), -- 1.9.1 ^ permalink raw reply related [flat|nested] 16+ messages in thread
* [v2 PATCH 2/3] clk: rockchip: add dclk_vop_frac ids for vop 2016-09-02 3:26 ` Chris Zhong (?) @ 2016-09-02 3:26 ` Chris Zhong 2016-09-02 20:43 ` Heiko Stübner [not found] ` <1472786785-2393-2-git-send-email-zyw-TNX95d0MmH7DzftRWevZcw@public.gmane.org> -1 siblings, 2 replies; 16+ messages in thread From: Chris Zhong @ 2016-09-02 3:26 UTC (permalink / raw) To: heiko, dianders Cc: linux-rockchip, zhengxing, ykk, Chris Zhong, devicetree, Jianqun Xu, linux-kernel, Rob Herring, Mark Rutland, Lin Huang From: Yakir Yang <ykk@rock-chips.com> Export the dclk_vop_frac out, so we can set the dclk_vop as the child of dclk_vop_frac, and then we can start to take use of the fractional dividers. Signed-off-by: Xing Zheng <zhengxing@rock-chips.com> Signed-off-by: Yakir Yang <ykk@rock-chips.com> Signed-off-by: Chris Zhong <zyw@rock-chips.com> --- include/dt-bindings/clock/rk3399-cru.h | 2 ++ 1 file changed, 2 insertions(+) diff --git a/include/dt-bindings/clock/rk3399-cru.h b/include/dt-bindings/clock/rk3399-cru.h index ce5f3e9..220a60f 100644 --- a/include/dt-bindings/clock/rk3399-cru.h +++ b/include/dt-bindings/clock/rk3399-cru.h @@ -138,6 +138,8 @@ #define DCLK_VOP0_DIV 182 #define DCLK_VOP1_DIV 183 #define DCLK_M0_PERILP 184 +#define DCLK_VOP0_FRAC 185 +#define DCLK_VOP1_FRAC 186 #define FCLK_CM0S 190 -- 1.9.1 ^ permalink raw reply related [flat|nested] 16+ messages in thread
* Re: [v2 PATCH 2/3] clk: rockchip: add dclk_vop_frac ids for vop 2016-09-02 3:26 ` [v2 PATCH 2/3] clk: rockchip: add dclk_vop_frac ids for vop Chris Zhong @ 2016-09-02 20:43 ` Heiko Stübner 2016-09-02 20:58 ` Chris Zhong [not found] ` <1472786785-2393-2-git-send-email-zyw-TNX95d0MmH7DzftRWevZcw@public.gmane.org> 1 sibling, 1 reply; 16+ messages in thread From: Heiko Stübner @ 2016-09-02 20:43 UTC (permalink / raw) To: Chris Zhong Cc: dianders, linux-rockchip, zhengxing, ykk, devicetree, Jianqun Xu, linux-kernel, Rob Herring, Mark Rutland, Lin Huang Am Donnerstag, 1. September 2016, 20:26:24 schrieb Chris Zhong: > From: Yakir Yang <ykk@rock-chips.com> > > Export the dclk_vop_frac out, so we can set the dclk_vop as the > child of dclk_vop_frac, and then we can start to take use of > the fractional dividers. > > Signed-off-by: Xing Zheng <zhengxing@rock-chips.com> > Signed-off-by: Yakir Yang <ykk@rock-chips.com> > Signed-off-by: Chris Zhong <zyw@rock-chips.com> Yakir is listed as author above, what relationship does Xing have to this patch and the 3rd one? ^ permalink raw reply [flat|nested] 16+ messages in thread
* Re: [v2 PATCH 2/3] clk: rockchip: add dclk_vop_frac ids for vop 2016-09-02 20:43 ` Heiko Stübner @ 2016-09-02 20:58 ` Chris Zhong 0 siblings, 0 replies; 16+ messages in thread From: Chris Zhong @ 2016-09-02 20:58 UTC (permalink / raw) To: Heiko Stübner Cc: Mark Rutland, devicetree-u79uwXL29TY76Z2rM5mHXA, Lin Huang, zhengxing-TNX95d0MmH7DzftRWevZcw, dianders-F7+t8E8rja9g9hUCZPvPmw, linux-kernel-u79uwXL29TY76Z2rM5mHXA, linux-rockchip-IAPFreCvJWM7uuMidbF8XUB+6BGkLq7r, Rob Herring, ykk-TNX95d0MmH7DzftRWevZcw, Jianqun Xu Hi Heiko On 09/02/2016 01:43 PM, Heiko Stübner wrote: > Am Donnerstag, 1. September 2016, 20:26:24 schrieb Chris Zhong: >> From: Yakir Yang <ykk-TNX95d0MmH7DzftRWevZcw@public.gmane.org> >> >> Export the dclk_vop_frac out, so we can set the dclk_vop as the >> child of dclk_vop_frac, and then we can start to take use of >> the fractional dividers. >> >> Signed-off-by: Xing Zheng <zhengxing-TNX95d0MmH7DzftRWevZcw@public.gmane.org> >> Signed-off-by: Yakir Yang <ykk-TNX95d0MmH7DzftRWevZcw@public.gmane.org> >> Signed-off-by: Chris Zhong <zyw-TNX95d0MmH7DzftRWevZcw@public.gmane.org> > Yakir is listed as author above, what relationship does Xing have to this > patch and the 3rd one? > > Yakir is the author of the [2/3] and [3/3] patch, and Doug is the author of [1/3] The others are committer, and these tags should be removed. ^ permalink raw reply [flat|nested] 16+ messages in thread
* Re: [v2 PATCH 2/3] clk: rockchip: add dclk_vop_frac ids for vop @ 2016-09-02 20:58 ` Chris Zhong 0 siblings, 0 replies; 16+ messages in thread From: Chris Zhong @ 2016-09-02 20:58 UTC (permalink / raw) To: Heiko Stübner Cc: dianders, linux-rockchip, zhengxing, ykk, devicetree, Jianqun Xu, linux-kernel, Rob Herring, Mark Rutland, Lin Huang Hi Heiko On 09/02/2016 01:43 PM, Heiko Stübner wrote: > Am Donnerstag, 1. September 2016, 20:26:24 schrieb Chris Zhong: >> From: Yakir Yang <ykk@rock-chips.com> >> >> Export the dclk_vop_frac out, so we can set the dclk_vop as the >> child of dclk_vop_frac, and then we can start to take use of >> the fractional dividers. >> >> Signed-off-by: Xing Zheng <zhengxing@rock-chips.com> >> Signed-off-by: Yakir Yang <ykk@rock-chips.com> >> Signed-off-by: Chris Zhong <zyw@rock-chips.com> > Yakir is listed as author above, what relationship does Xing have to this > patch and the 3rd one? > > Yakir is the author of the [2/3] and [3/3] patch, and Doug is the author of [1/3] The others are committer, and these tags should be removed. ^ permalink raw reply [flat|nested] 16+ messages in thread
[parent not found: <b2d57b28-19dc-c55c-39b7-4b01f9365967-TNX95d0MmH7DzftRWevZcw@public.gmane.org>]
* Re: [v2 PATCH 2/3] clk: rockchip: add dclk_vop_frac ids for vop 2016-09-02 20:58 ` Chris Zhong @ 2016-09-02 21:14 ` Heiko Stübner -1 siblings, 0 replies; 16+ messages in thread From: Heiko Stübner @ 2016-09-02 21:14 UTC (permalink / raw) To: Chris Zhong Cc: dianders-F7+t8E8rja9g9hUCZPvPmw, linux-rockchip-IAPFreCvJWM7uuMidbF8XUB+6BGkLq7r, zhengxing-TNX95d0MmH7DzftRWevZcw, ykk-TNX95d0MmH7DzftRWevZcw, devicetree-u79uwXL29TY76Z2rM5mHXA, Jianqun Xu, linux-kernel-u79uwXL29TY76Z2rM5mHXA, Rob Herring, Mark Rutland, Lin Huang Am Freitag, 2. September 2016, 13:58:19 schrieb Chris Zhong: > Hi Heiko > > On 09/02/2016 01:43 PM, Heiko Stübner wrote: > > Am Donnerstag, 1. September 2016, 20:26:24 schrieb Chris Zhong: > >> From: Yakir Yang <ykk-TNX95d0MmH7DzftRWevZcw@public.gmane.org> > >> > >> Export the dclk_vop_frac out, so we can set the dclk_vop as the > >> child of dclk_vop_frac, and then we can start to take use of > >> the fractional dividers. > >> > >> Signed-off-by: Xing Zheng <zhengxing-TNX95d0MmH7DzftRWevZcw@public.gmane.org> > >> Signed-off-by: Yakir Yang <ykk-TNX95d0MmH7DzftRWevZcw@public.gmane.org> > >> Signed-off-by: Chris Zhong <zyw-TNX95d0MmH7DzftRWevZcw@public.gmane.org> > > > > Yakir is listed as author above, what relationship does Xing have to this > > patch and the 3rd one? > > Yakir is the author of the [2/3] and [3/3] patch, and Doug is the author > of [1/3] > The others are committer, and these tags should be removed. not all of them ... i.e. your Signed-off needs to stay in, as you are the one sending in this set of patches ... I'll drop the Signed-off from Xing though. Thanks for clarifying Heiko -- To unsubscribe from this list: send the line "unsubscribe devicetree" in the body of a message to majordomo-u79uwXL29TY76Z2rM5mHXA@public.gmane.org More majordomo info at http://vger.kernel.org/majordomo-info.html ^ permalink raw reply [flat|nested] 16+ messages in thread
* Re: [v2 PATCH 2/3] clk: rockchip: add dclk_vop_frac ids for vop @ 2016-09-02 21:14 ` Heiko Stübner 0 siblings, 0 replies; 16+ messages in thread From: Heiko Stübner @ 2016-09-02 21:14 UTC (permalink / raw) To: Chris Zhong Cc: dianders, linux-rockchip, zhengxing, ykk, devicetree, Jianqun Xu, linux-kernel, Rob Herring, Mark Rutland, Lin Huang Am Freitag, 2. September 2016, 13:58:19 schrieb Chris Zhong: > Hi Heiko > > On 09/02/2016 01:43 PM, Heiko Stübner wrote: > > Am Donnerstag, 1. September 2016, 20:26:24 schrieb Chris Zhong: > >> From: Yakir Yang <ykk@rock-chips.com> > >> > >> Export the dclk_vop_frac out, so we can set the dclk_vop as the > >> child of dclk_vop_frac, and then we can start to take use of > >> the fractional dividers. > >> > >> Signed-off-by: Xing Zheng <zhengxing@rock-chips.com> > >> Signed-off-by: Yakir Yang <ykk@rock-chips.com> > >> Signed-off-by: Chris Zhong <zyw@rock-chips.com> > > > > Yakir is listed as author above, what relationship does Xing have to this > > patch and the 3rd one? > > Yakir is the author of the [2/3] and [3/3] patch, and Doug is the author > of [1/3] > The others are committer, and these tags should be removed. not all of them ... i.e. your Signed-off needs to stay in, as you are the one sending in this set of patches ... I'll drop the Signed-off from Xing though. Thanks for clarifying Heiko ^ permalink raw reply [flat|nested] 16+ messages in thread
[parent not found: <1472786785-2393-2-git-send-email-zyw-TNX95d0MmH7DzftRWevZcw@public.gmane.org>]
* Re: [v2 PATCH 2/3] clk: rockchip: add dclk_vop_frac ids for vop 2016-09-02 3:26 ` [v2 PATCH 2/3] clk: rockchip: add dclk_vop_frac ids for vop Chris Zhong @ 2016-09-04 21:50 ` Heiko Stuebner [not found] ` <1472786785-2393-2-git-send-email-zyw-TNX95d0MmH7DzftRWevZcw@public.gmane.org> 1 sibling, 0 replies; 16+ messages in thread From: Heiko Stuebner @ 2016-09-04 21:50 UTC (permalink / raw) To: Chris Zhong Cc: dianders-F7+t8E8rja9g9hUCZPvPmw, linux-rockchip-IAPFreCvJWM7uuMidbF8XUB+6BGkLq7r, zhengxing-TNX95d0MmH7DzftRWevZcw, ykk-TNX95d0MmH7DzftRWevZcw, devicetree-u79uwXL29TY76Z2rM5mHXA, Jianqun Xu, linux-kernel-u79uwXL29TY76Z2rM5mHXA, Rob Herring, Mark Rutland, Lin Huang Am Donnerstag, 1. September 2016, 20:26:24 CEST schrieb Chris Zhong: > From: Yakir Yang <ykk-TNX95d0MmH7DzftRWevZcw@public.gmane.org> > > Export the dclk_vop_frac out, so we can set the dclk_vop as the > child of dclk_vop_frac, and then we can start to take use of > the fractional dividers. > > Signed-off-by: Xing Zheng <zhengxing-TNX95d0MmH7DzftRWevZcw@public.gmane.org> > Signed-off-by: Yakir Yang <ykk-TNX95d0MmH7DzftRWevZcw@public.gmane.org> > Signed-off-by: Chris Zhong <zyw-TNX95d0MmH7DzftRWevZcw@public.gmane.org> applied to my clk-branch for 4.9 -- To unsubscribe from this list: send the line "unsubscribe devicetree" in the body of a message to majordomo-u79uwXL29TY76Z2rM5mHXA@public.gmane.org More majordomo info at http://vger.kernel.org/majordomo-info.html ^ permalink raw reply [flat|nested] 16+ messages in thread
* Re: [v2 PATCH 2/3] clk: rockchip: add dclk_vop_frac ids for vop @ 2016-09-04 21:50 ` Heiko Stuebner 0 siblings, 0 replies; 16+ messages in thread From: Heiko Stuebner @ 2016-09-04 21:50 UTC (permalink / raw) To: Chris Zhong Cc: dianders, linux-rockchip, zhengxing, ykk, devicetree, Jianqun Xu, linux-kernel, Rob Herring, Mark Rutland, Lin Huang Am Donnerstag, 1. September 2016, 20:26:24 CEST schrieb Chris Zhong: > From: Yakir Yang <ykk@rock-chips.com> > > Export the dclk_vop_frac out, so we can set the dclk_vop as the > child of dclk_vop_frac, and then we can start to take use of > the fractional dividers. > > Signed-off-by: Xing Zheng <zhengxing@rock-chips.com> > Signed-off-by: Yakir Yang <ykk@rock-chips.com> > Signed-off-by: Chris Zhong <zyw@rock-chips.com> applied to my clk-branch for 4.9 ^ permalink raw reply [flat|nested] 16+ messages in thread
* [v2 PATCH 3/3] clk: rockchip: use the dclk_vop_frac clock ids 2016-09-02 3:26 ` Chris Zhong @ 2016-09-02 3:26 ` Chris Zhong -1 siblings, 0 replies; 16+ messages in thread From: Chris Zhong @ 2016-09-02 3:26 UTC (permalink / raw) To: heiko, dianders Cc: linux-rockchip, zhengxing, ykk, Chris Zhong, Michael Turquette, Stephen Boyd, linux-kernel, linux-clk, linux-arm-kernel From: Yakir Yang <ykk@rock-chips.com> Export the dclk_vop_frac out, so we can set the dclk_vop as the child of dclk_vop_frac, and then we can start to take use of the fractional dividers. Signed-off-by: Xing Zheng <zhengxing@rock-chips.com> Signed-off-by: Yakir Yang <ykk@rock-chips.com> Signed-off-by: Chris Zhong <zyw@rock-chips.com> --- drivers/clk/rockchip/clk-rk3399.c | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/drivers/clk/rockchip/clk-rk3399.c b/drivers/clk/rockchip/clk-rk3399.c index 59417c5..2c7cba7 100644 --- a/drivers/clk/rockchip/clk-rk3399.c +++ b/drivers/clk/rockchip/clk-rk3399.c @@ -1168,7 +1168,7 @@ static struct rockchip_clk_branch rk3399_clk_branches[] __initdata = { RK3399_CLKSEL_CON(49), 8, 2, MFLAGS, 0, 8, DFLAGS, RK3399_CLKGATE_CON(10), 12, GFLAGS), - COMPOSITE_FRACMUX_NOGATE(0, "dclk_vop0_frac", "dclk_vop0_div", 0, + COMPOSITE_FRACMUX_NOGATE(DCLK_VOP0_FRAC, "dclk_vop0_frac", "dclk_vop0_div", 0, RK3399_CLKSEL_CON(106), 0, &rk3399_dclk_vop0_fracmux), @@ -1198,7 +1198,7 @@ static struct rockchip_clk_branch rk3399_clk_branches[] __initdata = { RK3399_CLKSEL_CON(50), 8, 2, MFLAGS, 0, 8, DFLAGS, RK3399_CLKGATE_CON(10), 13, GFLAGS), - COMPOSITE_FRACMUX_NOGATE(0, "dclk_vop1_frac", "dclk_vop1_div", 0, + COMPOSITE_FRACMUX_NOGATE(DCLK_VOP1_FRAC, "dclk_vop1_frac", "dclk_vop1_div", 0, RK3399_CLKSEL_CON(107), 0, &rk3399_dclk_vop1_fracmux), -- 1.9.1 ^ permalink raw reply related [flat|nested] 16+ messages in thread
* [v2 PATCH 3/3] clk: rockchip: use the dclk_vop_frac clock ids @ 2016-09-02 3:26 ` Chris Zhong 0 siblings, 0 replies; 16+ messages in thread From: Chris Zhong @ 2016-09-02 3:26 UTC (permalink / raw) To: linux-arm-kernel From: Yakir Yang <ykk@rock-chips.com> Export the dclk_vop_frac out, so we can set the dclk_vop as the child of dclk_vop_frac, and then we can start to take use of the fractional dividers. Signed-off-by: Xing Zheng <zhengxing@rock-chips.com> Signed-off-by: Yakir Yang <ykk@rock-chips.com> Signed-off-by: Chris Zhong <zyw@rock-chips.com> --- drivers/clk/rockchip/clk-rk3399.c | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/drivers/clk/rockchip/clk-rk3399.c b/drivers/clk/rockchip/clk-rk3399.c index 59417c5..2c7cba7 100644 --- a/drivers/clk/rockchip/clk-rk3399.c +++ b/drivers/clk/rockchip/clk-rk3399.c @@ -1168,7 +1168,7 @@ static struct rockchip_clk_branch rk3399_clk_branches[] __initdata = { RK3399_CLKSEL_CON(49), 8, 2, MFLAGS, 0, 8, DFLAGS, RK3399_CLKGATE_CON(10), 12, GFLAGS), - COMPOSITE_FRACMUX_NOGATE(0, "dclk_vop0_frac", "dclk_vop0_div", 0, + COMPOSITE_FRACMUX_NOGATE(DCLK_VOP0_FRAC, "dclk_vop0_frac", "dclk_vop0_div", 0, RK3399_CLKSEL_CON(106), 0, &rk3399_dclk_vop0_fracmux), @@ -1198,7 +1198,7 @@ static struct rockchip_clk_branch rk3399_clk_branches[] __initdata = { RK3399_CLKSEL_CON(50), 8, 2, MFLAGS, 0, 8, DFLAGS, RK3399_CLKGATE_CON(10), 13, GFLAGS), - COMPOSITE_FRACMUX_NOGATE(0, "dclk_vop1_frac", "dclk_vop1_div", 0, + COMPOSITE_FRACMUX_NOGATE(DCLK_VOP1_FRAC, "dclk_vop1_frac", "dclk_vop1_div", 0, RK3399_CLKSEL_CON(107), 0, &rk3399_dclk_vop1_fracmux), -- 1.9.1 ^ permalink raw reply related [flat|nested] 16+ messages in thread
* Re: [v2 PATCH 3/3] clk: rockchip: use the dclk_vop_frac clock ids 2016-09-02 3:26 ` Chris Zhong @ 2016-09-04 21:51 ` Heiko Stuebner -1 siblings, 0 replies; 16+ messages in thread From: Heiko Stuebner @ 2016-09-04 21:51 UTC (permalink / raw) To: Chris Zhong Cc: dianders, linux-rockchip, zhengxing, ykk, Michael Turquette, Stephen Boyd, linux-kernel, linux-clk, linux-arm-kernel Am Donnerstag, 1. September 2016, 20:26:25 CEST schrieb Chris Zhong: > From: Yakir Yang <ykk@rock-chips.com> > > Export the dclk_vop_frac out, so we can set the dclk_vop as the > child of dclk_vop_frac, and then we can start to take use of > the fractional dividers. > > Signed-off-by: Xing Zheng <zhengxing@rock-chips.com> > Signed-off-by: Yakir Yang <ykk@rock-chips.com> > Signed-off-by: Chris Zhong <zyw@rock-chips.com> applied to my clk-branch for 4.9 ^ permalink raw reply [flat|nested] 16+ messages in thread
* [v2 PATCH 3/3] clk: rockchip: use the dclk_vop_frac clock ids @ 2016-09-04 21:51 ` Heiko Stuebner 0 siblings, 0 replies; 16+ messages in thread From: Heiko Stuebner @ 2016-09-04 21:51 UTC (permalink / raw) To: linux-arm-kernel Am Donnerstag, 1. September 2016, 20:26:25 CEST schrieb Chris Zhong: > From: Yakir Yang <ykk@rock-chips.com> > > Export the dclk_vop_frac out, so we can set the dclk_vop as the > child of dclk_vop_frac, and then we can start to take use of > the fractional dividers. > > Signed-off-by: Xing Zheng <zhengxing@rock-chips.com> > Signed-off-by: Yakir Yang <ykk@rock-chips.com> > Signed-off-by: Chris Zhong <zyw@rock-chips.com> applied to my clk-branch for 4.9 ^ permalink raw reply [flat|nested] 16+ messages in thread
* Re: [v2 PATCH 1/3] clk: rockchip: Fractional dividers can't set parent rates 2016-09-02 3:26 ` Chris Zhong @ 2016-09-04 21:50 ` Heiko Stuebner -1 siblings, 0 replies; 16+ messages in thread From: Heiko Stuebner @ 2016-09-04 21:50 UTC (permalink / raw) To: Chris Zhong Cc: dianders, linux-rockchip, zhengxing, ykk, Michael Turquette, Stephen Boyd, linux-kernel, linux-clk, linux-arm-kernel Am Donnerstag, 1. September 2016, 20:26:23 CEST schrieb Chris Zhong: > From: Douglas Anderson <dianders@chromium.org> > > Currently the fractional divider clock time can't handle the > CLK_SET_RATE_PARENT flag. This is because, unlike normal dividers, > there is no clk_divider_bestdiv() function to try speeding up the parent > to see if it helps things. > > Eventually someone could try to figure out how to make fractional > dividers able to use CLK_SET_RATE_PARENT, but until they do let's not > confuse the common clock framework (and anyone using it) by setting the > flag. > > Signed-off-by: Douglas Anderson <dianders@chromium.org> > Signed-off-by: Chris Zhong <zyw@rock-chips.com> applied to my clk-branch for 4.9, after changing the subject to clk: rockchip: drop CLK_SET_RATE_PARENT from rk3399 fractional dividers Heiko ^ permalink raw reply [flat|nested] 16+ messages in thread
* [v2 PATCH 1/3] clk: rockchip: Fractional dividers can't set parent rates @ 2016-09-04 21:50 ` Heiko Stuebner 0 siblings, 0 replies; 16+ messages in thread From: Heiko Stuebner @ 2016-09-04 21:50 UTC (permalink / raw) To: linux-arm-kernel Am Donnerstag, 1. September 2016, 20:26:23 CEST schrieb Chris Zhong: > From: Douglas Anderson <dianders@chromium.org> > > Currently the fractional divider clock time can't handle the > CLK_SET_RATE_PARENT flag. This is because, unlike normal dividers, > there is no clk_divider_bestdiv() function to try speeding up the parent > to see if it helps things. > > Eventually someone could try to figure out how to make fractional > dividers able to use CLK_SET_RATE_PARENT, but until they do let's not > confuse the common clock framework (and anyone using it) by setting the > flag. > > Signed-off-by: Douglas Anderson <dianders@chromium.org> > Signed-off-by: Chris Zhong <zyw@rock-chips.com> applied to my clk-branch for 4.9, after changing the subject to clk: rockchip: drop CLK_SET_RATE_PARENT from rk3399 fractional dividers Heiko ^ permalink raw reply [flat|nested] 16+ messages in thread
end of thread, other threads:[~2016-09-04 21:51 UTC | newest]
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2016-09-02 3:26 [v2 PATCH 1/3] clk: rockchip: Fractional dividers can't set parent rates Chris Zhong
2016-09-02 3:26 ` Chris Zhong
2016-09-02 3:26 ` [v2 PATCH 2/3] clk: rockchip: add dclk_vop_frac ids for vop Chris Zhong
2016-09-02 20:43 ` Heiko Stübner
2016-09-02 20:58 ` Chris Zhong
2016-09-02 20:58 ` Chris Zhong
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2016-09-02 21:14 ` Heiko Stübner
2016-09-02 21:14 ` Heiko Stübner
[not found] ` <1472786785-2393-2-git-send-email-zyw-TNX95d0MmH7DzftRWevZcw@public.gmane.org>
2016-09-04 21:50 ` Heiko Stuebner
2016-09-04 21:50 ` Heiko Stuebner
2016-09-02 3:26 ` [v2 PATCH 3/3] clk: rockchip: use the dclk_vop_frac clock ids Chris Zhong
2016-09-02 3:26 ` Chris Zhong
2016-09-04 21:51 ` Heiko Stuebner
2016-09-04 21:51 ` Heiko Stuebner
2016-09-04 21:50 ` [v2 PATCH 1/3] clk: rockchip: Fractional dividers can't set parent rates Heiko Stuebner
2016-09-04 21:50 ` Heiko Stuebner
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