* [dpdk-dev] [PATCH v2 01/12] crypto/octeontx2: add PMD skeleton
2019-10-13 12:39 ` [dpdk-dev] [PATCH v2 00/12] " Anoob Joseph
@ 2019-10-13 12:39 ` Anoob Joseph
2019-10-15 7:56 ` Akhil Goyal
2019-10-13 12:39 ` [dpdk-dev] [PATCH v2 02/12] crypto/octeontx2: add device init sequence in probe Anoob Joseph
` (12 subsequent siblings)
13 siblings, 1 reply; 53+ messages in thread
From: Anoob Joseph @ 2019-10-13 12:39 UTC (permalink / raw)
To: Akhil Goyal, Pablo de Lara
Cc: Anoob Joseph, Fiona Trahe, Jerin Jacob, Narayana Prasad,
Shally Verma, Ankur Dwivedi, Kanaka Durga Kotamarthy, Sunila Sahu,
Tejasree Kondoj, dev
Adding OCTEON TX2 crypto PMD skeleton. Enabling the driver by default
in common_base.
Signed-off-by: Ankur Dwivedi <adwivedi@marvell.com>
Signed-off-by: Anoob Joseph <anoobj@marvell.com>
Signed-off-by: Tejasree Kondoj <ktejasree@marvell.com>
---
MAINTAINERS | 7 ++
config/common_base | 5 +
doc/guides/cryptodevs/features/octeontx2.ini | 8 ++
doc/guides/cryptodevs/index.rst | 1 +
doc/guides/cryptodevs/octeontx2.rst | 93 +++++++++++++++++
doc/guides/platform/octeontx2.rst | 3 +
doc/guides/rel_notes/release_19_11.rst | 6 ++
drivers/common/Makefile | 5 +-
drivers/crypto/Makefile | 1 +
drivers/crypto/meson.build | 21 +++-
drivers/crypto/octeontx2/Makefile | 37 +++++++
drivers/crypto/octeontx2/meson.build | 29 ++++++
drivers/crypto/octeontx2/otx2_cryptodev.c | 111 +++++++++++++++++++++
drivers/crypto/octeontx2/otx2_cryptodev.h | 29 ++++++
drivers/crypto/octeontx2/otx2_cryptodev_ops.c | 27 +++++
drivers/crypto/octeontx2/otx2_cryptodev_ops.h | 12 +++
.../octeontx2/rte_pmd_octeontx2_crypto_version.map | 4 +
mk/rte.app.mk | 6 +-
18 files changed, 400 insertions(+), 5 deletions(-)
create mode 100644 doc/guides/cryptodevs/features/octeontx2.ini
create mode 100644 doc/guides/cryptodevs/octeontx2.rst
create mode 100644 drivers/crypto/octeontx2/Makefile
create mode 100644 drivers/crypto/octeontx2/meson.build
create mode 100644 drivers/crypto/octeontx2/otx2_cryptodev.c
create mode 100644 drivers/crypto/octeontx2/otx2_cryptodev.h
create mode 100644 drivers/crypto/octeontx2/otx2_cryptodev_ops.c
create mode 100644 drivers/crypto/octeontx2/otx2_cryptodev_ops.h
create mode 100644 drivers/crypto/octeontx2/rte_pmd_octeontx2_crypto_version.map
diff --git a/MAINTAINERS b/MAINTAINERS
index 61f7911..d9977e6 100644
--- a/MAINTAINERS
+++ b/MAINTAINERS
@@ -970,6 +970,13 @@ F: drivers/crypto/nitrox/
F: doc/guides/cryptodevs/nitrox.rst
F: doc/guides/cryptodevs/features/nitrox.ini
+Marvell OCTEON TX2 crypto
+M: Ankur Dwivedi <adwivedi@marvell.com>
+M: Anoob Joseph <anoobj@marvell.com>
+F: drivers/crypto/octeontx2/
+F: doc/guides/cryptodevs/octeontx2.rst
+F: doc/guides/cryptodevs/features/octeontx2.ini
+
Null Crypto
M: Declan Doherty <declan.doherty@intel.com>
F: drivers/crypto/null/
diff --git a/config/common_base b/config/common_base
index 19a4523..8ae5ed4 100644
--- a/config/common_base
+++ b/config/common_base
@@ -593,6 +593,11 @@ CONFIG_RTE_LIBRTE_DPAA_MAX_CRYPTODEV=4
CONFIG_RTE_LIBRTE_PMD_OCTEONTX_CRYPTO=y
#
+# Compile PMD for Marvell OCTEON TX2 crypto device
+#
+CONFIG_RTE_LIBRTE_PMD_OCTEONTX2_CRYPTO=y
+
+#
# Compile PMD for QuickAssist based devices - see docs for details
#
CONFIG_RTE_LIBRTE_PMD_QAT=y
diff --git a/doc/guides/cryptodevs/features/octeontx2.ini b/doc/guides/cryptodevs/features/octeontx2.ini
new file mode 100644
index 0000000..35c9bee
--- /dev/null
+++ b/doc/guides/cryptodevs/features/octeontx2.ini
@@ -0,0 +1,8 @@
+;
+; Supported features of the 'octeontx2' crypto driver.
+;
+; Refer to default.ini for the full list of available PMD features.
+;
+[Features]
+Symmetric crypto = Y
+HW Accelerated = Y
diff --git a/doc/guides/cryptodevs/index.rst b/doc/guides/cryptodevs/index.rst
index d1e0d32..a67ed5a 100644
--- a/doc/guides/cryptodevs/index.rst
+++ b/doc/guides/cryptodevs/index.rst
@@ -19,6 +19,7 @@ Crypto Device Drivers
dpaa_sec
kasumi
octeontx
+ octeontx2
openssl
mvsam
nitrox
diff --git a/doc/guides/cryptodevs/octeontx2.rst b/doc/guides/cryptodevs/octeontx2.rst
new file mode 100644
index 0000000..10f578a
--- /dev/null
+++ b/doc/guides/cryptodevs/octeontx2.rst
@@ -0,0 +1,93 @@
+.. SPDX-License-Identifier: BSD-3-Clause
+ Copyright(c) 2019 Marvell International Ltd.
+
+
+Marvell OCTEON TX2 Crypto Poll Mode Driver
+==========================================
+
+The OCTEON TX2 crypto poll mode driver provides support for offloading
+cryptographic operations to cryptographic accelerator units on the
+**OCTEON TX2** :sup:`®` family of processors (CN9XXX).
+
+More information about OCTEON TX2 SoCs may be obtained from `<https://www.marvell.com>`_
+
+Features
+--------
+
+The OCTEON TX2 crypto PMD has support for:
+
+Installation
+------------
+
+The OCTEON TX2 crypto PMD may be compiled natively on an OCTEON TX2 platform or
+cross-compiled on an x86 platform.
+
+Enable OCTEON TX2 crypto PMD in your config file:
+
+* ``CONFIG_RTE_LIBRTE_PMD_OCTEONTX2_CRYPTO=y``
+
+Refer to :doc:`../platform/octeontx2` for instructions to build your DPDK
+application.
+
+.. note::
+
+ The OCTEON TX2 crypto PMD uses services from the kernel mode OCTEON TX2
+ crypto PF driver in linux. This driver is included in the OCTEON TX SDK.
+
+Initialization
+--------------
+
+List the CPT PF devices available on your OCTEON TX2 platform:
+
+.. code-block:: console
+
+ lspci -d:a0fd
+
+``a0fd`` is the CPT PF device id. You should see output similar to:
+
+.. code-block:: console
+
+ 0002:10:00.0 Class 1080: Device 177d:a0fd
+
+Set ``sriov_numvfs`` on the CPT PF device, to create a VF:
+
+.. code-block:: console
+
+ echo 1 > /sys/bus/pci/drivers/octeontx2-cpt/0002:10:00.0/sriov_numvfs
+
+Bind the CPT VF device to the vfio_pci driver:
+
+.. code-block:: console
+
+ echo '177d a0fe' > /sys/bus/pci/drivers/vfio-pci/new_id
+ echo 0002:10:00.1 > /sys/bus/pci/devices/0002:10:00.1/driver/unbind
+ echo 0002:10:00.1 > /sys/bus/pci/drivers/vfio-pci/bind
+
+Another way to bind the VF would be to use the ``dpdk-devbind.py`` script:
+
+.. code-block:: console
+
+ cd <dpdk directory>
+ ./usertools/dpdk-devbind.py -u 0002:10:00.1
+ ./usertools/dpdk-devbind.py -b vfio-pci 0002:10.00.1
+
+.. note::
+
+ Ensure that sufficient huge pages are available for your application::
+
+ echo 8 > /sys/kernel/mm/hugepages/hugepages-524288kB/nr_hugepages
+
+ Refer to :ref:`linux_gsg_hugepages` for more details.
+
+Debugging Options
+-----------------
+
+.. _table_octeontx2_crypto_debug_options:
+
+.. table:: OCTEON TX2 crypto PMD debug options
+
+ +---+------------+-------------------------------------------------------+
+ | # | Component | EAL log command |
+ +===+============+=======================================================+
+ | 1 | CPT | --log-level='pmd\.crypto\.octeontx2,8' |
+ +---+------------+-------------------------------------------------------+
diff --git a/doc/guides/platform/octeontx2.rst b/doc/guides/platform/octeontx2.rst
index 4194a43..f06dc68 100644
--- a/doc/guides/platform/octeontx2.rst
+++ b/doc/guides/platform/octeontx2.rst
@@ -132,6 +132,9 @@ This section lists dataplane H/W block(s) available in OCTEON TX2 SoC.
#. **DMA Rawdev Driver**
See :doc:`../rawdevs/octeontx2_dma` for DMA driver information.
+#. **Crypto Device Driver**
+ See :doc:`../cryptodevs/octeontx2` for CPT crypto device driver information.
+
Procedure to Setup Platform
---------------------------
diff --git a/doc/guides/rel_notes/release_19_11.rst b/doc/guides/rel_notes/release_19_11.rst
index 02fc8fb..06394ac 100644
--- a/doc/guides/rel_notes/release_19_11.rst
+++ b/doc/guides/rel_notes/release_19_11.rst
@@ -85,6 +85,12 @@ New Features
Added stateful decompression support in the Intel QuickAssist Technology PMD.
Please note that stateful compression is not supported.
+* **Added Marvell OCTEON TX2 crypto PMD**
+
+ Added a new PMD driver for h/w crypto offload block on ``OCTEON TX2`` SoC.
+
+ See :doc:`../cryptodevs/octeontx2` for more details
+
Removed Items
-------------
diff --git a/drivers/common/Makefile b/drivers/common/Makefile
index bc6f972..1ff033b 100644
--- a/drivers/common/Makefile
+++ b/drivers/common/Makefile
@@ -4,7 +4,9 @@
include $(RTE_SDK)/mk/rte.vars.mk
-ifeq ($(CONFIG_RTE_LIBRTE_PMD_OCTEONTX_CRYPTO),y)
+CPT-y := $(CONFIG_RTE_LIBRTE_PMD_OCTEONTX_CRYPTO)
+CPT-y += $(CONFIG_RTE_LIBRTE_PMD_OCTEONTX2_CRYPTO)
+ifneq (,$(findstring y,$(CPT-y)))
DIRS-y += cpt
endif
@@ -12,6 +14,7 @@ ifeq ($(CONFIG_RTE_LIBRTE_PMD_OCTEONTX_SSOVF)$(CONFIG_RTE_LIBRTE_OCTEONTX_MEMPOO
DIRS-y += octeontx
endif
OCTEONTX2-y := $(CONFIG_RTE_LIBRTE_OCTEONTX2_MEMPOOL)
+OCTEONTX2-y += $(CONFIG_RTE_LIBRTE_PMD_OCTEONTX2_CRYPTO)
ifeq ($(findstring y,$(OCTEONTX2-y)),y)
DIRS-y += octeontx2
endif
diff --git a/drivers/crypto/Makefile b/drivers/crypto/Makefile
index 7129bcf..8b00857 100644
--- a/drivers/crypto/Makefile
+++ b/drivers/crypto/Makefile
@@ -8,6 +8,7 @@ DIRS-$(CONFIG_RTE_LIBRTE_PMD_AESNI_MB) += aesni_mb
DIRS-$(CONFIG_RTE_LIBRTE_PMD_ARMV8_CRYPTO) += armv8
DIRS-$(CONFIG_RTE_LIBRTE_PMD_CCP) += ccp
DIRS-$(CONFIG_RTE_LIBRTE_PMD_OCTEONTX_CRYPTO) += octeontx
+DIRS-$(CONFIG_RTE_LIBRTE_PMD_OCTEONTX2_CRYPTO) += octeontx2
DIRS-$(CONFIG_RTE_LIBRTE_PMD_OPENSSL) += openssl
DIRS-$(CONFIG_RTE_LIBRTE_PMD_CRYPTO_SCHEDULER) += scheduler
DIRS-$(CONFIG_RTE_LIBRTE_PMD_SNOW3G) += snow3g
diff --git a/drivers/crypto/meson.build b/drivers/crypto/meson.build
index 1a358ff..229debd 100644
--- a/drivers/crypto/meson.build
+++ b/drivers/crypto/meson.build
@@ -1,9 +1,24 @@
# SPDX-License-Identifier: BSD-3-Clause
# Copyright(c) 2017 Intel Corporation
-drivers = ['aesni_gcm', 'aesni_mb', 'caam_jr', 'ccp', 'dpaa_sec', 'dpaa2_sec',
- 'kasumi', 'mvsam', 'nitrox', 'null', 'octeontx', 'openssl', 'qat',
- 'scheduler', 'snow3g', 'virtio', 'zuc']
+drivers = ['aesni_gcm',
+ 'aesni_mb',
+ 'caam_jr',
+ 'ccp',
+ 'dpaa_sec',
+ 'dpaa2_sec',
+ 'kasumi',
+ 'mvsam',
+ 'nitrox',
+ 'null',
+ 'octeontx',
+ 'octeontx2',
+ 'openssl',
+ 'qat',
+ 'scheduler',
+ 'snow3g',
+ 'virtio',
+ 'zuc']
std_deps = ['cryptodev'] # cryptodev pulls in all other needed deps
config_flag_fmt = 'RTE_LIBRTE_@0@_PMD'
diff --git a/drivers/crypto/octeontx2/Makefile b/drivers/crypto/octeontx2/Makefile
new file mode 100644
index 0000000..3273178
--- /dev/null
+++ b/drivers/crypto/octeontx2/Makefile
@@ -0,0 +1,37 @@
+# SPDX-License-Identifier: BSD-3-Clause
+# Copyright (C) 2019 Marvell International Ltd.
+#
+
+include $(RTE_SDK)/mk/rte.vars.mk
+
+# library name
+LIB = librte_pmd_octeontx2_crypto.a
+
+# library version
+LIBABIVER := 1
+
+# build flags
+CFLAGS += $(WERROR_FLAGS)
+
+LDLIBS += -lrte_eal -lrte_mbuf -lrte_mempool -lrte_ring
+LDLIBS += -lrte_cryptodev
+LDLIBS += -lrte_pci -lrte_bus_pci
+LDLIBS += -lrte_common_cpt -lrte_common_octeontx2
+
+VPATH += $(RTE_SDK)/drivers/crypto/octeontx2
+
+CFLAGS += -O3
+CFLAGS += -I$(RTE_SDK)/drivers/common/cpt
+CFLAGS += -I$(RTE_SDK)/drivers/common/octeontx2
+
+# PMD code
+SRCS-$(CONFIG_RTE_LIBRTE_PMD_OCTEONTX2_CRYPTO) += otx2_cryptodev.c
+SRCS-$(CONFIG_RTE_LIBRTE_PMD_OCTEONTX2_CRYPTO) += otx2_cryptodev_ops.c
+
+# export include files
+SYMLINK-y-include +=
+
+# versioning export map
+EXPORT_MAP := rte_pmd_octeontx2_crypto_version.map
+
+include $(RTE_SDK)/mk/rte.lib.mk
diff --git a/drivers/crypto/octeontx2/meson.build b/drivers/crypto/octeontx2/meson.build
new file mode 100644
index 0000000..2b55d2a
--- /dev/null
+++ b/drivers/crypto/octeontx2/meson.build
@@ -0,0 +1,29 @@
+# SPDX-License-Identifier: BSD-3-Clause
+# Copyright (C) 2019 Marvell International Ltd.
+
+if host_machine.system() != 'linux'
+ build = false
+endif
+
+deps += ['bus_pci']
+deps += ['common_cpt']
+deps += ['common_octeontx2']
+name = 'octeontx2_crypto'
+
+sources = files('otx2_cryptodev.c',
+ 'otx2_cryptodev_ops.c')
+
+extra_flags = []
+# This integrated controller runs only on a arm64 machine, remove 32bit warnings
+if not dpdk_conf.get('RTE_ARCH_64')
+ extra_flags += ['-Wno-int-to-pointer-cast', '-Wno-pointer-to-int-cast']
+endif
+
+foreach flag: extra_flags
+ if cc.has_argument(flag)
+ cflags += flag
+ endif
+endforeach
+
+includes += include_directories('../../common/cpt')
+includes += include_directories('../../common/octeontx2')
diff --git a/drivers/crypto/octeontx2/otx2_cryptodev.c b/drivers/crypto/octeontx2/otx2_cryptodev.c
new file mode 100644
index 0000000..ca9f227
--- /dev/null
+++ b/drivers/crypto/octeontx2/otx2_cryptodev.c
@@ -0,0 +1,111 @@
+/* SPDX-License-Identifier: BSD-3-Clause
+ * Copyright (C) 2019 Marvell International Ltd.
+ */
+
+#include <rte_bus_pci.h>
+#include <rte_common.h>
+#include <rte_crypto.h>
+#include <rte_cryptodev.h>
+#include <rte_cryptodev_pmd.h>
+#include <rte_dev.h>
+#include <rte_errno.h>
+#include <rte_mempool.h>
+#include <rte_pci.h>
+
+#include "otx2_common.h"
+#include "otx2_cryptodev.h"
+#include "otx2_cryptodev_ops.h"
+
+/* CPT common headers */
+#include "cpt_common.h"
+#include "cpt_pmd_logs.h"
+
+int otx2_cpt_logtype;
+
+static struct rte_pci_id pci_id_cpt_table[] = {
+ {
+ RTE_PCI_DEVICE(PCI_VENDOR_ID_CAVIUM,
+ PCI_DEVID_OCTEONTX2_RVU_CPT_VF)
+ },
+ /* sentinel */
+ {
+ .device_id = 0
+ },
+};
+
+static int
+otx2_cpt_pci_probe(struct rte_pci_driver *pci_drv __rte_unused,
+ struct rte_pci_device *pci_dev)
+{
+ struct rte_cryptodev_pmd_init_params init_params = {
+ .name = "",
+ .socket_id = rte_socket_id(),
+ .private_data_size = sizeof(struct otx2_cpt_vf)
+ };
+ char name[RTE_CRYPTODEV_NAME_MAX_LEN];
+ struct rte_cryptodev *dev;
+ int ret;
+
+ rte_pci_device_name(&pci_dev->addr, name, sizeof(name));
+
+ dev = rte_cryptodev_pmd_create(name, &pci_dev->device, &init_params);
+ if (dev == NULL) {
+ ret = -ENODEV;
+ goto exit;
+ }
+
+ dev->dev_ops = &otx2_cpt_ops;
+
+ dev->driver_id = otx2_cryptodev_driver_id;
+
+ dev->feature_flags = RTE_CRYPTODEV_FF_SYMMETRIC_CRYPTO |
+ RTE_CRYPTODEV_FF_HW_ACCELERATED;
+
+ return 0;
+
+exit:
+ CPT_LOG_ERR("Could not create device (vendor_id: 0x%x device_id: 0x%x)",
+ pci_dev->id.vendor_id, pci_dev->id.device_id);
+ return ret;
+}
+
+static int
+otx2_cpt_pci_remove(struct rte_pci_device *pci_dev)
+{
+ char name[RTE_CRYPTODEV_NAME_MAX_LEN];
+ struct rte_cryptodev *dev;
+
+ if (pci_dev == NULL)
+ return -EINVAL;
+
+ rte_pci_device_name(&pci_dev->addr, name, sizeof(name));
+
+ dev = rte_cryptodev_pmd_get_named_dev(name);
+ if (dev == NULL)
+ return -ENODEV;
+
+ return rte_cryptodev_pmd_destroy(dev);
+}
+
+static struct rte_pci_driver otx2_cryptodev_pmd = {
+ .id_table = pci_id_cpt_table,
+ .drv_flags = RTE_PCI_DRV_NEED_MAPPING,
+ .probe = otx2_cpt_pci_probe,
+ .remove = otx2_cpt_pci_remove,
+};
+
+static struct cryptodev_driver otx2_cryptodev_drv;
+
+RTE_INIT(otx2_cpt_init_log);
+RTE_PMD_REGISTER_PCI(CRYPTODEV_NAME_OCTEONTX2_PMD, otx2_cryptodev_pmd);
+RTE_PMD_REGISTER_PCI_TABLE(CRYPTODEV_NAME_OCTEONTX2_PMD, pci_id_cpt_table);
+RTE_PMD_REGISTER_CRYPTO_DRIVER(otx2_cryptodev_drv, otx2_cryptodev_pmd.driver,
+ otx2_cryptodev_driver_id);
+
+RTE_INIT(otx2_cpt_init_log)
+{
+ /* Bus level logs */
+ otx2_cpt_logtype = rte_log_register("pmd.crypto.octeontx2");
+ if (otx2_cpt_logtype >= 0)
+ rte_log_set_level(otx2_cpt_logtype, RTE_LOG_NOTICE);
+}
diff --git a/drivers/crypto/octeontx2/otx2_cryptodev.h b/drivers/crypto/octeontx2/otx2_cryptodev.h
new file mode 100644
index 0000000..c9fe0c8
--- /dev/null
+++ b/drivers/crypto/octeontx2/otx2_cryptodev.h
@@ -0,0 +1,29 @@
+/* SPDX-License-Identifier: BSD-3-Clause
+ * Copyright (C) 2019 Marvell International Ltd.
+ */
+
+#ifndef _OTX2_CRYPTODEV_H_
+#define _OTX2_CRYPTODEV_H_
+
+#include "cpt_common.h"
+
+/* Marvell OCTEON TX2 Crypto PMD device name */
+#define CRYPTODEV_NAME_OCTEONTX2_PMD crypto_octeontx2
+
+/**
+ * Device private data
+ */
+struct otx2_cpt_vf {
+ /* To be populated */
+};
+
+#define CPT_LOGTYPE otx2_cpt_logtype
+
+extern int otx2_cpt_logtype;
+
+/*
+ * Crypto device driver ID
+ */
+uint8_t otx2_cryptodev_driver_id;
+
+#endif /* _OTX2_CRYPTODEV_H_ */
diff --git a/drivers/crypto/octeontx2/otx2_cryptodev_ops.c b/drivers/crypto/octeontx2/otx2_cryptodev_ops.c
new file mode 100644
index 0000000..18ad470
--- /dev/null
+++ b/drivers/crypto/octeontx2/otx2_cryptodev_ops.c
@@ -0,0 +1,27 @@
+/* SPDX-License-Identifier: BSD-3-Clause
+ * Copyright (C) 2019 Marvell International Ltd.
+ */
+
+#include <rte_cryptodev_pmd.h>
+
+#include "otx2_cryptodev_ops.h"
+
+struct rte_cryptodev_ops otx2_cpt_ops = {
+ /* Device control ops */
+ .dev_configure = NULL,
+ .dev_start = NULL,
+ .dev_stop = NULL,
+ .dev_close = NULL,
+ .dev_infos_get = NULL,
+
+ .stats_get = NULL,
+ .stats_reset = NULL,
+ .queue_pair_setup = NULL,
+ .queue_pair_release = NULL,
+ .queue_pair_count = NULL,
+
+ /* Symmetric crypto ops */
+ .sym_session_get_size = NULL,
+ .sym_session_configure = NULL,
+ .sym_session_clear = NULL,
+};
diff --git a/drivers/crypto/octeontx2/otx2_cryptodev_ops.h b/drivers/crypto/octeontx2/otx2_cryptodev_ops.h
new file mode 100644
index 0000000..545614e
--- /dev/null
+++ b/drivers/crypto/octeontx2/otx2_cryptodev_ops.h
@@ -0,0 +1,12 @@
+/* SPDX-License-Identifier: BSD-3-Clause
+ * Copyright (C) 2019 Marvell International Ltd.
+ */
+
+#ifndef _OTX2_CRYPTODEV_OPS_H_
+#define _OTX2_CRYPTODEV_OPS_H_
+
+#include <rte_cryptodev_pmd.h>
+
+struct rte_cryptodev_ops otx2_cpt_ops;
+
+#endif /* _OTX2_CRYPTODEV_OPS_H_ */
diff --git a/drivers/crypto/octeontx2/rte_pmd_octeontx2_crypto_version.map b/drivers/crypto/octeontx2/rte_pmd_octeontx2_crypto_version.map
new file mode 100644
index 0000000..9a61188
--- /dev/null
+++ b/drivers/crypto/octeontx2/rte_pmd_octeontx2_crypto_version.map
@@ -0,0 +1,4 @@
+DPDK_19.08 {
+
+ local: *;
+};
diff --git a/mk/rte.app.mk b/mk/rte.app.mk
index 219c540..dbbb437 100644
--- a/mk/rte.app.mk
+++ b/mk/rte.app.mk
@@ -101,7 +101,9 @@ ifeq ($(CONFIG_RTE_EXEC_ENV_LINUX),y)
_LDLIBS-$(CONFIG_RTE_LIBRTE_KNI) += -lrte_kni
endif
-ifeq ($(CONFIG_RTE_LIBRTE_PMD_OCTEONTX_CRYPTO),y)
+OTX-CPT-y := $(CONFIG_RTE_LIBRTE_PMD_OCTEONTX_CRYPTO)
+OTX-CPT-y += $(CONFIG_RTE_LIBRTE_PMD_OCTEONTX2_CRYPTO)
+ifeq ($(findstring y,$(OTX-CPT-y)),y)
_LDLIBS-y += -lrte_common_cpt
endif
@@ -109,6 +111,7 @@ ifeq ($(CONFIG_RTE_LIBRTE_PMD_OCTEONTX_SSOVF)$(CONFIG_RTE_LIBRTE_OCTEONTX_MEMPOO
_LDLIBS-y += -lrte_common_octeontx
endif
OCTEONTX2-y := $(CONFIG_RTE_LIBRTE_OCTEONTX2_MEMPOOL)
+OCTEONTX2-y += $(CONFIG_RTE_LIBRTE_PMD_OCTEONTX2_CRYPTO)
OCTEONTX2-y += $(CONFIG_RTE_LIBRTE_PMD_OCTEONTX2_EVENTDEV)
OCTEONTX2-y += $(CONFIG_RTE_LIBRTE_PMD_OCTEONTX2_DMA_RAWDEV)
OCTEONTX2-y += $(CONFIG_RTE_LIBRTE_OCTEONTX2_PMD)
@@ -269,6 +272,7 @@ _LDLIBS-$(CONFIG_RTE_LIBRTE_PMD_ARMV8_CRYPTO) += -L$(ARMV8_CRYPTO_LIB_PATH) -
_LDLIBS-$(CONFIG_RTE_LIBRTE_PMD_MVSAM_CRYPTO) += -L$(LIBMUSDK_PATH)/lib -lrte_pmd_mvsam_crypto -lmusdk
_LDLIBS-$(CONFIG_RTE_LIBRTE_PMD_NITROX) += -lrte_pmd_nitrox
_LDLIBS-$(CONFIG_RTE_LIBRTE_PMD_OCTEONTX_CRYPTO) += -lrte_pmd_octeontx_crypto
+_LDLIBS-$(CONFIG_RTE_LIBRTE_PMD_OCTEONTX2_CRYPTO) += -lrte_pmd_octeontx2_crypto
_LDLIBS-$(CONFIG_RTE_LIBRTE_PMD_CRYPTO_SCHEDULER) += -lrte_pmd_crypto_scheduler
ifeq ($(CONFIG_RTE_LIBRTE_SECURITY),y)
ifeq ($(CONFIG_RTE_EAL_VFIO)$(CONFIG_RTE_LIBRTE_FSLMC_BUS),yy)
--
2.7.4
^ permalink raw reply related [flat|nested] 53+ messages in thread* Re: [dpdk-dev] [PATCH v2 01/12] crypto/octeontx2: add PMD skeleton
2019-10-13 12:39 ` [dpdk-dev] [PATCH v2 01/12] crypto/octeontx2: add PMD skeleton Anoob Joseph
@ 2019-10-15 7:56 ` Akhil Goyal
2019-10-15 8:44 ` Anoob Joseph
0 siblings, 1 reply; 53+ messages in thread
From: Akhil Goyal @ 2019-10-15 7:56 UTC (permalink / raw)
To: Anoob Joseph, Pablo de Lara
Cc: Fiona Trahe, Jerin Jacob, Narayana Prasad, Shally Verma,
Ankur Dwivedi, Kanaka Durga Kotamarthy, Sunila Sahu,
Tejasree Kondoj, dev@dpdk.org
> diff --git a/drivers/crypto/octeontx2/rte_pmd_octeontx2_crypto_version.map
> b/drivers/crypto/octeontx2/rte_pmd_octeontx2_crypto_version.map
> new file mode 100644
> index 0000000..9a61188
> --- /dev/null
> +++ b/drivers/crypto/octeontx2/rte_pmd_octeontx2_crypto_version.map
> @@ -0,0 +1,4 @@
> +DPDK_19.08 {
> +
> + local: *;
> +};
19.08?? Should be 19.11
^ permalink raw reply [flat|nested] 53+ messages in thread* Re: [dpdk-dev] [PATCH v2 01/12] crypto/octeontx2: add PMD skeleton
2019-10-15 7:56 ` Akhil Goyal
@ 2019-10-15 8:44 ` Anoob Joseph
0 siblings, 0 replies; 53+ messages in thread
From: Anoob Joseph @ 2019-10-15 8:44 UTC (permalink / raw)
To: Akhil Goyal, Pablo de Lara
Cc: Fiona Trahe, Jerin Jacob Kollanukkaran,
Narayana Prasad Raju Athreya, Shally Verma, Ankur Dwivedi,
Kanaka Durga Kotamarthy, Sunila Sahu, Tejasree Kondoj,
dev@dpdk.org
Hi Akhil,
Will fix the issue. Please do let me know if there are more comments. I can send v3 once you confirm.
Thanks,
Anoob
> -----Original Message-----
> From: Akhil Goyal <akhil.goyal@nxp.com>
> Sent: Tuesday, October 15, 2019 1:26 PM
> To: Anoob Joseph <anoobj@marvell.com>; Pablo de Lara
> <pablo.de.lara.guarch@intel.com>
> Cc: Fiona Trahe <fiona.trahe@intel.com>; Jerin Jacob Kollanukkaran
> <jerinj@marvell.com>; Narayana Prasad Raju Athreya
> <pathreya@marvell.com>; Shally Verma <shallyv@marvell.com>; Ankur
> Dwivedi <adwivedi@marvell.com>; Kanaka Durga Kotamarthy
> <kkotamarthy@marvell.com>; Sunila Sahu <ssahu@marvell.com>; Tejasree
> Kondoj <ktejasree@marvell.com>; dev@dpdk.org
> Subject: [EXT] RE: [PATCH v2 01/12] crypto/octeontx2: add PMD skeleton
>
> External Email
>
> ----------------------------------------------------------------------
> > diff --git
> a/drivers/crypto/octeontx2/rte_pmd_octeontx2_crypto_version.map
> > b/drivers/crypto/octeontx2/rte_pmd_octeontx2_crypto_version.map
> > new file mode 100644
> > index 0000000..9a61188
> > --- /dev/null
> > +++ b/drivers/crypto/octeontx2/rte_pmd_octeontx2_crypto_version.map
> > @@ -0,0 +1,4 @@
> > +DPDK_19.08 {
> > +
> > + local: *;
> > +};
>
> 19.08?? Should be 19.11
^ permalink raw reply [flat|nested] 53+ messages in thread
* [dpdk-dev] [PATCH v2 02/12] crypto/octeontx2: add device init sequence in probe
2019-10-13 12:39 ` [dpdk-dev] [PATCH v2 00/12] " Anoob Joseph
2019-10-13 12:39 ` [dpdk-dev] [PATCH v2 01/12] crypto/octeontx2: add PMD skeleton Anoob Joseph
@ 2019-10-13 12:39 ` Anoob Joseph
2019-10-13 12:39 ` [dpdk-dev] [PATCH v2 03/12] crypto/octeontx2: add device control ops Anoob Joseph
` (11 subsequent siblings)
13 siblings, 0 replies; 53+ messages in thread
From: Anoob Joseph @ 2019-10-13 12:39 UTC (permalink / raw)
To: Akhil Goyal, Pablo de Lara
Cc: Anoob Joseph, Fiona Trahe, Jerin Jacob, Narayana Prasad,
Shally Verma, Ankur Dwivedi, Kanaka Durga Kotamarthy, Sunila Sahu,
Tejasree Kondoj, dev
This patch adds the device init sequence for OCTEON TX2 crypto
device.
Signed-off-by: Ankur Dwivedi <adwivedi@marvell.com>
Signed-off-by: Anoob Joseph <anoobj@marvell.com>
Signed-off-by: Tejasree Kondoj <ktejasree@marvell.com>
---
drivers/crypto/octeontx2/Makefile | 10 +++++++
drivers/crypto/octeontx2/meson.build | 2 ++
drivers/crypto/octeontx2/otx2_cryptodev.c | 40 ++++++++++++++++++++++++++
drivers/crypto/octeontx2/otx2_cryptodev.h | 10 ++++++-
drivers/crypto/octeontx2/otx2_cryptodev_mbox.c | 28 ++++++++++++++++++
drivers/crypto/octeontx2/otx2_cryptodev_mbox.h | 13 +++++++++
6 files changed, 102 insertions(+), 1 deletion(-)
create mode 100644 drivers/crypto/octeontx2/otx2_cryptodev_mbox.c
create mode 100644 drivers/crypto/octeontx2/otx2_cryptodev_mbox.h
diff --git a/drivers/crypto/octeontx2/Makefile b/drivers/crypto/octeontx2/Makefile
index 3273178..10d8c39 100644
--- a/drivers/crypto/octeontx2/Makefile
+++ b/drivers/crypto/octeontx2/Makefile
@@ -23,9 +23,19 @@ VPATH += $(RTE_SDK)/drivers/crypto/octeontx2
CFLAGS += -O3
CFLAGS += -I$(RTE_SDK)/drivers/common/cpt
CFLAGS += -I$(RTE_SDK)/drivers/common/octeontx2
+CFLAGS += -I$(RTE_SDK)/drivers/mempool/octeontx2
+
+ifneq ($(CONFIG_RTE_ARCH_64),y)
+CFLAGS += -Wno-int-to-pointer-cast
+CFLAGS += -Wno-pointer-to-int-cast
+ifeq ($(CONFIG_RTE_TOOLCHAIN_ICC),y)
+CFLAGS += -diag-disable 2259
+endif
+endif
# PMD code
SRCS-$(CONFIG_RTE_LIBRTE_PMD_OCTEONTX2_CRYPTO) += otx2_cryptodev.c
+SRCS-$(CONFIG_RTE_LIBRTE_PMD_OCTEONTX2_CRYPTO) += otx2_cryptodev_mbox.c
SRCS-$(CONFIG_RTE_LIBRTE_PMD_OCTEONTX2_CRYPTO) += otx2_cryptodev_ops.c
# export include files
diff --git a/drivers/crypto/octeontx2/meson.build b/drivers/crypto/octeontx2/meson.build
index 2b55d2a..845d50d 100644
--- a/drivers/crypto/octeontx2/meson.build
+++ b/drivers/crypto/octeontx2/meson.build
@@ -11,6 +11,7 @@ deps += ['common_octeontx2']
name = 'octeontx2_crypto'
sources = files('otx2_cryptodev.c',
+ 'otx2_cryptodev_mbox.c',
'otx2_cryptodev_ops.c')
extra_flags = []
@@ -27,3 +28,4 @@ endforeach
includes += include_directories('../../common/cpt')
includes += include_directories('../../common/octeontx2')
+includes += include_directories('../../mempool/octeontx2')
diff --git a/drivers/crypto/octeontx2/otx2_cryptodev.c b/drivers/crypto/octeontx2/otx2_cryptodev.c
index ca9f227..efc17cb 100644
--- a/drivers/crypto/octeontx2/otx2_cryptodev.c
+++ b/drivers/crypto/octeontx2/otx2_cryptodev.c
@@ -14,7 +14,9 @@
#include "otx2_common.h"
#include "otx2_cryptodev.h"
+#include "otx2_cryptodev_mbox.h"
#include "otx2_cryptodev_ops.h"
+#include "otx2_dev.h"
/* CPT common headers */
#include "cpt_common.h"
@@ -44,6 +46,9 @@ otx2_cpt_pci_probe(struct rte_pci_driver *pci_drv __rte_unused,
};
char name[RTE_CRYPTODEV_NAME_MAX_LEN];
struct rte_cryptodev *dev;
+ struct otx2_dev *otx2_dev;
+ struct otx2_cpt_vf *vf;
+ uint16_t nb_queues;
int ret;
rte_pci_device_name(&pci_dev->addr, name, sizeof(name));
@@ -58,11 +63,46 @@ otx2_cpt_pci_probe(struct rte_pci_driver *pci_drv __rte_unused,
dev->driver_id = otx2_cryptodev_driver_id;
+ /* Get private data space allocated */
+ vf = dev->data->dev_private;
+
+ otx2_dev = &vf->otx2_dev;
+
+ /* Initialize the base otx2_dev object */
+ ret = otx2_dev_init(pci_dev, otx2_dev);
+ if (ret) {
+ CPT_LOG_ERR("Could not initialize otx2_dev");
+ goto pmd_destroy;
+ }
+
+ /* Get number of queues available on the device */
+ ret = otx2_cpt_available_queues_get(dev, &nb_queues);
+ if (ret) {
+ CPT_LOG_ERR("Could not determine the number of queues available");
+ goto otx2_dev_fini;
+ }
+
+ /* Don't exceed the limits set per VF */
+ nb_queues = RTE_MIN(nb_queues, OTX2_CPT_MAX_QUEUES_PER_VF);
+
+ if (nb_queues == 0) {
+ CPT_LOG_ERR("No free queues available on the device");
+ goto otx2_dev_fini;
+ }
+
+ vf->max_queues = nb_queues;
+
+ CPT_LOG_INFO("Max queues supported by device: %d", vf->max_queues);
+
dev->feature_flags = RTE_CRYPTODEV_FF_SYMMETRIC_CRYPTO |
RTE_CRYPTODEV_FF_HW_ACCELERATED;
return 0;
+otx2_dev_fini:
+ otx2_dev_fini(pci_dev, otx2_dev);
+pmd_destroy:
+ rte_cryptodev_pmd_destroy(dev);
exit:
CPT_LOG_ERR("Could not create device (vendor_id: 0x%x device_id: 0x%x)",
pci_dev->id.vendor_id, pci_dev->id.device_id);
diff --git a/drivers/crypto/octeontx2/otx2_cryptodev.h b/drivers/crypto/octeontx2/otx2_cryptodev.h
index c9fe0c8..d26c1f3 100644
--- a/drivers/crypto/octeontx2/otx2_cryptodev.h
+++ b/drivers/crypto/octeontx2/otx2_cryptodev.h
@@ -7,14 +7,22 @@
#include "cpt_common.h"
+#include "otx2_dev.h"
+
/* Marvell OCTEON TX2 Crypto PMD device name */
#define CRYPTODEV_NAME_OCTEONTX2_PMD crypto_octeontx2
+#define OTX2_CPT_MAX_LFS 64
+#define OTX2_CPT_MAX_QUEUES_PER_VF 64
+
/**
* Device private data
*/
struct otx2_cpt_vf {
- /* To be populated */
+ struct otx2_dev otx2_dev;
+ /**< Base class */
+ uint16_t max_queues;
+ /**< Max queues supported */
};
#define CPT_LOGTYPE otx2_cpt_logtype
diff --git a/drivers/crypto/octeontx2/otx2_cryptodev_mbox.c b/drivers/crypto/octeontx2/otx2_cryptodev_mbox.c
new file mode 100644
index 0000000..20fc1ac
--- /dev/null
+++ b/drivers/crypto/octeontx2/otx2_cryptodev_mbox.c
@@ -0,0 +1,28 @@
+/* SPDX-License-Identifier: BSD-3-Clause
+ * Copyright (C) 2019 Marvell International Ltd.
+ */
+#include <rte_cryptodev.h>
+
+#include "otx2_cryptodev.h"
+#include "otx2_cryptodev_mbox.h"
+#include "otx2_dev.h"
+#include "otx2_mbox.h"
+
+int
+otx2_cpt_available_queues_get(const struct rte_cryptodev *dev,
+ uint16_t *nb_queues)
+{
+ struct otx2_cpt_vf *vf = dev->data->dev_private;
+ struct otx2_dev *otx2_dev = &vf->otx2_dev;
+ struct free_rsrcs_rsp *rsp;
+ int ret;
+
+ otx2_mbox_alloc_msg_free_rsrc_cnt(otx2_dev->mbox);
+
+ ret = otx2_mbox_process_msg(otx2_dev->mbox, (void *)&rsp);
+ if (ret)
+ return -EIO;
+
+ *nb_queues = rsp->cpt;
+ return 0;
+}
diff --git a/drivers/crypto/octeontx2/otx2_cryptodev_mbox.h b/drivers/crypto/octeontx2/otx2_cryptodev_mbox.h
new file mode 100644
index 0000000..648c009
--- /dev/null
+++ b/drivers/crypto/octeontx2/otx2_cryptodev_mbox.h
@@ -0,0 +1,13 @@
+/* SPDX-License-Identifier: BSD-3-Clause
+ * Copyright (C) 2019 Marvell International Ltd.
+ */
+
+#ifndef _OTX2_CRYPTODEV_MBOX_H_
+#define _OTX2_CRYPTODEV_MBOX_H_
+
+#include <rte_cryptodev.h>
+
+int otx2_cpt_available_queues_get(const struct rte_cryptodev *dev,
+ uint16_t *nb_queues);
+
+#endif /* _OTX2_CRYPTODEV_MBOX_H_ */
--
2.7.4
^ permalink raw reply related [flat|nested] 53+ messages in thread* [dpdk-dev] [PATCH v2 03/12] crypto/octeontx2: add device control ops
2019-10-13 12:39 ` [dpdk-dev] [PATCH v2 00/12] " Anoob Joseph
2019-10-13 12:39 ` [dpdk-dev] [PATCH v2 01/12] crypto/octeontx2: add PMD skeleton Anoob Joseph
2019-10-13 12:39 ` [dpdk-dev] [PATCH v2 02/12] crypto/octeontx2: add device init sequence in probe Anoob Joseph
@ 2019-10-13 12:39 ` Anoob Joseph
2019-10-13 12:39 ` [dpdk-dev] [PATCH v2 04/12] crypto/octeontx2: add queue pair functions Anoob Joseph
` (10 subsequent siblings)
13 siblings, 0 replies; 53+ messages in thread
From: Anoob Joseph @ 2019-10-13 12:39 UTC (permalink / raw)
To: Akhil Goyal, Pablo de Lara
Cc: Ankur Dwivedi, Fiona Trahe, Jerin Jacob, Narayana Prasad,
Shally Verma, Kanaka Durga Kotamarthy, Sunila Sahu,
Tejasree Kondoj, dev, Anoob Joseph
From: Ankur Dwivedi <adwivedi@marvell.com>
This patch adds the device control functions.
Signed-off-by: Ankur Dwivedi <adwivedi@marvell.com>
Signed-off-by: Anoob Joseph <anoobj@marvell.com>
Signed-off-by: Tejasree Kondoj <ktejasree@marvell.com>
---
drivers/crypto/octeontx2/Makefile | 1 +
drivers/crypto/octeontx2/meson.build | 1 +
drivers/crypto/octeontx2/otx2_cryptodev.h | 6 +
.../crypto/octeontx2/otx2_cryptodev_hw_access.c | 126 +++++++++++++++++++++
.../crypto/octeontx2/otx2_cryptodev_hw_access.h | 27 +++++
drivers/crypto/octeontx2/otx2_cryptodev_mbox.c | 64 +++++++++++
drivers/crypto/octeontx2/otx2_cryptodev_mbox.h | 6 +
drivers/crypto/octeontx2/otx2_cryptodev_ops.c | 123 +++++++++++++++++++-
drivers/crypto/octeontx2/otx2_cryptodev_ops.h | 3 +
9 files changed, 352 insertions(+), 5 deletions(-)
create mode 100644 drivers/crypto/octeontx2/otx2_cryptodev_hw_access.c
create mode 100644 drivers/crypto/octeontx2/otx2_cryptodev_hw_access.h
diff --git a/drivers/crypto/octeontx2/Makefile b/drivers/crypto/octeontx2/Makefile
index 10d8c39..71bc4d1 100644
--- a/drivers/crypto/octeontx2/Makefile
+++ b/drivers/crypto/octeontx2/Makefile
@@ -35,6 +35,7 @@ endif
# PMD code
SRCS-$(CONFIG_RTE_LIBRTE_PMD_OCTEONTX2_CRYPTO) += otx2_cryptodev.c
+SRCS-$(CONFIG_RTE_LIBRTE_PMD_OCTEONTX2_CRYPTO) += otx2_cryptodev_hw_access.c
SRCS-$(CONFIG_RTE_LIBRTE_PMD_OCTEONTX2_CRYPTO) += otx2_cryptodev_mbox.c
SRCS-$(CONFIG_RTE_LIBRTE_PMD_OCTEONTX2_CRYPTO) += otx2_cryptodev_ops.c
diff --git a/drivers/crypto/octeontx2/meson.build b/drivers/crypto/octeontx2/meson.build
index 845d50d..944fa2c 100644
--- a/drivers/crypto/octeontx2/meson.build
+++ b/drivers/crypto/octeontx2/meson.build
@@ -11,6 +11,7 @@ deps += ['common_octeontx2']
name = 'octeontx2_crypto'
sources = files('otx2_cryptodev.c',
+ 'otx2_cryptodev_hw_access.c',
'otx2_cryptodev_mbox.c',
'otx2_cryptodev_ops.c')
diff --git a/drivers/crypto/octeontx2/otx2_cryptodev.h b/drivers/crypto/octeontx2/otx2_cryptodev.h
index d26c1f3..8e0ebc2 100644
--- a/drivers/crypto/octeontx2/otx2_cryptodev.h
+++ b/drivers/crypto/octeontx2/otx2_cryptodev.h
@@ -23,6 +23,12 @@ struct otx2_cpt_vf {
/**< Base class */
uint16_t max_queues;
/**< Max queues supported */
+ uint8_t nb_queues;
+ /**< Number of crypto queues attached */
+ uint16_t lf_msixoff[OTX2_CPT_MAX_LFS];
+ /**< MSI-X offsets */
+ uint8_t err_intr_registered:1;
+ /**< Are error interrupts registered? */
};
#define CPT_LOGTYPE otx2_cpt_logtype
diff --git a/drivers/crypto/octeontx2/otx2_cryptodev_hw_access.c b/drivers/crypto/octeontx2/otx2_cryptodev_hw_access.c
new file mode 100644
index 0000000..663f9ca
--- /dev/null
+++ b/drivers/crypto/octeontx2/otx2_cryptodev_hw_access.c
@@ -0,0 +1,126 @@
+/* SPDX-License-Identifier: BSD-3-Clause
+ * Copyright (C) 2019 Marvell International Ltd.
+ */
+
+#include "otx2_common.h"
+#include "otx2_cryptodev.h"
+#include "otx2_cryptodev_hw_access.h"
+
+#include "cpt_pmd_logs.h"
+
+static void
+otx2_cpt_lf_err_intr_handler(void *param)
+{
+ uintptr_t base = (uintptr_t)param;
+ uint8_t lf_id;
+ uint64_t intr;
+
+ lf_id = (base >> 12) & 0xFF;
+
+ intr = otx2_read64(base + OTX2_CPT_LF_MISC_INT);
+ if (intr == 0)
+ return;
+
+ CPT_LOG_ERR("LF %d MISC_INT: 0x%" PRIx64 "", lf_id, intr);
+
+ /* Clear interrupt */
+ otx2_write64(intr, base + OTX2_CPT_LF_MISC_INT);
+}
+
+static void
+otx2_cpt_lf_err_intr_unregister(const struct rte_cryptodev *dev,
+ uint16_t msix_off, uintptr_t base)
+{
+ struct rte_pci_device *pci_dev = RTE_DEV_TO_PCI(dev->device);
+ struct rte_intr_handle *handle = &pci_dev->intr_handle;
+
+ /* Disable error interrupts */
+ otx2_write64(~0ull, base + OTX2_CPT_LF_MISC_INT_ENA_W1C);
+
+ otx2_unregister_irq(handle, otx2_cpt_lf_err_intr_handler, (void *)base,
+ msix_off);
+}
+
+void
+otx2_cpt_err_intr_unregister(const struct rte_cryptodev *dev)
+{
+ struct otx2_cpt_vf *vf = dev->data->dev_private;
+ uintptr_t base;
+ uint32_t i;
+
+ for (i = 0; i < vf->nb_queues; i++) {
+ base = OTX2_CPT_LF_BAR2(vf, i);
+ otx2_cpt_lf_err_intr_unregister(dev, vf->lf_msixoff[i], base);
+ }
+
+ vf->err_intr_registered = 0;
+}
+
+static int
+otx2_cpt_lf_err_intr_register(const struct rte_cryptodev *dev,
+ uint16_t msix_off, uintptr_t base)
+{
+ struct rte_pci_device *pci_dev = RTE_DEV_TO_PCI(dev->device);
+ struct rte_intr_handle *handle = &pci_dev->intr_handle;
+ int ret;
+
+ /* Disable error interrupts */
+ otx2_write64(~0ull, base + OTX2_CPT_LF_MISC_INT_ENA_W1C);
+
+ /* Register error interrupt handler */
+ ret = otx2_register_irq(handle, otx2_cpt_lf_err_intr_handler,
+ (void *)base, msix_off);
+ if (ret)
+ return ret;
+
+ /* Enable error interrupts */
+ otx2_write64(~0ull, base + OTX2_CPT_LF_MISC_INT_ENA_W1S);
+
+ return 0;
+}
+
+int
+otx2_cpt_err_intr_register(const struct rte_cryptodev *dev)
+{
+ struct otx2_cpt_vf *vf = dev->data->dev_private;
+ uint32_t i, j, ret;
+ uintptr_t base;
+
+ for (i = 0; i < vf->nb_queues; i++) {
+ if (vf->lf_msixoff[i] == MSIX_VECTOR_INVALID) {
+ CPT_LOG_ERR("Invalid CPT LF MSI-X offset: 0x%x",
+ vf->lf_msixoff[i]);
+ return -EINVAL;
+ }
+ }
+
+ for (i = 0; i < vf->nb_queues; i++) {
+ base = OTX2_CPT_LF_BAR2(vf, i);
+ ret = otx2_cpt_lf_err_intr_register(dev, vf->lf_msixoff[i],
+ base);
+ if (ret)
+ goto intr_unregister;
+ }
+
+ vf->err_intr_registered = 1;
+ return 0;
+
+intr_unregister:
+ /* Unregister the ones already registered */
+ for (j = 0; j < i; j++) {
+ base = OTX2_CPT_LF_BAR2(vf, j);
+ otx2_cpt_lf_err_intr_unregister(dev, vf->lf_msixoff[j], base);
+ }
+
+ /*
+ * Failed to register error interrupt. Not returning error as this would
+ * prevent application from enabling larger number of devs.
+ *
+ * This failure is a known issue because otx2_dev_init() initializes
+ * interrupts based on static values from ATF, and the actual number
+ * of interrupts needed (which is based on LFs) can be determined only
+ * after otx2_dev_init() sets up interrupts which includes mbox
+ * interrupts.
+ */
+ return 0;
+}
diff --git a/drivers/crypto/octeontx2/otx2_cryptodev_hw_access.h b/drivers/crypto/octeontx2/otx2_cryptodev_hw_access.h
new file mode 100644
index 0000000..2af674d
--- /dev/null
+++ b/drivers/crypto/octeontx2/otx2_cryptodev_hw_access.h
@@ -0,0 +1,27 @@
+/* SPDX-License-Identifier: BSD-3-Clause
+ * Copyright (C) 2019 Marvell International Ltd.
+ */
+
+#ifndef _OTX2_CRYPTODEV_HW_ACCESS_H_
+#define _OTX2_CRYPTODEV_HW_ACCESS_H_
+
+#include <rte_cryptodev.h>
+
+#include "otx2_dev.h"
+
+/* Register offsets */
+
+/* CPT LF registers */
+#define OTX2_CPT_LF_MISC_INT 0xb0ull
+#define OTX2_CPT_LF_MISC_INT_ENA_W1S 0xd0ull
+#define OTX2_CPT_LF_MISC_INT_ENA_W1C 0xe0ull
+
+#define OTX2_CPT_LF_BAR2(vf, q_id) \
+ ((vf)->otx2_dev.bar2 + \
+ ((RVU_BLOCK_ADDR_CPT0 << 20) | ((q_id) << 12)))
+
+void otx2_cpt_err_intr_unregister(const struct rte_cryptodev *dev);
+
+int otx2_cpt_err_intr_register(const struct rte_cryptodev *dev);
+
+#endif /* _OTX2_CRYPTODEV_HW_ACCESS_H_ */
diff --git a/drivers/crypto/octeontx2/otx2_cryptodev_mbox.c b/drivers/crypto/octeontx2/otx2_cryptodev_mbox.c
index 20fc1ac..9b0117a 100644
--- a/drivers/crypto/octeontx2/otx2_cryptodev_mbox.c
+++ b/drivers/crypto/octeontx2/otx2_cryptodev_mbox.c
@@ -26,3 +26,67 @@ otx2_cpt_available_queues_get(const struct rte_cryptodev *dev,
*nb_queues = rsp->cpt;
return 0;
}
+
+int
+otx2_cpt_queues_attach(const struct rte_cryptodev *dev, uint8_t nb_queues)
+{
+ struct otx2_cpt_vf *vf = dev->data->dev_private;
+ struct otx2_mbox *mbox = vf->otx2_dev.mbox;
+ struct rsrc_attach_req *req;
+
+ /* Ask AF to attach required LFs */
+
+ req = otx2_mbox_alloc_msg_attach_resources(mbox);
+
+ /* 1 LF = 1 queue */
+ req->cptlfs = nb_queues;
+
+ if (otx2_mbox_process(mbox) < 0)
+ return -EIO;
+
+ /* Update number of attached queues */
+ vf->nb_queues = nb_queues;
+
+ return 0;
+}
+
+int
+otx2_cpt_queues_detach(const struct rte_cryptodev *dev)
+{
+ struct otx2_cpt_vf *vf = dev->data->dev_private;
+ struct otx2_mbox *mbox = vf->otx2_dev.mbox;
+ struct rsrc_detach_req *req;
+
+ req = otx2_mbox_alloc_msg_detach_resources(mbox);
+ req->cptlfs = true;
+ req->partial = true;
+ if (otx2_mbox_process(mbox) < 0)
+ return -EIO;
+
+ /* Queues have been detached */
+ vf->nb_queues = 0;
+
+ return 0;
+}
+
+int
+otx2_cpt_msix_offsets_get(const struct rte_cryptodev *dev)
+{
+ struct otx2_cpt_vf *vf = dev->data->dev_private;
+ struct otx2_mbox *mbox = vf->otx2_dev.mbox;
+ struct msix_offset_rsp *rsp;
+ uint32_t i, ret;
+
+ /* Get CPT MSI-X vector offsets */
+
+ otx2_mbox_alloc_msg_msix_offset(mbox);
+
+ ret = otx2_mbox_process_msg(mbox, (void *)&rsp);
+ if (ret)
+ return ret;
+
+ for (i = 0; i < vf->nb_queues; i++)
+ vf->lf_msixoff[i] = rsp->cptlf_msixoff[i];
+
+ return 0;
+}
diff --git a/drivers/crypto/octeontx2/otx2_cryptodev_mbox.h b/drivers/crypto/octeontx2/otx2_cryptodev_mbox.h
index 648c009..0a43061 100644
--- a/drivers/crypto/octeontx2/otx2_cryptodev_mbox.h
+++ b/drivers/crypto/octeontx2/otx2_cryptodev_mbox.h
@@ -10,4 +10,10 @@
int otx2_cpt_available_queues_get(const struct rte_cryptodev *dev,
uint16_t *nb_queues);
+int otx2_cpt_queues_attach(const struct rte_cryptodev *dev, uint8_t nb_queues);
+
+int otx2_cpt_queues_detach(const struct rte_cryptodev *dev);
+
+int otx2_cpt_msix_offsets_get(const struct rte_cryptodev *dev);
+
#endif /* _OTX2_CRYPTODEV_MBOX_H_ */
diff --git a/drivers/crypto/octeontx2/otx2_cryptodev_ops.c b/drivers/crypto/octeontx2/otx2_cryptodev_ops.c
index 18ad470..b1bb9ae 100644
--- a/drivers/crypto/octeontx2/otx2_cryptodev_ops.c
+++ b/drivers/crypto/octeontx2/otx2_cryptodev_ops.c
@@ -4,15 +4,128 @@
#include <rte_cryptodev_pmd.h>
+#include "otx2_cryptodev.h"
+#include "otx2_cryptodev_hw_access.h"
+#include "otx2_cryptodev_mbox.h"
#include "otx2_cryptodev_ops.h"
+#include "otx2_mbox.h"
+
+#include "cpt_hw_types.h"
+#include "cpt_pmd_logs.h"
+
+/* PMD ops */
+
+static int
+otx2_cpt_dev_config(struct rte_cryptodev *dev,
+ struct rte_cryptodev_config *conf)
+{
+ struct otx2_cpt_vf *vf = dev->data->dev_private;
+ int ret;
+
+ if (conf->nb_queue_pairs > vf->max_queues) {
+ CPT_LOG_ERR("Invalid number of queue pairs requested");
+ return -EINVAL;
+ }
+
+ dev->feature_flags &= ~conf->ff_disable;
+
+ /* Unregister error interrupts */
+ if (vf->err_intr_registered)
+ otx2_cpt_err_intr_unregister(dev);
+
+ /* Detach queues */
+ if (vf->nb_queues) {
+ ret = otx2_cpt_queues_detach(dev);
+ if (ret) {
+ CPT_LOG_ERR("Could not detach CPT queues");
+ return ret;
+ }
+ }
+
+ /* Attach queues */
+ ret = otx2_cpt_queues_attach(dev, conf->nb_queue_pairs);
+ if (ret) {
+ CPT_LOG_ERR("Could not attach CPT queues");
+ return -ENODEV;
+ }
+
+ ret = otx2_cpt_msix_offsets_get(dev);
+ if (ret) {
+ CPT_LOG_ERR("Could not get MSI-X offsets");
+ goto queues_detach;
+ }
+
+ /* Register error interrupts */
+ ret = otx2_cpt_err_intr_register(dev);
+ if (ret) {
+ CPT_LOG_ERR("Could not register error interrupts");
+ goto queues_detach;
+ }
+
+ rte_mb();
+ return 0;
+
+queues_detach:
+ otx2_cpt_queues_detach(dev);
+ return ret;
+}
+
+static int
+otx2_cpt_dev_start(struct rte_cryptodev *dev)
+{
+ RTE_SET_USED(dev);
+
+ CPT_PMD_INIT_FUNC_TRACE();
+
+ return 0;
+}
+
+static void
+otx2_cpt_dev_stop(struct rte_cryptodev *dev)
+{
+ RTE_SET_USED(dev);
+
+ CPT_PMD_INIT_FUNC_TRACE();
+}
+
+static int
+otx2_cpt_dev_close(struct rte_cryptodev *dev)
+{
+ int ret;
+
+ otx2_cpt_err_intr_unregister(dev);
+
+ ret = otx2_cpt_queues_detach(dev);
+ if (ret)
+ CPT_LOG_ERR("Could not detach CPT queues");
+
+ return ret;
+}
+
+static void
+otx2_cpt_dev_info_get(struct rte_cryptodev *dev,
+ struct rte_cryptodev_info *info)
+{
+ struct otx2_cpt_vf *vf = dev->data->dev_private;
+
+ if (info != NULL) {
+ info->max_nb_queue_pairs = vf->max_queues;
+ info->feature_flags = dev->feature_flags;
+ info->capabilities = NULL;
+ info->sym.max_nb_sessions = 0;
+ info->driver_id = otx2_cryptodev_driver_id;
+ info->min_mbuf_headroom_req = OTX2_CPT_MIN_HEADROOM_REQ;
+ info->min_mbuf_tailroom_req = OTX2_CPT_MIN_TAILROOM_REQ;
+ }
+}
struct rte_cryptodev_ops otx2_cpt_ops = {
/* Device control ops */
- .dev_configure = NULL,
- .dev_start = NULL,
- .dev_stop = NULL,
- .dev_close = NULL,
- .dev_infos_get = NULL,
+ .dev_configure = otx2_cpt_dev_config,
+ .dev_start = otx2_cpt_dev_start,
+ .dev_stop = otx2_cpt_dev_stop,
+ .dev_close = otx2_cpt_dev_close,
+ .dev_infos_get = otx2_cpt_dev_info_get,
.stats_get = NULL,
.stats_reset = NULL,
diff --git a/drivers/crypto/octeontx2/otx2_cryptodev_ops.h b/drivers/crypto/octeontx2/otx2_cryptodev_ops.h
index 545614e..9bd24e7 100644
--- a/drivers/crypto/octeontx2/otx2_cryptodev_ops.h
+++ b/drivers/crypto/octeontx2/otx2_cryptodev_ops.h
@@ -7,6 +7,9 @@
#include <rte_cryptodev_pmd.h>
+#define OTX2_CPT_MIN_HEADROOM_REQ 24
+#define OTX2_CPT_MIN_TAILROOM_REQ 8
+
struct rte_cryptodev_ops otx2_cpt_ops;
#endif /* _OTX2_CRYPTODEV_OPS_H_ */
--
2.7.4
^ permalink raw reply related [flat|nested] 53+ messages in thread* [dpdk-dev] [PATCH v2 04/12] crypto/octeontx2: add queue pair functions
2019-10-13 12:39 ` [dpdk-dev] [PATCH v2 00/12] " Anoob Joseph
` (2 preceding siblings ...)
2019-10-13 12:39 ` [dpdk-dev] [PATCH v2 03/12] crypto/octeontx2: add device control ops Anoob Joseph
@ 2019-10-13 12:39 ` Anoob Joseph
2019-10-13 12:39 ` [dpdk-dev] [PATCH v2 05/12] crypto/octeontx2: add symmetric capabilities Anoob Joseph
` (9 subsequent siblings)
13 siblings, 0 replies; 53+ messages in thread
From: Anoob Joseph @ 2019-10-13 12:39 UTC (permalink / raw)
To: Akhil Goyal, Pablo de Lara
Cc: Ankur Dwivedi, Fiona Trahe, Jerin Jacob, Narayana Prasad,
Shally Verma, Kanaka Durga Kotamarthy, Sunila Sahu,
Tejasree Kondoj, dev, Anoob Joseph
From: Ankur Dwivedi <adwivedi@marvell.com>
This patch adds the queue pair setup and queue pair release functions
for OCTEON TX2 crypto pmd.
Signed-off-by: Ankur Dwivedi <adwivedi@marvell.com>
Signed-off-by: Anoob Joseph <anoobj@marvell.com>
Signed-off-by: Tejasree Kondoj <ktejasree@marvell.com>
---
.../crypto/octeontx2/otx2_cryptodev_hw_access.c | 99 +++++++
.../crypto/octeontx2/otx2_cryptodev_hw_access.h | 126 +++++++++
drivers/crypto/octeontx2/otx2_cryptodev_mbox.c | 83 ++++++
drivers/crypto/octeontx2/otx2_cryptodev_mbox.h | 6 +
drivers/crypto/octeontx2/otx2_cryptodev_ops.c | 306 ++++++++++++++++++++-
5 files changed, 617 insertions(+), 3 deletions(-)
diff --git a/drivers/crypto/octeontx2/otx2_cryptodev_hw_access.c b/drivers/crypto/octeontx2/otx2_cryptodev_hw_access.c
index 663f9ca..9e4f782 100644
--- a/drivers/crypto/octeontx2/otx2_cryptodev_hw_access.c
+++ b/drivers/crypto/octeontx2/otx2_cryptodev_hw_access.c
@@ -1,10 +1,14 @@
/* SPDX-License-Identifier: BSD-3-Clause
* Copyright (C) 2019 Marvell International Ltd.
*/
+#include <rte_cryptodev.h>
#include "otx2_common.h"
#include "otx2_cryptodev.h"
#include "otx2_cryptodev_hw_access.h"
+#include "otx2_cryptodev_mbox.h"
+#include "otx2_cryptodev_ops.h"
+#include "otx2_dev.h"
#include "cpt_pmd_logs.h"
@@ -124,3 +128,98 @@ otx2_cpt_err_intr_register(const struct rte_cryptodev *dev)
*/
return 0;
}
+
+int
+otx2_cpt_iq_enable(const struct rte_cryptodev *dev,
+ const struct otx2_cpt_qp *qp, uint8_t grp_mask, uint8_t pri,
+ uint32_t size_div40)
+{
+ union otx2_cpt_af_lf_ctl af_lf_ctl;
+ union otx2_cpt_lf_inprog inprog;
+ union otx2_cpt_lf_q_base base;
+ union otx2_cpt_lf_q_size size;
+ union otx2_cpt_lf_ctl lf_ctl;
+ int ret;
+
+ /* Set engine group mask and priority */
+
+ ret = otx2_cpt_af_reg_read(dev, OTX2_CPT_AF_LF_CTL(qp->id),
+ &af_lf_ctl.u);
+ if (ret)
+ return ret;
+ af_lf_ctl.s.grp = grp_mask;
+ af_lf_ctl.s.pri = pri ? 1 : 0;
+ ret = otx2_cpt_af_reg_write(dev, OTX2_CPT_AF_LF_CTL(qp->id),
+ af_lf_ctl.u);
+ if (ret)
+ return ret;
+
+ /* Set instruction queue base address */
+
+ base.u = otx2_read64(qp->base + OTX2_CPT_LF_Q_BASE);
+ base.s.fault = 0;
+ base.s.stopped = 0;
+ base.s.addr = qp->iq_dma_addr >> 7;
+ otx2_write64(base.u, qp->base + OTX2_CPT_LF_Q_BASE);
+
+ /* Set instruction queue size */
+
+ size.u = otx2_read64(qp->base + OTX2_CPT_LF_Q_SIZE);
+ size.s.size_div40 = size_div40;
+ otx2_write64(size.u, qp->base + OTX2_CPT_LF_Q_SIZE);
+
+ /* Enable instruction queue */
+
+ lf_ctl.u = otx2_read64(qp->base + OTX2_CPT_LF_CTL);
+ lf_ctl.s.ena = 1;
+ otx2_write64(lf_ctl.u, qp->base + OTX2_CPT_LF_CTL);
+
+ /* Start instruction execution */
+
+ inprog.u = otx2_read64(qp->base + OTX2_CPT_LF_INPROG);
+ inprog.s.eena = 1;
+ otx2_write64(inprog.u, qp->base + OTX2_CPT_LF_INPROG);
+
+ return 0;
+}
+
+void
+otx2_cpt_iq_disable(struct otx2_cpt_qp *qp)
+{
+ union otx2_cpt_lf_q_grp_ptr grp_ptr;
+ union otx2_cpt_lf_inprog inprog;
+ union otx2_cpt_lf_ctl ctl;
+ int cnt;
+
+ /* Stop instruction execution */
+ inprog.u = otx2_read64(qp->base + OTX2_CPT_LF_INPROG);
+ inprog.s.eena = 0x0;
+ otx2_write64(inprog.u, qp->base + OTX2_CPT_LF_INPROG);
+
+ /* Disable instructions enqueuing */
+ ctl.u = otx2_read64(qp->base + OTX2_CPT_LF_CTL);
+ ctl.s.ena = 0;
+ otx2_write64(ctl.u, qp->base + OTX2_CPT_LF_CTL);
+
+ /* Wait for instruction queue to become empty */
+ cnt = 0;
+ do {
+ inprog.u = otx2_read64(qp->base + OTX2_CPT_LF_INPROG);
+ if (inprog.s.grb_partial)
+ cnt = 0;
+ else
+ cnt++;
+ grp_ptr.u = otx2_read64(qp->base + OTX2_CPT_LF_Q_GRP_PTR);
+ } while ((cnt < 10) && (grp_ptr.s.nq_ptr != grp_ptr.s.dq_ptr));
+
+ cnt = 0;
+ do {
+ inprog.u = otx2_read64(qp->base + OTX2_CPT_LF_INPROG);
+ if ((inprog.s.inflight == 0) &&
+ (inprog.s.gwb_cnt < 40) &&
+ ((inprog.s.grb_cnt == 0) || (inprog.s.grb_cnt == 40)))
+ cnt++;
+ else
+ cnt = 0;
+ } while (cnt < 10);
+}
diff --git a/drivers/crypto/octeontx2/otx2_cryptodev_hw_access.h b/drivers/crypto/octeontx2/otx2_cryptodev_hw_access.h
index 2af674d..87d4e77 100644
--- a/drivers/crypto/octeontx2/otx2_cryptodev_hw_access.h
+++ b/drivers/crypto/octeontx2/otx2_cryptodev_hw_access.h
@@ -5,23 +5,149 @@
#ifndef _OTX2_CRYPTODEV_HW_ACCESS_H_
#define _OTX2_CRYPTODEV_HW_ACCESS_H_
+#include <stdint.h>
+
#include <rte_cryptodev.h>
+#include <rte_memory.h>
+
+#include "cpt_common.h"
+#include "cpt_hw_types.h"
#include "otx2_dev.h"
+/* CPT instruction queue length */
+#define OTX2_CPT_IQ_LEN 8200
+
+#define OTX2_CPT_DEFAULT_CMD_QLEN OTX2_CPT_IQ_LEN
+
+/* Mask which selects all engine groups */
+#define OTX2_CPT_ENG_GRPS_MASK 0xFF
+
/* Register offsets */
+/* LMT LF registers */
+#define OTX2_LMT_LF_LMTLINE(a) (0x0ull | (uint64_t)(a) << 3)
+
/* CPT LF registers */
+#define OTX2_CPT_LF_CTL 0x10ull
+#define OTX2_CPT_LF_INPROG 0x40ull
#define OTX2_CPT_LF_MISC_INT 0xb0ull
#define OTX2_CPT_LF_MISC_INT_ENA_W1S 0xd0ull
#define OTX2_CPT_LF_MISC_INT_ENA_W1C 0xe0ull
+#define OTX2_CPT_LF_Q_BASE 0xf0ull
+#define OTX2_CPT_LF_Q_SIZE 0x100ull
+#define OTX2_CPT_LF_Q_GRP_PTR 0x120ull
+#define OTX2_CPT_LF_NQ(a) (0x400ull | (uint64_t)(a) << 3)
+
+#define OTX2_CPT_AF_LF_CTL(a) (0x27000ull | (uint64_t)(a) << 3)
#define OTX2_CPT_LF_BAR2(vf, q_id) \
((vf)->otx2_dev.bar2 + \
((RVU_BLOCK_ADDR_CPT0 << 20) | ((q_id) << 12)))
+#define OTX2_CPT_QUEUE_HI_PRIO 0x1
+
+union otx2_cpt_lf_ctl {
+ uint64_t u;
+ struct {
+ uint64_t ena : 1;
+ uint64_t fc_ena : 1;
+ uint64_t fc_up_crossing : 1;
+ uint64_t reserved_3_3 : 1;
+ uint64_t fc_hyst_bits : 4;
+ uint64_t reserved_8_63 : 56;
+ } s;
+};
+
+union otx2_cpt_lf_inprog {
+ uint64_t u;
+ struct {
+ uint64_t inflight : 9;
+ uint64_t reserved_9_15 : 7;
+ uint64_t eena : 1;
+ uint64_t grp_drp : 1;
+ uint64_t reserved_18_30 : 13;
+ uint64_t grb_partial : 1;
+ uint64_t grb_cnt : 8;
+ uint64_t gwb_cnt : 8;
+ uint64_t reserved_48_63 : 16;
+ } s;
+};
+
+union otx2_cpt_lf_q_base {
+ uint64_t u;
+ struct {
+ uint64_t fault : 1;
+ uint64_t stopped : 1;
+ uint64_t reserved_2_6 : 5;
+ uint64_t addr : 46;
+ uint64_t reserved_53_63 : 11;
+ } s;
+};
+
+union otx2_cpt_lf_q_size {
+ uint64_t u;
+ struct {
+ uint64_t size_div40 : 15;
+ uint64_t reserved_15_63 : 49;
+ } s;
+};
+
+union otx2_cpt_af_lf_ctl {
+ uint64_t u;
+ struct {
+ uint64_t pri : 1;
+ uint64_t reserved_1_8 : 8;
+ uint64_t pf_func_inst : 1;
+ uint64_t cont_err : 1;
+ uint64_t reserved_11_15 : 5;
+ uint64_t nixtx_en : 1;
+ uint64_t reserved_17_47 : 31;
+ uint64_t grp : 8;
+ uint64_t reserved_56_63 : 8;
+ } s;
+};
+
+union otx2_cpt_lf_q_grp_ptr {
+ uint64_t u;
+ struct {
+ uint64_t dq_ptr : 15;
+ uint64_t reserved_31_15 : 17;
+ uint64_t nq_ptr : 15;
+ uint64_t reserved_47_62 : 16;
+ uint64_t xq_xor : 1;
+ } s;
+};
+
+struct otx2_cpt_qp {
+ uint32_t id;
+ /**< Queue pair id */
+ uintptr_t base;
+ /**< Base address where BAR is mapped */
+ void *lmtline;
+ /**< Address of LMTLINE */
+ rte_iova_t lf_nq_reg;
+ /**< LF enqueue register address */
+ struct pending_queue pend_q;
+ /**< Pending queue */
+ struct rte_mempool *sess_mp;
+ /**< Session mempool */
+ struct rte_mempool *sess_mp_priv;
+ /**< Session private data mempool */
+ struct cpt_qp_meta_info meta_info;
+ /**< Metabuf info required to support operations on the queue pair */
+ rte_iova_t iq_dma_addr;
+ /**< Instruction queue address */
+};
+
void otx2_cpt_err_intr_unregister(const struct rte_cryptodev *dev);
int otx2_cpt_err_intr_register(const struct rte_cryptodev *dev);
+int otx2_cpt_iq_enable(const struct rte_cryptodev *dev,
+ const struct otx2_cpt_qp *qp, uint8_t grp_mask,
+ uint8_t pri, uint32_t size_div40);
+
+void otx2_cpt_iq_disable(struct otx2_cpt_qp *qp);
+
#endif /* _OTX2_CRYPTODEV_HW_ACCESS_H_ */
diff --git a/drivers/crypto/octeontx2/otx2_cryptodev_mbox.c b/drivers/crypto/octeontx2/otx2_cryptodev_mbox.c
index 9b0117a..b54e407 100644
--- a/drivers/crypto/octeontx2/otx2_cryptodev_mbox.c
+++ b/drivers/crypto/octeontx2/otx2_cryptodev_mbox.c
@@ -8,6 +8,8 @@
#include "otx2_dev.h"
#include "otx2_mbox.h"
+#include "cpt_pmd_logs.h"
+
int
otx2_cpt_available_queues_get(const struct rte_cryptodev *dev,
uint16_t *nb_queues)
@@ -90,3 +92,84 @@ otx2_cpt_msix_offsets_get(const struct rte_cryptodev *dev)
return 0;
}
+
+static int
+otx2_cpt_send_mbox_msg(struct otx2_cpt_vf *vf)
+{
+ struct otx2_mbox *mbox = vf->otx2_dev.mbox;
+ int ret;
+
+ otx2_mbox_msg_send(mbox, 0);
+
+ ret = otx2_mbox_wait_for_rsp(mbox, 0);
+ if (ret < 0) {
+ CPT_LOG_ERR("Could not get mailbox response");
+ return ret;
+ }
+
+ return 0;
+}
+
+int
+otx2_cpt_af_reg_read(const struct rte_cryptodev *dev, uint64_t reg,
+ uint64_t *val)
+{
+ struct otx2_cpt_vf *vf = dev->data->dev_private;
+ struct otx2_mbox *mbox = vf->otx2_dev.mbox;
+ struct otx2_mbox_dev *mdev = &mbox->dev[0];
+ struct cpt_rd_wr_reg_msg *msg;
+ int ret, off;
+
+ msg = (struct cpt_rd_wr_reg_msg *)
+ otx2_mbox_alloc_msg_rsp(mbox, 0, sizeof(*msg),
+ sizeof(*msg));
+ if (msg == NULL) {
+ CPT_LOG_ERR("Could not allocate mailbox message");
+ return -EFAULT;
+ }
+
+ msg->hdr.id = MBOX_MSG_CPT_RD_WR_REGISTER;
+ msg->hdr.sig = OTX2_MBOX_REQ_SIG;
+ msg->hdr.pcifunc = vf->otx2_dev.pf_func;
+ msg->is_write = 0;
+ msg->reg_offset = reg;
+ msg->ret_val = val;
+
+ ret = otx2_cpt_send_mbox_msg(vf);
+ if (ret < 0)
+ return ret;
+
+ off = mbox->rx_start +
+ RTE_ALIGN(sizeof(struct mbox_hdr), MBOX_MSG_ALIGN);
+ msg = (struct cpt_rd_wr_reg_msg *) ((uintptr_t)mdev->mbase + off);
+
+ *val = msg->val;
+
+ return 0;
+}
+
+int
+otx2_cpt_af_reg_write(const struct rte_cryptodev *dev, uint64_t reg,
+ uint64_t val)
+{
+ struct otx2_cpt_vf *vf = dev->data->dev_private;
+ struct otx2_mbox *mbox = vf->otx2_dev.mbox;
+ struct cpt_rd_wr_reg_msg *msg;
+
+ msg = (struct cpt_rd_wr_reg_msg *)
+ otx2_mbox_alloc_msg_rsp(mbox, 0, sizeof(*msg),
+ sizeof(*msg));
+ if (msg == NULL) {
+ CPT_LOG_ERR("Could not allocate mailbox message");
+ return -EFAULT;
+ }
+
+ msg->hdr.id = MBOX_MSG_CPT_RD_WR_REGISTER;
+ msg->hdr.sig = OTX2_MBOX_REQ_SIG;
+ msg->hdr.pcifunc = vf->otx2_dev.pf_func;
+ msg->is_write = 1;
+ msg->reg_offset = reg;
+ msg->val = val;
+
+ return otx2_cpt_send_mbox_msg(vf);
+}
diff --git a/drivers/crypto/octeontx2/otx2_cryptodev_mbox.h b/drivers/crypto/octeontx2/otx2_cryptodev_mbox.h
index 0a43061..a298718 100644
--- a/drivers/crypto/octeontx2/otx2_cryptodev_mbox.h
+++ b/drivers/crypto/octeontx2/otx2_cryptodev_mbox.h
@@ -16,4 +16,10 @@ int otx2_cpt_queues_detach(const struct rte_cryptodev *dev);
int otx2_cpt_msix_offsets_get(const struct rte_cryptodev *dev);
+int otx2_cpt_af_reg_read(const struct rte_cryptodev *dev, uint64_t reg,
+ uint64_t *val);
+
+int otx2_cpt_af_reg_write(const struct rte_cryptodev *dev, uint64_t reg,
+ uint64_t val);
+
#endif /* _OTX2_CRYPTODEV_MBOX_H_ */
diff --git a/drivers/crypto/octeontx2/otx2_cryptodev_ops.c b/drivers/crypto/octeontx2/otx2_cryptodev_ops.c
index b1bb9ae..de53055 100644
--- a/drivers/crypto/octeontx2/otx2_cryptodev_ops.c
+++ b/drivers/crypto/octeontx2/otx2_cryptodev_ops.c
@@ -2,7 +2,10 @@
* Copyright (C) 2019 Marvell International Ltd.
*/
+#include <unistd.h>
+
#include <rte_cryptodev_pmd.h>
+#include <rte_errno.h>
#include "otx2_cryptodev.h"
#include "otx2_cryptodev_hw_access.h"
@@ -12,6 +15,233 @@
#include "cpt_hw_types.h"
#include "cpt_pmd_logs.h"
+#include "cpt_pmd_ops_helper.h"
+
+#define METABUF_POOL_CACHE_SIZE 512
+
+/* Forward declarations */
+
+static int
+otx2_cpt_queue_pair_release(struct rte_cryptodev *dev, uint16_t qp_id);
+
+static void
+qp_memzone_name_get(char *name, int size, int dev_id, int qp_id)
+{
+ snprintf(name, size, "otx2_cpt_lf_mem_%u:%u", dev_id, qp_id);
+}
+
+static int
+otx2_cpt_metabuf_mempool_create(const struct rte_cryptodev *dev,
+ struct otx2_cpt_qp *qp, uint8_t qp_id,
+ int nb_elements)
+{
+ char mempool_name[RTE_MEMPOOL_NAMESIZE];
+ int sg_mlen, lb_mlen, max_mlen, ret;
+ struct cpt_qp_meta_info *meta_info;
+ struct rte_mempool *pool;
+
+ /* Get meta len for scatter gather mode */
+ sg_mlen = cpt_pmd_ops_helper_get_mlen_sg_mode();
+
+ /* Extra 32B saved for future considerations */
+ sg_mlen += 4 * sizeof(uint64_t);
+
+ /* Get meta len for linear buffer (direct) mode */
+ lb_mlen = cpt_pmd_ops_helper_get_mlen_direct_mode();
+
+ /* Extra 32B saved for future considerations */
+ lb_mlen += 4 * sizeof(uint64_t);
+
+ /* Check max requirement for meta buffer */
+ max_mlen = RTE_MAX(lb_mlen, sg_mlen);
+
+ /* Allocate mempool */
+
+ snprintf(mempool_name, RTE_MEMPOOL_NAMESIZE, "otx2_cpt_mb_%u:%u",
+ dev->data->dev_id, qp_id);
+
+ pool = rte_mempool_create_empty(mempool_name, nb_elements, max_mlen,
+ METABUF_POOL_CACHE_SIZE, 0,
+ rte_socket_id(), 0);
+
+ if (pool == NULL) {
+ CPT_LOG_ERR("Could not create mempool for metabuf");
+ return rte_errno;
+ }
+
+ ret = rte_mempool_set_ops_byname(pool, RTE_MBUF_DEFAULT_MEMPOOL_OPS,
+ NULL);
+ if (ret) {
+ CPT_LOG_ERR("Could not set mempool ops");
+ goto mempool_free;
+ }
+
+ ret = rte_mempool_populate_default(pool);
+ if (ret <= 0) {
+ CPT_LOG_ERR("Could not populate metabuf pool");
+ goto mempool_free;
+ }
+
+ meta_info = &qp->meta_info;
+
+ meta_info->pool = pool;
+ meta_info->lb_mlen = lb_mlen;
+ meta_info->sg_mlen = sg_mlen;
+
+ return 0;
+
+mempool_free:
+ rte_mempool_free(pool);
+ return ret;
+}
+
+static void
+otx2_cpt_metabuf_mempool_destroy(struct otx2_cpt_qp *qp)
+{
+ struct cpt_qp_meta_info *meta_info = &qp->meta_info;
+
+ rte_mempool_free(meta_info->pool);
+
+ meta_info->pool = NULL;
+ meta_info->lb_mlen = 0;
+ meta_info->sg_mlen = 0;
+}
+
+static struct otx2_cpt_qp *
+otx2_cpt_qp_create(const struct rte_cryptodev *dev, uint16_t qp_id,
+ uint8_t group)
+{
+ struct otx2_cpt_vf *vf = dev->data->dev_private;
+ uint64_t pg_sz = sysconf(_SC_PAGESIZE);
+ const struct rte_memzone *lf_mem;
+ uint32_t len, iq_len, size_div40;
+ char name[RTE_MEMZONE_NAMESIZE];
+ uint64_t used_len, iova;
+ struct otx2_cpt_qp *qp;
+ uint64_t lmtline;
+ uint8_t *va;
+ int ret;
+
+ /* Allocate queue pair */
+ qp = rte_zmalloc_socket("OCTEON TX2 Crypto PMD Queue Pair", sizeof(*qp),
+ OTX2_ALIGN, 0);
+ if (qp == NULL) {
+ CPT_LOG_ERR("Could not allocate queue pair");
+ return NULL;
+ }
+
+ iq_len = OTX2_CPT_IQ_LEN;
+
+ /*
+ * Queue size must be a multiple of 40 and effective queue size to
+ * software is (size_div40 - 1) * 40
+ */
+ size_div40 = (iq_len + 40 - 1) / 40 + 1;
+
+ /* For pending queue */
+ len = iq_len * RTE_ALIGN(sizeof(struct rid), 8);
+
+ /* Space for instruction group memory */
+ len += size_div40 * 16;
+
+ /* So that instruction queues start as pg size aligned */
+ len = RTE_ALIGN(len, pg_sz);
+
+ /* For instruction queues */
+ len += OTX2_CPT_IQ_LEN * sizeof(union cpt_inst_s);
+
+ /* Wastage after instruction queues */
+ len = RTE_ALIGN(len, pg_sz);
+
+ qp_memzone_name_get(name, RTE_MEMZONE_NAMESIZE, dev->data->dev_id,
+ qp_id);
+
+ lf_mem = rte_memzone_reserve_aligned(name, len, vf->otx2_dev.node,
+ RTE_MEMZONE_SIZE_HINT_ONLY | RTE_MEMZONE_256MB,
+ RTE_CACHE_LINE_SIZE);
+ if (lf_mem == NULL) {
+ CPT_LOG_ERR("Could not allocate reserved memzone");
+ goto qp_free;
+ }
+
+ va = lf_mem->addr;
+ iova = lf_mem->iova;
+
+ memset(va, 0, len);
+
+ ret = otx2_cpt_metabuf_mempool_create(dev, qp, qp_id, iq_len);
+ if (ret) {
+ CPT_LOG_ERR("Could not create mempool for metabuf");
+ goto lf_mem_free;
+ }
+
+ /* Initialize pending queue */
+ qp->pend_q.rid_queue = (struct rid *)va;
+ qp->pend_q.enq_tail = 0;
+ qp->pend_q.deq_head = 0;
+ qp->pend_q.pending_count = 0;
+
+ used_len = iq_len * RTE_ALIGN(sizeof(struct rid), 8);
+ used_len += size_div40 * 16;
+ used_len = RTE_ALIGN(used_len, pg_sz);
+ iova += used_len;
+
+ qp->iq_dma_addr = iova;
+ qp->id = qp_id;
+ qp->base = OTX2_CPT_LF_BAR2(vf, qp_id);
+
+ lmtline = vf->otx2_dev.bar2 +
+ (RVU_BLOCK_ADDR_LMT << 20 | qp_id << 12) +
+ OTX2_LMT_LF_LMTLINE(0);
+
+ qp->lmtline = (void *)lmtline;
+
+ qp->lf_nq_reg = qp->base + OTX2_CPT_LF_NQ(0);
+
+ otx2_cpt_iq_disable(qp);
+
+ ret = otx2_cpt_iq_enable(dev, qp, group, OTX2_CPT_QUEUE_HI_PRIO,
+ size_div40);
+ if (ret) {
+ CPT_LOG_ERR("Could not enable instruction queue");
+ goto mempool_destroy;
+ }
+
+ return qp;
+
+mempool_destroy:
+ otx2_cpt_metabuf_mempool_destroy(qp);
+lf_mem_free:
+ rte_memzone_free(lf_mem);
+qp_free:
+ rte_free(qp);
+ return NULL;
+}
+
+static int
+otx2_cpt_qp_destroy(const struct rte_cryptodev *dev, struct otx2_cpt_qp *qp)
+{
+ const struct rte_memzone *lf_mem;
+ char name[RTE_MEMZONE_NAMESIZE];
+ int ret;
+
+ otx2_cpt_iq_disable(qp);
+
+ otx2_cpt_metabuf_mempool_destroy(qp);
+
+ qp_memzone_name_get(name, RTE_MEMZONE_NAMESIZE, dev->data->dev_id,
+ qp->id);
+
+ lf_mem = rte_memzone_lookup(name);
+
+ ret = rte_memzone_free(lf_mem);
+ if (ret)
+ return ret;
+
+ rte_free(qp);
+
+ return 0;
+}
/* PMD ops */
@@ -91,7 +321,13 @@ otx2_cpt_dev_stop(struct rte_cryptodev *dev)
static int
otx2_cpt_dev_close(struct rte_cryptodev *dev)
{
- int ret;
+ int i, ret;
+
+ for (i = 0; i < dev->data->nb_queue_pairs; i++) {
+ ret = otx2_cpt_queue_pair_release(dev, i);
+ if (ret)
+ return ret;
+ }
otx2_cpt_err_intr_unregister(dev);
@@ -119,6 +355,70 @@ otx2_cpt_dev_info_get(struct rte_cryptodev *dev,
}
}
+static int
+otx2_cpt_queue_pair_setup(struct rte_cryptodev *dev, uint16_t qp_id,
+ const struct rte_cryptodev_qp_conf *conf,
+ int socket_id __rte_unused)
+{
+ uint8_t grp_mask = OTX2_CPT_ENG_GRPS_MASK;
+ struct rte_pci_device *pci_dev;
+ struct otx2_cpt_qp *qp;
+
+ CPT_PMD_INIT_FUNC_TRACE();
+
+ if (dev->data->queue_pairs[qp_id] != NULL)
+ otx2_cpt_queue_pair_release(dev, qp_id);
+
+ if (conf->nb_descriptors > OTX2_CPT_DEFAULT_CMD_QLEN) {
+ CPT_LOG_ERR("Could not setup queue pair for %u descriptors",
+ conf->nb_descriptors);
+ return -EINVAL;
+ }
+
+ pci_dev = RTE_DEV_TO_PCI(dev->device);
+
+ if (pci_dev->mem_resource[2].addr == NULL) {
+ CPT_LOG_ERR("Invalid PCI mem address");
+ return -EIO;
+ }
+
+ qp = otx2_cpt_qp_create(dev, qp_id, grp_mask);
+ if (qp == NULL) {
+ CPT_LOG_ERR("Could not create queue pair %d", qp_id);
+ return -ENOMEM;
+ }
+
+ qp->sess_mp = conf->mp_session;
+ qp->sess_mp_priv = conf->mp_session_private;
+ dev->data->queue_pairs[qp_id] = qp;
+
+ return 0;
+}
+
+static int
+otx2_cpt_queue_pair_release(struct rte_cryptodev *dev, uint16_t qp_id)
+{
+ struct otx2_cpt_qp *qp = dev->data->queue_pairs[qp_id];
+ int ret;
+
+ CPT_PMD_INIT_FUNC_TRACE();
+
+ if (qp == NULL)
+ return -EINVAL;
+
+ CPT_LOG_INFO("Releasing queue pair %d", qp_id);
+
+ ret = otx2_cpt_qp_destroy(dev, qp);
+ if (ret) {
+ CPT_LOG_ERR("Could not destroy queue pair %d", qp_id);
+ return ret;
+ }
+
+ dev->data->queue_pairs[qp_id] = NULL;
+
+ return 0;
+}
+
struct rte_cryptodev_ops otx2_cpt_ops = {
/* Device control ops */
.dev_configure = otx2_cpt_dev_config,
@@ -129,8 +429,8 @@ struct rte_cryptodev_ops otx2_cpt_ops = {
.stats_get = NULL,
.stats_reset = NULL,
- .queue_pair_setup = NULL,
- .queue_pair_release = NULL,
+ .queue_pair_setup = otx2_cpt_queue_pair_setup,
+ .queue_pair_release = otx2_cpt_queue_pair_release,
.queue_pair_count = NULL,
/* Symmetric crypto ops */
--
2.7.4
^ permalink raw reply related [flat|nested] 53+ messages in thread* [dpdk-dev] [PATCH v2 05/12] crypto/octeontx2: add symmetric capabilities
2019-10-13 12:39 ` [dpdk-dev] [PATCH v2 00/12] " Anoob Joseph
` (3 preceding siblings ...)
2019-10-13 12:39 ` [dpdk-dev] [PATCH v2 04/12] crypto/octeontx2: add queue pair functions Anoob Joseph
@ 2019-10-13 12:39 ` Anoob Joseph
2019-10-13 12:39 ` [dpdk-dev] [PATCH v2 06/12] crypto/octeontx2: add session related functions Anoob Joseph
` (8 subsequent siblings)
13 siblings, 0 replies; 53+ messages in thread
From: Anoob Joseph @ 2019-10-13 12:39 UTC (permalink / raw)
To: Akhil Goyal, Pablo de Lara
Cc: Anoob Joseph, Fiona Trahe, Jerin Jacob, Narayana Prasad,
Shally Verma, Ankur Dwivedi, Kanaka Durga Kotamarthy, Sunila Sahu,
Tejasree Kondoj, dev
This patch adds the symmetric capabilities for OCTEON TX2 crypto PMD.
Signed-off-by: Ankur Dwivedi <adwivedi@marvell.com>
Signed-off-by: Anoob Joseph <anoobj@marvell.com>
Signed-off-by: Tejasree Kondoj <ktejasree@marvell.com>
---
doc/guides/cryptodevs/features/octeontx2.ini | 59 ++
doc/guides/cryptodevs/octeontx2.rst | 41 ++
drivers/crypto/octeontx2/Makefile | 1 +
drivers/crypto/octeontx2/meson.build | 1 +
drivers/crypto/octeontx2/otx2_cryptodev.c | 6 +-
.../crypto/octeontx2/otx2_cryptodev_capabilities.c | 604 +++++++++++++++++++++
.../crypto/octeontx2/otx2_cryptodev_capabilities.h | 16 +
drivers/crypto/octeontx2/otx2_cryptodev_ops.c | 3 +-
8 files changed, 729 insertions(+), 2 deletions(-)
create mode 100644 drivers/crypto/octeontx2/otx2_cryptodev_capabilities.c
create mode 100644 drivers/crypto/octeontx2/otx2_cryptodev_capabilities.h
diff --git a/doc/guides/cryptodevs/features/octeontx2.ini b/doc/guides/cryptodevs/features/octeontx2.ini
index 35c9bee..4e82463 100644
--- a/doc/guides/cryptodevs/features/octeontx2.ini
+++ b/doc/guides/cryptodevs/features/octeontx2.ini
@@ -5,4 +5,63 @@
;
[Features]
Symmetric crypto = Y
+Sym operation chaining = Y
HW Accelerated = Y
+In Place SGL = Y
+OOP SGL In LB Out = Y
+OOP SGL In SGL Out = Y
+
+;
+; Supported crypto algorithms of 'octeontx2' crypto driver.
+;
+[Cipher]
+NULL = Y
+3DES CBC = Y
+3DES ECB = Y
+AES CBC (128) = Y
+AES CBC (192) = Y
+AES CBC (256) = Y
+AES CTR (128) = Y
+AES CTR (192) = Y
+AES CTR (256) = Y
+AES XTS (128) = Y
+AES XTS (256) = Y
+DES CBC = Y
+KASUMI F8 = Y
+SNOW3G UEA2 = Y
+ZUC EEA3 = Y
+
+;
+; Supported authentication algorithms of 'octeontx2' crypto driver.
+;
+[Auth]
+NULL = Y
+AES GMAC = Y
+KASUMI F9 = Y
+MD5 = Y
+MD5 HMAC = Y
+SHA1 = Y
+SHA1 HMAC = Y
+SHA224 = Y
+SHA224 HMAC = Y
+SHA256 = Y
+SHA256 HMAC = Y
+SHA384 = Y
+SHA384 HMAC = Y
+SHA512 = Y
+SHA512 HMAC = Y
+SNOW3G UIA2 = Y
+ZUC EIA3 = Y
+
+;
+; Supported AEAD algorithms of 'octeontx2' crypto driver.
+;
+[AEAD]
+AES GCM (128) = Y
+AES GCM (192) = Y
+AES GCM (256) = Y
+
+;
+; Supported Asymmetric algorithms of the 'octeontx2' crypto driver.
+;
+[Asymmetric]
diff --git a/doc/guides/cryptodevs/octeontx2.rst b/doc/guides/cryptodevs/octeontx2.rst
index 10f578a..47e9150 100644
--- a/doc/guides/cryptodevs/octeontx2.rst
+++ b/doc/guides/cryptodevs/octeontx2.rst
@@ -16,6 +16,47 @@ Features
The OCTEON TX2 crypto PMD has support for:
+Symmetric Crypto Algorithms
+~~~~~~~~~~~~~~~~~~~~~~~~~~~
+
+Cipher algorithms:
+
+* ``RTE_CRYPTO_CIPHER_NULL``
+* ``RTE_CRYPTO_CIPHER_3DES_CBC``
+* ``RTE_CRYPTO_CIPHER_3DES_ECB``
+* ``RTE_CRYPTO_CIPHER_AES_CBC``
+* ``RTE_CRYPTO_CIPHER_AES_CTR``
+* ``RTE_CRYPTO_CIPHER_AES_XTS``
+* ``RTE_CRYPTO_CIPHER_DES_CBC``
+* ``RTE_CRYPTO_CIPHER_KASUMI_F8``
+* ``RTE_CRYPTO_CIPHER_SNOW3G_UEA2``
+* ``RTE_CRYPTO_CIPHER_ZUC_EEA3``
+
+Hash algorithms:
+
+* ``RTE_CRYPTO_AUTH_NULL``
+* ``RTE_CRYPTO_AUTH_AES_GMAC``
+* ``RTE_CRYPTO_AUTH_KASUMI_F9``
+* ``RTE_CRYPTO_AUTH_MD5``
+* ``RTE_CRYPTO_AUTH_MD5_HMAC``
+* ``RTE_CRYPTO_AUTH_SHA1``
+* ``RTE_CRYPTO_AUTH_SHA1_HMAC``
+* ``RTE_CRYPTO_AUTH_SHA224``
+* ``RTE_CRYPTO_AUTH_SHA224_HMAC``
+* ``RTE_CRYPTO_AUTH_SHA256``
+* ``RTE_CRYPTO_AUTH_SHA256_HMAC``
+* ``RTE_CRYPTO_AUTH_SHA384``
+* ``RTE_CRYPTO_AUTH_SHA384_HMAC``
+* ``RTE_CRYPTO_AUTH_SHA512``
+* ``RTE_CRYPTO_AUTH_SHA512_HMAC``
+* ``RTE_CRYPTO_AUTH_SNOW3G_UIA2``
+* ``RTE_CRYPTO_AUTH_ZUC_EIA3``
+
+AEAD algorithms:
+
+* ``RTE_CRYPTO_AEAD_AES_GCM``
+
+
Installation
------------
diff --git a/drivers/crypto/octeontx2/Makefile b/drivers/crypto/octeontx2/Makefile
index 71bc4d1..968efac 100644
--- a/drivers/crypto/octeontx2/Makefile
+++ b/drivers/crypto/octeontx2/Makefile
@@ -35,6 +35,7 @@ endif
# PMD code
SRCS-$(CONFIG_RTE_LIBRTE_PMD_OCTEONTX2_CRYPTO) += otx2_cryptodev.c
+SRCS-$(CONFIG_RTE_LIBRTE_PMD_OCTEONTX2_CRYPTO) += otx2_cryptodev_capabilities.c
SRCS-$(CONFIG_RTE_LIBRTE_PMD_OCTEONTX2_CRYPTO) += otx2_cryptodev_hw_access.c
SRCS-$(CONFIG_RTE_LIBRTE_PMD_OCTEONTX2_CRYPTO) += otx2_cryptodev_mbox.c
SRCS-$(CONFIG_RTE_LIBRTE_PMD_OCTEONTX2_CRYPTO) += otx2_cryptodev_ops.c
diff --git a/drivers/crypto/octeontx2/meson.build b/drivers/crypto/octeontx2/meson.build
index 944fa2c..ee2e907 100644
--- a/drivers/crypto/octeontx2/meson.build
+++ b/drivers/crypto/octeontx2/meson.build
@@ -11,6 +11,7 @@ deps += ['common_octeontx2']
name = 'octeontx2_crypto'
sources = files('otx2_cryptodev.c',
+ 'otx2_cryptodev_capabilities.c',
'otx2_cryptodev_hw_access.c',
'otx2_cryptodev_mbox.c',
'otx2_cryptodev_ops.c')
diff --git a/drivers/crypto/octeontx2/otx2_cryptodev.c b/drivers/crypto/octeontx2/otx2_cryptodev.c
index efc17cb..32c0b48 100644
--- a/drivers/crypto/octeontx2/otx2_cryptodev.c
+++ b/drivers/crypto/octeontx2/otx2_cryptodev.c
@@ -95,7 +95,11 @@ otx2_cpt_pci_probe(struct rte_pci_driver *pci_drv __rte_unused,
CPT_LOG_INFO("Max queues supported by device: %d", vf->max_queues);
dev->feature_flags = RTE_CRYPTODEV_FF_SYMMETRIC_CRYPTO |
- RTE_CRYPTODEV_FF_HW_ACCELERATED;
+ RTE_CRYPTODEV_FF_HW_ACCELERATED |
+ RTE_CRYPTODEV_FF_SYM_OPERATION_CHAINING |
+ RTE_CRYPTODEV_FF_IN_PLACE_SGL |
+ RTE_CRYPTODEV_FF_OOP_SGL_IN_LB_OUT |
+ RTE_CRYPTODEV_FF_OOP_SGL_IN_SGL_OUT;
return 0;
diff --git a/drivers/crypto/octeontx2/otx2_cryptodev_capabilities.c b/drivers/crypto/octeontx2/otx2_cryptodev_capabilities.c
new file mode 100644
index 0000000..3a70470
--- /dev/null
+++ b/drivers/crypto/octeontx2/otx2_cryptodev_capabilities.c
@@ -0,0 +1,604 @@
+/* SPDX-License-Identifier: BSD-3-Clause
+ * Copyright (C) 2019 Marvell International Ltd.
+ */
+
+#include <rte_cryptodev.h>
+
+#include "otx2_cryptodev_capabilities.h"
+
+static const struct rte_cryptodev_capabilities otx2_cpt_sym_capabilities[] = {
+ /* Symmetric capabilities */
+ { /* NULL (AUTH) */
+ .op = RTE_CRYPTO_OP_TYPE_SYMMETRIC,
+ {.sym = {
+ .xform_type = RTE_CRYPTO_SYM_XFORM_AUTH,
+ {.auth = {
+ .algo = RTE_CRYPTO_AUTH_NULL,
+ .block_size = 1,
+ .key_size = {
+ .min = 0,
+ .max = 0,
+ .increment = 0
+ },
+ .digest_size = {
+ .min = 0,
+ .max = 0,
+ .increment = 0
+ },
+ }, },
+ }, },
+ },
+ { /* AES GMAC (AUTH) */
+ .op = RTE_CRYPTO_OP_TYPE_SYMMETRIC,
+ {.sym = {
+ .xform_type = RTE_CRYPTO_SYM_XFORM_AUTH,
+ {.auth = {
+ .algo = RTE_CRYPTO_AUTH_AES_GMAC,
+ .block_size = 16,
+ .key_size = {
+ .min = 16,
+ .max = 32,
+ .increment = 8
+ },
+ .digest_size = {
+ .min = 8,
+ .max = 16,
+ .increment = 4
+ },
+ .iv_size = {
+ .min = 12,
+ .max = 12,
+ .increment = 0
+ }
+ }, }
+ }, }
+ },
+ { /* KASUMI (F9) */
+ .op = RTE_CRYPTO_OP_TYPE_SYMMETRIC,
+ {.sym = {
+ .xform_type = RTE_CRYPTO_SYM_XFORM_AUTH,
+ {.auth = {
+ .algo = RTE_CRYPTO_AUTH_KASUMI_F9,
+ .block_size = 8,
+ .key_size = {
+ .min = 16,
+ .max = 16,
+ .increment = 0
+ },
+ .digest_size = {
+ .min = 4,
+ .max = 4,
+ .increment = 0
+ },
+ }, }
+ }, }
+ },
+ { /* MD5 */
+ .op = RTE_CRYPTO_OP_TYPE_SYMMETRIC,
+ {.sym = {
+ .xform_type = RTE_CRYPTO_SYM_XFORM_AUTH,
+ {.auth = {
+ .algo = RTE_CRYPTO_AUTH_MD5,
+ .block_size = 64,
+ .key_size = {
+ .min = 0,
+ .max = 0,
+ .increment = 0
+ },
+ .digest_size = {
+ .min = 16,
+ .max = 16,
+ .increment = 0
+ },
+ }, }
+ }, }
+ },
+ { /* MD5 HMAC */
+ .op = RTE_CRYPTO_OP_TYPE_SYMMETRIC,
+ {.sym = {
+ .xform_type = RTE_CRYPTO_SYM_XFORM_AUTH,
+ {.auth = {
+ .algo = RTE_CRYPTO_AUTH_MD5_HMAC,
+ .block_size = 64,
+ .key_size = {
+ .min = 8,
+ .max = 64,
+ .increment = 8
+ },
+ .digest_size = {
+ .min = 16,
+ .max = 16,
+ .increment = 0
+ },
+ }, }
+ }, }
+ },
+ { /* SHA1 */
+ .op = RTE_CRYPTO_OP_TYPE_SYMMETRIC,
+ {.sym = {
+ .xform_type = RTE_CRYPTO_SYM_XFORM_AUTH,
+ {.auth = {
+ .algo = RTE_CRYPTO_AUTH_SHA1,
+ .block_size = 64,
+ .key_size = {
+ .min = 0,
+ .max = 0,
+ .increment = 0
+ },
+ .digest_size = {
+ .min = 20,
+ .max = 20,
+ .increment = 0
+ },
+ }, }
+ }, }
+ },
+ { /* SHA1 HMAC */
+ .op = RTE_CRYPTO_OP_TYPE_SYMMETRIC,
+ {.sym = {
+ .xform_type = RTE_CRYPTO_SYM_XFORM_AUTH,
+ {.auth = {
+ .algo = RTE_CRYPTO_AUTH_SHA1_HMAC,
+ .block_size = 64,
+ .key_size = {
+ .min = 64,
+ .max = 64,
+ .increment = 0
+ },
+ .digest_size = {
+ .min = 20,
+ .max = 20,
+ .increment = 0
+ },
+ }, }
+ }, }
+ },
+ { /* SHA224 */
+ .op = RTE_CRYPTO_OP_TYPE_SYMMETRIC,
+ {.sym = {
+ .xform_type = RTE_CRYPTO_SYM_XFORM_AUTH,
+ {.auth = {
+ .algo = RTE_CRYPTO_AUTH_SHA224,
+ .block_size = 64,
+ .key_size = {
+ .min = 0,
+ .max = 0,
+ .increment = 0
+ },
+ .digest_size = {
+ .min = 28,
+ .max = 28,
+ .increment = 0
+ },
+ }, }
+ }, }
+ },
+ { /* SHA224 HMAC */
+ .op = RTE_CRYPTO_OP_TYPE_SYMMETRIC,
+ {.sym = {
+ .xform_type = RTE_CRYPTO_SYM_XFORM_AUTH,
+ {.auth = {
+ .algo = RTE_CRYPTO_AUTH_SHA224_HMAC,
+ .block_size = 64,
+ .key_size = {
+ .min = 64,
+ .max = 64,
+ .increment = 0
+ },
+ .digest_size = {
+ .min = 28,
+ .max = 28,
+ .increment = 0
+ },
+ }, }
+ }, }
+ },
+ { /* SHA256 */
+ .op = RTE_CRYPTO_OP_TYPE_SYMMETRIC,
+ {.sym = {
+ .xform_type = RTE_CRYPTO_SYM_XFORM_AUTH,
+ {.auth = {
+ .algo = RTE_CRYPTO_AUTH_SHA256,
+ .block_size = 64,
+ .key_size = {
+ .min = 0,
+ .max = 0,
+ .increment = 0
+ },
+ .digest_size = {
+ .min = 32,
+ .max = 32,
+ .increment = 0
+ },
+ }, }
+ }, }
+ },
+ { /* SHA256 HMAC */
+ .op = RTE_CRYPTO_OP_TYPE_SYMMETRIC,
+ {.sym = {
+ .xform_type = RTE_CRYPTO_SYM_XFORM_AUTH,
+ {.auth = {
+ .algo = RTE_CRYPTO_AUTH_SHA256_HMAC,
+ .block_size = 64,
+ .key_size = {
+ .min = 64,
+ .max = 64,
+ .increment = 0
+ },
+ .digest_size = {
+ .min = 32,
+ .max = 32,
+ .increment = 0
+ },
+ }, }
+ }, }
+ },
+ { /* SHA384 */
+ .op = RTE_CRYPTO_OP_TYPE_SYMMETRIC,
+ {.sym = {
+ .xform_type = RTE_CRYPTO_SYM_XFORM_AUTH,
+ {.auth = {
+ .algo = RTE_CRYPTO_AUTH_SHA384,
+ .block_size = 64,
+ .key_size = {
+ .min = 0,
+ .max = 0,
+ .increment = 0
+ },
+ .digest_size = {
+ .min = 48,
+ .max = 48,
+ .increment = 0
+ },
+ }, }
+ }, }
+ },
+ { /* SHA384 HMAC */
+ .op = RTE_CRYPTO_OP_TYPE_SYMMETRIC,
+ {.sym = {
+ .xform_type = RTE_CRYPTO_SYM_XFORM_AUTH,
+ {.auth = {
+ .algo = RTE_CRYPTO_AUTH_SHA384_HMAC,
+ .block_size = 64,
+ .key_size = {
+ .min = 64,
+ .max = 64,
+ .increment = 0
+ },
+ .digest_size = {
+ .min = 48,
+ .max = 48,
+ .increment = 0
+ },
+ }, }
+ }, }
+ },
+ { /* SHA512 */
+ .op = RTE_CRYPTO_OP_TYPE_SYMMETRIC,
+ {.sym = {
+ .xform_type = RTE_CRYPTO_SYM_XFORM_AUTH,
+ {.auth = {
+ .algo = RTE_CRYPTO_AUTH_SHA512,
+ .block_size = 128,
+ .key_size = {
+ .min = 0,
+ .max = 0,
+ .increment = 0
+ },
+ .digest_size = {
+ .min = 64,
+ .max = 64,
+ .increment = 0
+ },
+ }, }
+ }, }
+ },
+ { /* SHA512 HMAC */
+ .op = RTE_CRYPTO_OP_TYPE_SYMMETRIC,
+ {.sym = {
+ .xform_type = RTE_CRYPTO_SYM_XFORM_AUTH,
+ {.auth = {
+ .algo = RTE_CRYPTO_AUTH_SHA512_HMAC,
+ .block_size = 128,
+ .key_size = {
+ .min = 64,
+ .max = 64,
+ .increment = 0
+ },
+ .digest_size = {
+ .min = 64,
+ .max = 64,
+ .increment = 0
+ },
+ }, }
+ }, }
+ },
+ { /* SNOW 3G (UIA2) */
+ .op = RTE_CRYPTO_OP_TYPE_SYMMETRIC,
+ {.sym = {
+ .xform_type = RTE_CRYPTO_SYM_XFORM_AUTH,
+ {.auth = {
+ .algo = RTE_CRYPTO_AUTH_SNOW3G_UIA2,
+ .block_size = 16,
+ .key_size = {
+ .min = 16,
+ .max = 16,
+ .increment = 0
+ },
+ .digest_size = {
+ .min = 4,
+ .max = 4,
+ .increment = 0
+ },
+ .iv_size = {
+ .min = 16,
+ .max = 16,
+ .increment = 0
+ }
+ }, }
+ }, }
+ },
+ { /* ZUC (EIA3) */
+ .op = RTE_CRYPTO_OP_TYPE_SYMMETRIC,
+ {.sym = {
+ .xform_type = RTE_CRYPTO_SYM_XFORM_AUTH,
+ {.auth = {
+ .algo = RTE_CRYPTO_AUTH_ZUC_EIA3,
+ .block_size = 16,
+ .key_size = {
+ .min = 16,
+ .max = 16,
+ .increment = 0
+ },
+ .digest_size = {
+ .min = 4,
+ .max = 4,
+ .increment = 0
+ },
+ .iv_size = {
+ .min = 16,
+ .max = 16,
+ .increment = 0
+ }
+ }, }
+ }, }
+ },
+ { /* NULL (CIPHER) */
+ .op = RTE_CRYPTO_OP_TYPE_SYMMETRIC,
+ {.sym = {
+ .xform_type = RTE_CRYPTO_SYM_XFORM_CIPHER,
+ {.cipher = {
+ .algo = RTE_CRYPTO_CIPHER_NULL,
+ .block_size = 1,
+ .key_size = {
+ .min = 0,
+ .max = 0,
+ .increment = 0
+ },
+ .iv_size = {
+ .min = 0,
+ .max = 0,
+ .increment = 0
+ }
+ }, },
+ }, }
+ },
+ { /* 3DES CBC */
+ .op = RTE_CRYPTO_OP_TYPE_SYMMETRIC,
+ {.sym = {
+ .xform_type = RTE_CRYPTO_SYM_XFORM_CIPHER,
+ {.cipher = {
+ .algo = RTE_CRYPTO_CIPHER_3DES_CBC,
+ .block_size = 8,
+ .key_size = {
+ .min = 24,
+ .max = 24,
+ .increment = 0
+ },
+ .iv_size = {
+ .min = 8,
+ .max = 16,
+ .increment = 8
+ }
+ }, }
+ }, }
+ },
+ { /* 3DES ECB */
+ .op = RTE_CRYPTO_OP_TYPE_SYMMETRIC,
+ {.sym = {
+ .xform_type = RTE_CRYPTO_SYM_XFORM_CIPHER,
+ {.cipher = {
+ .algo = RTE_CRYPTO_CIPHER_3DES_ECB,
+ .block_size = 8,
+ .key_size = {
+ .min = 24,
+ .max = 24,
+ .increment = 0
+ },
+ .iv_size = {
+ .min = 0,
+ .max = 0,
+ .increment = 0
+ }
+ }, }
+ }, }
+ },
+ { /* AES CBC */
+ .op = RTE_CRYPTO_OP_TYPE_SYMMETRIC,
+ {.sym = {
+ .xform_type = RTE_CRYPTO_SYM_XFORM_CIPHER,
+ {.cipher = {
+ .algo = RTE_CRYPTO_CIPHER_AES_CBC,
+ .block_size = 16,
+ .key_size = {
+ .min = 16,
+ .max = 32,
+ .increment = 8
+ },
+ .iv_size = {
+ .min = 16,
+ .max = 16,
+ .increment = 0
+ }
+ }, }
+ }, }
+ },
+ { /* AES CTR */
+ .op = RTE_CRYPTO_OP_TYPE_SYMMETRIC,
+ {.sym = {
+ .xform_type = RTE_CRYPTO_SYM_XFORM_CIPHER,
+ {.cipher = {
+ .algo = RTE_CRYPTO_CIPHER_AES_CTR,
+ .block_size = 16,
+ .key_size = {
+ .min = 16,
+ .max = 32,
+ .increment = 8
+ },
+ .iv_size = {
+ .min = 12,
+ .max = 16,
+ .increment = 4
+ }
+ }, }
+ }, }
+ },
+ { /* AES XTS */
+ .op = RTE_CRYPTO_OP_TYPE_SYMMETRIC,
+ {.sym = {
+ .xform_type = RTE_CRYPTO_SYM_XFORM_CIPHER,
+ {.cipher = {
+ .algo = RTE_CRYPTO_CIPHER_AES_XTS,
+ .block_size = 16,
+ .key_size = {
+ .min = 32,
+ .max = 64,
+ .increment = 0
+ },
+ .iv_size = {
+ .min = 16,
+ .max = 16,
+ .increment = 0
+ }
+ }, }
+ }, }
+ },
+ { /* DES CBC */
+ .op = RTE_CRYPTO_OP_TYPE_SYMMETRIC,
+ {.sym = {
+ .xform_type = RTE_CRYPTO_SYM_XFORM_CIPHER,
+ {.cipher = {
+ .algo = RTE_CRYPTO_CIPHER_DES_CBC,
+ .block_size = 8,
+ .key_size = {
+ .min = 8,
+ .max = 8,
+ .increment = 0
+ },
+ .iv_size = {
+ .min = 8,
+ .max = 8,
+ .increment = 0
+ }
+ }, }
+ }, }
+ },
+ { /* KASUMI (F8) */
+ .op = RTE_CRYPTO_OP_TYPE_SYMMETRIC,
+ {.sym = {
+ .xform_type = RTE_CRYPTO_SYM_XFORM_CIPHER,
+ {.cipher = {
+ .algo = RTE_CRYPTO_CIPHER_KASUMI_F8,
+ .block_size = 8,
+ .key_size = {
+ .min = 16,
+ .max = 16,
+ .increment = 0
+ },
+ .iv_size = {
+ .min = 8,
+ .max = 8,
+ .increment = 0
+ }
+ }, }
+ }, }
+ },
+ { /* SNOW 3G (UEA2) */
+ .op = RTE_CRYPTO_OP_TYPE_SYMMETRIC,
+ {.sym = {
+ .xform_type = RTE_CRYPTO_SYM_XFORM_CIPHER,
+ {.cipher = {
+ .algo = RTE_CRYPTO_CIPHER_SNOW3G_UEA2,
+ .block_size = 16,
+ .key_size = {
+ .min = 16,
+ .max = 16,
+ .increment = 0
+ },
+ .iv_size = {
+ .min = 16,
+ .max = 16,
+ .increment = 0
+ }
+ }, }
+ }, }
+ },
+ { /* ZUC (EEA3) */
+ .op = RTE_CRYPTO_OP_TYPE_SYMMETRIC,
+ {.sym = {
+ .xform_type = RTE_CRYPTO_SYM_XFORM_CIPHER,
+ {.cipher = {
+ .algo = RTE_CRYPTO_CIPHER_ZUC_EEA3,
+ .block_size = 16,
+ .key_size = {
+ .min = 16,
+ .max = 16,
+ .increment = 0
+ },
+ .iv_size = {
+ .min = 16,
+ .max = 16,
+ .increment = 0
+ }
+ }, }
+ }, }
+ },
+ { /* AES GCM */
+ .op = RTE_CRYPTO_OP_TYPE_SYMMETRIC,
+ {.sym = {
+ .xform_type = RTE_CRYPTO_SYM_XFORM_AEAD,
+ {.aead = {
+ .algo = RTE_CRYPTO_AEAD_AES_GCM,
+ .block_size = 16,
+ .key_size = {
+ .min = 16,
+ .max = 32,
+ .increment = 8
+ },
+ .digest_size = {
+ .min = 8,
+ .max = 16,
+ .increment = 4
+ },
+ .aad_size = {
+ .min = 0,
+ .max = 1024,
+ .increment = 1
+ },
+ .iv_size = {
+ .min = 12,
+ .max = 12,
+ .increment = 0
+ }
+ }, }
+ }, }
+ },
+ /* End of symmetric capabilities */
+ RTE_CRYPTODEV_END_OF_CAPABILITIES_LIST()
+};
+
+const struct rte_cryptodev_capabilities *
+otx2_cpt_capabilities_get(void)
+{
+ return otx2_cpt_sym_capabilities;
+}
diff --git a/drivers/crypto/octeontx2/otx2_cryptodev_capabilities.h b/drivers/crypto/octeontx2/otx2_cryptodev_capabilities.h
new file mode 100644
index 0000000..f103c32
--- /dev/null
+++ b/drivers/crypto/octeontx2/otx2_cryptodev_capabilities.h
@@ -0,0 +1,16 @@
+/* SPDX-License-Identifier: BSD-3-Clause
+ * Copyright (C) 2019 Marvell International Ltd.
+ */
+
+#ifndef _OTX2_CRYPTODEV_CAPABILITIES_H_
+#define _OTX2_CRYPTODEV_CAPABILITIES_H_
+
+#include <rte_cryptodev.h>
+
+/*
+ * Get capabilities list for the device
+ *
+ */
+const struct rte_cryptodev_capabilities *otx2_cpt_capabilities_get(void);
+
+#endif /* _OTX2_CRYPTODEV_CAPABILITIES_H_ */
diff --git a/drivers/crypto/octeontx2/otx2_cryptodev_ops.c b/drivers/crypto/octeontx2/otx2_cryptodev_ops.c
index de53055..79961f3 100644
--- a/drivers/crypto/octeontx2/otx2_cryptodev_ops.c
+++ b/drivers/crypto/octeontx2/otx2_cryptodev_ops.c
@@ -8,6 +8,7 @@
#include <rte_errno.h>
#include "otx2_cryptodev.h"
+#include "otx2_cryptodev_capabilities.h"
#include "otx2_cryptodev_hw_access.h"
#include "otx2_cryptodev_mbox.h"
#include "otx2_cryptodev_ops.h"
@@ -347,7 +348,7 @@ otx2_cpt_dev_info_get(struct rte_cryptodev *dev,
if (info != NULL) {
info->max_nb_queue_pairs = vf->max_queues;
info->feature_flags = dev->feature_flags;
- info->capabilities = NULL;
+ info->capabilities = otx2_cpt_capabilities_get();
info->sym.max_nb_sessions = 0;
info->driver_id = otx2_cryptodev_driver_id;
info->min_mbuf_headroom_req = OTX2_CPT_MIN_HEADROOM_REQ;
--
2.7.4
^ permalink raw reply related [flat|nested] 53+ messages in thread* [dpdk-dev] [PATCH v2 06/12] crypto/octeontx2: add session related functions
2019-10-13 12:39 ` [dpdk-dev] [PATCH v2 00/12] " Anoob Joseph
` (4 preceding siblings ...)
2019-10-13 12:39 ` [dpdk-dev] [PATCH v2 05/12] crypto/octeontx2: add symmetric capabilities Anoob Joseph
@ 2019-10-13 12:39 ` Anoob Joseph
2019-10-13 12:39 ` [dpdk-dev] [PATCH v2 07/12] crypto/octeontx2: add enqueue/dequeue ops Anoob Joseph
` (7 subsequent siblings)
13 siblings, 0 replies; 53+ messages in thread
From: Anoob Joseph @ 2019-10-13 12:39 UTC (permalink / raw)
To: Akhil Goyal, Pablo de Lara
Cc: Ankur Dwivedi, Fiona Trahe, Jerin Jacob, Narayana Prasad,
Shally Verma, Kanaka Durga Kotamarthy, Sunila Sahu,
Tejasree Kondoj, dev, Anoob Joseph
From: Ankur Dwivedi <adwivedi@marvell.com>
This patch adds the symmetric session related callbacks.
Signed-off-by: Ankur Dwivedi <adwivedi@marvell.com>
Signed-off-by: Anoob Joseph <anoobj@marvell.com>
Signed-off-by: Tejasree Kondoj <ktejasree@marvell.com>
---
drivers/common/cpt/cpt_mcode_defines.h | 2 +
drivers/crypto/octeontx2/otx2_cryptodev_ops.c | 117 +++++++++++++++++++++++++-
drivers/crypto/octeontx2/otx2_cryptodev_ops.h | 5 ++
3 files changed, 121 insertions(+), 3 deletions(-)
diff --git a/drivers/common/cpt/cpt_mcode_defines.h b/drivers/common/cpt/cpt_mcode_defines.h
index 91d30a5..f356e62 100644
--- a/drivers/common/cpt/cpt_mcode_defines.h
+++ b/drivers/common/cpt/cpt_mcode_defines.h
@@ -226,6 +226,8 @@ struct cpt_sess_misc {
uint16_t is_null:1;
/** Flag for GMAC */
uint16_t is_gmac:1;
+ /** Engine group */
+ uint16_t egrp:3;
/** AAD length */
uint16_t aad_length;
/** MAC len in bytes */
diff --git a/drivers/crypto/octeontx2/otx2_cryptodev_ops.c b/drivers/crypto/octeontx2/otx2_cryptodev_ops.c
index 79961f3..d4dc1de 100644
--- a/drivers/crypto/octeontx2/otx2_cryptodev_ops.c
+++ b/drivers/crypto/octeontx2/otx2_cryptodev_ops.c
@@ -17,6 +17,7 @@
#include "cpt_hw_types.h"
#include "cpt_pmd_logs.h"
#include "cpt_pmd_ops_helper.h"
+#include "cpt_ucode.h"
#define METABUF_POOL_CACHE_SIZE 512
@@ -244,6 +245,90 @@ otx2_cpt_qp_destroy(const struct rte_cryptodev *dev, struct otx2_cpt_qp *qp)
return 0;
}
+static int
+sym_session_configure(int driver_id, struct rte_crypto_sym_xform *xform,
+ struct rte_cryptodev_sym_session *sess,
+ struct rte_mempool *pool)
+{
+ struct cpt_sess_misc *misc;
+ void *priv;
+ int ret;
+
+ if (unlikely(cpt_is_algo_supported(xform))) {
+ CPT_LOG_ERR("Crypto xform not supported");
+ return -ENOTSUP;
+ }
+
+ if (unlikely(rte_mempool_get(pool, &priv))) {
+ CPT_LOG_ERR("Could not allocate session private data");
+ return -ENOMEM;
+ }
+
+ misc = priv;
+
+ for ( ; xform != NULL; xform = xform->next) {
+ switch (xform->type) {
+ case RTE_CRYPTO_SYM_XFORM_AEAD:
+ ret = fill_sess_aead(xform, misc);
+ break;
+ case RTE_CRYPTO_SYM_XFORM_CIPHER:
+ ret = fill_sess_cipher(xform, misc);
+ break;
+ case RTE_CRYPTO_SYM_XFORM_AUTH:
+ if (xform->auth.algo == RTE_CRYPTO_AUTH_AES_GMAC)
+ ret = fill_sess_gmac(xform, misc);
+ else
+ ret = fill_sess_auth(xform, misc);
+ break;
+ default:
+ ret = -1;
+ }
+
+ if (ret)
+ goto priv_put;
+ }
+
+ set_sym_session_private_data(sess, driver_id, misc);
+
+ misc->ctx_dma_addr = rte_mempool_virt2iova(misc) +
+ sizeof(struct cpt_sess_misc);
+
+ /*
+ * IE engines support IPsec operations
+ * SE engines support IPsec operations and Air-Crypto operations
+ */
+ if (misc->zsk_flag)
+ misc->egrp = OTX2_CPT_EGRP_SE;
+ else
+ misc->egrp = OTX2_CPT_EGRP_SE_IE;
+
+ return 0;
+
+priv_put:
+ rte_mempool_put(pool, priv);
+
+ CPT_LOG_ERR("Crypto xform not supported");
+ return -ENOTSUP;
+}
+
+static void
+sym_session_clear(int driver_id, struct rte_cryptodev_sym_session *sess)
+{
+ void *priv = get_sym_session_private_data(sess, driver_id);
+ struct rte_mempool *pool;
+
+ if (priv == NULL)
+ return;
+
+ memset(priv, 0, cpt_get_session_size());
+
+ pool = rte_mempool_from_obj(priv);
+
+ set_sym_session_private_data(sess, driver_id, NULL);
+
+ rte_mempool_put(pool, priv);
+}
+
/* PMD ops */
static int
@@ -420,6 +505,32 @@ otx2_cpt_queue_pair_release(struct rte_cryptodev *dev, uint16_t qp_id)
return 0;
}
+static unsigned int
+otx2_cpt_sym_session_get_size(struct rte_cryptodev *dev __rte_unused)
+{
+ return cpt_get_session_size();
+}
+
+static int
+otx2_cpt_sym_session_configure(struct rte_cryptodev *dev,
+ struct rte_crypto_sym_xform *xform,
+ struct rte_cryptodev_sym_session *sess,
+ struct rte_mempool *pool)
+{
+ CPT_PMD_INIT_FUNC_TRACE();
+
+ return sym_session_configure(dev->driver_id, xform, sess, pool);
+}
+
+static void
+otx2_cpt_sym_session_clear(struct rte_cryptodev *dev,
+ struct rte_cryptodev_sym_session *sess)
+{
+ CPT_PMD_INIT_FUNC_TRACE();
+
+ return sym_session_clear(dev->driver_id, sess);
+}
+
struct rte_cryptodev_ops otx2_cpt_ops = {
/* Device control ops */
.dev_configure = otx2_cpt_dev_config,
@@ -435,7 +546,7 @@ struct rte_cryptodev_ops otx2_cpt_ops = {
.queue_pair_count = NULL,
/* Symmetric crypto ops */
- .sym_session_get_size = NULL,
- .sym_session_configure = NULL,
- .sym_session_clear = NULL,
+ .sym_session_get_size = otx2_cpt_sym_session_get_size,
+ .sym_session_configure = otx2_cpt_sym_session_configure,
+ .sym_session_clear = otx2_cpt_sym_session_clear,
};
diff --git a/drivers/crypto/octeontx2/otx2_cryptodev_ops.h b/drivers/crypto/octeontx2/otx2_cryptodev_ops.h
index 9bd24e7..ba93a66 100644
--- a/drivers/crypto/octeontx2/otx2_cryptodev_ops.h
+++ b/drivers/crypto/octeontx2/otx2_cryptodev_ops.h
@@ -10,6 +10,11 @@
#define OTX2_CPT_MIN_HEADROOM_REQ 24
#define OTX2_CPT_MIN_TAILROOM_REQ 8
+enum otx2_cpt_egrp {
+ OTX2_CPT_EGRP_SE = 0,
+ OTX2_CPT_EGRP_SE_IE = 1,
+};
+
struct rte_cryptodev_ops otx2_cpt_ops;
#endif /* _OTX2_CRYPTODEV_OPS_H_ */
--
2.7.4
^ permalink raw reply related [flat|nested] 53+ messages in thread* [dpdk-dev] [PATCH v2 07/12] crypto/octeontx2: add enqueue/dequeue ops
2019-10-13 12:39 ` [dpdk-dev] [PATCH v2 00/12] " Anoob Joseph
` (5 preceding siblings ...)
2019-10-13 12:39 ` [dpdk-dev] [PATCH v2 06/12] crypto/octeontx2: add session related functions Anoob Joseph
@ 2019-10-13 12:39 ` Anoob Joseph
2019-10-15 11:19 ` Gavin Hu (Arm Technology China)
2019-10-13 12:39 ` [dpdk-dev] [PATCH v2 08/12] test: add OCTEON TX2 tests Anoob Joseph
` (6 subsequent siblings)
13 siblings, 1 reply; 53+ messages in thread
From: Anoob Joseph @ 2019-10-13 12:39 UTC (permalink / raw)
To: Akhil Goyal, Pablo de Lara
Cc: Anoob Joseph, Fiona Trahe, Jerin Jacob, Narayana Prasad,
Shally Verma, Ankur Dwivedi, Kanaka Durga Kotamarthy, Sunila Sahu,
Tejasree Kondoj, dev
This patch adds the enqueue burst and dequeue burst callbacks for the
OCTEON TX2 crypto driver.
Signed-off-by: Ankur Dwivedi <adwivedi@marvell.com>
Signed-off-by: Anoob Joseph <anoobj@marvell.com>
Signed-off-by: Tejasree Kondoj <ktejasree@marvell.com>
---
drivers/common/cpt/cpt_hw_types.h | 52 ++++
drivers/crypto/octeontx2/Makefile | 1 +
drivers/crypto/octeontx2/meson.build | 1 +
.../crypto/octeontx2/otx2_cryptodev_hw_access.h | 16 ++
drivers/crypto/octeontx2/otx2_cryptodev_ops.c | 289 +++++++++++++++++++++
5 files changed, 359 insertions(+)
diff --git a/drivers/common/cpt/cpt_hw_types.h b/drivers/common/cpt/cpt_hw_types.h
index 4c2893b..e2b127d 100644
--- a/drivers/common/cpt/cpt_hw_types.h
+++ b/drivers/common/cpt/cpt_hw_types.h
@@ -197,6 +197,44 @@ typedef union cpt_inst_s {
};
#endif /* Word 7 - End */
} s8x;
+ struct cpt_inst_s_9s {
+#if (RTE_BYTE_ORDER == RTE_BIG_ENDIAN) /* Word 0 - Big Endian */
+ uint64_t nixtx_addr : 60;
+ uint64_t doneint : 1;
+ uint64_t nixtxl : 3;
+#else /* Word 0 - Little Endian */
+ uint64_t nixtxl : 3;
+ uint64_t doneint : 1;
+ uint64_t nixtx_addr : 60;
+#endif /* Word 0 - End */
+ uint64_t res_addr;
+#if (RTE_BYTE_ORDER == RTE_BIG_ENDIAN) /* Word 2 - Big Endian */
+ uint64_t rvu_pf_func : 16;
+ uint64_t reserved_172_175 : 4;
+ uint64_t grp : 10;
+ uint64_t tt : 2;
+ uint64_t tag : 32;
+#else /* Word 2 - Little Endian */
+ uint64_t tag : 32;
+ uint64_t tt : 2;
+ uint64_t grp : 10;
+ uint64_t reserved_172_175 : 4;
+ uint64_t rvu_pf_func : 16;
+#endif /* Word 2 - End */
+#if (RTE_BYTE_ORDER == RTE_BIG_ENDIAN) /* Word 3 - Big Endian */
+ uint64_t wq_ptr : 61;
+ uint64_t reserved_194_193 : 2;
+ uint64_t qord : 1;
+#else /* Word 3 - Little Endian */
+ uint64_t qord : 1;
+ uint64_t reserved_194_193 : 2;
+ uint64_t wq_ptr : 61;
+#endif /* Word 3 - End */
+ uint64_t ei0;
+ uint64_t ei1;
+ uint64_t ei2;
+ uint64_t ei3;
+ } s9x;
} cpt_inst_s_t;
/**
@@ -243,6 +281,20 @@ typedef union cpt_res_s {
uint64_t reserved_64_127 : 64;
#endif /* Word 1 - End */
} s8x;
+ struct cpt_res_s_9s {
+#if (RTE_BYTE_ORDER == RTE_BIG_ENDIAN) /* Word 0 - Big Endian */
+ uint64_t reserved_17_63:47;
+ uint64_t doneint:1;
+ uint64_t uc_compcode:8;
+ uint64_t compcode:8;
+#else /* Word 0 - Little Endian */
+ uint64_t compcode:8;
+ uint64_t uc_compcode:8;
+ uint64_t doneint:1;
+ uint64_t reserved_17_63:47;
+#endif /* Word 0 - End */
+ uint64_t reserved_64_127;
+ } s9x;
} cpt_res_s_t;
/**
diff --git a/drivers/crypto/octeontx2/Makefile b/drivers/crypto/octeontx2/Makefile
index 968efac..ce116b8 100644
--- a/drivers/crypto/octeontx2/Makefile
+++ b/drivers/crypto/octeontx2/Makefile
@@ -24,6 +24,7 @@ CFLAGS += -O3
CFLAGS += -I$(RTE_SDK)/drivers/common/cpt
CFLAGS += -I$(RTE_SDK)/drivers/common/octeontx2
CFLAGS += -I$(RTE_SDK)/drivers/mempool/octeontx2
+CFLAGS += -DALLOW_EXPERIMENTAL_API
ifneq ($(CONFIG_RTE_ARCH_64),y)
CFLAGS += -Wno-int-to-pointer-cast
diff --git a/drivers/crypto/octeontx2/meson.build b/drivers/crypto/octeontx2/meson.build
index ee2e907..b6e5b73 100644
--- a/drivers/crypto/octeontx2/meson.build
+++ b/drivers/crypto/octeontx2/meson.build
@@ -10,6 +10,7 @@ deps += ['common_cpt']
deps += ['common_octeontx2']
name = 'octeontx2_crypto'
+allow_experimental_apis = true
sources = files('otx2_cryptodev.c',
'otx2_cryptodev_capabilities.c',
'otx2_cryptodev_hw_access.c',
diff --git a/drivers/crypto/octeontx2/otx2_cryptodev_hw_access.h b/drivers/crypto/octeontx2/otx2_cryptodev_hw_access.h
index 87d4e77..6f78aa4 100644
--- a/drivers/crypto/octeontx2/otx2_cryptodev_hw_access.h
+++ b/drivers/crypto/octeontx2/otx2_cryptodev_hw_access.h
@@ -12,6 +12,7 @@
#include "cpt_common.h"
#include "cpt_hw_types.h"
+#include "cpt_mcode_defines.h"
#include "otx2_dev.h"
@@ -119,6 +120,21 @@ union otx2_cpt_lf_q_grp_ptr {
} s;
};
+/*
+ * Enumeration cpt_9x_comp_e
+ *
+ * CPT 9X Completion Enumeration
+ * Enumerates the values of CPT_RES_S[COMPCODE].
+ */
+enum cpt_9x_comp_e {
+ CPT_9X_COMP_E_NOTDONE = 0x00,
+ CPT_9X_COMP_E_GOOD = 0x01,
+ CPT_9X_COMP_E_FAULT = 0x02,
+ CPT_9X_COMP_E_HWERR = 0x04,
+ CPT_9X_COMP_E_INSTERR = 0x05,
+ CPT_9X_COMP_E_LAST_ENTRY = 0x06
+};
+
struct otx2_cpt_qp {
uint32_t id;
/**< Queue pair id */
diff --git a/drivers/crypto/octeontx2/otx2_cryptodev_ops.c b/drivers/crypto/octeontx2/otx2_cryptodev_ops.c
index d4dc1de..ef6e7e7 100644
--- a/drivers/crypto/octeontx2/otx2_cryptodev_ops.c
+++ b/drivers/crypto/octeontx2/otx2_cryptodev_ops.c
@@ -329,6 +329,292 @@ sym_session_clear(int driver_id, struct rte_cryptodev_sym_session *sess)
rte_mempool_put(pool, priv);
}
+static __rte_always_inline int32_t __hot
+otx2_cpt_enqueue_req(const struct otx2_cpt_qp *qp,
+ struct pending_queue *pend_q,
+ struct cpt_request_info *req)
+{
+ void *lmtline = qp->lmtline;
+ union cpt_inst_s inst;
+ uint64_t lmt_status;
+
+ if (unlikely(pend_q->pending_count >= OTX2_CPT_DEFAULT_CMD_QLEN))
+ return -EAGAIN;
+
+ inst.u[0] = 0;
+ inst.s9x.res_addr = req->comp_baddr;
+ inst.u[2] = 0;
+ inst.u[3] = 0;
+
+ inst.s9x.ei0 = req->ist.ei0;
+ inst.s9x.ei1 = req->ist.ei1;
+ inst.s9x.ei2 = req->ist.ei2;
+ inst.s9x.ei3 = req->ist.ei3;
+
+ req->time_out = rte_get_timer_cycles() +
+ DEFAULT_COMMAND_TIMEOUT * rte_get_timer_hz();
+
+ do {
+ /* Copy CPT command to LMTLINE */
+ memcpy(lmtline, &inst, sizeof(inst));
+
+ /*
+ * Make sure compiler does not reorder memcpy and ldeor.
+ * LMTST transactions are always flushed from the write
+ * buffer immediately, a DMB is not required to push out
+ * LMTSTs.
+ */
+ rte_cio_wmb();
+ lmt_status = otx2_lmt_submit(qp->lf_nq_reg);
+ } while (lmt_status == 0);
+
+ pend_q->rid_queue[pend_q->enq_tail].rid = (uintptr_t)req;
+
+ /* We will use soft queue length here to limit requests */
+ MOD_INC(pend_q->enq_tail, OTX2_CPT_DEFAULT_CMD_QLEN);
+ pend_q->pending_count += 1;
+
+ return 0;
+}
+
+static __rte_always_inline int __hot
+otx2_cpt_enqueue_sym(struct otx2_cpt_qp *qp, struct rte_crypto_op *op,
+ struct pending_queue *pend_q)
+{
+ struct rte_crypto_sym_op *sym_op = op->sym;
+ struct cpt_request_info *req;
+ struct cpt_sess_misc *sess;
+ vq_cmd_word3_t *w3;
+ uint64_t cpt_op;
+ void *mdata;
+ int ret;
+
+ sess = get_sym_session_private_data(sym_op->session,
+ otx2_cryptodev_driver_id);
+
+ cpt_op = sess->cpt_op;
+
+ if (cpt_op & CPT_OP_CIPHER_MASK)
+ ret = fill_fc_params(op, sess, &qp->meta_info, &mdata,
+ (void **)&req);
+ else
+ ret = fill_digest_params(op, sess, &qp->meta_info, &mdata,
+ (void **)&req);
+
+ if (unlikely(ret)) {
+ CPT_LOG_DP_ERR("Crypto req : op %p, cpt_op 0x%x ret 0x%x",
+ op, (unsigned int)cpt_op, ret);
+ return ret;
+ }
+
+ w3 = ((vq_cmd_word3_t *)(&req->ist.ei3));
+ w3->s.grp = sess->egrp;
+
+ ret = otx2_cpt_enqueue_req(qp, pend_q, req);
+
+ if (unlikely(ret)) {
+ /* Free buffer allocated by fill params routines */
+ free_op_meta(mdata, qp->meta_info.pool);
+ }
+
+ return ret;
+}
+
+static __rte_always_inline int __hot
+otx2_cpt_enqueue_sym_sessless(struct otx2_cpt_qp *qp, struct rte_crypto_op *op,
+ struct pending_queue *pend_q)
+{
+ const int driver_id = otx2_cryptodev_driver_id;
+ struct rte_crypto_sym_op *sym_op = op->sym;
+ struct rte_cryptodev_sym_session *sess;
+ int ret;
+
+ /* Create temporary session */
+
+ if (rte_mempool_get(qp->sess_mp, (void **)&sess))
+ return -ENOMEM;
+
+ ret = sym_session_configure(driver_id, sym_op->xform, sess,
+ qp->sess_mp_priv);
+ if (ret)
+ goto sess_put;
+
+ sym_op->session = sess;
+
+ ret = otx2_cpt_enqueue_sym(qp, op, pend_q);
+
+ if (unlikely(ret))
+ goto priv_put;
+
+ return 0;
+
+priv_put:
+ sym_session_clear(driver_id, sess);
+sess_put:
+ rte_mempool_put(qp->sess_mp, sess);
+ return ret;
+}
+
+static uint16_t
+otx2_cpt_enqueue_burst(void *qptr, struct rte_crypto_op **ops, uint16_t nb_ops)
+{
+ uint16_t nb_allowed, count = 0;
+ struct otx2_cpt_qp *qp = qptr;
+ struct pending_queue *pend_q;
+ struct rte_crypto_op *op;
+ int ret;
+
+ pend_q = &qp->pend_q;
+
+ nb_allowed = OTX2_CPT_DEFAULT_CMD_QLEN - pend_q->pending_count;
+ if (nb_ops > nb_allowed)
+ nb_ops = nb_allowed;
+
+ for (count = 0; count < nb_ops; count++) {
+ op = ops[count];
+ if (op->type == RTE_CRYPTO_OP_TYPE_SYMMETRIC) {
+ if (op->sess_type == RTE_CRYPTO_OP_WITH_SESSION)
+ ret = otx2_cpt_enqueue_sym(qp, op, pend_q);
+ else
+ ret = otx2_cpt_enqueue_sym_sessless(qp, op,
+ pend_q);
+ } else
+ break;
+
+ if (unlikely(ret))
+ break;
+ }
+
+ return count;
+}
+
+static inline void
+otx2_cpt_dequeue_post_process(struct otx2_cpt_qp *qp, struct rte_crypto_op *cop,
+ uintptr_t *rsp, uint8_t cc)
+{
+ if (cop->type == RTE_CRYPTO_OP_TYPE_SYMMETRIC) {
+ if (likely(cc == NO_ERR)) {
+ /* Verify authentication data if required */
+ if (unlikely(rsp[2]))
+ compl_auth_verify(cop, (uint8_t *)rsp[2],
+ rsp[3]);
+ else
+ cop->status = RTE_CRYPTO_OP_STATUS_SUCCESS;
+ } else {
+ if (cc == ERR_GC_ICV_MISCOMPARE)
+ cop->status = RTE_CRYPTO_OP_STATUS_AUTH_FAILED;
+ else
+ cop->status = RTE_CRYPTO_OP_STATUS_ERROR;
+ }
+
+ if (unlikely(cop->sess_type == RTE_CRYPTO_OP_SESSIONLESS)) {
+ sym_session_clear(otx2_cryptodev_driver_id,
+ cop->sym->session);
+ rte_mempool_put(qp->sess_mp, cop->sym->session);
+ cop->sym->session = NULL;
+ }
+ }
+}
+
+static __rte_always_inline uint8_t
+otx2_cpt_compcode_get(struct cpt_request_info *req)
+{
+ volatile struct cpt_res_s_9s *res;
+ uint8_t ret;
+
+ res = (volatile struct cpt_res_s_9s *)req->completion_addr;
+
+ if (unlikely(res->compcode == CPT_9X_COMP_E_NOTDONE)) {
+ if (rte_get_timer_cycles() < req->time_out)
+ return ERR_REQ_PENDING;
+
+ CPT_LOG_DP_ERR("Request timed out");
+ return ERR_REQ_TIMEOUT;
+ }
+
+ if (likely(res->compcode == CPT_9X_COMP_E_GOOD)) {
+ ret = NO_ERR;
+ if (unlikely(res->uc_compcode)) {
+ ret = res->uc_compcode;
+ CPT_LOG_DP_DEBUG("Request failed with microcode error");
+ CPT_LOG_DP_DEBUG("MC completion code 0x%x",
+ res->uc_compcode);
+ }
+ } else {
+ CPT_LOG_DP_DEBUG("HW completion code 0x%x", res->compcode);
+
+ ret = res->compcode;
+ switch (res->compcode) {
+ case CPT_9X_COMP_E_INSTERR:
+ CPT_LOG_DP_ERR("Request failed with instruction error");
+ break;
+ case CPT_9X_COMP_E_FAULT:
+ CPT_LOG_DP_ERR("Request failed with DMA fault");
+ break;
+ case CPT_9X_COMP_E_HWERR:
+ CPT_LOG_DP_ERR("Request failed with hardware error");
+ break;
+ default:
+ CPT_LOG_DP_ERR("Request failed with unknown completion code");
+ }
+ }
+
+ return ret;
+}
+
+static uint16_t
+otx2_cpt_dequeue_burst(void *qptr, struct rte_crypto_op **ops, uint16_t nb_ops)
+{
+ int i, nb_pending, nb_completed;
+ struct otx2_cpt_qp *qp = qptr;
+ struct pending_queue *pend_q;
+ struct cpt_request_info *req;
+ struct rte_crypto_op *cop;
+ uint8_t cc[nb_ops];
+ struct rid *rid;
+ uintptr_t *rsp;
+ void *metabuf;
+
+ pend_q = &qp->pend_q;
+
+ nb_pending = pend_q->pending_count;
+
+ if (nb_ops > nb_pending)
+ nb_ops = nb_pending;
+
+ for (i = 0; i < nb_ops; i++) {
+ rid = &pend_q->rid_queue[pend_q->deq_head];
+ req = (struct cpt_request_info *)(rid->rid);
+
+ cc[i] = otx2_cpt_compcode_get(req);
+
+ if (unlikely(cc[i] == ERR_REQ_PENDING))
+ break;
+
+ ops[i] = req->op;
+
+ MOD_INC(pend_q->deq_head, OTX2_CPT_DEFAULT_CMD_QLEN);
+ pend_q->pending_count -= 1;
+ }
+
+ nb_completed = i;
+
+ for (i = 0; i < nb_completed; i++) {
+ rsp = (void *)ops[i];
+
+ metabuf = (void *)rsp[0];
+ cop = (void *)rsp[1];
+
+ ops[i] = cop;
+
+ otx2_cpt_dequeue_post_process(qp, cop, rsp, cc[i]);
+
+ free_op_meta(metabuf, qp->meta_info.pool);
+ }
+
+ return nb_completed;
+}
+
/* PMD ops */
static int
@@ -378,6 +664,9 @@ otx2_cpt_dev_config(struct rte_cryptodev *dev,
goto queues_detach;
}
+ dev->enqueue_burst = otx2_cpt_enqueue_burst;
+ dev->dequeue_burst = otx2_cpt_dequeue_burst;
+
rte_mb();
return 0;
--
2.7.4
^ permalink raw reply related [flat|nested] 53+ messages in thread* Re: [dpdk-dev] [PATCH v2 07/12] crypto/octeontx2: add enqueue/dequeue ops
2019-10-13 12:39 ` [dpdk-dev] [PATCH v2 07/12] crypto/octeontx2: add enqueue/dequeue ops Anoob Joseph
@ 2019-10-15 11:19 ` Gavin Hu (Arm Technology China)
2019-10-16 9:57 ` Anoob Joseph
0 siblings, 1 reply; 53+ messages in thread
From: Gavin Hu (Arm Technology China) @ 2019-10-15 11:19 UTC (permalink / raw)
To: Anoob Joseph, Akhil.goyal@nxp.com, Pablo de Lara
Cc: Fiona Trahe, jerinj@marvell.com, Narayana Prasad, Shally Verma,
Ankur Dwivedi, Kanaka Durga Kotamarthy, Sunila Sahu,
Tejasree Kondoj, dev@dpdk.org, Honnappa Nagarahalli, nd, nd
Hi Anoob,
This is a typical producer-consumer case, enqueue and dequeue operations must be conducted in a synchronized way, otherwise stale or earlier-than-arrival data will be got.
Out-of-synchronization issues are more prone to happen on weak memory ordered platforms, like arm and PPC, if execution in the program order is assumed.
I see in this patch MOD_INC() and other reads/writes of the indexes might get reordered with regard to real enqueue and deque operations, this may cause synchronization errors.
I have a fix for rte ring using C11 to keep synchronized operations, please refer to: http://patches.dpdk.org/patch/47733/
/Gavin
> -----Original Message-----
> From: dev <dev-bounces@dpdk.org> On Behalf Of Anoob Joseph
> Sent: Sunday, October 13, 2019 8:40 PM
> To: Akhil.goyal@nxp.com; Pablo de Lara <pablo.de.lara.guarch@intel.com>
> Cc: Anoob Joseph <anoobj@marvell.com>; Fiona Trahe
> <fiona.trahe@intel.com>; jerinj@marvell.com; Narayana Prasad
> <pathreya@marvell.com>; Shally Verma <shallyv@marvell.com>; Ankur
> Dwivedi <adwivedi@marvell.com>; Kanaka Durga Kotamarthy
> <kkotamarthy@marvell.com>; Sunila Sahu <ssahu@marvell.com>; Tejasree
> Kondoj <ktejasree@marvell.com>; dev@dpdk.org
> Subject: [dpdk-dev] [PATCH v2 07/12] crypto/octeontx2: add
> enqueue/dequeue ops
>
> This patch adds the enqueue burst and dequeue burst callbacks for the
> OCTEON TX2 crypto driver.
<snip>
^ permalink raw reply [flat|nested] 53+ messages in thread
* Re: [dpdk-dev] [PATCH v2 07/12] crypto/octeontx2: add enqueue/dequeue ops
2019-10-15 11:19 ` Gavin Hu (Arm Technology China)
@ 2019-10-16 9:57 ` Anoob Joseph
0 siblings, 0 replies; 53+ messages in thread
From: Anoob Joseph @ 2019-10-16 9:57 UTC (permalink / raw)
To: Gavin Hu (Arm Technology China), Akhil.goyal@nxp.com,
Pablo de Lara
Cc: Fiona Trahe, Jerin Jacob Kollanukkaran,
Narayana Prasad Raju Athreya, Shally Verma, Ankur Dwivedi,
Kanaka Durga Kotamarthy, Sunila Sahu, Tejasree Kondoj,
dev@dpdk.org, Honnappa Nagarahalli, nd, nd
Hi Gavin,
Thanks for your review and suggestion. I agree with your suggestion and would be taking up the rework. But since we are close to RC1, I would like to defer this to the next release cycle. This change would touch all features supported and hence, will require an extensive QA internally.
Thanks,
Anoob
> -----Original Message-----
> From: Gavin Hu (Arm Technology China) <Gavin.Hu@arm.com>
> Sent: Tuesday, October 15, 2019 4:50 PM
> To: Anoob Joseph <anoobj@marvell.com>; Akhil.goyal@nxp.com; Pablo de
> Lara <pablo.de.lara.guarch@intel.com>
> Cc: Fiona Trahe <fiona.trahe@intel.com>; Jerin Jacob Kollanukkaran
> <jerinj@marvell.com>; Narayana Prasad Raju Athreya
> <pathreya@marvell.com>; Shally Verma <shallyv@marvell.com>; Ankur
> Dwivedi <adwivedi@marvell.com>; Kanaka Durga Kotamarthy
> <kkotamarthy@marvell.com>; Sunila Sahu <ssahu@marvell.com>; Tejasree
> Kondoj <ktejasree@marvell.com>; dev@dpdk.org; Honnappa Nagarahalli
> <Honnappa.Nagarahalli@arm.com>; nd <nd@arm.com>; nd <nd@arm.com>
> Subject: [EXT] RE: [dpdk-dev] [PATCH v2 07/12] crypto/octeontx2: add
> enqueue/dequeue ops
>
> External Email
>
> ----------------------------------------------------------------------
> Hi Anoob,
>
> This is a typical producer-consumer case, enqueue and dequeue operations
> must be conducted in a synchronized way, otherwise stale or earlier-than-
> arrival data will be got.
> Out-of-synchronization issues are more prone to happen on weak memory
> ordered platforms, like arm and PPC, if execution in the program order is
> assumed.
> I see in this patch MOD_INC() and other reads/writes of the indexes might
> get reordered with regard to real enqueue and deque operations, this may
> cause synchronization errors.
> I have a fix for rte ring using C11 to keep synchronized operations, please
> refer to: https://urldefense.proofpoint.com/v2/url?u=http-
> 3A__patches.dpdk.org_patch_47733_&d=DwIFAg&c=nKjWec2b6R0mOyPaz7
> xtfQ&r=jPfB8rwwviRSxyLWs2n6B-WYLn1v9SyTMrT5EQqh2TU&m=-
> CQNFLhmDggI38cEto5lpU668oUfOgbIO8Akw7ViaVM&s=c5-
> AH2gQk6Kqi_AKdacCs0k-w42Qrisy4Ev9SF3fG6w&e=
> /Gavin
>
> > -----Original Message-----
> > From: dev <dev-bounces@dpdk.org> On Behalf Of Anoob Joseph
> > Sent: Sunday, October 13, 2019 8:40 PM
> > To: Akhil.goyal@nxp.com; Pablo de Lara
> > <pablo.de.lara.guarch@intel.com>
> > Cc: Anoob Joseph <anoobj@marvell.com>; Fiona Trahe
> > <fiona.trahe@intel.com>; jerinj@marvell.com; Narayana Prasad
> > <pathreya@marvell.com>; Shally Verma <shallyv@marvell.com>; Ankur
> > Dwivedi <adwivedi@marvell.com>; Kanaka Durga Kotamarthy
> > <kkotamarthy@marvell.com>; Sunila Sahu <ssahu@marvell.com>;
> Tejasree
> > Kondoj <ktejasree@marvell.com>; dev@dpdk.org
> > Subject: [dpdk-dev] [PATCH v2 07/12] crypto/octeontx2: add
> > enqueue/dequeue ops
> >
> > This patch adds the enqueue burst and dequeue burst callbacks for the
> > OCTEON TX2 crypto driver.
>
> <snip>
^ permalink raw reply [flat|nested] 53+ messages in thread
* [dpdk-dev] [PATCH v2 08/12] test: add OCTEON TX2 tests
2019-10-13 12:39 ` [dpdk-dev] [PATCH v2 00/12] " Anoob Joseph
` (6 preceding siblings ...)
2019-10-13 12:39 ` [dpdk-dev] [PATCH v2 07/12] crypto/octeontx2: add enqueue/dequeue ops Anoob Joseph
@ 2019-10-13 12:39 ` Anoob Joseph
2019-10-13 12:39 ` [dpdk-dev] [PATCH v2 09/12] crypto/octeontx2: allocate memory for asymmetric operation Anoob Joseph
` (5 subsequent siblings)
13 siblings, 0 replies; 53+ messages in thread
From: Anoob Joseph @ 2019-10-13 12:39 UTC (permalink / raw)
To: Akhil Goyal, Pablo de Lara
Cc: Anoob Joseph, Fiona Trahe, Jerin Jacob, Narayana Prasad,
Shally Verma, Ankur Dwivedi, Kanaka Durga Kotamarthy, Sunila Sahu,
Tejasree Kondoj, dev
This patch adds the OCTEON TX2 crypto validation tests.
Signed-off-by: Ankur Dwivedi <adwivedi@marvell.com>
Signed-off-by: Anoob Joseph <anoobj@marvell.com>
Signed-off-by: Tejasree Kondoj <ktejasree@marvell.com>
---
app/test/meson.build | 1 +
app/test/test_cryptodev.c | 323 ++++++++++++++++++++++++++++
app/test/test_cryptodev.h | 1 +
app/test/test_cryptodev_aes_test_vectors.h | 114 ++++++----
app/test/test_cryptodev_blockcipher.c | 7 +
app/test/test_cryptodev_blockcipher.h | 1 +
app/test/test_cryptodev_des_test_vectors.h | 12 +-
app/test/test_cryptodev_hash_test_vectors.h | 75 ++++---
doc/guides/cryptodevs/octeontx2.rst | 11 +
9 files changed, 478 insertions(+), 67 deletions(-)
diff --git a/app/test/meson.build b/app/test/meson.build
index 2c23c63..a88b0eb 100644
--- a/app/test/meson.build
+++ b/app/test/meson.build
@@ -271,6 +271,7 @@ driver_test_names = [
'cryptodev_dpaa_sec_autotest',
'cryptodev_dpaa2_sec_autotest',
'cryptodev_null_autotest',
+ 'cryptodev_octeontx2_autotest',
'cryptodev_openssl_autotest',
'cryptodev_openssl_asym_autotest',
'cryptodev_qat_autotest',
diff --git a/app/test/test_cryptodev.c b/app/test/test_cryptodev.c
index ffed298..c65af0d 100644
--- a/app/test/test_cryptodev.c
+++ b/app/test/test_cryptodev.c
@@ -2404,6 +2404,101 @@ test_authonly_octeontx_all(void)
return TEST_SUCCESS;
}
+static int
+test_AES_chain_octeontx2_all(void)
+{
+ struct crypto_testsuite_params *ts_params = &testsuite_params;
+ int status;
+
+ status = test_blockcipher_all_tests(ts_params->mbuf_pool,
+ ts_params->op_mpool, ts_params->session_mpool,
+ ts_params->session_priv_mpool,
+ ts_params->valid_devs[0],
+ rte_cryptodev_driver_id_get(
+ RTE_STR(CRYPTODEV_NAME_OCTEONTX2_PMD)),
+ BLKCIPHER_AES_CHAIN_TYPE);
+
+ TEST_ASSERT_EQUAL(status, 0, "Test failed");
+
+ return TEST_SUCCESS;
+}
+
+static int
+test_AES_cipheronly_octeontx2_all(void)
+{
+ struct crypto_testsuite_params *ts_params = &testsuite_params;
+ int status;
+
+ status = test_blockcipher_all_tests(ts_params->mbuf_pool,
+ ts_params->op_mpool, ts_params->session_mpool,
+ ts_params->session_priv_mpool,
+ ts_params->valid_devs[0],
+ rte_cryptodev_driver_id_get(
+ RTE_STR(CRYPTODEV_NAME_OCTEONTX2_PMD)),
+ BLKCIPHER_AES_CIPHERONLY_TYPE);
+
+ TEST_ASSERT_EQUAL(status, 0, "Test failed");
+
+ return TEST_SUCCESS;
+}
+
+static int
+test_3DES_chain_octeontx2_all(void)
+{
+ struct crypto_testsuite_params *ts_params = &testsuite_params;
+ int status;
+
+ status = test_blockcipher_all_tests(ts_params->mbuf_pool,
+ ts_params->op_mpool, ts_params->session_mpool,
+ ts_params->session_priv_mpool,
+ ts_params->valid_devs[0],
+ rte_cryptodev_driver_id_get(
+ RTE_STR(CRYPTODEV_NAME_OCTEONTX2_PMD)),
+ BLKCIPHER_3DES_CHAIN_TYPE);
+
+ TEST_ASSERT_EQUAL(status, 0, "Test failed");
+
+ return TEST_SUCCESS;
+}
+
+static int
+test_3DES_cipheronly_octeontx2_all(void)
+{
+ struct crypto_testsuite_params *ts_params = &testsuite_params;
+ int status;
+
+ status = test_blockcipher_all_tests(ts_params->mbuf_pool,
+ ts_params->op_mpool, ts_params->session_mpool,
+ ts_params->session_priv_mpool,
+ ts_params->valid_devs[0],
+ rte_cryptodev_driver_id_get(
+ RTE_STR(CRYPTODEV_NAME_OCTEONTX2_PMD)),
+ BLKCIPHER_3DES_CIPHERONLY_TYPE);
+
+ TEST_ASSERT_EQUAL(status, 0, "Test failed");
+
+ return TEST_SUCCESS;
+}
+
+static int
+test_authonly_octeontx2_all(void)
+{
+ struct crypto_testsuite_params *ts_params = &testsuite_params;
+ int status;
+
+ status = test_blockcipher_all_tests(ts_params->mbuf_pool,
+ ts_params->op_mpool, ts_params->session_mpool,
+ ts_params->session_priv_mpool,
+ ts_params->valid_devs[0],
+ rte_cryptodev_driver_id_get(
+ RTE_STR(CRYPTODEV_NAME_OCTEONTX2_PMD)),
+ BLKCIPHER_AUTHONLY_TYPE);
+
+ TEST_ASSERT_EQUAL(status, 0, "Test failed");
+
+ return TEST_SUCCESS;
+}
+
/* ***** SNOW 3G Tests ***** */
static int
create_wireless_algo_hash_session(uint8_t dev_id,
@@ -12951,6 +13046,218 @@ static struct unit_test_suite cryptodev_nitrox_testsuite = {
}
};
+static struct unit_test_suite cryptodev_octeontx2_testsuite = {
+ .suite_name = "Crypto Device OCTEON TX2 Unit Test Suite",
+ .setup = testsuite_setup,
+ .teardown = testsuite_teardown,
+ .unit_test_cases = {
+ TEST_CASE_ST(ut_setup, ut_teardown,
+ test_AES_chain_octeontx2_all),
+ TEST_CASE_ST(ut_setup, ut_teardown,
+ test_AES_cipheronly_octeontx2_all),
+ TEST_CASE_ST(ut_setup, ut_teardown,
+ test_3DES_chain_octeontx2_all),
+ TEST_CASE_ST(ut_setup, ut_teardown,
+ test_3DES_cipheronly_octeontx2_all),
+ TEST_CASE_ST(ut_setup, ut_teardown,
+ test_authonly_octeontx2_all),
+
+ /** AES GCM Authenticated Encryption */
+ TEST_CASE_ST(ut_setup, ut_teardown,
+ test_AES_GCM_authenticated_encryption_test_case_1),
+ TEST_CASE_ST(ut_setup, ut_teardown,
+ test_AES_GCM_authenticated_encryption_test_case_2),
+ TEST_CASE_ST(ut_setup, ut_teardown,
+ test_AES_GCM_authenticated_encryption_test_case_3),
+ TEST_CASE_ST(ut_setup, ut_teardown,
+ test_AES_GCM_authenticated_encryption_test_case_4),
+ TEST_CASE_ST(ut_setup, ut_teardown,
+ test_AES_GCM_authenticated_encryption_test_case_5),
+ TEST_CASE_ST(ut_setup, ut_teardown,
+ test_AES_GCM_authenticated_encryption_test_case_6),
+ TEST_CASE_ST(ut_setup, ut_teardown,
+ test_AES_GCM_authenticated_encryption_test_case_7),
+
+ /** AES GCM Authenticated Decryption */
+ TEST_CASE_ST(ut_setup, ut_teardown,
+ test_AES_GCM_authenticated_decryption_test_case_1),
+ TEST_CASE_ST(ut_setup, ut_teardown,
+ test_AES_GCM_authenticated_decryption_test_case_2),
+ TEST_CASE_ST(ut_setup, ut_teardown,
+ test_AES_GCM_authenticated_decryption_test_case_3),
+ TEST_CASE_ST(ut_setup, ut_teardown,
+ test_AES_GCM_authenticated_decryption_test_case_4),
+ TEST_CASE_ST(ut_setup, ut_teardown,
+ test_AES_GCM_authenticated_decryption_test_case_5),
+ TEST_CASE_ST(ut_setup, ut_teardown,
+ test_AES_GCM_authenticated_decryption_test_case_6),
+ TEST_CASE_ST(ut_setup, ut_teardown,
+ test_AES_GCM_authenticated_decryption_test_case_7),
+ /** AES GMAC Authentication */
+ TEST_CASE_ST(ut_setup, ut_teardown,
+ test_AES_GMAC_authentication_test_case_1),
+ TEST_CASE_ST(ut_setup, ut_teardown,
+ test_AES_GMAC_authentication_verify_test_case_1),
+ TEST_CASE_ST(ut_setup, ut_teardown,
+ test_AES_GMAC_authentication_test_case_2),
+ TEST_CASE_ST(ut_setup, ut_teardown,
+ test_AES_GMAC_authentication_verify_test_case_2),
+ TEST_CASE_ST(ut_setup, ut_teardown,
+ test_AES_GMAC_authentication_test_case_3),
+ TEST_CASE_ST(ut_setup, ut_teardown,
+ test_AES_GMAC_authentication_verify_test_case_3),
+
+ /** SNOW 3G encrypt only (UEA2) */
+ TEST_CASE_ST(ut_setup, ut_teardown,
+ test_snow3g_encryption_test_case_1),
+ TEST_CASE_ST(ut_setup, ut_teardown,
+ test_snow3g_encryption_test_case_2),
+ TEST_CASE_ST(ut_setup, ut_teardown,
+ test_snow3g_encryption_test_case_3),
+ TEST_CASE_ST(ut_setup, ut_teardown,
+ test_snow3g_encryption_test_case_4),
+ TEST_CASE_ST(ut_setup, ut_teardown,
+ test_snow3g_encryption_test_case_5),
+
+ TEST_CASE_ST(ut_setup, ut_teardown,
+ test_snow3g_encryption_test_case_1_oop),
+ TEST_CASE_ST(ut_setup, ut_teardown,
+ test_snow3g_decryption_test_case_1_oop),
+ TEST_CASE_ST(ut_setup, ut_teardown,
+ test_snow3g_encryption_test_case_1_oop_sgl),
+
+ /** SNOW 3G decrypt only (UEA2) */
+ TEST_CASE_ST(ut_setup, ut_teardown,
+ test_snow3g_decryption_test_case_1),
+ TEST_CASE_ST(ut_setup, ut_teardown,
+ test_snow3g_decryption_test_case_2),
+ TEST_CASE_ST(ut_setup, ut_teardown,
+ test_snow3g_decryption_test_case_3),
+ TEST_CASE_ST(ut_setup, ut_teardown,
+ test_snow3g_decryption_test_case_4),
+ TEST_CASE_ST(ut_setup, ut_teardown,
+ test_snow3g_decryption_test_case_5),
+
+ TEST_CASE_ST(ut_setup, ut_teardown,
+ test_snow3g_hash_generate_test_case_1),
+ TEST_CASE_ST(ut_setup, ut_teardown,
+ test_snow3g_hash_generate_test_case_2),
+ TEST_CASE_ST(ut_setup, ut_teardown,
+ test_snow3g_hash_generate_test_case_3),
+ TEST_CASE_ST(ut_setup, ut_teardown,
+ test_snow3g_hash_verify_test_case_1),
+ TEST_CASE_ST(ut_setup, ut_teardown,
+ test_snow3g_hash_verify_test_case_2),
+ TEST_CASE_ST(ut_setup, ut_teardown,
+ test_snow3g_hash_verify_test_case_3),
+
+ /** ZUC encrypt only (EEA3) */
+ TEST_CASE_ST(ut_setup, ut_teardown,
+ test_zuc_encryption_test_case_1),
+ TEST_CASE_ST(ut_setup, ut_teardown,
+ test_zuc_encryption_test_case_2),
+ TEST_CASE_ST(ut_setup, ut_teardown,
+ test_zuc_encryption_test_case_3),
+ TEST_CASE_ST(ut_setup, ut_teardown,
+ test_zuc_encryption_test_case_4),
+ TEST_CASE_ST(ut_setup, ut_teardown,
+ test_zuc_encryption_test_case_5),
+ TEST_CASE_ST(ut_setup, ut_teardown,
+ test_zuc_hash_generate_test_case_1),
+ TEST_CASE_ST(ut_setup, ut_teardown,
+ test_zuc_hash_generate_test_case_2),
+ TEST_CASE_ST(ut_setup, ut_teardown,
+ test_zuc_hash_generate_test_case_3),
+ TEST_CASE_ST(ut_setup, ut_teardown,
+ test_zuc_hash_generate_test_case_4),
+ TEST_CASE_ST(ut_setup, ut_teardown,
+ test_zuc_hash_generate_test_case_5),
+ TEST_CASE_ST(ut_setup, ut_teardown,
+ test_zuc_encryption_test_case_6_sgl),
+
+ /** KASUMI encrypt only (UEA1) */
+ TEST_CASE_ST(ut_setup, ut_teardown,
+ test_kasumi_encryption_test_case_1),
+ TEST_CASE_ST(ut_setup, ut_teardown,
+ test_kasumi_encryption_test_case_2),
+ TEST_CASE_ST(ut_setup, ut_teardown,
+ test_kasumi_encryption_test_case_3),
+ TEST_CASE_ST(ut_setup, ut_teardown,
+ test_kasumi_encryption_test_case_4),
+ TEST_CASE_ST(ut_setup, ut_teardown,
+ test_kasumi_encryption_test_case_5),
+ TEST_CASE_ST(ut_setup, ut_teardown,
+ test_kasumi_encryption_test_case_1_sgl),
+ TEST_CASE_ST(ut_setup, ut_teardown,
+ test_kasumi_encryption_test_case_1_oop_sgl),
+ /** KASUMI decrypt only (UEA1) */
+ TEST_CASE_ST(ut_setup, ut_teardown,
+ test_kasumi_decryption_test_case_1),
+ TEST_CASE_ST(ut_setup, ut_teardown,
+ test_kasumi_decryption_test_case_2),
+ TEST_CASE_ST(ut_setup, ut_teardown,
+ test_kasumi_decryption_test_case_3),
+ TEST_CASE_ST(ut_setup, ut_teardown,
+ test_kasumi_decryption_test_case_4),
+ TEST_CASE_ST(ut_setup, ut_teardown,
+ test_kasumi_decryption_test_case_5),
+
+ TEST_CASE_ST(ut_setup, ut_teardown,
+ test_kasumi_encryption_test_case_1_oop),
+ TEST_CASE_ST(ut_setup, ut_teardown,
+ test_kasumi_decryption_test_case_1_oop),
+
+ /** KASUMI hash only (UIA1) */
+ TEST_CASE_ST(ut_setup, ut_teardown,
+ test_kasumi_hash_generate_test_case_1),
+ TEST_CASE_ST(ut_setup, ut_teardown,
+ test_kasumi_hash_generate_test_case_2),
+ TEST_CASE_ST(ut_setup, ut_teardown,
+ test_kasumi_hash_generate_test_case_3),
+ TEST_CASE_ST(ut_setup, ut_teardown,
+ test_kasumi_hash_generate_test_case_4),
+ TEST_CASE_ST(ut_setup, ut_teardown,
+ test_kasumi_hash_generate_test_case_5),
+ TEST_CASE_ST(ut_setup, ut_teardown,
+ test_kasumi_hash_generate_test_case_6),
+ TEST_CASE_ST(ut_setup, ut_teardown,
+ test_kasumi_hash_verify_test_case_1),
+ TEST_CASE_ST(ut_setup, ut_teardown,
+ test_kasumi_hash_verify_test_case_2),
+ TEST_CASE_ST(ut_setup, ut_teardown,
+ test_kasumi_hash_verify_test_case_3),
+ TEST_CASE_ST(ut_setup, ut_teardown,
+ test_kasumi_hash_verify_test_case_4),
+ TEST_CASE_ST(ut_setup, ut_teardown,
+ test_kasumi_hash_verify_test_case_5),
+
+ /** NULL tests */
+ TEST_CASE_ST(ut_setup, ut_teardown,
+ test_null_cipher_only_operation),
+ TEST_CASE_ST(ut_setup, ut_teardown,
+ test_null_auth_only_operation),
+ TEST_CASE_ST(ut_setup, ut_teardown,
+ test_null_cipher_auth_operation),
+ TEST_CASE_ST(ut_setup, ut_teardown,
+ test_null_auth_cipher_operation),
+
+ /** Negative tests */
+ TEST_CASE_ST(ut_setup, ut_teardown,
+ authentication_verify_HMAC_SHA1_fail_data_corrupt),
+ TEST_CASE_ST(ut_setup, ut_teardown,
+ authentication_verify_HMAC_SHA1_fail_tag_corrupt),
+ TEST_CASE_ST(ut_setup, ut_teardown,
+ authentication_verify_AES128_GMAC_fail_data_corrupt),
+ TEST_CASE_ST(ut_setup, ut_teardown,
+ authentication_verify_AES128_GMAC_fail_tag_corrupt),
+ TEST_CASE_ST(ut_setup, ut_teardown,
+ auth_decryption_AES128CBC_HMAC_SHA1_fail_data_corrupt),
+ TEST_CASE_ST(ut_setup, ut_teardown,
+ auth_decryption_AES128CBC_HMAC_SHA1_fail_tag_corrupt),
+ TEST_CASES_END() /**< NULL terminate unit test array */
+ }
+};
+
static int
test_cryptodev_qat(void /*argv __rte_unused, int argc __rte_unused*/)
{
@@ -13219,6 +13526,21 @@ test_cryptodev_octeontx(void)
}
static int
+test_cryptodev_octeontx2(void)
+{
+ gbl_driver_id = rte_cryptodev_driver_id_get(
+ RTE_STR(CRYPTODEV_NAME_OCTEONTX2_PMD));
+ if (gbl_driver_id == -1) {
+ RTE_LOG(ERR, USER1, "OCTEON TX2 PMD must be loaded. Check if "
+ "CONFIG_RTE_LIBRTE_PMD_OCTEONTX2_CRYPTO is "
+ "enabled in config file to run this "
+ "testsuite.\n");
+ return TEST_FAILED;
+ }
+ return unit_test_suite_runner(&cryptodev_octeontx2_testsuite);
+}
+
+static int
test_cryptodev_caam_jr(void /*argv __rte_unused, int argc __rte_unused*/)
{
gbl_driver_id = rte_cryptodev_driver_id_get(
@@ -13265,5 +13587,6 @@ REGISTER_TEST_COMMAND(cryptodev_dpaa_sec_autotest, test_cryptodev_dpaa_sec);
REGISTER_TEST_COMMAND(cryptodev_ccp_autotest, test_cryptodev_ccp);
REGISTER_TEST_COMMAND(cryptodev_virtio_autotest, test_cryptodev_virtio);
REGISTER_TEST_COMMAND(cryptodev_octeontx_autotest, test_cryptodev_octeontx);
+REGISTER_TEST_COMMAND(cryptodev_octeontx2_autotest, test_cryptodev_octeontx2);
REGISTER_TEST_COMMAND(cryptodev_caam_jr_autotest, test_cryptodev_caam_jr);
REGISTER_TEST_COMMAND(cryptodev_nitrox_autotest, test_cryptodev_nitrox);
diff --git a/app/test/test_cryptodev.h b/app/test/test_cryptodev.h
index d20586e..def304e 100644
--- a/app/test/test_cryptodev.h
+++ b/app/test/test_cryptodev.h
@@ -66,6 +66,7 @@
#define CRYPTODEV_NAME_CCP_PMD crypto_ccp
#define CRYPTODEV_NAME_VIRTIO_PMD crypto_virtio
#define CRYPTODEV_NAME_OCTEONTX_SYM_PMD crypto_octeontx
+#define CRYPTODEV_NAME_OCTEONTX2_PMD crypto_octeontx2
#define CRYPTODEV_NAME_CAAM_JR_PMD crypto_caam_jr
#define CRYPTODEV_NAME_NITROX_PMD crypto_nitrox_sym
diff --git a/app/test/test_cryptodev_aes_test_vectors.h b/app/test/test_cryptodev_aes_test_vectors.h
index 46239ef..4c2548e 100644
--- a/app/test/test_cryptodev_aes_test_vectors.h
+++ b/app/test/test_cryptodev_aes_test_vectors.h
@@ -1640,7 +1640,8 @@ static const struct blockcipher_test_case aes_chain_test_cases[] = {
BLOCKCIPHER_TEST_TARGET_PMD_MVSAM |
BLOCKCIPHER_TEST_TARGET_PMD_CCP |
BLOCKCIPHER_TEST_TARGET_PMD_OCTEONTX |
- BLOCKCIPHER_TEST_TARGET_PMD_NITROX
+ BLOCKCIPHER_TEST_TARGET_PMD_NITROX |
+ BLOCKCIPHER_TEST_TARGET_PMD_OCTEONTX2
},
{
.test_descr = "AES-128-CBC HMAC-SHA1 Encryption Digest "
@@ -1650,7 +1651,8 @@ static const struct blockcipher_test_case aes_chain_test_cases[] = {
.pmd_mask = BLOCKCIPHER_TEST_TARGET_PMD_ARMV8 |
BLOCKCIPHER_TEST_TARGET_PMD_MVSAM |
BLOCKCIPHER_TEST_TARGET_PMD_OCTEONTX |
- BLOCKCIPHER_TEST_TARGET_PMD_NITROX
+ BLOCKCIPHER_TEST_TARGET_PMD_NITROX |
+ BLOCKCIPHER_TEST_TARGET_PMD_OCTEONTX2
},
{
.test_descr = "AES-128-CBC HMAC-SHA1 Encryption Digest "
@@ -1667,7 +1669,8 @@ static const struct blockcipher_test_case aes_chain_test_cases[] = {
BLOCKCIPHER_TEST_TARGET_PMD_DPAA_SEC |
BLOCKCIPHER_TEST_TARGET_PMD_CAAM_JR |
BLOCKCIPHER_TEST_TARGET_PMD_OCTEONTX |
- BLOCKCIPHER_TEST_TARGET_PMD_NITROX
+ BLOCKCIPHER_TEST_TARGET_PMD_NITROX |
+ BLOCKCIPHER_TEST_TARGET_PMD_OCTEONTX2
},
{
.test_descr = "AES-128-CBC HMAC-SHA1 Decryption Digest "
@@ -1685,7 +1688,8 @@ static const struct blockcipher_test_case aes_chain_test_cases[] = {
BLOCKCIPHER_TEST_TARGET_PMD_MVSAM |
BLOCKCIPHER_TEST_TARGET_PMD_CCP |
BLOCKCIPHER_TEST_TARGET_PMD_OCTEONTX |
- BLOCKCIPHER_TEST_TARGET_PMD_NITROX
+ BLOCKCIPHER_TEST_TARGET_PMD_NITROX |
+ BLOCKCIPHER_TEST_TARGET_PMD_OCTEONTX2
},
{
.test_descr = "AES-128-CBC HMAC-SHA1 Decryption Digest "
@@ -1697,7 +1701,8 @@ static const struct blockcipher_test_case aes_chain_test_cases[] = {
BLOCKCIPHER_TEST_TARGET_PMD_DPAA_SEC |
BLOCKCIPHER_TEST_TARGET_PMD_CAAM_JR |
BLOCKCIPHER_TEST_TARGET_PMD_OCTEONTX |
- BLOCKCIPHER_TEST_TARGET_PMD_NITROX
+ BLOCKCIPHER_TEST_TARGET_PMD_NITROX |
+ BLOCKCIPHER_TEST_TARGET_PMD_OCTEONTX2
},
{
.test_descr = "AES-128-CBC HMAC-SHA1 Decryption Digest "
@@ -1707,7 +1712,8 @@ static const struct blockcipher_test_case aes_chain_test_cases[] = {
.pmd_mask = BLOCKCIPHER_TEST_TARGET_PMD_ARMV8 |
BLOCKCIPHER_TEST_TARGET_PMD_MVSAM |
BLOCKCIPHER_TEST_TARGET_PMD_OCTEONTX |
- BLOCKCIPHER_TEST_TARGET_PMD_NITROX
+ BLOCKCIPHER_TEST_TARGET_PMD_NITROX |
+ BLOCKCIPHER_TEST_TARGET_PMD_OCTEONTX2
},
{
.test_descr = "AES-128-CBC HMAC-SHA256 Encryption Digest",
@@ -1724,7 +1730,8 @@ static const struct blockcipher_test_case aes_chain_test_cases[] = {
BLOCKCIPHER_TEST_TARGET_PMD_MVSAM |
BLOCKCIPHER_TEST_TARGET_PMD_CCP |
BLOCKCIPHER_TEST_TARGET_PMD_OCTEONTX |
- BLOCKCIPHER_TEST_TARGET_PMD_NITROX
+ BLOCKCIPHER_TEST_TARGET_PMD_NITROX |
+ BLOCKCIPHER_TEST_TARGET_PMD_OCTEONTX2
},
{
.test_descr = "AES-128-CBC HMAC-SHA256 Encryption Digest "
@@ -1734,7 +1741,8 @@ static const struct blockcipher_test_case aes_chain_test_cases[] = {
.pmd_mask = BLOCKCIPHER_TEST_TARGET_PMD_ARMV8 |
BLOCKCIPHER_TEST_TARGET_PMD_MVSAM |
BLOCKCIPHER_TEST_TARGET_PMD_OCTEONTX |
- BLOCKCIPHER_TEST_TARGET_PMD_NITROX
+ BLOCKCIPHER_TEST_TARGET_PMD_NITROX |
+ BLOCKCIPHER_TEST_TARGET_PMD_OCTEONTX2
},
{
.test_descr = "AES-128-CBC HMAC-SHA256 Decryption Digest "
@@ -1751,7 +1759,8 @@ static const struct blockcipher_test_case aes_chain_test_cases[] = {
BLOCKCIPHER_TEST_TARGET_PMD_MVSAM |
BLOCKCIPHER_TEST_TARGET_PMD_CCP |
BLOCKCIPHER_TEST_TARGET_PMD_OCTEONTX |
- BLOCKCIPHER_TEST_TARGET_PMD_NITROX
+ BLOCKCIPHER_TEST_TARGET_PMD_NITROX |
+ BLOCKCIPHER_TEST_TARGET_PMD_OCTEONTX2
},
{
.test_descr = "AES-128-CBC HMAC-SHA256 Decryption Digest "
@@ -1761,7 +1770,8 @@ static const struct blockcipher_test_case aes_chain_test_cases[] = {
.pmd_mask = BLOCKCIPHER_TEST_TARGET_PMD_ARMV8 |
BLOCKCIPHER_TEST_TARGET_PMD_MVSAM |
BLOCKCIPHER_TEST_TARGET_PMD_OCTEONTX |
- BLOCKCIPHER_TEST_TARGET_PMD_NITROX
+ BLOCKCIPHER_TEST_TARGET_PMD_NITROX |
+ BLOCKCIPHER_TEST_TARGET_PMD_OCTEONTX2
},
{
.test_descr = "AES-128-CBC HMAC-SHA512 Encryption Digest",
@@ -1776,7 +1786,8 @@ static const struct blockcipher_test_case aes_chain_test_cases[] = {
BLOCKCIPHER_TEST_TARGET_PMD_CAAM_JR |
BLOCKCIPHER_TEST_TARGET_PMD_MVSAM |
BLOCKCIPHER_TEST_TARGET_PMD_CCP |
- BLOCKCIPHER_TEST_TARGET_PMD_OCTEONTX
+ BLOCKCIPHER_TEST_TARGET_PMD_OCTEONTX |
+ BLOCKCIPHER_TEST_TARGET_PMD_OCTEONTX2
},
{
.test_descr = "AES-128-CBC HMAC-SHA512 Encryption Digest "
@@ -1787,7 +1798,8 @@ static const struct blockcipher_test_case aes_chain_test_cases[] = {
.pmd_mask = BLOCKCIPHER_TEST_TARGET_PMD_MB |
BLOCKCIPHER_TEST_TARGET_PMD_OPENSSL |
BLOCKCIPHER_TEST_TARGET_PMD_CCP |
- BLOCKCIPHER_TEST_TARGET_PMD_OCTEONTX
+ BLOCKCIPHER_TEST_TARGET_PMD_OCTEONTX |
+ BLOCKCIPHER_TEST_TARGET_PMD_OCTEONTX2
},
{
.test_descr = "AES-128-CBC HMAC-SHA512 Encryption Digest "
@@ -1799,7 +1811,8 @@ static const struct blockcipher_test_case aes_chain_test_cases[] = {
BLOCKCIPHER_TEST_FEATURE_OOP,
.pmd_mask =
BLOCKCIPHER_TEST_TARGET_PMD_OPENSSL |
- BLOCKCIPHER_TEST_TARGET_PMD_OCTEONTX
+ BLOCKCIPHER_TEST_TARGET_PMD_OCTEONTX |
+ BLOCKCIPHER_TEST_TARGET_PMD_OCTEONTX2
},
{
.test_descr = "AES-128-CBC HMAC-SHA512 Decryption Digest "
@@ -1815,7 +1828,8 @@ static const struct blockcipher_test_case aes_chain_test_cases[] = {
BLOCKCIPHER_TEST_TARGET_PMD_CAAM_JR |
BLOCKCIPHER_TEST_TARGET_PMD_MVSAM |
BLOCKCIPHER_TEST_TARGET_PMD_CCP |
- BLOCKCIPHER_TEST_TARGET_PMD_OCTEONTX
+ BLOCKCIPHER_TEST_TARGET_PMD_OCTEONTX |
+ BLOCKCIPHER_TEST_TARGET_PMD_OCTEONTX2
},
{
.test_descr = "AES-128-CBC HMAC-SHA512 Decryption Digest "
@@ -1830,7 +1844,8 @@ static const struct blockcipher_test_case aes_chain_test_cases[] = {
BLOCKCIPHER_TEST_TARGET_PMD_DPAA2_SEC |
BLOCKCIPHER_TEST_TARGET_PMD_DPAA_SEC |
BLOCKCIPHER_TEST_TARGET_PMD_SCHEDULER |
- BLOCKCIPHER_TEST_TARGET_PMD_OCTEONTX
+ BLOCKCIPHER_TEST_TARGET_PMD_OCTEONTX |
+ BLOCKCIPHER_TEST_TARGET_PMD_OCTEONTX2
},
{
.test_descr = "AES-128-CBC XCBC Encryption Digest",
@@ -1862,7 +1877,8 @@ static const struct blockcipher_test_case aes_chain_test_cases[] = {
BLOCKCIPHER_TEST_TARGET_PMD_CAAM_JR |
BLOCKCIPHER_TEST_TARGET_PMD_MB |
BLOCKCIPHER_TEST_TARGET_PMD_OCTEONTX |
- BLOCKCIPHER_TEST_TARGET_PMD_NITROX
+ BLOCKCIPHER_TEST_TARGET_PMD_NITROX |
+ BLOCKCIPHER_TEST_TARGET_PMD_OCTEONTX2
},
{
.test_descr = "AES-128-CBC HMAC-SHA1 Encryption Digest "
@@ -1888,7 +1904,8 @@ static const struct blockcipher_test_case aes_chain_test_cases[] = {
BLOCKCIPHER_TEST_TARGET_PMD_CAAM_JR |
BLOCKCIPHER_TEST_TARGET_PMD_OCTEONTX |
BLOCKCIPHER_TEST_TARGET_PMD_MB |
- BLOCKCIPHER_TEST_TARGET_PMD_NITROX
+ BLOCKCIPHER_TEST_TARGET_PMD_NITROX |
+ BLOCKCIPHER_TEST_TARGET_PMD_OCTEONTX2
},
{
.test_descr = "AES-128-CBC HMAC-SHA224 Encryption Digest",
@@ -1903,7 +1920,8 @@ static const struct blockcipher_test_case aes_chain_test_cases[] = {
BLOCKCIPHER_TEST_TARGET_PMD_CAAM_JR |
BLOCKCIPHER_TEST_TARGET_PMD_CCP |
BLOCKCIPHER_TEST_TARGET_PMD_OCTEONTX |
- BLOCKCIPHER_TEST_TARGET_PMD_NITROX
+ BLOCKCIPHER_TEST_TARGET_PMD_NITROX |
+ BLOCKCIPHER_TEST_TARGET_PMD_OCTEONTX2
},
{
.test_descr = "AES-128-CBC HMAC-SHA224 Decryption Digest "
@@ -1919,7 +1937,8 @@ static const struct blockcipher_test_case aes_chain_test_cases[] = {
BLOCKCIPHER_TEST_TARGET_PMD_CAAM_JR |
BLOCKCIPHER_TEST_TARGET_PMD_CCP |
BLOCKCIPHER_TEST_TARGET_PMD_OCTEONTX |
- BLOCKCIPHER_TEST_TARGET_PMD_NITROX
+ BLOCKCIPHER_TEST_TARGET_PMD_NITROX |
+ BLOCKCIPHER_TEST_TARGET_PMD_OCTEONTX2
},
{
.test_descr = "AES-128-CBC HMAC-SHA384 Encryption Digest",
@@ -1959,7 +1978,8 @@ static const struct blockcipher_test_case aes_chain_test_cases[] = {
.pmd_mask = BLOCKCIPHER_TEST_TARGET_PMD_ARMV8 |
BLOCKCIPHER_TEST_TARGET_PMD_OPENSSL |
BLOCKCIPHER_TEST_TARGET_PMD_CCP |
- BLOCKCIPHER_TEST_TARGET_PMD_OCTEONTX
+ BLOCKCIPHER_TEST_TARGET_PMD_OCTEONTX |
+ BLOCKCIPHER_TEST_TARGET_PMD_OCTEONTX2
},
{
.test_descr =
@@ -1971,7 +1991,8 @@ static const struct blockcipher_test_case aes_chain_test_cases[] = {
.pmd_mask = BLOCKCIPHER_TEST_TARGET_PMD_ARMV8 |
BLOCKCIPHER_TEST_TARGET_PMD_OPENSSL |
BLOCKCIPHER_TEST_TARGET_PMD_CCP |
- BLOCKCIPHER_TEST_TARGET_PMD_OCTEONTX
+ BLOCKCIPHER_TEST_TARGET_PMD_OCTEONTX |
+ BLOCKCIPHER_TEST_TARGET_PMD_OCTEONTX2
},
{
.test_descr = "NULL-CIPHER-NULL-AUTH encrypt & gen x8byte",
@@ -2074,7 +2095,8 @@ static const struct blockcipher_test_case aes_cipheronly_test_cases[] = {
BLOCKCIPHER_TEST_TARGET_PMD_MVSAM |
BLOCKCIPHER_TEST_TARGET_PMD_CCP |
BLOCKCIPHER_TEST_TARGET_PMD_VIRTIO |
- BLOCKCIPHER_TEST_TARGET_PMD_OCTEONTX
+ BLOCKCIPHER_TEST_TARGET_PMD_OCTEONTX |
+ BLOCKCIPHER_TEST_TARGET_PMD_OCTEONTX2
},
{
.test_descr = "AES-128-CBC Decryption",
@@ -2090,7 +2112,8 @@ static const struct blockcipher_test_case aes_cipheronly_test_cases[] = {
BLOCKCIPHER_TEST_TARGET_PMD_MVSAM |
BLOCKCIPHER_TEST_TARGET_PMD_CCP |
BLOCKCIPHER_TEST_TARGET_PMD_VIRTIO |
- BLOCKCIPHER_TEST_TARGET_PMD_OCTEONTX
+ BLOCKCIPHER_TEST_TARGET_PMD_OCTEONTX |
+ BLOCKCIPHER_TEST_TARGET_PMD_OCTEONTX2
},
{
.test_descr = "AES-192-CBC Encryption",
@@ -2105,7 +2128,8 @@ static const struct blockcipher_test_case aes_cipheronly_test_cases[] = {
BLOCKCIPHER_TEST_TARGET_PMD_CAAM_JR |
BLOCKCIPHER_TEST_TARGET_PMD_CCP |
BLOCKCIPHER_TEST_TARGET_PMD_VIRTIO |
- BLOCKCIPHER_TEST_TARGET_PMD_OCTEONTX
+ BLOCKCIPHER_TEST_TARGET_PMD_OCTEONTX |
+ BLOCKCIPHER_TEST_TARGET_PMD_OCTEONTX2
},
{
.test_descr = "AES-192-CBC Encryption Scater gather",
@@ -2117,7 +2141,8 @@ static const struct blockcipher_test_case aes_cipheronly_test_cases[] = {
BLOCKCIPHER_TEST_TARGET_PMD_DPAA_SEC |
BLOCKCIPHER_TEST_TARGET_PMD_DPAA2_SEC |
BLOCKCIPHER_TEST_TARGET_PMD_CAAM_JR |
- BLOCKCIPHER_TEST_TARGET_PMD_OCTEONTX
+ BLOCKCIPHER_TEST_TARGET_PMD_OCTEONTX |
+ BLOCKCIPHER_TEST_TARGET_PMD_OCTEONTX2
},
{
.test_descr = "AES-192-CBC Decryption",
@@ -2132,7 +2157,8 @@ static const struct blockcipher_test_case aes_cipheronly_test_cases[] = {
BLOCKCIPHER_TEST_TARGET_PMD_CAAM_JR |
BLOCKCIPHER_TEST_TARGET_PMD_CCP |
BLOCKCIPHER_TEST_TARGET_PMD_VIRTIO |
- BLOCKCIPHER_TEST_TARGET_PMD_OCTEONTX
+ BLOCKCIPHER_TEST_TARGET_PMD_OCTEONTX |
+ BLOCKCIPHER_TEST_TARGET_PMD_OCTEONTX2
},
{
.test_descr = "AES-192-CBC Decryption Scatter Gather",
@@ -2142,7 +2168,8 @@ static const struct blockcipher_test_case aes_cipheronly_test_cases[] = {
.pmd_mask = BLOCKCIPHER_TEST_TARGET_PMD_DPAA2_SEC |
BLOCKCIPHER_TEST_TARGET_PMD_DPAA_SEC |
BLOCKCIPHER_TEST_TARGET_PMD_CAAM_JR |
- BLOCKCIPHER_TEST_TARGET_PMD_OCTEONTX
+ BLOCKCIPHER_TEST_TARGET_PMD_OCTEONTX |
+ BLOCKCIPHER_TEST_TARGET_PMD_OCTEONTX2
},
{
.test_descr = "AES-256-CBC Encryption",
@@ -2158,7 +2185,8 @@ static const struct blockcipher_test_case aes_cipheronly_test_cases[] = {
BLOCKCIPHER_TEST_TARGET_PMD_MVSAM |
BLOCKCIPHER_TEST_TARGET_PMD_CCP |
BLOCKCIPHER_TEST_TARGET_PMD_VIRTIO |
- BLOCKCIPHER_TEST_TARGET_PMD_OCTEONTX
+ BLOCKCIPHER_TEST_TARGET_PMD_OCTEONTX |
+ BLOCKCIPHER_TEST_TARGET_PMD_OCTEONTX2
},
{
.test_descr = "AES-256-CBC Decryption",
@@ -2174,7 +2202,8 @@ static const struct blockcipher_test_case aes_cipheronly_test_cases[] = {
BLOCKCIPHER_TEST_TARGET_PMD_MVSAM |
BLOCKCIPHER_TEST_TARGET_PMD_CCP |
BLOCKCIPHER_TEST_TARGET_PMD_VIRTIO |
- BLOCKCIPHER_TEST_TARGET_PMD_OCTEONTX
+ BLOCKCIPHER_TEST_TARGET_PMD_OCTEONTX |
+ BLOCKCIPHER_TEST_TARGET_PMD_OCTEONTX2
},
{
.test_descr = "AES-256-CBC OOP Encryption",
@@ -2217,7 +2246,8 @@ static const struct blockcipher_test_case aes_cipheronly_test_cases[] = {
BLOCKCIPHER_TEST_TARGET_PMD_CAAM_JR |
BLOCKCIPHER_TEST_TARGET_PMD_MVSAM |
BLOCKCIPHER_TEST_TARGET_PMD_CCP |
- BLOCKCIPHER_TEST_TARGET_PMD_OCTEONTX
+ BLOCKCIPHER_TEST_TARGET_PMD_OCTEONTX |
+ BLOCKCIPHER_TEST_TARGET_PMD_OCTEONTX2
},
{
.test_descr = "AES-128-CTR Decryption",
@@ -2232,7 +2262,8 @@ static const struct blockcipher_test_case aes_cipheronly_test_cases[] = {
BLOCKCIPHER_TEST_TARGET_PMD_CAAM_JR |
BLOCKCIPHER_TEST_TARGET_PMD_MVSAM |
BLOCKCIPHER_TEST_TARGET_PMD_CCP |
- BLOCKCIPHER_TEST_TARGET_PMD_OCTEONTX
+ BLOCKCIPHER_TEST_TARGET_PMD_OCTEONTX |
+ BLOCKCIPHER_TEST_TARGET_PMD_OCTEONTX2
},
{
.test_descr = "AES-192-CTR Encryption",
@@ -2246,7 +2277,8 @@ static const struct blockcipher_test_case aes_cipheronly_test_cases[] = {
BLOCKCIPHER_TEST_TARGET_PMD_DPAA_SEC |
BLOCKCIPHER_TEST_TARGET_PMD_CAAM_JR |
BLOCKCIPHER_TEST_TARGET_PMD_CCP |
- BLOCKCIPHER_TEST_TARGET_PMD_OCTEONTX
+ BLOCKCIPHER_TEST_TARGET_PMD_OCTEONTX |
+ BLOCKCIPHER_TEST_TARGET_PMD_OCTEONTX2
},
{
.test_descr = "AES-192-CTR Decryption",
@@ -2260,7 +2292,8 @@ static const struct blockcipher_test_case aes_cipheronly_test_cases[] = {
BLOCKCIPHER_TEST_TARGET_PMD_DPAA_SEC |
BLOCKCIPHER_TEST_TARGET_PMD_CAAM_JR |
BLOCKCIPHER_TEST_TARGET_PMD_CCP |
- BLOCKCIPHER_TEST_TARGET_PMD_OCTEONTX
+ BLOCKCIPHER_TEST_TARGET_PMD_OCTEONTX |
+ BLOCKCIPHER_TEST_TARGET_PMD_OCTEONTX2
},
{
.test_descr = "AES-256-CTR Encryption",
@@ -2275,7 +2308,8 @@ static const struct blockcipher_test_case aes_cipheronly_test_cases[] = {
BLOCKCIPHER_TEST_TARGET_PMD_CAAM_JR |
BLOCKCIPHER_TEST_TARGET_PMD_MVSAM |
BLOCKCIPHER_TEST_TARGET_PMD_CCP |
- BLOCKCIPHER_TEST_TARGET_PMD_OCTEONTX
+ BLOCKCIPHER_TEST_TARGET_PMD_OCTEONTX |
+ BLOCKCIPHER_TEST_TARGET_PMD_OCTEONTX2
},
{
.test_descr = "AES-256-CTR Decryption",
@@ -2290,28 +2324,32 @@ static const struct blockcipher_test_case aes_cipheronly_test_cases[] = {
BLOCKCIPHER_TEST_TARGET_PMD_CAAM_JR |
BLOCKCIPHER_TEST_TARGET_PMD_MVSAM |
BLOCKCIPHER_TEST_TARGET_PMD_CCP |
- BLOCKCIPHER_TEST_TARGET_PMD_OCTEONTX
+ BLOCKCIPHER_TEST_TARGET_PMD_OCTEONTX |
+ BLOCKCIPHER_TEST_TARGET_PMD_OCTEONTX2
},
{
.test_descr = "AES-128-CTR Encryption (12-byte IV)",
.test_data = &aes_test_data_1_IV_12_bytes,
.op_mask = BLOCKCIPHER_TEST_OP_ENCRYPT,
.pmd_mask = BLOCKCIPHER_TEST_TARGET_PMD_MB |
- BLOCKCIPHER_TEST_TARGET_PMD_OCTEONTX
+ BLOCKCIPHER_TEST_TARGET_PMD_OCTEONTX |
+ BLOCKCIPHER_TEST_TARGET_PMD_OCTEONTX2
},
{
.test_descr = "AES-192-CTR Encryption (12-byte IV)",
.test_data = &aes_test_data_2_IV_12_bytes,
.op_mask = BLOCKCIPHER_TEST_OP_ENCRYPT,
.pmd_mask = BLOCKCIPHER_TEST_TARGET_PMD_MB |
- BLOCKCIPHER_TEST_TARGET_PMD_OCTEONTX
+ BLOCKCIPHER_TEST_TARGET_PMD_OCTEONTX |
+ BLOCKCIPHER_TEST_TARGET_PMD_OCTEONTX2
},
{
.test_descr = "AES-256-CTR Encryption (12-byte IV)",
.test_data = &aes_test_data_3_IV_12_bytes,
.op_mask = BLOCKCIPHER_TEST_OP_ENCRYPT,
.pmd_mask = BLOCKCIPHER_TEST_TARGET_PMD_MB |
- BLOCKCIPHER_TEST_TARGET_PMD_OCTEONTX
+ BLOCKCIPHER_TEST_TARGET_PMD_OCTEONTX |
+ BLOCKCIPHER_TEST_TARGET_PMD_OCTEONTX2
},
{
.test_descr = "AES-128-XTS Encryption (16-byte plaintext)",
diff --git a/app/test/test_cryptodev_blockcipher.c b/app/test/test_cryptodev_blockcipher.c
index 885a20e..5bfe2d0 100644
--- a/app/test/test_cryptodev_blockcipher.c
+++ b/app/test/test_cryptodev_blockcipher.c
@@ -77,6 +77,8 @@ test_blockcipher_one_case(const struct blockcipher_test_case *t,
RTE_STR(CRYPTODEV_NAME_VIRTIO_PMD));
int octeontx_pmd = rte_cryptodev_driver_id_get(
RTE_STR(CRYPTODEV_NAME_OCTEONTX_SYM_PMD));
+ int octeontx2_pmd = rte_cryptodev_driver_id_get(
+ RTE_STR(CRYPTODEV_NAME_OCTEONTX2_PMD));
int null_pmd = rte_cryptodev_driver_id_get(
RTE_STR(CRYPTODEV_NAME_NULL_PMD));
int nitrox_pmd = rte_cryptodev_driver_id_get(
@@ -127,6 +129,7 @@ test_blockcipher_one_case(const struct blockcipher_test_case *t,
driver_id == ccp_pmd ||
driver_id == virtio_pmd ||
driver_id == octeontx_pmd ||
+ driver_id == octeontx2_pmd ||
driver_id == null_pmd ||
driver_id == nitrox_pmd) { /* Fall through */
digest_len = tdata->digest.len;
@@ -718,6 +721,8 @@ test_blockcipher_all_tests(struct rte_mempool *mbuf_pool,
RTE_STR(CRYPTODEV_NAME_VIRTIO_PMD));
int octeontx_pmd = rte_cryptodev_driver_id_get(
RTE_STR(CRYPTODEV_NAME_OCTEONTX_SYM_PMD));
+ int octeontx2_pmd = rte_cryptodev_driver_id_get(
+ RTE_STR(CRYPTODEV_NAME_OCTEONTX2_PMD));
int null_pmd = rte_cryptodev_driver_id_get(
RTE_STR(CRYPTODEV_NAME_NULL_PMD));
int nitrox_pmd = rte_cryptodev_driver_id_get(
@@ -792,6 +797,8 @@ test_blockcipher_all_tests(struct rte_mempool *mbuf_pool,
target_pmd_mask = BLOCKCIPHER_TEST_TARGET_PMD_VIRTIO;
else if (driver_id == octeontx_pmd)
target_pmd_mask = BLOCKCIPHER_TEST_TARGET_PMD_OCTEONTX;
+ else if (driver_id == octeontx2_pmd)
+ target_pmd_mask = BLOCKCIPHER_TEST_TARGET_PMD_OCTEONTX2;
else if (driver_id == null_pmd)
target_pmd_mask = BLOCKCIPHER_TEST_TARGET_PMD_NULL;
else if (driver_id == nitrox_pmd)
diff --git a/app/test/test_cryptodev_blockcipher.h b/app/test/test_cryptodev_blockcipher.h
index 1a65cda..204ba7b 100644
--- a/app/test/test_cryptodev_blockcipher.h
+++ b/app/test/test_cryptodev_blockcipher.h
@@ -33,6 +33,7 @@
#define BLOCKCIPHER_TEST_TARGET_PMD_CCP 0x0800 /* CCP flag */
#define BLOCKCIPHER_TEST_TARGET_PMD_NULL 0x1000 /* NULL flag */
#define BLOCKCIPHER_TEST_TARGET_PMD_NITROX 0x2000 /* NITROX flag */
+#define BLOCKCIPHER_TEST_TARGET_PMD_OCTEONTX2 0x4000 /* OCTEON TX2 flag */
#define BLOCKCIPHER_TEST_OP_CIPHER (BLOCKCIPHER_TEST_OP_ENCRYPT | \
BLOCKCIPHER_TEST_OP_DECRYPT)
diff --git a/app/test/test_cryptodev_des_test_vectors.h b/app/test/test_cryptodev_des_test_vectors.h
index a71b0e9..9d2d0e7 100644
--- a/app/test/test_cryptodev_des_test_vectors.h
+++ b/app/test/test_cryptodev_des_test_vectors.h
@@ -1114,7 +1114,8 @@ static const struct blockcipher_test_case triple_des_chain_test_cases[] = {
BLOCKCIPHER_TEST_TARGET_PMD_CAAM_JR |
BLOCKCIPHER_TEST_TARGET_PMD_MVSAM |
BLOCKCIPHER_TEST_TARGET_PMD_CCP |
- BLOCKCIPHER_TEST_TARGET_PMD_OCTEONTX
+ BLOCKCIPHER_TEST_TARGET_PMD_OCTEONTX |
+ BLOCKCIPHER_TEST_TARGET_PMD_OCTEONTX2
},
{
.test_descr = "3DES-192-CBC HMAC-SHA1 Decryption Digest Verify",
@@ -1127,7 +1128,8 @@ static const struct blockcipher_test_case triple_des_chain_test_cases[] = {
BLOCKCIPHER_TEST_TARGET_PMD_CAAM_JR |
BLOCKCIPHER_TEST_TARGET_PMD_MVSAM |
BLOCKCIPHER_TEST_TARGET_PMD_CCP |
- BLOCKCIPHER_TEST_TARGET_PMD_OCTEONTX
+ BLOCKCIPHER_TEST_TARGET_PMD_OCTEONTX |
+ BLOCKCIPHER_TEST_TARGET_PMD_OCTEONTX2
},
{
.test_descr = "3DES-192-CBC SHA1 Encryption Digest",
@@ -1296,7 +1298,8 @@ static const struct blockcipher_test_case triple_des_cipheronly_test_cases[] = {
BLOCKCIPHER_TEST_TARGET_PMD_MVSAM |
BLOCKCIPHER_TEST_TARGET_PMD_CCP |
BLOCKCIPHER_TEST_TARGET_PMD_MB |
- BLOCKCIPHER_TEST_TARGET_PMD_OCTEONTX
+ BLOCKCIPHER_TEST_TARGET_PMD_OCTEONTX |
+ BLOCKCIPHER_TEST_TARGET_PMD_OCTEONTX2
},
{
.test_descr = "3DES-192-CBC Decryption",
@@ -1310,7 +1313,8 @@ static const struct blockcipher_test_case triple_des_cipheronly_test_cases[] = {
BLOCKCIPHER_TEST_TARGET_PMD_MVSAM |
BLOCKCIPHER_TEST_TARGET_PMD_CCP |
BLOCKCIPHER_TEST_TARGET_PMD_MB |
- BLOCKCIPHER_TEST_TARGET_PMD_OCTEONTX
+ BLOCKCIPHER_TEST_TARGET_PMD_OCTEONTX |
+ BLOCKCIPHER_TEST_TARGET_PMD_OCTEONTX2
},
{
.test_descr = "3DES-128-CTR Encryption",
diff --git a/app/test/test_cryptodev_hash_test_vectors.h b/app/test/test_cryptodev_hash_test_vectors.h
index 6f201c0..cff2831 100644
--- a/app/test/test_cryptodev_hash_test_vectors.h
+++ b/app/test/test_cryptodev_hash_test_vectors.h
@@ -413,7 +413,8 @@ static const struct blockcipher_test_case hash_test_cases[] = {
.op_mask = BLOCKCIPHER_TEST_OP_AUTH_GEN,
.pmd_mask = BLOCKCIPHER_TEST_TARGET_PMD_OPENSSL |
BLOCKCIPHER_TEST_TARGET_PMD_MVSAM |
- BLOCKCIPHER_TEST_TARGET_PMD_OCTEONTX
+ BLOCKCIPHER_TEST_TARGET_PMD_OCTEONTX |
+ BLOCKCIPHER_TEST_TARGET_PMD_OCTEONTX2
},
{
.test_descr = "MD5 Digest Verify",
@@ -421,7 +422,8 @@ static const struct blockcipher_test_case hash_test_cases[] = {
.op_mask = BLOCKCIPHER_TEST_OP_AUTH_VERIFY,
.pmd_mask = BLOCKCIPHER_TEST_TARGET_PMD_OPENSSL |
BLOCKCIPHER_TEST_TARGET_PMD_MVSAM |
- BLOCKCIPHER_TEST_TARGET_PMD_OCTEONTX
+ BLOCKCIPHER_TEST_TARGET_PMD_OCTEONTX |
+ BLOCKCIPHER_TEST_TARGET_PMD_OCTEONTX2
},
{
.test_descr = "HMAC-MD5 Digest",
@@ -435,7 +437,8 @@ static const struct blockcipher_test_case hash_test_cases[] = {
BLOCKCIPHER_TEST_TARGET_PMD_CAAM_JR |
BLOCKCIPHER_TEST_TARGET_PMD_QAT |
BLOCKCIPHER_TEST_TARGET_PMD_MVSAM |
- BLOCKCIPHER_TEST_TARGET_PMD_OCTEONTX
+ BLOCKCIPHER_TEST_TARGET_PMD_OCTEONTX |
+ BLOCKCIPHER_TEST_TARGET_PMD_OCTEONTX2
},
{
.test_descr = "HMAC-MD5 Digest Verify",
@@ -449,7 +452,8 @@ static const struct blockcipher_test_case hash_test_cases[] = {
BLOCKCIPHER_TEST_TARGET_PMD_CAAM_JR |
BLOCKCIPHER_TEST_TARGET_PMD_QAT |
BLOCKCIPHER_TEST_TARGET_PMD_MVSAM |
- BLOCKCIPHER_TEST_TARGET_PMD_OCTEONTX
+ BLOCKCIPHER_TEST_TARGET_PMD_OCTEONTX |
+ BLOCKCIPHER_TEST_TARGET_PMD_OCTEONTX2
},
{
.test_descr = "SHA1 Digest",
@@ -461,7 +465,8 @@ static const struct blockcipher_test_case hash_test_cases[] = {
#if IMB_VERSION_NUM >= IMB_VERSION(0, 52, 0)
BLOCKCIPHER_TEST_TARGET_PMD_MB |
#endif
- BLOCKCIPHER_TEST_TARGET_PMD_OCTEONTX
+ BLOCKCIPHER_TEST_TARGET_PMD_OCTEONTX |
+ BLOCKCIPHER_TEST_TARGET_PMD_OCTEONTX2
},
{
.test_descr = "SHA1 Digest Verify",
@@ -473,7 +478,8 @@ static const struct blockcipher_test_case hash_test_cases[] = {
#if IMB_VERSION_NUM >= IMB_VERSION(0, 52, 0)
BLOCKCIPHER_TEST_TARGET_PMD_MB |
#endif
- BLOCKCIPHER_TEST_TARGET_PMD_OCTEONTX
+ BLOCKCIPHER_TEST_TARGET_PMD_OCTEONTX |
+ BLOCKCIPHER_TEST_TARGET_PMD_OCTEONTX2
},
{
.test_descr = "HMAC-SHA1 Digest",
@@ -488,7 +494,8 @@ static const struct blockcipher_test_case hash_test_cases[] = {
BLOCKCIPHER_TEST_TARGET_PMD_QAT |
BLOCKCIPHER_TEST_TARGET_PMD_CCP |
BLOCKCIPHER_TEST_TARGET_PMD_MVSAM |
- BLOCKCIPHER_TEST_TARGET_PMD_OCTEONTX
+ BLOCKCIPHER_TEST_TARGET_PMD_OCTEONTX |
+ BLOCKCIPHER_TEST_TARGET_PMD_OCTEONTX2
},
{
.test_descr = "HMAC-SHA1 Digest Scatter Gather",
@@ -498,7 +505,8 @@ static const struct blockcipher_test_case hash_test_cases[] = {
.pmd_mask = BLOCKCIPHER_TEST_TARGET_PMD_DPAA2_SEC |
BLOCKCIPHER_TEST_TARGET_PMD_DPAA_SEC |
BLOCKCIPHER_TEST_TARGET_PMD_CAAM_JR |
- BLOCKCIPHER_TEST_TARGET_PMD_OCTEONTX
+ BLOCKCIPHER_TEST_TARGET_PMD_OCTEONTX |
+ BLOCKCIPHER_TEST_TARGET_PMD_OCTEONTX2
},
{
.test_descr = "HMAC-SHA1 Digest Verify",
@@ -513,7 +521,8 @@ static const struct blockcipher_test_case hash_test_cases[] = {
BLOCKCIPHER_TEST_TARGET_PMD_QAT |
BLOCKCIPHER_TEST_TARGET_PMD_CCP |
BLOCKCIPHER_TEST_TARGET_PMD_MVSAM |
- BLOCKCIPHER_TEST_TARGET_PMD_OCTEONTX
+ BLOCKCIPHER_TEST_TARGET_PMD_OCTEONTX |
+ BLOCKCIPHER_TEST_TARGET_PMD_OCTEONTX2
},
{
.test_descr = "HMAC-SHA1 Digest Verify Scatter Gather",
@@ -523,7 +532,8 @@ static const struct blockcipher_test_case hash_test_cases[] = {
.pmd_mask = BLOCKCIPHER_TEST_TARGET_PMD_DPAA2_SEC |
BLOCKCIPHER_TEST_TARGET_PMD_DPAA_SEC |
BLOCKCIPHER_TEST_TARGET_PMD_CAAM_JR |
- BLOCKCIPHER_TEST_TARGET_PMD_OCTEONTX
+ BLOCKCIPHER_TEST_TARGET_PMD_OCTEONTX |
+ BLOCKCIPHER_TEST_TARGET_PMD_OCTEONTX2
},
{
.test_descr = "SHA224 Digest",
@@ -535,7 +545,8 @@ static const struct blockcipher_test_case hash_test_cases[] = {
#if IMB_VERSION_NUM >= IMB_VERSION(0, 52, 0)
BLOCKCIPHER_TEST_TARGET_PMD_MB |
#endif
- BLOCKCIPHER_TEST_TARGET_PMD_OCTEONTX
+ BLOCKCIPHER_TEST_TARGET_PMD_OCTEONTX |
+ BLOCKCIPHER_TEST_TARGET_PMD_OCTEONTX2
},
{
.test_descr = "SHA224 Digest Verify",
@@ -547,7 +558,8 @@ static const struct blockcipher_test_case hash_test_cases[] = {
#if IMB_VERSION_NUM >= IMB_VERSION(0, 52, 0)
BLOCKCIPHER_TEST_TARGET_PMD_MB |
#endif
- BLOCKCIPHER_TEST_TARGET_PMD_OCTEONTX
+ BLOCKCIPHER_TEST_TARGET_PMD_OCTEONTX |
+ BLOCKCIPHER_TEST_TARGET_PMD_OCTEONTX2
},
{
.test_descr = "HMAC-SHA224 Digest",
@@ -561,7 +573,8 @@ static const struct blockcipher_test_case hash_test_cases[] = {
BLOCKCIPHER_TEST_TARGET_PMD_CAAM_JR |
BLOCKCIPHER_TEST_TARGET_PMD_CCP |
BLOCKCIPHER_TEST_TARGET_PMD_QAT |
- BLOCKCIPHER_TEST_TARGET_PMD_OCTEONTX
+ BLOCKCIPHER_TEST_TARGET_PMD_OCTEONTX |
+ BLOCKCIPHER_TEST_TARGET_PMD_OCTEONTX2
},
{
.test_descr = "HMAC-SHA224 Digest Verify",
@@ -575,7 +588,8 @@ static const struct blockcipher_test_case hash_test_cases[] = {
BLOCKCIPHER_TEST_TARGET_PMD_CAAM_JR |
BLOCKCIPHER_TEST_TARGET_PMD_CCP |
BLOCKCIPHER_TEST_TARGET_PMD_QAT |
- BLOCKCIPHER_TEST_TARGET_PMD_OCTEONTX
+ BLOCKCIPHER_TEST_TARGET_PMD_OCTEONTX |
+ BLOCKCIPHER_TEST_TARGET_PMD_OCTEONTX2
},
{
.test_descr = "SHA256 Digest",
@@ -587,7 +601,8 @@ static const struct blockcipher_test_case hash_test_cases[] = {
#if IMB_VERSION_NUM >= IMB_VERSION(0, 52, 0)
BLOCKCIPHER_TEST_TARGET_PMD_MB |
#endif
- BLOCKCIPHER_TEST_TARGET_PMD_OCTEONTX
+ BLOCKCIPHER_TEST_TARGET_PMD_OCTEONTX |
+ BLOCKCIPHER_TEST_TARGET_PMD_OCTEONTX2
},
{
.test_descr = "SHA256 Digest Verify",
@@ -599,7 +614,8 @@ static const struct blockcipher_test_case hash_test_cases[] = {
#if IMB_VERSION_NUM >= IMB_VERSION(0, 52, 0)
BLOCKCIPHER_TEST_TARGET_PMD_MB |
#endif
- BLOCKCIPHER_TEST_TARGET_PMD_OCTEONTX
+ BLOCKCIPHER_TEST_TARGET_PMD_OCTEONTX |
+ BLOCKCIPHER_TEST_TARGET_PMD_OCTEONTX2
},
{
.test_descr = "HMAC-SHA256 Digest",
@@ -614,7 +630,8 @@ static const struct blockcipher_test_case hash_test_cases[] = {
BLOCKCIPHER_TEST_TARGET_PMD_QAT |
BLOCKCIPHER_TEST_TARGET_PMD_CCP |
BLOCKCIPHER_TEST_TARGET_PMD_MVSAM |
- BLOCKCIPHER_TEST_TARGET_PMD_OCTEONTX
+ BLOCKCIPHER_TEST_TARGET_PMD_OCTEONTX |
+ BLOCKCIPHER_TEST_TARGET_PMD_OCTEONTX2
},
{
.test_descr = "HMAC-SHA256 Digest Verify",
@@ -629,7 +646,8 @@ static const struct blockcipher_test_case hash_test_cases[] = {
BLOCKCIPHER_TEST_TARGET_PMD_QAT |
BLOCKCIPHER_TEST_TARGET_PMD_CCP |
BLOCKCIPHER_TEST_TARGET_PMD_MVSAM |
- BLOCKCIPHER_TEST_TARGET_PMD_OCTEONTX
+ BLOCKCIPHER_TEST_TARGET_PMD_OCTEONTX |
+ BLOCKCIPHER_TEST_TARGET_PMD_OCTEONTX2
},
{
.test_descr = "SHA384 Digest",
@@ -641,7 +659,8 @@ static const struct blockcipher_test_case hash_test_cases[] = {
#if IMB_VERSION_NUM >= IMB_VERSION(0, 52, 0)
BLOCKCIPHER_TEST_TARGET_PMD_MB |
#endif
- BLOCKCIPHER_TEST_TARGET_PMD_OCTEONTX
+ BLOCKCIPHER_TEST_TARGET_PMD_OCTEONTX |
+ BLOCKCIPHER_TEST_TARGET_PMD_OCTEONTX2
},
{
.test_descr = "SHA384 Digest Verify",
@@ -653,7 +672,8 @@ static const struct blockcipher_test_case hash_test_cases[] = {
#if IMB_VERSION_NUM >= IMB_VERSION(0, 52, 0)
BLOCKCIPHER_TEST_TARGET_PMD_MB |
#endif
- BLOCKCIPHER_TEST_TARGET_PMD_OCTEONTX
+ BLOCKCIPHER_TEST_TARGET_PMD_OCTEONTX |
+ BLOCKCIPHER_TEST_TARGET_PMD_OCTEONTX2
},
{
.test_descr = "HMAC-SHA384 Digest",
@@ -668,7 +688,8 @@ static const struct blockcipher_test_case hash_test_cases[] = {
BLOCKCIPHER_TEST_TARGET_PMD_QAT |
BLOCKCIPHER_TEST_TARGET_PMD_CCP |
BLOCKCIPHER_TEST_TARGET_PMD_MVSAM |
- BLOCKCIPHER_TEST_TARGET_PMD_OCTEONTX
+ BLOCKCIPHER_TEST_TARGET_PMD_OCTEONTX |
+ BLOCKCIPHER_TEST_TARGET_PMD_OCTEONTX2
},
{
.test_descr = "HMAC-SHA384 Digest Verify",
@@ -683,7 +704,8 @@ static const struct blockcipher_test_case hash_test_cases[] = {
BLOCKCIPHER_TEST_TARGET_PMD_QAT |
BLOCKCIPHER_TEST_TARGET_PMD_CCP |
BLOCKCIPHER_TEST_TARGET_PMD_MVSAM |
- BLOCKCIPHER_TEST_TARGET_PMD_OCTEONTX
+ BLOCKCIPHER_TEST_TARGET_PMD_OCTEONTX |
+ BLOCKCIPHER_TEST_TARGET_PMD_OCTEONTX2
},
{
.test_descr = "SHA512 Digest",
@@ -707,7 +729,8 @@ static const struct blockcipher_test_case hash_test_cases[] = {
#if IMB_VERSION_NUM >= IMB_VERSION(0, 52, 0)
BLOCKCIPHER_TEST_TARGET_PMD_MB |
#endif
- BLOCKCIPHER_TEST_TARGET_PMD_OCTEONTX
+ BLOCKCIPHER_TEST_TARGET_PMD_OCTEONTX |
+ BLOCKCIPHER_TEST_TARGET_PMD_OCTEONTX2
},
{
.test_descr = "HMAC-SHA512 Digest",
@@ -722,7 +745,8 @@ static const struct blockcipher_test_case hash_test_cases[] = {
BLOCKCIPHER_TEST_TARGET_PMD_QAT |
BLOCKCIPHER_TEST_TARGET_PMD_CCP |
BLOCKCIPHER_TEST_TARGET_PMD_MVSAM |
- BLOCKCIPHER_TEST_TARGET_PMD_OCTEONTX
+ BLOCKCIPHER_TEST_TARGET_PMD_OCTEONTX |
+ BLOCKCIPHER_TEST_TARGET_PMD_OCTEONTX2
},
{
.test_descr = "HMAC-SHA512 Digest Verify",
@@ -737,7 +761,8 @@ static const struct blockcipher_test_case hash_test_cases[] = {
BLOCKCIPHER_TEST_TARGET_PMD_QAT |
BLOCKCIPHER_TEST_TARGET_PMD_CCP |
BLOCKCIPHER_TEST_TARGET_PMD_MVSAM |
- BLOCKCIPHER_TEST_TARGET_PMD_OCTEONTX
+ BLOCKCIPHER_TEST_TARGET_PMD_OCTEONTX |
+ BLOCKCIPHER_TEST_TARGET_PMD_OCTEONTX2
},
{
.test_descr = "CMAC Digest 12B",
diff --git a/doc/guides/cryptodevs/octeontx2.rst b/doc/guides/cryptodevs/octeontx2.rst
index 47e9150..406d746 100644
--- a/doc/guides/cryptodevs/octeontx2.rst
+++ b/doc/guides/cryptodevs/octeontx2.rst
@@ -132,3 +132,14 @@ Debugging Options
+===+============+=======================================================+
| 1 | CPT | --log-level='pmd\.crypto\.octeontx2,8' |
+---+------------+-------------------------------------------------------+
+
+Testing
+-------
+
+The symmetric crypto operations on OCTEON TX2 crypto PMD may be verified by running the test
+application:
+
+.. code-block:: console
+
+ ./test
+ RTE>>cryptodev_octeontx2_autotest
--
2.7.4
^ permalink raw reply related [flat|nested] 53+ messages in thread* [dpdk-dev] [PATCH v2 09/12] crypto/octeontx2: allocate memory for asymmetric operation
2019-10-13 12:39 ` [dpdk-dev] [PATCH v2 00/12] " Anoob Joseph
` (7 preceding siblings ...)
2019-10-13 12:39 ` [dpdk-dev] [PATCH v2 08/12] test: add OCTEON TX2 tests Anoob Joseph
@ 2019-10-13 12:39 ` Anoob Joseph
2019-10-13 12:40 ` [dpdk-dev] [PATCH v2 10/12] crypto/octeontx2: add asymmetric session operations Anoob Joseph
` (4 subsequent siblings)
13 siblings, 0 replies; 53+ messages in thread
From: Anoob Joseph @ 2019-10-13 12:39 UTC (permalink / raw)
To: Akhil Goyal, Pablo de Lara
Cc: Kanaka Durga Kotamarthy, Fiona Trahe, Jerin Jacob,
Narayana Prasad, Shally Verma, Ankur Dwivedi, Sunila Sahu,
Tejasree Kondoj, dev, Anoob Joseph
From: Kanaka Durga Kotamarthy <kkotamarthy@marvell.com>
This patch determines metabuf length needed to perform asymmetric crypto
operation.
Signed-off-by: Anoob Joseph <anoobj@marvell.com>
Signed-off-by: Kanaka Durga Kotamarthy <kkotamarthy@marvell.com>
Signed-off-by: Sunila Sahu <ssahu@marvell.com>
---
drivers/crypto/octeontx2/otx2_cryptodev_ops.c | 37 +++++++++++++++++++--------
1 file changed, 26 insertions(+), 11 deletions(-)
diff --git a/drivers/crypto/octeontx2/otx2_cryptodev_ops.c b/drivers/crypto/octeontx2/otx2_cryptodev_ops.c
index ef6e7e7..1d35379 100644
--- a/drivers/crypto/octeontx2/otx2_cryptodev_ops.c
+++ b/drivers/crypto/octeontx2/otx2_cryptodev_ops.c
@@ -38,24 +38,39 @@ otx2_cpt_metabuf_mempool_create(const struct rte_cryptodev *dev,
int nb_elements)
{
char mempool_name[RTE_MEMPOOL_NAMESIZE];
- int sg_mlen, lb_mlen, max_mlen, ret;
struct cpt_qp_meta_info *meta_info;
struct rte_mempool *pool;
+ int ret, max_mlen;
+ int asym_mlen = 0;
+ int lb_mlen = 0;
+ int sg_mlen = 0;
- /* Get meta len for scatter gather mode */
- sg_mlen = cpt_pmd_ops_helper_get_mlen_sg_mode();
+ if (dev->feature_flags & RTE_CRYPTODEV_FF_SYMMETRIC_CRYPTO) {
- /* Extra 32B saved for future considerations */
- sg_mlen += 4 * sizeof(uint64_t);
+ /* Get meta len for scatter gather mode */
+ sg_mlen = cpt_pmd_ops_helper_get_mlen_sg_mode();
- /* Get meta len for linear buffer (direct) mode */
- lb_mlen = cpt_pmd_ops_helper_get_mlen_direct_mode();
+ /* Extra 32B saved for future considerations */
+ sg_mlen += 4 * sizeof(uint64_t);
- /* Extra 32B saved for future considerations */
- lb_mlen += 4 * sizeof(uint64_t);
+ /* Get meta len for linear buffer (direct) mode */
+ lb_mlen = cpt_pmd_ops_helper_get_mlen_direct_mode();
- /* Check max requirement for meta buffer */
- max_mlen = RTE_MAX(lb_mlen, sg_mlen);
+ /* Extra 32B saved for future considerations */
+ lb_mlen += 4 * sizeof(uint64_t);
+ }
+
+ if (dev->feature_flags & RTE_CRYPTODEV_FF_ASYMMETRIC_CRYPTO) {
+
+ /* Get meta len required for asymmetric operations */
+ asym_mlen = cpt_pmd_ops_helper_asym_get_mlen();
+ }
+
+ /*
+ * Check max requirement for meta buffer to
+ * support crypto op of any type (sym/asym).
+ */
+ max_mlen = RTE_MAX(RTE_MAX(lb_mlen, sg_mlen), asym_mlen);
/* Allocate mempool */
--
2.7.4
^ permalink raw reply related [flat|nested] 53+ messages in thread* [dpdk-dev] [PATCH v2 10/12] crypto/octeontx2: add asymmetric session operations
2019-10-13 12:39 ` [dpdk-dev] [PATCH v2 00/12] " Anoob Joseph
` (8 preceding siblings ...)
2019-10-13 12:39 ` [dpdk-dev] [PATCH v2 09/12] crypto/octeontx2: allocate memory for asymmetric operation Anoob Joseph
@ 2019-10-13 12:40 ` Anoob Joseph
2019-10-13 12:40 ` [dpdk-dev] [PATCH v2 11/12] crypto/octeontx2: add asymmetric in enqueue/dequeue ops Anoob Joseph
` (3 subsequent siblings)
13 siblings, 0 replies; 53+ messages in thread
From: Anoob Joseph @ 2019-10-13 12:40 UTC (permalink / raw)
To: Akhil Goyal, Pablo de Lara
Cc: Kanaka Durga Kotamarthy, Fiona Trahe, Jerin Jacob,
Narayana Prasad, Shally Verma, Ankur Dwivedi, Sunila Sahu,
Tejasree Kondoj, dev, Anoob Joseph
From: Kanaka Durga Kotamarthy <kkotamarthy@marvell.com>
This patch adds asymmetric session setup and free routines. RSA and
modexp operations are supported.
Signed-off-by: Anoob Joseph <anoobj@marvell.com>
Signed-off-by: Kanaka Durga Kotamarthy <kkotamarthy@marvell.com>
Signed-off-by: Sunila Sahu <ssahu@marvell.com>
---
doc/guides/cryptodevs/features/octeontx2.ini | 4 ++
doc/guides/cryptodevs/octeontx2.rst | 6 ++
drivers/crypto/octeontx2/otx2_cryptodev.c | 4 +-
.../crypto/octeontx2/otx2_cryptodev_capabilities.c | 39 ++++++++++++-
drivers/crypto/octeontx2/otx2_cryptodev_ops.c | 67 ++++++++++++++++++++++
5 files changed, 117 insertions(+), 3 deletions(-)
diff --git a/doc/guides/cryptodevs/features/octeontx2.ini b/doc/guides/cryptodevs/features/octeontx2.ini
index 4e82463..7d07053 100644
--- a/doc/guides/cryptodevs/features/octeontx2.ini
+++ b/doc/guides/cryptodevs/features/octeontx2.ini
@@ -5,11 +5,13 @@
;
[Features]
Symmetric crypto = Y
+Asymmetric crypto = Y
Sym operation chaining = Y
HW Accelerated = Y
In Place SGL = Y
OOP SGL In LB Out = Y
OOP SGL In SGL Out = Y
+RSA PRIV OP KEY QT = Y
;
; Supported crypto algorithms of 'octeontx2' crypto driver.
@@ -65,3 +67,5 @@ AES GCM (256) = Y
; Supported Asymmetric algorithms of the 'octeontx2' crypto driver.
;
[Asymmetric]
+RSA = Y
+Modular Exponentiation = Y
diff --git a/doc/guides/cryptodevs/octeontx2.rst b/doc/guides/cryptodevs/octeontx2.rst
index 406d746..ad33c66 100644
--- a/doc/guides/cryptodevs/octeontx2.rst
+++ b/doc/guides/cryptodevs/octeontx2.rst
@@ -56,6 +56,12 @@ AEAD algorithms:
* ``RTE_CRYPTO_AEAD_AES_GCM``
+Asymmetric Crypto Algorithms
+~~~~~~~~~~~~~~~~~~~~~~~~~~~~
+
+* ``RTE_CRYPTO_ASYM_XFORM_RSA``
+* ``RTE_CRYPTO_ASYM_XFORM_MODEX``
+
Installation
------------
diff --git a/drivers/crypto/octeontx2/otx2_cryptodev.c b/drivers/crypto/octeontx2/otx2_cryptodev.c
index 32c0b48..7fd216b 100644
--- a/drivers/crypto/octeontx2/otx2_cryptodev.c
+++ b/drivers/crypto/octeontx2/otx2_cryptodev.c
@@ -99,7 +99,9 @@ otx2_cpt_pci_probe(struct rte_pci_driver *pci_drv __rte_unused,
RTE_CRYPTODEV_FF_SYM_OPERATION_CHAINING |
RTE_CRYPTODEV_FF_IN_PLACE_SGL |
RTE_CRYPTODEV_FF_OOP_SGL_IN_LB_OUT |
- RTE_CRYPTODEV_FF_OOP_SGL_IN_SGL_OUT;
+ RTE_CRYPTODEV_FF_OOP_SGL_IN_SGL_OUT |
+ RTE_CRYPTODEV_FF_ASYMMETRIC_CRYPTO |
+ RTE_CRYPTODEV_FF_RSA_PRIV_OP_KEY_QT;
return 0;
diff --git a/drivers/crypto/octeontx2/otx2_cryptodev_capabilities.c b/drivers/crypto/octeontx2/otx2_cryptodev_capabilities.c
index 3a70470..b9e3fe3 100644
--- a/drivers/crypto/octeontx2/otx2_cryptodev_capabilities.c
+++ b/drivers/crypto/octeontx2/otx2_cryptodev_capabilities.c
@@ -6,7 +6,8 @@
#include "otx2_cryptodev_capabilities.h"
-static const struct rte_cryptodev_capabilities otx2_cpt_sym_capabilities[] = {
+static const struct
+rte_cryptodev_capabilities otx2_cpt_capabilities[] = {
/* Symmetric capabilities */
{ /* NULL (AUTH) */
.op = RTE_CRYPTO_OP_TYPE_SYMMETRIC,
@@ -594,11 +595,45 @@ static const struct rte_cryptodev_capabilities otx2_cpt_sym_capabilities[] = {
}, }
},
/* End of symmetric capabilities */
+
+ /* Asymmetric capabilities */
+ { /* RSA */
+ .op = RTE_CRYPTO_OP_TYPE_ASYMMETRIC,
+ {.asym = {
+ .xform_capa = {
+ .xform_type = RTE_CRYPTO_ASYM_XFORM_RSA,
+ .op_types = ((1 << RTE_CRYPTO_ASYM_OP_SIGN) |
+ (1 << RTE_CRYPTO_ASYM_OP_VERIFY) |
+ (1 << RTE_CRYPTO_ASYM_OP_ENCRYPT) |
+ (1 << RTE_CRYPTO_ASYM_OP_DECRYPT)),
+ {.modlen = {
+ .min = 17,
+ .max = 1024,
+ .increment = 1
+ }, }
+ }
+ }, }
+ },
+ { /* MOD_EXP */
+ .op = RTE_CRYPTO_OP_TYPE_ASYMMETRIC,
+ {.asym = {
+ .xform_capa = {
+ .xform_type = RTE_CRYPTO_ASYM_XFORM_MODEX,
+ .op_types = 0,
+ {.modlen = {
+ .min = 17,
+ .max = 1024,
+ .increment = 1
+ }, }
+ }
+ }, }
+ },
+ /* End of asymmetric capabilities */
RTE_CRYPTODEV_END_OF_CAPABILITIES_LIST()
};
const struct rte_cryptodev_capabilities *
otx2_cpt_capabilities_get(void)
{
- return otx2_cpt_sym_capabilities;
+ return otx2_cpt_capabilities;
}
diff --git a/drivers/crypto/octeontx2/otx2_cryptodev_ops.c b/drivers/crypto/octeontx2/otx2_cryptodev_ops.c
index 1d35379..fbca4dc 100644
--- a/drivers/crypto/octeontx2/otx2_cryptodev_ops.c
+++ b/drivers/crypto/octeontx2/otx2_cryptodev_ops.c
@@ -18,6 +18,7 @@
#include "cpt_pmd_logs.h"
#include "cpt_pmd_ops_helper.h"
#include "cpt_ucode.h"
+#include "cpt_ucode_asym.h"
#define METABUF_POOL_CACHE_SIZE 512
@@ -835,6 +836,66 @@ otx2_cpt_sym_session_clear(struct rte_cryptodev *dev,
return sym_session_clear(dev->driver_id, sess);
}
+static unsigned int
+otx2_cpt_asym_session_size_get(struct rte_cryptodev *dev __rte_unused)
+{
+ return sizeof(struct cpt_asym_sess_misc);
+}
+
+static int
+otx2_cpt_asym_session_cfg(struct rte_cryptodev *dev,
+ struct rte_crypto_asym_xform *xform,
+ struct rte_cryptodev_asym_session *sess,
+ struct rte_mempool *pool)
+{
+ struct cpt_asym_sess_misc *priv;
+ int ret;
+
+ CPT_PMD_INIT_FUNC_TRACE();
+
+ if (rte_mempool_get(pool, (void **)&priv)) {
+ CPT_LOG_ERR("Could not allocate session_private_data");
+ return -ENOMEM;
+ }
+
+ memset(priv, 0, sizeof(struct cpt_asym_sess_misc));
+
+ ret = cpt_fill_asym_session_parameters(priv, xform);
+ if (ret) {
+ CPT_LOG_ERR("Could not configure session parameters");
+
+ /* Return session to mempool */
+ rte_mempool_put(pool, priv);
+ return ret;
+ }
+
+ set_asym_session_private_data(sess, dev->driver_id, priv);
+ return 0;
+}
+
+static void
+otx2_cpt_asym_session_clear(struct rte_cryptodev *dev,
+ struct rte_cryptodev_asym_session *sess)
+{
+ struct cpt_asym_sess_misc *priv;
+ struct rte_mempool *sess_mp;
+
+ CPT_PMD_INIT_FUNC_TRACE();
+
+ priv = get_asym_session_private_data(sess, dev->driver_id);
+ if (priv == NULL)
+ return;
+
+ /* Free resources allocated in session_cfg */
+ cpt_free_asym_session_parameters(priv);
+
+ /* Reset and free object back to pool */
+ memset(priv, 0, otx2_cpt_asym_session_size_get(dev));
+ sess_mp = rte_mempool_from_obj(priv);
+ set_asym_session_private_data(sess, dev->driver_id, NULL);
+ rte_mempool_put(sess_mp, priv);
+}
+
struct rte_cryptodev_ops otx2_cpt_ops = {
/* Device control ops */
.dev_configure = otx2_cpt_dev_config,
@@ -853,4 +914,10 @@ struct rte_cryptodev_ops otx2_cpt_ops = {
.sym_session_get_size = otx2_cpt_sym_session_get_size,
.sym_session_configure = otx2_cpt_sym_session_configure,
.sym_session_clear = otx2_cpt_sym_session_clear,
+
+ /* Asymmetric crypto ops */
+ .asym_session_get_size = otx2_cpt_asym_session_size_get,
+ .asym_session_configure = otx2_cpt_asym_session_cfg,
+ .asym_session_clear = otx2_cpt_asym_session_clear,
+
};
--
2.7.4
^ permalink raw reply related [flat|nested] 53+ messages in thread* [dpdk-dev] [PATCH v2 11/12] crypto/octeontx2: add asymmetric in enqueue/dequeue ops
2019-10-13 12:39 ` [dpdk-dev] [PATCH v2 00/12] " Anoob Joseph
` (9 preceding siblings ...)
2019-10-13 12:40 ` [dpdk-dev] [PATCH v2 10/12] crypto/octeontx2: add asymmetric session operations Anoob Joseph
@ 2019-10-13 12:40 ` Anoob Joseph
2019-10-13 12:40 ` [dpdk-dev] [PATCH v2 12/12] app/test: register octeontx2 PMD to asym testsuite Anoob Joseph
` (2 subsequent siblings)
13 siblings, 0 replies; 53+ messages in thread
From: Anoob Joseph @ 2019-10-13 12:40 UTC (permalink / raw)
To: Akhil Goyal, Pablo de Lara
Cc: Sunila Sahu, Fiona Trahe, Jerin Jacob, Narayana Prasad,
Shally Verma, Ankur Dwivedi, Kanaka Durga Kotamarthy,
Tejasree Kondoj, dev, Anoob Joseph
From: Sunila Sahu <ssahu@marvell.com>
This patch adds asymmetric support in enqueue/dequeue ops.
Signed-off-by: Anoob Joseph <anoobj@marvell.com>
Signed-off-by: Kanaka Durga Kotamarthy <kkotamarthy@marvell.com>
Signed-off-by: Sunila Sahu <ssahu@marvell.com>
---
drivers/crypto/octeontx2/otx2_cryptodev_ops.c | 177 ++++++++++++++++++++++++++
drivers/crypto/octeontx2/otx2_cryptodev_ops.h | 1 +
2 files changed, 178 insertions(+)
diff --git a/drivers/crypto/octeontx2/otx2_cryptodev_ops.c b/drivers/crypto/octeontx2/otx2_cryptodev_ops.c
index fbca4dc..db8fe66 100644
--- a/drivers/crypto/octeontx2/otx2_cryptodev_ops.c
+++ b/drivers/crypto/octeontx2/otx2_cryptodev_ops.c
@@ -393,6 +393,78 @@ otx2_cpt_enqueue_req(const struct otx2_cpt_qp *qp,
return 0;
}
+static __rte_always_inline int32_t __hot
+otx2_cpt_enqueue_asym(struct otx2_cpt_qp *qp,
+ struct rte_crypto_op *op,
+ struct pending_queue *pend_q)
+{
+ struct cpt_qp_meta_info *minfo = &qp->meta_info;
+ struct rte_crypto_asym_op *asym_op = op->asym;
+ struct asym_op_params params = {0};
+ struct cpt_asym_sess_misc *sess;
+ vq_cmd_word3_t *w3;
+ uintptr_t *cop;
+ void *mdata;
+ int ret;
+
+ if (unlikely(rte_mempool_get(minfo->pool, &mdata) < 0)) {
+ CPT_LOG_ERR("Could not allocate meta buffer for request");
+ return -ENOMEM;
+ }
+
+ sess = get_asym_session_private_data(asym_op->session,
+ otx2_cryptodev_driver_id);
+
+ /* Store IO address of the mdata to meta_buf */
+ params.meta_buf = rte_mempool_virt2iova(mdata);
+
+ cop = mdata;
+ cop[0] = (uintptr_t)mdata;
+ cop[1] = (uintptr_t)op;
+ cop[2] = cop[3] = 0ULL;
+
+ params.req = RTE_PTR_ADD(cop, 4 * sizeof(uintptr_t));
+ params.req->op = cop;
+
+ /* Adjust meta_buf to point to end of cpt_request_info structure */
+ params.meta_buf += (4 * sizeof(uintptr_t)) +
+ sizeof(struct cpt_request_info);
+ switch (sess->xfrm_type) {
+ case RTE_CRYPTO_ASYM_XFORM_MODEX:
+ ret = cpt_modex_prep(¶ms, &sess->mod_ctx);
+ if (unlikely(ret))
+ goto req_fail;
+ break;
+ case RTE_CRYPTO_ASYM_XFORM_RSA:
+ ret = cpt_enqueue_rsa_op(op, ¶ms, sess);
+ if (unlikely(ret))
+ goto req_fail;
+ break;
+ default:
+ op->status = RTE_CRYPTO_OP_STATUS_INVALID_ARGS;
+ ret = -EINVAL;
+ goto req_fail;
+ }
+
+ /* Set engine group of AE */
+ w3 = (vq_cmd_word3_t *)¶ms.req->ist.ei3;
+ w3->s.grp = OTX2_CPT_EGRP_AE;
+
+ ret = otx2_cpt_enqueue_req(qp, pend_q, params.req);
+
+ if (unlikely(ret)) {
+ CPT_LOG_DP_ERR("Could not enqueue crypto req");
+ goto req_fail;
+ }
+
+ return 0;
+
+req_fail:
+ free_op_meta(mdata, minfo->pool);
+
+ return ret;
+}
+
static __rte_always_inline int __hot
otx2_cpt_enqueue_sym(struct otx2_cpt_qp *qp, struct rte_crypto_op *op,
struct pending_queue *pend_q)
@@ -494,6 +566,11 @@ otx2_cpt_enqueue_burst(void *qptr, struct rte_crypto_op **ops, uint16_t nb_ops)
else
ret = otx2_cpt_enqueue_sym_sessless(qp, op,
pend_q);
+ } else if (op->type == RTE_CRYPTO_OP_TYPE_ASYMMETRIC) {
+ if (op->sess_type == RTE_CRYPTO_OP_WITH_SESSION)
+ ret = otx2_cpt_enqueue_asym(qp, op, pend_q);
+ else
+ break;
} else
break;
@@ -504,6 +581,92 @@ otx2_cpt_enqueue_burst(void *qptr, struct rte_crypto_op **ops, uint16_t nb_ops)
return count;
}
+static __rte_always_inline void
+otx2_cpt_asym_rsa_op(struct rte_crypto_op *cop, struct cpt_request_info *req,
+ struct rte_crypto_rsa_xform *rsa_ctx)
+{
+ struct rte_crypto_rsa_op_param *rsa = &cop->asym->rsa;
+
+ switch (rsa->op_type) {
+ case RTE_CRYPTO_ASYM_OP_ENCRYPT:
+ rsa->cipher.length = rsa_ctx->n.length;
+ memcpy(rsa->cipher.data, req->rptr, rsa->cipher.length);
+ break;
+ case RTE_CRYPTO_ASYM_OP_DECRYPT:
+ if (rsa->pad == RTE_CRYPTO_RSA_PADDING_NONE) {
+ rsa->message.length = rsa_ctx->n.length;
+ memcpy(rsa->message.data, req->rptr,
+ rsa->message.length);
+ } else {
+ /* Get length of decrypted output */
+ rsa->message.length = rte_cpu_to_be_16
+ (*((uint16_t *)req->rptr));
+ /*
+ * Offset output data pointer by length field
+ * (2 bytes) and copy decrypted data.
+ */
+ memcpy(rsa->message.data, req->rptr + 2,
+ rsa->message.length);
+ }
+ break;
+ case RTE_CRYPTO_ASYM_OP_SIGN:
+ rsa->sign.length = rsa_ctx->n.length;
+ memcpy(rsa->sign.data, req->rptr, rsa->sign.length);
+ break;
+ case RTE_CRYPTO_ASYM_OP_VERIFY:
+ if (rsa->pad == RTE_CRYPTO_RSA_PADDING_NONE) {
+ rsa->sign.length = rsa_ctx->n.length;
+ memcpy(rsa->sign.data, req->rptr, rsa->sign.length);
+ } else {
+ /* Get length of signed output */
+ rsa->sign.length = rte_cpu_to_be_16
+ (*((uint16_t *)req->rptr));
+ /*
+ * Offset output data pointer by length field
+ * (2 bytes) and copy signed data.
+ */
+ memcpy(rsa->sign.data, req->rptr + 2,
+ rsa->sign.length);
+ }
+ if (memcmp(rsa->sign.data, rsa->message.data,
+ rsa->message.length)) {
+ CPT_LOG_DP_ERR("RSA verification failed");
+ cop->status = RTE_CRYPTO_OP_STATUS_ERROR;
+ }
+ break;
+ default:
+ CPT_LOG_DP_DEBUG("Invalid RSA operation type");
+ cop->status = RTE_CRYPTO_OP_STATUS_INVALID_ARGS;
+ break;
+ }
+}
+
+static void
+otx2_cpt_asym_post_process(struct rte_crypto_op *cop,
+ struct cpt_request_info *req)
+{
+ struct rte_crypto_asym_op *op = cop->asym;
+ struct cpt_asym_sess_misc *sess;
+
+ sess = get_asym_session_private_data(op->session,
+ otx2_cryptodev_driver_id);
+
+ switch (sess->xfrm_type) {
+ case RTE_CRYPTO_ASYM_XFORM_RSA:
+ otx2_cpt_asym_rsa_op(cop, req, &sess->rsa_ctx);
+ break;
+ case RTE_CRYPTO_ASYM_XFORM_MODEX:
+ op->modex.result.length = sess->mod_ctx.modulus.length;
+ memcpy(op->modex.result.data, req->rptr,
+ op->modex.result.length);
+ break;
+ default:
+ CPT_LOG_DP_DEBUG("Invalid crypto xform type");
+ cop->status = RTE_CRYPTO_OP_STATUS_INVALID_ARGS;
+ break;
+ }
+}
+
static inline void
otx2_cpt_dequeue_post_process(struct otx2_cpt_qp *qp, struct rte_crypto_op *cop,
uintptr_t *rsp, uint8_t cc)
@@ -530,6 +693,20 @@ otx2_cpt_dequeue_post_process(struct otx2_cpt_qp *qp, struct rte_crypto_op *cop,
cop->sym->session = NULL;
}
}
+
+ if (cop->type == RTE_CRYPTO_OP_TYPE_ASYMMETRIC) {
+ if (likely(cc == NO_ERR)) {
+ cop->status = RTE_CRYPTO_OP_STATUS_SUCCESS;
+ /*
+ * Pass cpt_req_info stored in metabuf during
+ * enqueue.
+ */
+ rsp = RTE_PTR_ADD(rsp, 4 * sizeof(uintptr_t));
+ otx2_cpt_asym_post_process(cop,
+ (struct cpt_request_info *)rsp);
+ } else
+ cop->status = RTE_CRYPTO_OP_STATUS_ERROR;
+ }
}
static __rte_always_inline uint8_t
diff --git a/drivers/crypto/octeontx2/otx2_cryptodev_ops.h b/drivers/crypto/octeontx2/otx2_cryptodev_ops.h
index ba93a66..a2724f7 100644
--- a/drivers/crypto/octeontx2/otx2_cryptodev_ops.h
+++ b/drivers/crypto/octeontx2/otx2_cryptodev_ops.h
@@ -13,6 +13,7 @@
enum otx2_cpt_egrp {
OTX2_CPT_EGRP_SE = 0,
OTX2_CPT_EGRP_SE_IE = 1,
+ OTX2_CPT_EGRP_AE = 2
};
struct rte_cryptodev_ops otx2_cpt_ops;
--
2.7.4
^ permalink raw reply related [flat|nested] 53+ messages in thread* [dpdk-dev] [PATCH v2 12/12] app/test: register octeontx2 PMD to asym testsuite
2019-10-13 12:39 ` [dpdk-dev] [PATCH v2 00/12] " Anoob Joseph
` (10 preceding siblings ...)
2019-10-13 12:40 ` [dpdk-dev] [PATCH v2 11/12] crypto/octeontx2: add asymmetric in enqueue/dequeue ops Anoob Joseph
@ 2019-10-13 12:40 ` Anoob Joseph
2019-10-16 13:32 ` [dpdk-dev] [PATCH v2 00/12] add OCTEON TX2 crypto PMD Akhil Goyal
2019-10-16 15:25 ` [dpdk-dev] [PATCH v3 00/11] " Anoob Joseph
13 siblings, 0 replies; 53+ messages in thread
From: Anoob Joseph @ 2019-10-13 12:40 UTC (permalink / raw)
To: Akhil Goyal, Pablo de Lara
Cc: Sunila Sahu, Fiona Trahe, Jerin Jacob, Narayana Prasad,
Shally Verma, Ankur Dwivedi, Kanaka Durga Kotamarthy,
Tejasree Kondoj, dev, Anoob Joseph
From: Sunila Sahu <ssahu@marvell.com>
This patch updates asymmetric crypto unit-test application to
validate asymmetric crypto operation supported by octeontx2 PMD.
Signed-off-by: Anoob Joseph <anoobj@marvell.com>
Signed-off-by: Kanaka Durga Kotamarthy <kkotamarthy@marvell.com>
Signed-off-by: Sunila Sahu <ssahu@marvell.com>
---
app/test/test_cryptodev_asym.c | 20 ++++++++++++++++++++
doc/guides/cryptodevs/octeontx2.rst | 8 ++++++++
2 files changed, 28 insertions(+)
diff --git a/app/test/test_cryptodev_asym.c b/app/test/test_cryptodev_asym.c
index 241c384..6cc2f97 100644
--- a/app/test/test_cryptodev_asym.c
+++ b/app/test/test_cryptodev_asym.c
@@ -1851,6 +1851,23 @@ test_cryptodev_octeontx_asym(void)
return unit_test_suite_runner(&cryptodev_octeontx_asym_testsuite);
}
+static int
+test_cryptodev_octeontx2_asym(void)
+{
+ gbl_driver_id = rte_cryptodev_driver_id_get(
+ RTE_STR(CRYPTODEV_NAME_OCTEONTX2_PMD));
+ if (gbl_driver_id == -1) {
+ RTE_LOG(ERR, USER1, "OCTEONTX2 PMD must be loaded. Check if "
+ "CONFIG_RTE_LIBRTE_PMD_OCTEONTX2_CRYPTO is "
+ "enabled in config file to run this "
+ "testsuite.\n");
+ return TEST_FAILED;
+ }
+
+ /* Use test suite registered for crypto_octeontx PMD */
+ return unit_test_suite_runner(&cryptodev_octeontx_asym_testsuite);
+}
+
REGISTER_TEST_COMMAND(cryptodev_openssl_asym_autotest,
test_cryptodev_openssl_asym);
@@ -1858,3 +1875,6 @@ REGISTER_TEST_COMMAND(cryptodev_qat_asym_autotest, test_cryptodev_qat_asym);
REGISTER_TEST_COMMAND(cryptodev_octeontx_asym_autotest,
test_cryptodev_octeontx_asym);
+
+REGISTER_TEST_COMMAND(cryptodev_octeontx2_asym_autotest,
+ test_cryptodev_octeontx2_asym);
diff --git a/doc/guides/cryptodevs/octeontx2.rst b/doc/guides/cryptodevs/octeontx2.rst
index ad33c66..8bdb83f 100644
--- a/doc/guides/cryptodevs/octeontx2.rst
+++ b/doc/guides/cryptodevs/octeontx2.rst
@@ -149,3 +149,11 @@ application:
./test
RTE>>cryptodev_octeontx2_autotest
+
+The asymmetric crypto operations on OCTEON TX2 crypto PMD may be verified by running the test
+application:
+
+.. code-block:: console
+
+ ./test
+ RTE>>cryptodev_octeontx2_asym_autotest
--
2.7.4
^ permalink raw reply related [flat|nested] 53+ messages in thread* Re: [dpdk-dev] [PATCH v2 00/12] add OCTEON TX2 crypto PMD
2019-10-13 12:39 ` [dpdk-dev] [PATCH v2 00/12] " Anoob Joseph
` (11 preceding siblings ...)
2019-10-13 12:40 ` [dpdk-dev] [PATCH v2 12/12] app/test: register octeontx2 PMD to asym testsuite Anoob Joseph
@ 2019-10-16 13:32 ` Akhil Goyal
2019-10-16 13:39 ` Anoob Joseph
2019-10-16 15:25 ` [dpdk-dev] [PATCH v3 00/11] " Anoob Joseph
13 siblings, 1 reply; 53+ messages in thread
From: Akhil Goyal @ 2019-10-16 13:32 UTC (permalink / raw)
To: Anoob Joseph, Pablo de Lara
Cc: Fiona Trahe, Jerin Jacob, Narayana Prasad, Shally Verma,
Ankur Dwivedi, Kanaka Durga Kotamarthy, Sunila Sahu,
Tejasree Kondoj, dev@dpdk.org
Please rebase this series. Build cannot be verified by CI. There are apply issues.
>
> The series introduces poll mode driver to enable crypto offload engine
> on Marvell OCTEON TX2 SoC.
>
> Changes in v2:
> * Merged series adding sym features and asym features into one.
> * Squashed patches as directed by Akhil.
> * Added check for ASYM SESSIONLESS (not supported currently)
> * Minor updates to documentation
>
> Ankur Dwivedi (3):
> crypto/octeontx2: add device control ops
> crypto/octeontx2: add queue pair functions
> crypto/octeontx2: add session related functions
>
> Anoob Joseph (5):
> crypto/octeontx2: add PMD skeleton
> crypto/octeontx2: add device init sequence in probe
> crypto/octeontx2: add symmetric capabilities
> crypto/octeontx2: add enqueue/dequeue ops
> test: add OCTEON TX2 tests
>
> Kanaka Durga Kotamarthy (2):
> crypto/octeontx2: allocate memory for asymmetric operation
> crypto/octeontx2: add asymmetric session operations
>
> Sunila Sahu (2):
> crypto/octeontx2: add asymmetric in enqueue/dequeue ops
> app/test: register octeontx2 PMD to asym testsuite
>
> MAINTAINERS | 7 +
> app/test/meson.build | 1 +
> app/test/test_cryptodev.c | 323 ++++++
> app/test/test_cryptodev.h | 1 +
> app/test/test_cryptodev_aes_test_vectors.h | 114 +-
> app/test/test_cryptodev_asym.c | 20 +
> app/test/test_cryptodev_blockcipher.c | 7 +
> app/test/test_cryptodev_blockcipher.h | 1 +
> app/test/test_cryptodev_des_test_vectors.h | 12 +-
> app/test/test_cryptodev_hash_test_vectors.h | 75 +-
> config/common_base | 5 +
> doc/guides/cryptodevs/features/octeontx2.ini | 71 ++
> doc/guides/cryptodevs/index.rst | 1 +
> doc/guides/cryptodevs/octeontx2.rst | 159 +++
> doc/guides/platform/octeontx2.rst | 3 +
> doc/guides/rel_notes/release_19_11.rst | 6 +
> drivers/common/Makefile | 5 +-
> drivers/common/cpt/cpt_hw_types.h | 52 +
> drivers/common/cpt/cpt_mcode_defines.h | 2 +
> drivers/crypto/Makefile | 1 +
> drivers/crypto/meson.build | 21 +-
> drivers/crypto/octeontx2/Makefile | 50 +
> drivers/crypto/octeontx2/meson.build | 34 +
> drivers/crypto/octeontx2/otx2_cryptodev.c | 157 +++
> drivers/crypto/octeontx2/otx2_cryptodev.h | 43 +
> .../crypto/octeontx2/otx2_cryptodev_capabilities.c | 639 ++++++++++++
> .../crypto/octeontx2/otx2_cryptodev_capabilities.h | 16 +
> .../crypto/octeontx2/otx2_cryptodev_hw_access.c | 225 ++++
> .../crypto/octeontx2/otx2_cryptodev_hw_access.h | 169 +++
> drivers/crypto/octeontx2/otx2_cryptodev_mbox.c | 175 ++++
> drivers/crypto/octeontx2/otx2_cryptodev_mbox.h | 25 +
> drivers/crypto/octeontx2/otx2_cryptodev_ops.c | 1100
> ++++++++++++++++++++
> drivers/crypto/octeontx2/otx2_cryptodev_ops.h | 21 +
> .../octeontx2/rte_pmd_octeontx2_crypto_version.map | 4 +
> mk/rte.app.mk | 6 +-
> 35 files changed, 3479 insertions(+), 72 deletions(-)
> create mode 100644 doc/guides/cryptodevs/features/octeontx2.ini
> create mode 100644 doc/guides/cryptodevs/octeontx2.rst
> create mode 100644 drivers/crypto/octeontx2/Makefile
> create mode 100644 drivers/crypto/octeontx2/meson.build
> create mode 100644 drivers/crypto/octeontx2/otx2_cryptodev.c
> create mode 100644 drivers/crypto/octeontx2/otx2_cryptodev.h
> create mode 100644 drivers/crypto/octeontx2/otx2_cryptodev_capabilities.c
> create mode 100644 drivers/crypto/octeontx2/otx2_cryptodev_capabilities.h
> create mode 100644 drivers/crypto/octeontx2/otx2_cryptodev_hw_access.c
> create mode 100644 drivers/crypto/octeontx2/otx2_cryptodev_hw_access.h
> create mode 100644 drivers/crypto/octeontx2/otx2_cryptodev_mbox.c
> create mode 100644 drivers/crypto/octeontx2/otx2_cryptodev_mbox.h
> create mode 100644 drivers/crypto/octeontx2/otx2_cryptodev_ops.c
> create mode 100644 drivers/crypto/octeontx2/otx2_cryptodev_ops.h
> create mode 100644
> drivers/crypto/octeontx2/rte_pmd_octeontx2_crypto_version.map
>
> --
> 2.7.4
^ permalink raw reply [flat|nested] 53+ messages in thread* Re: [dpdk-dev] [PATCH v2 00/12] add OCTEON TX2 crypto PMD
2019-10-16 13:32 ` [dpdk-dev] [PATCH v2 00/12] add OCTEON TX2 crypto PMD Akhil Goyal
@ 2019-10-16 13:39 ` Anoob Joseph
0 siblings, 0 replies; 53+ messages in thread
From: Anoob Joseph @ 2019-10-16 13:39 UTC (permalink / raw)
To: Akhil Goyal, Pablo de Lara
Cc: Fiona Trahe, Jerin Jacob Kollanukkaran,
Narayana Prasad Raju Athreya, Shally Verma, Ankur Dwivedi,
Kanaka Durga Kotamarthy, Sunila Sahu, Tejasree Kondoj,
dev@dpdk.org
Hi Akhil,
I'll rebase the series and send in a short while.
Thanks,
Anoob
> -----Original Message-----
> From: Akhil Goyal <akhil.goyal@nxp.com>
> Sent: Wednesday, October 16, 2019 7:02 PM
> To: Anoob Joseph <anoobj@marvell.com>; Pablo de Lara
> <pablo.de.lara.guarch@intel.com>
> Cc: Fiona Trahe <fiona.trahe@intel.com>; Jerin Jacob Kollanukkaran
> <jerinj@marvell.com>; Narayana Prasad Raju Athreya
> <pathreya@marvell.com>; Shally Verma <shallyv@marvell.com>; Ankur Dwivedi
> <adwivedi@marvell.com>; Kanaka Durga Kotamarthy
> <kkotamarthy@marvell.com>; Sunila Sahu <ssahu@marvell.com>; Tejasree
> Kondoj <ktejasree@marvell.com>; dev@dpdk.org
> Subject: [EXT] RE: [PATCH v2 00/12] add OCTEON TX2 crypto PMD
>
> External Email
>
> ----------------------------------------------------------------------
> Please rebase this series. Build cannot be verified by CI. There are apply issues.
> >
> > The series introduces poll mode driver to enable crypto offload engine
> > on Marvell OCTEON TX2 SoC.
> >
> > Changes in v2:
> > * Merged series adding sym features and asym features into one.
> > * Squashed patches as directed by Akhil.
> > * Added check for ASYM SESSIONLESS (not supported currently)
> > * Minor updates to documentation
> >
> > Ankur Dwivedi (3):
> > crypto/octeontx2: add device control ops
> > crypto/octeontx2: add queue pair functions
> > crypto/octeontx2: add session related functions
> >
> > Anoob Joseph (5):
> > crypto/octeontx2: add PMD skeleton
> > crypto/octeontx2: add device init sequence in probe
> > crypto/octeontx2: add symmetric capabilities
> > crypto/octeontx2: add enqueue/dequeue ops
> > test: add OCTEON TX2 tests
> >
> > Kanaka Durga Kotamarthy (2):
> > crypto/octeontx2: allocate memory for asymmetric operation
> > crypto/octeontx2: add asymmetric session operations
> >
> > Sunila Sahu (2):
> > crypto/octeontx2: add asymmetric in enqueue/dequeue ops
> > app/test: register octeontx2 PMD to asym testsuite
> >
> > MAINTAINERS | 7 +
> > app/test/meson.build | 1 +
> > app/test/test_cryptodev.c | 323 ++++++
> > app/test/test_cryptodev.h | 1 +
> > app/test/test_cryptodev_aes_test_vectors.h | 114 +-
> > app/test/test_cryptodev_asym.c | 20 +
> > app/test/test_cryptodev_blockcipher.c | 7 +
> > app/test/test_cryptodev_blockcipher.h | 1 +
> > app/test/test_cryptodev_des_test_vectors.h | 12 +-
> > app/test/test_cryptodev_hash_test_vectors.h | 75 +-
> > config/common_base | 5 +
> > doc/guides/cryptodevs/features/octeontx2.ini | 71 ++
> > doc/guides/cryptodevs/index.rst | 1 +
> > doc/guides/cryptodevs/octeontx2.rst | 159 +++
> > doc/guides/platform/octeontx2.rst | 3 +
> > doc/guides/rel_notes/release_19_11.rst | 6 +
> > drivers/common/Makefile | 5 +-
> > drivers/common/cpt/cpt_hw_types.h | 52 +
> > drivers/common/cpt/cpt_mcode_defines.h | 2 +
> > drivers/crypto/Makefile | 1 +
> > drivers/crypto/meson.build | 21 +-
> > drivers/crypto/octeontx2/Makefile | 50 +
> > drivers/crypto/octeontx2/meson.build | 34 +
> > drivers/crypto/octeontx2/otx2_cryptodev.c | 157 +++
> > drivers/crypto/octeontx2/otx2_cryptodev.h | 43 +
> > .../crypto/octeontx2/otx2_cryptodev_capabilities.c | 639 ++++++++++++
> > .../crypto/octeontx2/otx2_cryptodev_capabilities.h | 16 +
> > .../crypto/octeontx2/otx2_cryptodev_hw_access.c | 225 ++++
> > .../crypto/octeontx2/otx2_cryptodev_hw_access.h | 169 +++
> > drivers/crypto/octeontx2/otx2_cryptodev_mbox.c | 175 ++++
> > drivers/crypto/octeontx2/otx2_cryptodev_mbox.h | 25 +
> > drivers/crypto/octeontx2/otx2_cryptodev_ops.c | 1100
> > ++++++++++++++++++++
> > drivers/crypto/octeontx2/otx2_cryptodev_ops.h | 21 +
> > .../octeontx2/rte_pmd_octeontx2_crypto_version.map | 4 +
> > mk/rte.app.mk | 6 +-
> > 35 files changed, 3479 insertions(+), 72 deletions(-) create mode
> > 100644 doc/guides/cryptodevs/features/octeontx2.ini
> > create mode 100644 doc/guides/cryptodevs/octeontx2.rst
> > create mode 100644 drivers/crypto/octeontx2/Makefile create mode
> > 100644 drivers/crypto/octeontx2/meson.build
> > create mode 100644 drivers/crypto/octeontx2/otx2_cryptodev.c
> > create mode 100644 drivers/crypto/octeontx2/otx2_cryptodev.h
> > create mode 100644
> > drivers/crypto/octeontx2/otx2_cryptodev_capabilities.c
> > create mode 100644
> > drivers/crypto/octeontx2/otx2_cryptodev_capabilities.h
> > create mode 100644
> > drivers/crypto/octeontx2/otx2_cryptodev_hw_access.c
> > create mode 100644
> > drivers/crypto/octeontx2/otx2_cryptodev_hw_access.h
> > create mode 100644 drivers/crypto/octeontx2/otx2_cryptodev_mbox.c
> > create mode 100644 drivers/crypto/octeontx2/otx2_cryptodev_mbox.h
> > create mode 100644 drivers/crypto/octeontx2/otx2_cryptodev_ops.c
> > create mode 100644 drivers/crypto/octeontx2/otx2_cryptodev_ops.h
> > create mode 100644
> > drivers/crypto/octeontx2/rte_pmd_octeontx2_crypto_version.map
> >
> > --
> > 2.7.4
^ permalink raw reply [flat|nested] 53+ messages in thread
* [dpdk-dev] [PATCH v3 00/11] add OCTEON TX2 crypto PMD
2019-10-13 12:39 ` [dpdk-dev] [PATCH v2 00/12] " Anoob Joseph
` (12 preceding siblings ...)
2019-10-16 13:32 ` [dpdk-dev] [PATCH v2 00/12] add OCTEON TX2 crypto PMD Akhil Goyal
@ 2019-10-16 15:25 ` Anoob Joseph
2019-10-16 15:25 ` [dpdk-dev] [PATCH v3 01/11] crypto/octeontx2: add PMD skeleton Anoob Joseph
` (11 more replies)
13 siblings, 12 replies; 53+ messages in thread
From: Anoob Joseph @ 2019-10-16 15:25 UTC (permalink / raw)
To: Akhil Goyal, Pablo de Lara
Cc: Anoob Joseph, Fiona Trahe, Jerin Jacob, Narayana Prasad,
Shally Verma, Ankur Dwivedi, Kanaka Durga Kotamarthy, Sunila Sahu,
Tejasree Kondoj, dev
The series introduces poll mode driver to enable crypto offload engine
on Marvell OCTEON TX2 SoC.
Changes in v3:
* Rebased on tip of dpdk-next-crypto("36112de91a44")
* Updated version map to use right DPDK version
* Added sanity checks in dev_close() routine.
Changes in v2:
* Merged series adding sym features and asym features into one.
* Squashed patches as directed by Akhil.
* Added check for ASYM SESSIONLESS (not supported currently)
* Minor updates to documentation
Ankur Dwivedi (3):
crypto/octeontx2: add device control ops
crypto/octeontx2: add queue pair functions
crypto/octeontx2: add session related functions
Anoob Joseph (5):
crypto/octeontx2: add PMD skeleton
crypto/octeontx2: add device init sequence in probe
crypto/octeontx2: add symmetric capabilities
crypto/octeontx2: add enqueue/dequeue ops
test: add OCTEON TX2 tests
Kanaka Durga Kotamarthy (1):
crypto/octeontx2: add asymmetric session operations
Sunila Sahu (2):
crypto/octeontx2: add asymmetric in enqueue/dequeue ops
app/test: register octeontx2 PMD to asym testsuite
MAINTAINERS | 7 +
app/test/meson.build | 1 +
app/test/test_cryptodev.c | 323 ++++++
app/test/test_cryptodev.h | 1 +
app/test/test_cryptodev_aes_test_vectors.h | 114 +-
app/test/test_cryptodev_asym.c | 20 +
app/test/test_cryptodev_blockcipher.c | 7 +
app/test/test_cryptodev_blockcipher.h | 1 +
app/test/test_cryptodev_des_test_vectors.h | 12 +-
app/test/test_cryptodev_hash_test_vectors.h | 75 +-
config/common_base | 5 +
doc/guides/cryptodevs/features/octeontx2.ini | 71 ++
doc/guides/cryptodevs/index.rst | 1 +
doc/guides/cryptodevs/octeontx2.rst | 159 +++
doc/guides/platform/octeontx2.rst | 3 +
doc/guides/rel_notes/release_19_11.rst | 6 +
drivers/common/Makefile | 5 +-
drivers/common/cpt/cpt_hw_types.h | 52 +
drivers/common/cpt/cpt_mcode_defines.h | 2 +
drivers/crypto/Makefile | 1 +
drivers/crypto/meson.build | 21 +-
drivers/crypto/octeontx2/Makefile | 50 +
drivers/crypto/octeontx2/meson.build | 34 +
drivers/crypto/octeontx2/otx2_cryptodev.c | 157 +++
drivers/crypto/octeontx2/otx2_cryptodev.h | 43 +
.../crypto/octeontx2/otx2_cryptodev_capabilities.c | 639 +++++++++++
.../crypto/octeontx2/otx2_cryptodev_capabilities.h | 16 +
.../crypto/octeontx2/otx2_cryptodev_hw_access.c | 225 ++++
.../crypto/octeontx2/otx2_cryptodev_hw_access.h | 169 +++
drivers/crypto/octeontx2/otx2_cryptodev_mbox.c | 175 ++++
drivers/crypto/octeontx2/otx2_cryptodev_mbox.h | 25 +
drivers/crypto/octeontx2/otx2_cryptodev_ops.c | 1106 ++++++++++++++++++++
drivers/crypto/octeontx2/otx2_cryptodev_ops.h | 21 +
.../octeontx2/rte_pmd_octeontx2_crypto_version.map | 4 +
mk/rte.app.mk | 6 +-
35 files changed, 3485 insertions(+), 72 deletions(-)
create mode 100644 doc/guides/cryptodevs/features/octeontx2.ini
create mode 100644 doc/guides/cryptodevs/octeontx2.rst
create mode 100644 drivers/crypto/octeontx2/Makefile
create mode 100644 drivers/crypto/octeontx2/meson.build
create mode 100644 drivers/crypto/octeontx2/otx2_cryptodev.c
create mode 100644 drivers/crypto/octeontx2/otx2_cryptodev.h
create mode 100644 drivers/crypto/octeontx2/otx2_cryptodev_capabilities.c
create mode 100644 drivers/crypto/octeontx2/otx2_cryptodev_capabilities.h
create mode 100644 drivers/crypto/octeontx2/otx2_cryptodev_hw_access.c
create mode 100644 drivers/crypto/octeontx2/otx2_cryptodev_hw_access.h
create mode 100644 drivers/crypto/octeontx2/otx2_cryptodev_mbox.c
create mode 100644 drivers/crypto/octeontx2/otx2_cryptodev_mbox.h
create mode 100644 drivers/crypto/octeontx2/otx2_cryptodev_ops.c
create mode 100644 drivers/crypto/octeontx2/otx2_cryptodev_ops.h
create mode 100644 drivers/crypto/octeontx2/rte_pmd_octeontx2_crypto_version.map
--
2.7.4
^ permalink raw reply [flat|nested] 53+ messages in thread* [dpdk-dev] [PATCH v3 01/11] crypto/octeontx2: add PMD skeleton
2019-10-16 15:25 ` [dpdk-dev] [PATCH v3 00/11] " Anoob Joseph
@ 2019-10-16 15:25 ` Anoob Joseph
2019-10-16 15:25 ` [dpdk-dev] [PATCH v3 02/11] crypto/octeontx2: add device init sequence in probe Anoob Joseph
` (10 subsequent siblings)
11 siblings, 0 replies; 53+ messages in thread
From: Anoob Joseph @ 2019-10-16 15:25 UTC (permalink / raw)
To: Akhil Goyal, Pablo de Lara
Cc: Anoob Joseph, Fiona Trahe, Jerin Jacob, Narayana Prasad,
Shally Verma, Ankur Dwivedi, Kanaka Durga Kotamarthy, Sunila Sahu,
Tejasree Kondoj, dev
Adding OCTEON TX2 crypto PMD skeleton. Enabling the driver by default
in common_base.
Signed-off-by: Ankur Dwivedi <adwivedi@marvell.com>
Signed-off-by: Anoob Joseph <anoobj@marvell.com>
Signed-off-by: Tejasree Kondoj <ktejasree@marvell.com>
---
MAINTAINERS | 7 ++
config/common_base | 5 +
doc/guides/cryptodevs/features/octeontx2.ini | 8 ++
doc/guides/cryptodevs/index.rst | 1 +
doc/guides/cryptodevs/octeontx2.rst | 93 +++++++++++++++++
doc/guides/platform/octeontx2.rst | 3 +
doc/guides/rel_notes/release_19_11.rst | 6 ++
drivers/common/Makefile | 5 +-
drivers/crypto/Makefile | 1 +
drivers/crypto/meson.build | 21 +++-
drivers/crypto/octeontx2/Makefile | 37 +++++++
drivers/crypto/octeontx2/meson.build | 29 ++++++
drivers/crypto/octeontx2/otx2_cryptodev.c | 111 +++++++++++++++++++++
drivers/crypto/octeontx2/otx2_cryptodev.h | 29 ++++++
drivers/crypto/octeontx2/otx2_cryptodev_ops.c | 27 +++++
drivers/crypto/octeontx2/otx2_cryptodev_ops.h | 12 +++
.../octeontx2/rte_pmd_octeontx2_crypto_version.map | 4 +
mk/rte.app.mk | 6 +-
18 files changed, 400 insertions(+), 5 deletions(-)
create mode 100644 doc/guides/cryptodevs/features/octeontx2.ini
create mode 100644 doc/guides/cryptodevs/octeontx2.rst
create mode 100644 drivers/crypto/octeontx2/Makefile
create mode 100644 drivers/crypto/octeontx2/meson.build
create mode 100644 drivers/crypto/octeontx2/otx2_cryptodev.c
create mode 100644 drivers/crypto/octeontx2/otx2_cryptodev.h
create mode 100644 drivers/crypto/octeontx2/otx2_cryptodev_ops.c
create mode 100644 drivers/crypto/octeontx2/otx2_cryptodev_ops.h
create mode 100644 drivers/crypto/octeontx2/rte_pmd_octeontx2_crypto_version.map
diff --git a/MAINTAINERS b/MAINTAINERS
index f8a56e2..b064e48 100644
--- a/MAINTAINERS
+++ b/MAINTAINERS
@@ -980,6 +980,13 @@ F: drivers/crypto/nitrox/
F: doc/guides/cryptodevs/nitrox.rst
F: doc/guides/cryptodevs/features/nitrox.ini
+Marvell OCTEON TX2 crypto
+M: Ankur Dwivedi <adwivedi@marvell.com>
+M: Anoob Joseph <anoobj@marvell.com>
+F: drivers/crypto/octeontx2/
+F: doc/guides/cryptodevs/octeontx2.rst
+F: doc/guides/cryptodevs/features/octeontx2.ini
+
Null Crypto
M: Declan Doherty <declan.doherty@intel.com>
F: drivers/crypto/null/
diff --git a/config/common_base b/config/common_base
index e843a21..895db64 100644
--- a/config/common_base
+++ b/config/common_base
@@ -592,6 +592,11 @@ CONFIG_RTE_LIBRTE_DPAA_MAX_CRYPTODEV=4
CONFIG_RTE_LIBRTE_PMD_OCTEONTX_CRYPTO=y
#
+# Compile PMD for Marvell OCTEON TX2 crypto device
+#
+CONFIG_RTE_LIBRTE_PMD_OCTEONTX2_CRYPTO=y
+
+#
# Compile PMD for QuickAssist based devices - see docs for details
#
CONFIG_RTE_LIBRTE_PMD_QAT=y
diff --git a/doc/guides/cryptodevs/features/octeontx2.ini b/doc/guides/cryptodevs/features/octeontx2.ini
new file mode 100644
index 0000000..35c9bee
--- /dev/null
+++ b/doc/guides/cryptodevs/features/octeontx2.ini
@@ -0,0 +1,8 @@
+;
+; Supported features of the 'octeontx2' crypto driver.
+;
+; Refer to default.ini for the full list of available PMD features.
+;
+[Features]
+Symmetric crypto = Y
+HW Accelerated = Y
diff --git a/doc/guides/cryptodevs/index.rst b/doc/guides/cryptodevs/index.rst
index d1e0d32..a67ed5a 100644
--- a/doc/guides/cryptodevs/index.rst
+++ b/doc/guides/cryptodevs/index.rst
@@ -19,6 +19,7 @@ Crypto Device Drivers
dpaa_sec
kasumi
octeontx
+ octeontx2
openssl
mvsam
nitrox
diff --git a/doc/guides/cryptodevs/octeontx2.rst b/doc/guides/cryptodevs/octeontx2.rst
new file mode 100644
index 0000000..10f578a
--- /dev/null
+++ b/doc/guides/cryptodevs/octeontx2.rst
@@ -0,0 +1,93 @@
+.. SPDX-License-Identifier: BSD-3-Clause
+ Copyright(c) 2019 Marvell International Ltd.
+
+
+Marvell OCTEON TX2 Crypto Poll Mode Driver
+==========================================
+
+The OCTEON TX2 crypto poll mode driver provides support for offloading
+cryptographic operations to cryptographic accelerator units on the
+**OCTEON TX2** :sup:`®` family of processors (CN9XXX).
+
+More information about OCTEON TX2 SoCs may be obtained from `<https://www.marvell.com>`_
+
+Features
+--------
+
+The OCTEON TX2 crypto PMD has support for:
+
+Installation
+------------
+
+The OCTEON TX2 crypto PMD may be compiled natively on an OCTEON TX2 platform or
+cross-compiled on an x86 platform.
+
+Enable OCTEON TX2 crypto PMD in your config file:
+
+* ``CONFIG_RTE_LIBRTE_PMD_OCTEONTX2_CRYPTO=y``
+
+Refer to :doc:`../platform/octeontx2` for instructions to build your DPDK
+application.
+
+.. note::
+
+ The OCTEON TX2 crypto PMD uses services from the kernel mode OCTEON TX2
+ crypto PF driver in linux. This driver is included in the OCTEON TX SDK.
+
+Initialization
+--------------
+
+List the CPT PF devices available on your OCTEON TX2 platform:
+
+.. code-block:: console
+
+ lspci -d:a0fd
+
+``a0fd`` is the CPT PF device id. You should see output similar to:
+
+.. code-block:: console
+
+ 0002:10:00.0 Class 1080: Device 177d:a0fd
+
+Set ``sriov_numvfs`` on the CPT PF device, to create a VF:
+
+.. code-block:: console
+
+ echo 1 > /sys/bus/pci/drivers/octeontx2-cpt/0002:10:00.0/sriov_numvfs
+
+Bind the CPT VF device to the vfio_pci driver:
+
+.. code-block:: console
+
+ echo '177d a0fe' > /sys/bus/pci/drivers/vfio-pci/new_id
+ echo 0002:10:00.1 > /sys/bus/pci/devices/0002:10:00.1/driver/unbind
+ echo 0002:10:00.1 > /sys/bus/pci/drivers/vfio-pci/bind
+
+Another way to bind the VF would be to use the ``dpdk-devbind.py`` script:
+
+.. code-block:: console
+
+ cd <dpdk directory>
+ ./usertools/dpdk-devbind.py -u 0002:10:00.1
+ ./usertools/dpdk-devbind.py -b vfio-pci 0002:10.00.1
+
+.. note::
+
+ Ensure that sufficient huge pages are available for your application::
+
+ echo 8 > /sys/kernel/mm/hugepages/hugepages-524288kB/nr_hugepages
+
+ Refer to :ref:`linux_gsg_hugepages` for more details.
+
+Debugging Options
+-----------------
+
+.. _table_octeontx2_crypto_debug_options:
+
+.. table:: OCTEON TX2 crypto PMD debug options
+
+ +---+------------+-------------------------------------------------------+
+ | # | Component | EAL log command |
+ +===+============+=======================================================+
+ | 1 | CPT | --log-level='pmd\.crypto\.octeontx2,8' |
+ +---+------------+-------------------------------------------------------+
diff --git a/doc/guides/platform/octeontx2.rst b/doc/guides/platform/octeontx2.rst
index 1ee5eac..1c7d98f 100644
--- a/doc/guides/platform/octeontx2.rst
+++ b/doc/guides/platform/octeontx2.rst
@@ -131,6 +131,9 @@ This section lists dataplane H/W block(s) available in OCTEON TX2 SoC.
#. **DMA Rawdev Driver**
See :doc:`../rawdevs/octeontx2_dma` for DMA driver information.
+#. **Crypto Device Driver**
+ See :doc:`../cryptodevs/octeontx2` for CPT crypto device driver information.
+
Procedure to Setup Platform
---------------------------
diff --git a/doc/guides/rel_notes/release_19_11.rst b/doc/guides/rel_notes/release_19_11.rst
index f1673e1..94c5a97 100644
--- a/doc/guides/rel_notes/release_19_11.rst
+++ b/doc/guides/rel_notes/release_19_11.rst
@@ -131,6 +131,12 @@ New Features
Added eBPF JIT support for arm64 architecture to improve the eBPF program
performance.
+* **Added Marvell OCTEON TX2 crypto PMD**
+
+ Added a new PMD driver for h/w crypto offload block on ``OCTEON TX2`` SoC.
+
+ See :doc:`../cryptodevs/octeontx2` for more details
+
Removed Items
-------------
diff --git a/drivers/common/Makefile b/drivers/common/Makefile
index bc6f972..1ff033b 100644
--- a/drivers/common/Makefile
+++ b/drivers/common/Makefile
@@ -4,7 +4,9 @@
include $(RTE_SDK)/mk/rte.vars.mk
-ifeq ($(CONFIG_RTE_LIBRTE_PMD_OCTEONTX_CRYPTO),y)
+CPT-y := $(CONFIG_RTE_LIBRTE_PMD_OCTEONTX_CRYPTO)
+CPT-y += $(CONFIG_RTE_LIBRTE_PMD_OCTEONTX2_CRYPTO)
+ifneq (,$(findstring y,$(CPT-y)))
DIRS-y += cpt
endif
@@ -12,6 +14,7 @@ ifeq ($(CONFIG_RTE_LIBRTE_PMD_OCTEONTX_SSOVF)$(CONFIG_RTE_LIBRTE_OCTEONTX_MEMPOO
DIRS-y += octeontx
endif
OCTEONTX2-y := $(CONFIG_RTE_LIBRTE_OCTEONTX2_MEMPOOL)
+OCTEONTX2-y += $(CONFIG_RTE_LIBRTE_PMD_OCTEONTX2_CRYPTO)
ifeq ($(findstring y,$(OCTEONTX2-y)),y)
DIRS-y += octeontx2
endif
diff --git a/drivers/crypto/Makefile b/drivers/crypto/Makefile
index 7129bcf..8b00857 100644
--- a/drivers/crypto/Makefile
+++ b/drivers/crypto/Makefile
@@ -8,6 +8,7 @@ DIRS-$(CONFIG_RTE_LIBRTE_PMD_AESNI_MB) += aesni_mb
DIRS-$(CONFIG_RTE_LIBRTE_PMD_ARMV8_CRYPTO) += armv8
DIRS-$(CONFIG_RTE_LIBRTE_PMD_CCP) += ccp
DIRS-$(CONFIG_RTE_LIBRTE_PMD_OCTEONTX_CRYPTO) += octeontx
+DIRS-$(CONFIG_RTE_LIBRTE_PMD_OCTEONTX2_CRYPTO) += octeontx2
DIRS-$(CONFIG_RTE_LIBRTE_PMD_OPENSSL) += openssl
DIRS-$(CONFIG_RTE_LIBRTE_PMD_CRYPTO_SCHEDULER) += scheduler
DIRS-$(CONFIG_RTE_LIBRTE_PMD_SNOW3G) += snow3g
diff --git a/drivers/crypto/meson.build b/drivers/crypto/meson.build
index 1a358ff..229debd 100644
--- a/drivers/crypto/meson.build
+++ b/drivers/crypto/meson.build
@@ -1,9 +1,24 @@
# SPDX-License-Identifier: BSD-3-Clause
# Copyright(c) 2017 Intel Corporation
-drivers = ['aesni_gcm', 'aesni_mb', 'caam_jr', 'ccp', 'dpaa_sec', 'dpaa2_sec',
- 'kasumi', 'mvsam', 'nitrox', 'null', 'octeontx', 'openssl', 'qat',
- 'scheduler', 'snow3g', 'virtio', 'zuc']
+drivers = ['aesni_gcm',
+ 'aesni_mb',
+ 'caam_jr',
+ 'ccp',
+ 'dpaa_sec',
+ 'dpaa2_sec',
+ 'kasumi',
+ 'mvsam',
+ 'nitrox',
+ 'null',
+ 'octeontx',
+ 'octeontx2',
+ 'openssl',
+ 'qat',
+ 'scheduler',
+ 'snow3g',
+ 'virtio',
+ 'zuc']
std_deps = ['cryptodev'] # cryptodev pulls in all other needed deps
config_flag_fmt = 'RTE_LIBRTE_@0@_PMD'
diff --git a/drivers/crypto/octeontx2/Makefile b/drivers/crypto/octeontx2/Makefile
new file mode 100644
index 0000000..3273178
--- /dev/null
+++ b/drivers/crypto/octeontx2/Makefile
@@ -0,0 +1,37 @@
+# SPDX-License-Identifier: BSD-3-Clause
+# Copyright (C) 2019 Marvell International Ltd.
+#
+
+include $(RTE_SDK)/mk/rte.vars.mk
+
+# library name
+LIB = librte_pmd_octeontx2_crypto.a
+
+# library version
+LIBABIVER := 1
+
+# build flags
+CFLAGS += $(WERROR_FLAGS)
+
+LDLIBS += -lrte_eal -lrte_mbuf -lrte_mempool -lrte_ring
+LDLIBS += -lrte_cryptodev
+LDLIBS += -lrte_pci -lrte_bus_pci
+LDLIBS += -lrte_common_cpt -lrte_common_octeontx2
+
+VPATH += $(RTE_SDK)/drivers/crypto/octeontx2
+
+CFLAGS += -O3
+CFLAGS += -I$(RTE_SDK)/drivers/common/cpt
+CFLAGS += -I$(RTE_SDK)/drivers/common/octeontx2
+
+# PMD code
+SRCS-$(CONFIG_RTE_LIBRTE_PMD_OCTEONTX2_CRYPTO) += otx2_cryptodev.c
+SRCS-$(CONFIG_RTE_LIBRTE_PMD_OCTEONTX2_CRYPTO) += otx2_cryptodev_ops.c
+
+# export include files
+SYMLINK-y-include +=
+
+# versioning export map
+EXPORT_MAP := rte_pmd_octeontx2_crypto_version.map
+
+include $(RTE_SDK)/mk/rte.lib.mk
diff --git a/drivers/crypto/octeontx2/meson.build b/drivers/crypto/octeontx2/meson.build
new file mode 100644
index 0000000..2b55d2a
--- /dev/null
+++ b/drivers/crypto/octeontx2/meson.build
@@ -0,0 +1,29 @@
+# SPDX-License-Identifier: BSD-3-Clause
+# Copyright (C) 2019 Marvell International Ltd.
+
+if host_machine.system() != 'linux'
+ build = false
+endif
+
+deps += ['bus_pci']
+deps += ['common_cpt']
+deps += ['common_octeontx2']
+name = 'octeontx2_crypto'
+
+sources = files('otx2_cryptodev.c',
+ 'otx2_cryptodev_ops.c')
+
+extra_flags = []
+# This integrated controller runs only on a arm64 machine, remove 32bit warnings
+if not dpdk_conf.get('RTE_ARCH_64')
+ extra_flags += ['-Wno-int-to-pointer-cast', '-Wno-pointer-to-int-cast']
+endif
+
+foreach flag: extra_flags
+ if cc.has_argument(flag)
+ cflags += flag
+ endif
+endforeach
+
+includes += include_directories('../../common/cpt')
+includes += include_directories('../../common/octeontx2')
diff --git a/drivers/crypto/octeontx2/otx2_cryptodev.c b/drivers/crypto/octeontx2/otx2_cryptodev.c
new file mode 100644
index 0000000..ca9f227
--- /dev/null
+++ b/drivers/crypto/octeontx2/otx2_cryptodev.c
@@ -0,0 +1,111 @@
+/* SPDX-License-Identifier: BSD-3-Clause
+ * Copyright (C) 2019 Marvell International Ltd.
+ */
+
+#include <rte_bus_pci.h>
+#include <rte_common.h>
+#include <rte_crypto.h>
+#include <rte_cryptodev.h>
+#include <rte_cryptodev_pmd.h>
+#include <rte_dev.h>
+#include <rte_errno.h>
+#include <rte_mempool.h>
+#include <rte_pci.h>
+
+#include "otx2_common.h"
+#include "otx2_cryptodev.h"
+#include "otx2_cryptodev_ops.h"
+
+/* CPT common headers */
+#include "cpt_common.h"
+#include "cpt_pmd_logs.h"
+
+int otx2_cpt_logtype;
+
+static struct rte_pci_id pci_id_cpt_table[] = {
+ {
+ RTE_PCI_DEVICE(PCI_VENDOR_ID_CAVIUM,
+ PCI_DEVID_OCTEONTX2_RVU_CPT_VF)
+ },
+ /* sentinel */
+ {
+ .device_id = 0
+ },
+};
+
+static int
+otx2_cpt_pci_probe(struct rte_pci_driver *pci_drv __rte_unused,
+ struct rte_pci_device *pci_dev)
+{
+ struct rte_cryptodev_pmd_init_params init_params = {
+ .name = "",
+ .socket_id = rte_socket_id(),
+ .private_data_size = sizeof(struct otx2_cpt_vf)
+ };
+ char name[RTE_CRYPTODEV_NAME_MAX_LEN];
+ struct rte_cryptodev *dev;
+ int ret;
+
+ rte_pci_device_name(&pci_dev->addr, name, sizeof(name));
+
+ dev = rte_cryptodev_pmd_create(name, &pci_dev->device, &init_params);
+ if (dev == NULL) {
+ ret = -ENODEV;
+ goto exit;
+ }
+
+ dev->dev_ops = &otx2_cpt_ops;
+
+ dev->driver_id = otx2_cryptodev_driver_id;
+
+ dev->feature_flags = RTE_CRYPTODEV_FF_SYMMETRIC_CRYPTO |
+ RTE_CRYPTODEV_FF_HW_ACCELERATED;
+
+ return 0;
+
+exit:
+ CPT_LOG_ERR("Could not create device (vendor_id: 0x%x device_id: 0x%x)",
+ pci_dev->id.vendor_id, pci_dev->id.device_id);
+ return ret;
+}
+
+static int
+otx2_cpt_pci_remove(struct rte_pci_device *pci_dev)
+{
+ char name[RTE_CRYPTODEV_NAME_MAX_LEN];
+ struct rte_cryptodev *dev;
+
+ if (pci_dev == NULL)
+ return -EINVAL;
+
+ rte_pci_device_name(&pci_dev->addr, name, sizeof(name));
+
+ dev = rte_cryptodev_pmd_get_named_dev(name);
+ if (dev == NULL)
+ return -ENODEV;
+
+ return rte_cryptodev_pmd_destroy(dev);
+}
+
+static struct rte_pci_driver otx2_cryptodev_pmd = {
+ .id_table = pci_id_cpt_table,
+ .drv_flags = RTE_PCI_DRV_NEED_MAPPING,
+ .probe = otx2_cpt_pci_probe,
+ .remove = otx2_cpt_pci_remove,
+};
+
+static struct cryptodev_driver otx2_cryptodev_drv;
+
+RTE_INIT(otx2_cpt_init_log);
+RTE_PMD_REGISTER_PCI(CRYPTODEV_NAME_OCTEONTX2_PMD, otx2_cryptodev_pmd);
+RTE_PMD_REGISTER_PCI_TABLE(CRYPTODEV_NAME_OCTEONTX2_PMD, pci_id_cpt_table);
+RTE_PMD_REGISTER_CRYPTO_DRIVER(otx2_cryptodev_drv, otx2_cryptodev_pmd.driver,
+ otx2_cryptodev_driver_id);
+
+RTE_INIT(otx2_cpt_init_log)
+{
+ /* Bus level logs */
+ otx2_cpt_logtype = rte_log_register("pmd.crypto.octeontx2");
+ if (otx2_cpt_logtype >= 0)
+ rte_log_set_level(otx2_cpt_logtype, RTE_LOG_NOTICE);
+}
diff --git a/drivers/crypto/octeontx2/otx2_cryptodev.h b/drivers/crypto/octeontx2/otx2_cryptodev.h
new file mode 100644
index 0000000..c9fe0c8
--- /dev/null
+++ b/drivers/crypto/octeontx2/otx2_cryptodev.h
@@ -0,0 +1,29 @@
+/* SPDX-License-Identifier: BSD-3-Clause
+ * Copyright (C) 2019 Marvell International Ltd.
+ */
+
+#ifndef _OTX2_CRYPTODEV_H_
+#define _OTX2_CRYPTODEV_H_
+
+#include "cpt_common.h"
+
+/* Marvell OCTEON TX2 Crypto PMD device name */
+#define CRYPTODEV_NAME_OCTEONTX2_PMD crypto_octeontx2
+
+/**
+ * Device private data
+ */
+struct otx2_cpt_vf {
+ /* To be populated */
+};
+
+#define CPT_LOGTYPE otx2_cpt_logtype
+
+extern int otx2_cpt_logtype;
+
+/*
+ * Crypto device driver ID
+ */
+uint8_t otx2_cryptodev_driver_id;
+
+#endif /* _OTX2_CRYPTODEV_H_ */
diff --git a/drivers/crypto/octeontx2/otx2_cryptodev_ops.c b/drivers/crypto/octeontx2/otx2_cryptodev_ops.c
new file mode 100644
index 0000000..18ad470
--- /dev/null
+++ b/drivers/crypto/octeontx2/otx2_cryptodev_ops.c
@@ -0,0 +1,27 @@
+/* SPDX-License-Identifier: BSD-3-Clause
+ * Copyright (C) 2019 Marvell International Ltd.
+ */
+
+#include <rte_cryptodev_pmd.h>
+
+#include "otx2_cryptodev_ops.h"
+
+struct rte_cryptodev_ops otx2_cpt_ops = {
+ /* Device control ops */
+ .dev_configure = NULL,
+ .dev_start = NULL,
+ .dev_stop = NULL,
+ .dev_close = NULL,
+ .dev_infos_get = NULL,
+
+ .stats_get = NULL,
+ .stats_reset = NULL,
+ .queue_pair_setup = NULL,
+ .queue_pair_release = NULL,
+ .queue_pair_count = NULL,
+
+ /* Symmetric crypto ops */
+ .sym_session_get_size = NULL,
+ .sym_session_configure = NULL,
+ .sym_session_clear = NULL,
+};
diff --git a/drivers/crypto/octeontx2/otx2_cryptodev_ops.h b/drivers/crypto/octeontx2/otx2_cryptodev_ops.h
new file mode 100644
index 0000000..545614e
--- /dev/null
+++ b/drivers/crypto/octeontx2/otx2_cryptodev_ops.h
@@ -0,0 +1,12 @@
+/* SPDX-License-Identifier: BSD-3-Clause
+ * Copyright (C) 2019 Marvell International Ltd.
+ */
+
+#ifndef _OTX2_CRYPTODEV_OPS_H_
+#define _OTX2_CRYPTODEV_OPS_H_
+
+#include <rte_cryptodev_pmd.h>
+
+struct rte_cryptodev_ops otx2_cpt_ops;
+
+#endif /* _OTX2_CRYPTODEV_OPS_H_ */
diff --git a/drivers/crypto/octeontx2/rte_pmd_octeontx2_crypto_version.map b/drivers/crypto/octeontx2/rte_pmd_octeontx2_crypto_version.map
new file mode 100644
index 0000000..b7b7c91
--- /dev/null
+++ b/drivers/crypto/octeontx2/rte_pmd_octeontx2_crypto_version.map
@@ -0,0 +1,4 @@
+DPDK_19.11 {
+
+ local: *;
+};
diff --git a/mk/rte.app.mk b/mk/rte.app.mk
index b91273f..e79f16e 100644
--- a/mk/rte.app.mk
+++ b/mk/rte.app.mk
@@ -101,7 +101,9 @@ ifeq ($(CONFIG_RTE_EXEC_ENV_LINUX),y)
_LDLIBS-$(CONFIG_RTE_LIBRTE_KNI) += -lrte_kni
endif
-ifeq ($(CONFIG_RTE_LIBRTE_PMD_OCTEONTX_CRYPTO),y)
+OTX-CPT-y := $(CONFIG_RTE_LIBRTE_PMD_OCTEONTX_CRYPTO)
+OTX-CPT-y += $(CONFIG_RTE_LIBRTE_PMD_OCTEONTX2_CRYPTO)
+ifeq ($(findstring y,$(OTX-CPT-y)),y)
_LDLIBS-y += -lrte_common_cpt
endif
@@ -109,6 +111,7 @@ ifeq ($(CONFIG_RTE_LIBRTE_PMD_OCTEONTX_SSOVF)$(CONFIG_RTE_LIBRTE_OCTEONTX_MEMPOO
_LDLIBS-y += -lrte_common_octeontx
endif
OCTEONTX2-y := $(CONFIG_RTE_LIBRTE_OCTEONTX2_MEMPOOL)
+OCTEONTX2-y += $(CONFIG_RTE_LIBRTE_PMD_OCTEONTX2_CRYPTO)
OCTEONTX2-y += $(CONFIG_RTE_LIBRTE_PMD_OCTEONTX2_EVENTDEV)
OCTEONTX2-y += $(CONFIG_RTE_LIBRTE_PMD_OCTEONTX2_DMA_RAWDEV)
OCTEONTX2-y += $(CONFIG_RTE_LIBRTE_OCTEONTX2_PMD)
@@ -270,6 +273,7 @@ _LDLIBS-$(CONFIG_RTE_LIBRTE_PMD_ARMV8_CRYPTO) += -L$(ARMV8_CRYPTO_LIB_PATH) -
_LDLIBS-$(CONFIG_RTE_LIBRTE_PMD_MVSAM_CRYPTO) += -L$(LIBMUSDK_PATH)/lib -lrte_pmd_mvsam_crypto -lmusdk
_LDLIBS-$(CONFIG_RTE_LIBRTE_PMD_NITROX) += -lrte_pmd_nitrox
_LDLIBS-$(CONFIG_RTE_LIBRTE_PMD_OCTEONTX_CRYPTO) += -lrte_pmd_octeontx_crypto
+_LDLIBS-$(CONFIG_RTE_LIBRTE_PMD_OCTEONTX2_CRYPTO) += -lrte_pmd_octeontx2_crypto
_LDLIBS-$(CONFIG_RTE_LIBRTE_PMD_CRYPTO_SCHEDULER) += -lrte_pmd_crypto_scheduler
ifeq ($(CONFIG_RTE_LIBRTE_SECURITY),y)
ifeq ($(CONFIG_RTE_EAL_VFIO)$(CONFIG_RTE_LIBRTE_FSLMC_BUS),yy)
--
2.7.4
^ permalink raw reply related [flat|nested] 53+ messages in thread* [dpdk-dev] [PATCH v3 02/11] crypto/octeontx2: add device init sequence in probe
2019-10-16 15:25 ` [dpdk-dev] [PATCH v3 00/11] " Anoob Joseph
2019-10-16 15:25 ` [dpdk-dev] [PATCH v3 01/11] crypto/octeontx2: add PMD skeleton Anoob Joseph
@ 2019-10-16 15:25 ` Anoob Joseph
2019-10-16 15:25 ` [dpdk-dev] [PATCH v3 03/11] crypto/octeontx2: add device control ops Anoob Joseph
` (9 subsequent siblings)
11 siblings, 0 replies; 53+ messages in thread
From: Anoob Joseph @ 2019-10-16 15:25 UTC (permalink / raw)
To: Akhil Goyal, Pablo de Lara
Cc: Anoob Joseph, Fiona Trahe, Jerin Jacob, Narayana Prasad,
Shally Verma, Ankur Dwivedi, Kanaka Durga Kotamarthy, Sunila Sahu,
Tejasree Kondoj, dev
This patch adds the device init sequence for OCTEON TX2 crypto
device.
Signed-off-by: Ankur Dwivedi <adwivedi@marvell.com>
Signed-off-by: Anoob Joseph <anoobj@marvell.com>
Signed-off-by: Tejasree Kondoj <ktejasree@marvell.com>
---
drivers/crypto/octeontx2/Makefile | 10 +++++++
drivers/crypto/octeontx2/meson.build | 2 ++
drivers/crypto/octeontx2/otx2_cryptodev.c | 40 ++++++++++++++++++++++++++
drivers/crypto/octeontx2/otx2_cryptodev.h | 10 ++++++-
drivers/crypto/octeontx2/otx2_cryptodev_mbox.c | 28 ++++++++++++++++++
drivers/crypto/octeontx2/otx2_cryptodev_mbox.h | 13 +++++++++
6 files changed, 102 insertions(+), 1 deletion(-)
create mode 100644 drivers/crypto/octeontx2/otx2_cryptodev_mbox.c
create mode 100644 drivers/crypto/octeontx2/otx2_cryptodev_mbox.h
diff --git a/drivers/crypto/octeontx2/Makefile b/drivers/crypto/octeontx2/Makefile
index 3273178..10d8c39 100644
--- a/drivers/crypto/octeontx2/Makefile
+++ b/drivers/crypto/octeontx2/Makefile
@@ -23,9 +23,19 @@ VPATH += $(RTE_SDK)/drivers/crypto/octeontx2
CFLAGS += -O3
CFLAGS += -I$(RTE_SDK)/drivers/common/cpt
CFLAGS += -I$(RTE_SDK)/drivers/common/octeontx2
+CFLAGS += -I$(RTE_SDK)/drivers/mempool/octeontx2
+
+ifneq ($(CONFIG_RTE_ARCH_64),y)
+CFLAGS += -Wno-int-to-pointer-cast
+CFLAGS += -Wno-pointer-to-int-cast
+ifeq ($(CONFIG_RTE_TOOLCHAIN_ICC),y)
+CFLAGS += -diag-disable 2259
+endif
+endif
# PMD code
SRCS-$(CONFIG_RTE_LIBRTE_PMD_OCTEONTX2_CRYPTO) += otx2_cryptodev.c
+SRCS-$(CONFIG_RTE_LIBRTE_PMD_OCTEONTX2_CRYPTO) += otx2_cryptodev_mbox.c
SRCS-$(CONFIG_RTE_LIBRTE_PMD_OCTEONTX2_CRYPTO) += otx2_cryptodev_ops.c
# export include files
diff --git a/drivers/crypto/octeontx2/meson.build b/drivers/crypto/octeontx2/meson.build
index 2b55d2a..845d50d 100644
--- a/drivers/crypto/octeontx2/meson.build
+++ b/drivers/crypto/octeontx2/meson.build
@@ -11,6 +11,7 @@ deps += ['common_octeontx2']
name = 'octeontx2_crypto'
sources = files('otx2_cryptodev.c',
+ 'otx2_cryptodev_mbox.c',
'otx2_cryptodev_ops.c')
extra_flags = []
@@ -27,3 +28,4 @@ endforeach
includes += include_directories('../../common/cpt')
includes += include_directories('../../common/octeontx2')
+includes += include_directories('../../mempool/octeontx2')
diff --git a/drivers/crypto/octeontx2/otx2_cryptodev.c b/drivers/crypto/octeontx2/otx2_cryptodev.c
index ca9f227..efc17cb 100644
--- a/drivers/crypto/octeontx2/otx2_cryptodev.c
+++ b/drivers/crypto/octeontx2/otx2_cryptodev.c
@@ -14,7 +14,9 @@
#include "otx2_common.h"
#include "otx2_cryptodev.h"
+#include "otx2_cryptodev_mbox.h"
#include "otx2_cryptodev_ops.h"
+#include "otx2_dev.h"
/* CPT common headers */
#include "cpt_common.h"
@@ -44,6 +46,9 @@ otx2_cpt_pci_probe(struct rte_pci_driver *pci_drv __rte_unused,
};
char name[RTE_CRYPTODEV_NAME_MAX_LEN];
struct rte_cryptodev *dev;
+ struct otx2_dev *otx2_dev;
+ struct otx2_cpt_vf *vf;
+ uint16_t nb_queues;
int ret;
rte_pci_device_name(&pci_dev->addr, name, sizeof(name));
@@ -58,11 +63,46 @@ otx2_cpt_pci_probe(struct rte_pci_driver *pci_drv __rte_unused,
dev->driver_id = otx2_cryptodev_driver_id;
+ /* Get private data space allocated */
+ vf = dev->data->dev_private;
+
+ otx2_dev = &vf->otx2_dev;
+
+ /* Initialize the base otx2_dev object */
+ ret = otx2_dev_init(pci_dev, otx2_dev);
+ if (ret) {
+ CPT_LOG_ERR("Could not initialize otx2_dev");
+ goto pmd_destroy;
+ }
+
+ /* Get number of queues available on the device */
+ ret = otx2_cpt_available_queues_get(dev, &nb_queues);
+ if (ret) {
+ CPT_LOG_ERR("Could not determine the number of queues available");
+ goto otx2_dev_fini;
+ }
+
+ /* Don't exceed the limits set per VF */
+ nb_queues = RTE_MIN(nb_queues, OTX2_CPT_MAX_QUEUES_PER_VF);
+
+ if (nb_queues == 0) {
+ CPT_LOG_ERR("No free queues available on the device");
+ goto otx2_dev_fini;
+ }
+
+ vf->max_queues = nb_queues;
+
+ CPT_LOG_INFO("Max queues supported by device: %d", vf->max_queues);
+
dev->feature_flags = RTE_CRYPTODEV_FF_SYMMETRIC_CRYPTO |
RTE_CRYPTODEV_FF_HW_ACCELERATED;
return 0;
+otx2_dev_fini:
+ otx2_dev_fini(pci_dev, otx2_dev);
+pmd_destroy:
+ rte_cryptodev_pmd_destroy(dev);
exit:
CPT_LOG_ERR("Could not create device (vendor_id: 0x%x device_id: 0x%x)",
pci_dev->id.vendor_id, pci_dev->id.device_id);
diff --git a/drivers/crypto/octeontx2/otx2_cryptodev.h b/drivers/crypto/octeontx2/otx2_cryptodev.h
index c9fe0c8..d26c1f3 100644
--- a/drivers/crypto/octeontx2/otx2_cryptodev.h
+++ b/drivers/crypto/octeontx2/otx2_cryptodev.h
@@ -7,14 +7,22 @@
#include "cpt_common.h"
+#include "otx2_dev.h"
+
/* Marvell OCTEON TX2 Crypto PMD device name */
#define CRYPTODEV_NAME_OCTEONTX2_PMD crypto_octeontx2
+#define OTX2_CPT_MAX_LFS 64
+#define OTX2_CPT_MAX_QUEUES_PER_VF 64
+
/**
* Device private data
*/
struct otx2_cpt_vf {
- /* To be populated */
+ struct otx2_dev otx2_dev;
+ /**< Base class */
+ uint16_t max_queues;
+ /**< Max queues supported */
};
#define CPT_LOGTYPE otx2_cpt_logtype
diff --git a/drivers/crypto/octeontx2/otx2_cryptodev_mbox.c b/drivers/crypto/octeontx2/otx2_cryptodev_mbox.c
new file mode 100644
index 0000000..20fc1ac
--- /dev/null
+++ b/drivers/crypto/octeontx2/otx2_cryptodev_mbox.c
@@ -0,0 +1,28 @@
+/* SPDX-License-Identifier: BSD-3-Clause
+ * Copyright (C) 2019 Marvell International Ltd.
+ */
+#include <rte_cryptodev.h>
+
+#include "otx2_cryptodev.h"
+#include "otx2_cryptodev_mbox.h"
+#include "otx2_dev.h"
+#include "otx2_mbox.h"
+
+int
+otx2_cpt_available_queues_get(const struct rte_cryptodev *dev,
+ uint16_t *nb_queues)
+{
+ struct otx2_cpt_vf *vf = dev->data->dev_private;
+ struct otx2_dev *otx2_dev = &vf->otx2_dev;
+ struct free_rsrcs_rsp *rsp;
+ int ret;
+
+ otx2_mbox_alloc_msg_free_rsrc_cnt(otx2_dev->mbox);
+
+ ret = otx2_mbox_process_msg(otx2_dev->mbox, (void *)&rsp);
+ if (ret)
+ return -EIO;
+
+ *nb_queues = rsp->cpt;
+ return 0;
+}
diff --git a/drivers/crypto/octeontx2/otx2_cryptodev_mbox.h b/drivers/crypto/octeontx2/otx2_cryptodev_mbox.h
new file mode 100644
index 0000000..648c009
--- /dev/null
+++ b/drivers/crypto/octeontx2/otx2_cryptodev_mbox.h
@@ -0,0 +1,13 @@
+/* SPDX-License-Identifier: BSD-3-Clause
+ * Copyright (C) 2019 Marvell International Ltd.
+ */
+
+#ifndef _OTX2_CRYPTODEV_MBOX_H_
+#define _OTX2_CRYPTODEV_MBOX_H_
+
+#include <rte_cryptodev.h>
+
+int otx2_cpt_available_queues_get(const struct rte_cryptodev *dev,
+ uint16_t *nb_queues);
+
+#endif /* _OTX2_CRYPTODEV_MBOX_H_ */
--
2.7.4
^ permalink raw reply related [flat|nested] 53+ messages in thread* [dpdk-dev] [PATCH v3 03/11] crypto/octeontx2: add device control ops
2019-10-16 15:25 ` [dpdk-dev] [PATCH v3 00/11] " Anoob Joseph
2019-10-16 15:25 ` [dpdk-dev] [PATCH v3 01/11] crypto/octeontx2: add PMD skeleton Anoob Joseph
2019-10-16 15:25 ` [dpdk-dev] [PATCH v3 02/11] crypto/octeontx2: add device init sequence in probe Anoob Joseph
@ 2019-10-16 15:25 ` Anoob Joseph
2019-10-16 15:25 ` [dpdk-dev] [PATCH v3 04/11] crypto/octeontx2: add queue pair functions Anoob Joseph
` (8 subsequent siblings)
11 siblings, 0 replies; 53+ messages in thread
From: Anoob Joseph @ 2019-10-16 15:25 UTC (permalink / raw)
To: Akhil Goyal, Pablo de Lara
Cc: Ankur Dwivedi, Fiona Trahe, Jerin Jacob, Narayana Prasad,
Shally Verma, Kanaka Durga Kotamarthy, Sunila Sahu,
Tejasree Kondoj, dev, Anoob Joseph
From: Ankur Dwivedi <adwivedi@marvell.com>
This patch adds the device control functions.
Signed-off-by: Ankur Dwivedi <adwivedi@marvell.com>
Signed-off-by: Anoob Joseph <anoobj@marvell.com>
Signed-off-by: Tejasree Kondoj <ktejasree@marvell.com>
---
drivers/crypto/octeontx2/Makefile | 1 +
drivers/crypto/octeontx2/meson.build | 1 +
drivers/crypto/octeontx2/otx2_cryptodev.h | 6 +
.../crypto/octeontx2/otx2_cryptodev_hw_access.c | 126 ++++++++++++++++++++
.../crypto/octeontx2/otx2_cryptodev_hw_access.h | 27 +++++
drivers/crypto/octeontx2/otx2_cryptodev_mbox.c | 64 ++++++++++
drivers/crypto/octeontx2/otx2_cryptodev_mbox.h | 6 +
drivers/crypto/octeontx2/otx2_cryptodev_ops.c | 129 ++++++++++++++++++++-
drivers/crypto/octeontx2/otx2_cryptodev_ops.h | 3 +
9 files changed, 358 insertions(+), 5 deletions(-)
create mode 100644 drivers/crypto/octeontx2/otx2_cryptodev_hw_access.c
create mode 100644 drivers/crypto/octeontx2/otx2_cryptodev_hw_access.h
diff --git a/drivers/crypto/octeontx2/Makefile b/drivers/crypto/octeontx2/Makefile
index 10d8c39..71bc4d1 100644
--- a/drivers/crypto/octeontx2/Makefile
+++ b/drivers/crypto/octeontx2/Makefile
@@ -35,6 +35,7 @@ endif
# PMD code
SRCS-$(CONFIG_RTE_LIBRTE_PMD_OCTEONTX2_CRYPTO) += otx2_cryptodev.c
+SRCS-$(CONFIG_RTE_LIBRTE_PMD_OCTEONTX2_CRYPTO) += otx2_cryptodev_hw_access.c
SRCS-$(CONFIG_RTE_LIBRTE_PMD_OCTEONTX2_CRYPTO) += otx2_cryptodev_mbox.c
SRCS-$(CONFIG_RTE_LIBRTE_PMD_OCTEONTX2_CRYPTO) += otx2_cryptodev_ops.c
diff --git a/drivers/crypto/octeontx2/meson.build b/drivers/crypto/octeontx2/meson.build
index 845d50d..944fa2c 100644
--- a/drivers/crypto/octeontx2/meson.build
+++ b/drivers/crypto/octeontx2/meson.build
@@ -11,6 +11,7 @@ deps += ['common_octeontx2']
name = 'octeontx2_crypto'
sources = files('otx2_cryptodev.c',
+ 'otx2_cryptodev_hw_access.c',
'otx2_cryptodev_mbox.c',
'otx2_cryptodev_ops.c')
diff --git a/drivers/crypto/octeontx2/otx2_cryptodev.h b/drivers/crypto/octeontx2/otx2_cryptodev.h
index d26c1f3..8e0ebc2 100644
--- a/drivers/crypto/octeontx2/otx2_cryptodev.h
+++ b/drivers/crypto/octeontx2/otx2_cryptodev.h
@@ -23,6 +23,12 @@ struct otx2_cpt_vf {
/**< Base class */
uint16_t max_queues;
/**< Max queues supported */
+ uint8_t nb_queues;
+ /**< Number of crypto queues attached */
+ uint16_t lf_msixoff[OTX2_CPT_MAX_LFS];
+ /**< MSI-X offsets */
+ uint8_t err_intr_registered:1;
+ /**< Are error interrupts registered? */
};
#define CPT_LOGTYPE otx2_cpt_logtype
diff --git a/drivers/crypto/octeontx2/otx2_cryptodev_hw_access.c b/drivers/crypto/octeontx2/otx2_cryptodev_hw_access.c
new file mode 100644
index 0000000..663f9ca
--- /dev/null
+++ b/drivers/crypto/octeontx2/otx2_cryptodev_hw_access.c
@@ -0,0 +1,126 @@
+/* SPDX-License-Identifier: BSD-3-Clause
+ * Copyright (C) 2019 Marvell International Ltd.
+ */
+
+#include "otx2_common.h"
+#include "otx2_cryptodev.h"
+#include "otx2_cryptodev_hw_access.h"
+
+#include "cpt_pmd_logs.h"
+
+static void
+otx2_cpt_lf_err_intr_handler(void *param)
+{
+ uintptr_t base = (uintptr_t)param;
+ uint8_t lf_id;
+ uint64_t intr;
+
+ lf_id = (base >> 12) & 0xFF;
+
+ intr = otx2_read64(base + OTX2_CPT_LF_MISC_INT);
+ if (intr == 0)
+ return;
+
+ CPT_LOG_ERR("LF %d MISC_INT: 0x%" PRIx64 "", lf_id, intr);
+
+ /* Clear interrupt */
+ otx2_write64(intr, base + OTX2_CPT_LF_MISC_INT);
+}
+
+static void
+otx2_cpt_lf_err_intr_unregister(const struct rte_cryptodev *dev,
+ uint16_t msix_off, uintptr_t base)
+{
+ struct rte_pci_device *pci_dev = RTE_DEV_TO_PCI(dev->device);
+ struct rte_intr_handle *handle = &pci_dev->intr_handle;
+
+ /* Disable error interrupts */
+ otx2_write64(~0ull, base + OTX2_CPT_LF_MISC_INT_ENA_W1C);
+
+ otx2_unregister_irq(handle, otx2_cpt_lf_err_intr_handler, (void *)base,
+ msix_off);
+}
+
+void
+otx2_cpt_err_intr_unregister(const struct rte_cryptodev *dev)
+{
+ struct otx2_cpt_vf *vf = dev->data->dev_private;
+ uintptr_t base;
+ uint32_t i;
+
+ for (i = 0; i < vf->nb_queues; i++) {
+ base = OTX2_CPT_LF_BAR2(vf, i);
+ otx2_cpt_lf_err_intr_unregister(dev, vf->lf_msixoff[i], base);
+ }
+
+ vf->err_intr_registered = 0;
+}
+
+static int
+otx2_cpt_lf_err_intr_register(const struct rte_cryptodev *dev,
+ uint16_t msix_off, uintptr_t base)
+{
+ struct rte_pci_device *pci_dev = RTE_DEV_TO_PCI(dev->device);
+ struct rte_intr_handle *handle = &pci_dev->intr_handle;
+ int ret;
+
+ /* Disable error interrupts */
+ otx2_write64(~0ull, base + OTX2_CPT_LF_MISC_INT_ENA_W1C);
+
+ /* Register error interrupt handler */
+ ret = otx2_register_irq(handle, otx2_cpt_lf_err_intr_handler,
+ (void *)base, msix_off);
+ if (ret)
+ return ret;
+
+ /* Enable error interrupts */
+ otx2_write64(~0ull, base + OTX2_CPT_LF_MISC_INT_ENA_W1S);
+
+ return 0;
+}
+
+int
+otx2_cpt_err_intr_register(const struct rte_cryptodev *dev)
+{
+ struct otx2_cpt_vf *vf = dev->data->dev_private;
+ uint32_t i, j, ret;
+ uintptr_t base;
+
+ for (i = 0; i < vf->nb_queues; i++) {
+ if (vf->lf_msixoff[i] == MSIX_VECTOR_INVALID) {
+ CPT_LOG_ERR("Invalid CPT LF MSI-X offset: 0x%x",
+ vf->lf_msixoff[i]);
+ return -EINVAL;
+ }
+ }
+
+ for (i = 0; i < vf->nb_queues; i++) {
+ base = OTX2_CPT_LF_BAR2(vf, i);
+ ret = otx2_cpt_lf_err_intr_register(dev, vf->lf_msixoff[i],
+ base);
+ if (ret)
+ goto intr_unregister;
+ }
+
+ vf->err_intr_registered = 1;
+ return 0;
+
+intr_unregister:
+ /* Unregister the ones already registered */
+ for (j = 0; j < i; j++) {
+ base = OTX2_CPT_LF_BAR2(vf, j);
+ otx2_cpt_lf_err_intr_unregister(dev, vf->lf_msixoff[j], base);
+ }
+
+ /*
+ * Failed to register error interrupt. Not returning error as this would
+ * prevent application from enabling larger number of devs.
+ *
+ * This failure is a known issue because otx2_dev_init() initializes
+ * interrupts based on static values from ATF, and the actual number
+ * of interrupts needed (which is based on LFs) can be determined only
+ * after otx2_dev_init() sets up interrupts which includes mbox
+ * interrupts.
+ */
+ return 0;
+}
diff --git a/drivers/crypto/octeontx2/otx2_cryptodev_hw_access.h b/drivers/crypto/octeontx2/otx2_cryptodev_hw_access.h
new file mode 100644
index 0000000..2af674d
--- /dev/null
+++ b/drivers/crypto/octeontx2/otx2_cryptodev_hw_access.h
@@ -0,0 +1,27 @@
+/* SPDX-License-Identifier: BSD-3-Clause
+ * Copyright (C) 2019 Marvell International Ltd.
+ */
+
+#ifndef _OTX2_CRYPTODEV_HW_ACCESS_H_
+#define _OTX2_CRYPTODEV_HW_ACCESS_H_
+
+#include <rte_cryptodev.h>
+
+#include "otx2_dev.h"
+
+/* Register offsets */
+
+/* CPT LF registers */
+#define OTX2_CPT_LF_MISC_INT 0xb0ull
+#define OTX2_CPT_LF_MISC_INT_ENA_W1S 0xd0ull
+#define OTX2_CPT_LF_MISC_INT_ENA_W1C 0xe0ull
+
+#define OTX2_CPT_LF_BAR2(vf, q_id) \
+ ((vf)->otx2_dev.bar2 + \
+ ((RVU_BLOCK_ADDR_CPT0 << 20) | ((q_id) << 12)))
+
+void otx2_cpt_err_intr_unregister(const struct rte_cryptodev *dev);
+
+int otx2_cpt_err_intr_register(const struct rte_cryptodev *dev);
+
+#endif /* _OTX2_CRYPTODEV_HW_ACCESS_H_ */
diff --git a/drivers/crypto/octeontx2/otx2_cryptodev_mbox.c b/drivers/crypto/octeontx2/otx2_cryptodev_mbox.c
index 20fc1ac..9b0117a 100644
--- a/drivers/crypto/octeontx2/otx2_cryptodev_mbox.c
+++ b/drivers/crypto/octeontx2/otx2_cryptodev_mbox.c
@@ -26,3 +26,67 @@ otx2_cpt_available_queues_get(const struct rte_cryptodev *dev,
*nb_queues = rsp->cpt;
return 0;
}
+
+int
+otx2_cpt_queues_attach(const struct rte_cryptodev *dev, uint8_t nb_queues)
+{
+ struct otx2_cpt_vf *vf = dev->data->dev_private;
+ struct otx2_mbox *mbox = vf->otx2_dev.mbox;
+ struct rsrc_attach_req *req;
+
+ /* Ask AF to attach required LFs */
+
+ req = otx2_mbox_alloc_msg_attach_resources(mbox);
+
+ /* 1 LF = 1 queue */
+ req->cptlfs = nb_queues;
+
+ if (otx2_mbox_process(mbox) < 0)
+ return -EIO;
+
+ /* Update number of attached queues */
+ vf->nb_queues = nb_queues;
+
+ return 0;
+}
+
+int
+otx2_cpt_queues_detach(const struct rte_cryptodev *dev)
+{
+ struct otx2_cpt_vf *vf = dev->data->dev_private;
+ struct otx2_mbox *mbox = vf->otx2_dev.mbox;
+ struct rsrc_detach_req *req;
+
+ req = otx2_mbox_alloc_msg_detach_resources(mbox);
+ req->cptlfs = true;
+ req->partial = true;
+ if (otx2_mbox_process(mbox) < 0)
+ return -EIO;
+
+ /* Queues have been detached */
+ vf->nb_queues = 0;
+
+ return 0;
+}
+
+int
+otx2_cpt_msix_offsets_get(const struct rte_cryptodev *dev)
+{
+ struct otx2_cpt_vf *vf = dev->data->dev_private;
+ struct otx2_mbox *mbox = vf->otx2_dev.mbox;
+ struct msix_offset_rsp *rsp;
+ uint32_t i, ret;
+
+ /* Get CPT MSI-X vector offsets */
+
+ otx2_mbox_alloc_msg_msix_offset(mbox);
+
+ ret = otx2_mbox_process_msg(mbox, (void *)&rsp);
+ if (ret)
+ return ret;
+
+ for (i = 0; i < vf->nb_queues; i++)
+ vf->lf_msixoff[i] = rsp->cptlf_msixoff[i];
+
+ return 0;
+}
diff --git a/drivers/crypto/octeontx2/otx2_cryptodev_mbox.h b/drivers/crypto/octeontx2/otx2_cryptodev_mbox.h
index 648c009..0a43061 100644
--- a/drivers/crypto/octeontx2/otx2_cryptodev_mbox.h
+++ b/drivers/crypto/octeontx2/otx2_cryptodev_mbox.h
@@ -10,4 +10,10 @@
int otx2_cpt_available_queues_get(const struct rte_cryptodev *dev,
uint16_t *nb_queues);
+int otx2_cpt_queues_attach(const struct rte_cryptodev *dev, uint8_t nb_queues);
+
+int otx2_cpt_queues_detach(const struct rte_cryptodev *dev);
+
+int otx2_cpt_msix_offsets_get(const struct rte_cryptodev *dev);
+
#endif /* _OTX2_CRYPTODEV_MBOX_H_ */
diff --git a/drivers/crypto/octeontx2/otx2_cryptodev_ops.c b/drivers/crypto/octeontx2/otx2_cryptodev_ops.c
index 18ad470..ac84ed6 100644
--- a/drivers/crypto/octeontx2/otx2_cryptodev_ops.c
+++ b/drivers/crypto/octeontx2/otx2_cryptodev_ops.c
@@ -4,15 +4,134 @@
#include <rte_cryptodev_pmd.h>
+#include "otx2_cryptodev.h"
+#include "otx2_cryptodev_hw_access.h"
+#include "otx2_cryptodev_mbox.h"
#include "otx2_cryptodev_ops.h"
+#include "otx2_mbox.h"
+
+#include "cpt_hw_types.h"
+#include "cpt_pmd_logs.h"
+
+/* PMD ops */
+
+static int
+otx2_cpt_dev_config(struct rte_cryptodev *dev,
+ struct rte_cryptodev_config *conf)
+{
+ struct otx2_cpt_vf *vf = dev->data->dev_private;
+ int ret;
+
+ if (conf->nb_queue_pairs > vf->max_queues) {
+ CPT_LOG_ERR("Invalid number of queue pairs requested");
+ return -EINVAL;
+ }
+
+ dev->feature_flags &= ~conf->ff_disable;
+
+ /* Unregister error interrupts */
+ if (vf->err_intr_registered)
+ otx2_cpt_err_intr_unregister(dev);
+
+ /* Detach queues */
+ if (vf->nb_queues) {
+ ret = otx2_cpt_queues_detach(dev);
+ if (ret) {
+ CPT_LOG_ERR("Could not detach CPT queues");
+ return ret;
+ }
+ }
+
+ /* Attach queues */
+ ret = otx2_cpt_queues_attach(dev, conf->nb_queue_pairs);
+ if (ret) {
+ CPT_LOG_ERR("Could not attach CPT queues");
+ return -ENODEV;
+ }
+
+ ret = otx2_cpt_msix_offsets_get(dev);
+ if (ret) {
+ CPT_LOG_ERR("Could not get MSI-X offsets");
+ goto queues_detach;
+ }
+
+ /* Register error interrupts */
+ ret = otx2_cpt_err_intr_register(dev);
+ if (ret) {
+ CPT_LOG_ERR("Could not register error interrupts");
+ goto queues_detach;
+ }
+
+ rte_mb();
+ return 0;
+
+queues_detach:
+ otx2_cpt_queues_detach(dev);
+ return ret;
+}
+
+static int
+otx2_cpt_dev_start(struct rte_cryptodev *dev)
+{
+ RTE_SET_USED(dev);
+
+ CPT_PMD_INIT_FUNC_TRACE();
+
+ return 0;
+}
+
+static void
+otx2_cpt_dev_stop(struct rte_cryptodev *dev)
+{
+ RTE_SET_USED(dev);
+
+ CPT_PMD_INIT_FUNC_TRACE();
+}
+
+static int
+otx2_cpt_dev_close(struct rte_cryptodev *dev)
+{
+ struct otx2_cpt_vf *vf = dev->data->dev_private;
+ int ret = 0;
+
+ /* Unregister error interrupts */
+ if (vf->err_intr_registered)
+ otx2_cpt_err_intr_unregister(dev);
+
+ /* Detach queues */
+ if (vf->nb_queues) {
+ ret = otx2_cpt_queues_detach(dev);
+ if (ret)
+ CPT_LOG_ERR("Could not detach CPT queues");
+ }
+
+ return ret;
+}
+
+static void
+otx2_cpt_dev_info_get(struct rte_cryptodev *dev,
+ struct rte_cryptodev_info *info)
+{
+ struct otx2_cpt_vf *vf = dev->data->dev_private;
+
+ if (info != NULL) {
+ info->max_nb_queue_pairs = vf->max_queues;
+ info->feature_flags = dev->feature_flags;
+ info->capabilities = NULL;
+ info->sym.max_nb_sessions = 0;
+ info->driver_id = otx2_cryptodev_driver_id;
+ info->min_mbuf_headroom_req = OTX2_CPT_MIN_HEADROOM_REQ;
+ info->min_mbuf_tailroom_req = OTX2_CPT_MIN_TAILROOM_REQ;
+ }
+}
struct rte_cryptodev_ops otx2_cpt_ops = {
/* Device control ops */
- .dev_configure = NULL,
- .dev_start = NULL,
- .dev_stop = NULL,
- .dev_close = NULL,
- .dev_infos_get = NULL,
+ .dev_configure = otx2_cpt_dev_config,
+ .dev_start = otx2_cpt_dev_start,
+ .dev_stop = otx2_cpt_dev_stop,
+ .dev_close = otx2_cpt_dev_close,
+ .dev_infos_get = otx2_cpt_dev_info_get,
.stats_get = NULL,
.stats_reset = NULL,
diff --git a/drivers/crypto/octeontx2/otx2_cryptodev_ops.h b/drivers/crypto/octeontx2/otx2_cryptodev_ops.h
index 545614e..9bd24e7 100644
--- a/drivers/crypto/octeontx2/otx2_cryptodev_ops.h
+++ b/drivers/crypto/octeontx2/otx2_cryptodev_ops.h
@@ -7,6 +7,9 @@
#include <rte_cryptodev_pmd.h>
+#define OTX2_CPT_MIN_HEADROOM_REQ 24
+#define OTX2_CPT_MIN_TAILROOM_REQ 8
+
struct rte_cryptodev_ops otx2_cpt_ops;
#endif /* _OTX2_CRYPTODEV_OPS_H_ */
--
2.7.4
^ permalink raw reply related [flat|nested] 53+ messages in thread* [dpdk-dev] [PATCH v3 04/11] crypto/octeontx2: add queue pair functions
2019-10-16 15:25 ` [dpdk-dev] [PATCH v3 00/11] " Anoob Joseph
` (2 preceding siblings ...)
2019-10-16 15:25 ` [dpdk-dev] [PATCH v3 03/11] crypto/octeontx2: add device control ops Anoob Joseph
@ 2019-10-16 15:25 ` Anoob Joseph
2019-10-16 15:25 ` [dpdk-dev] [PATCH v3 05/11] crypto/octeontx2: add symmetric capabilities Anoob Joseph
` (7 subsequent siblings)
11 siblings, 0 replies; 53+ messages in thread
From: Anoob Joseph @ 2019-10-16 15:25 UTC (permalink / raw)
To: Akhil Goyal, Pablo de Lara
Cc: Ankur Dwivedi, Fiona Trahe, Jerin Jacob, Narayana Prasad,
Shally Verma, Kanaka Durga Kotamarthy, Sunila Sahu,
Tejasree Kondoj, dev, Anoob Joseph
From: Ankur Dwivedi <adwivedi@marvell.com>
This patch adds the queue pair setup and queue pair release functions
for OCTEON TX2 crypto pmd.
Signed-off-by: Ankur Dwivedi <adwivedi@marvell.com>
Signed-off-by: Anoob Joseph <anoobj@marvell.com>
Signed-off-by: Tejasree Kondoj <ktejasree@marvell.com>
---
.../crypto/octeontx2/otx2_cryptodev_hw_access.c | 99 +++++++
.../crypto/octeontx2/otx2_cryptodev_hw_access.h | 126 +++++++++
drivers/crypto/octeontx2/otx2_cryptodev_mbox.c | 83 ++++++
drivers/crypto/octeontx2/otx2_cryptodev_mbox.h | 6 +
drivers/crypto/octeontx2/otx2_cryptodev_ops.c | 306 ++++++++++++++++++++-
5 files changed, 617 insertions(+), 3 deletions(-)
diff --git a/drivers/crypto/octeontx2/otx2_cryptodev_hw_access.c b/drivers/crypto/octeontx2/otx2_cryptodev_hw_access.c
index 663f9ca..9e4f782 100644
--- a/drivers/crypto/octeontx2/otx2_cryptodev_hw_access.c
+++ b/drivers/crypto/octeontx2/otx2_cryptodev_hw_access.c
@@ -1,10 +1,14 @@
/* SPDX-License-Identifier: BSD-3-Clause
* Copyright (C) 2019 Marvell International Ltd.
*/
+#include <rte_cryptodev.h>
#include "otx2_common.h"
#include "otx2_cryptodev.h"
#include "otx2_cryptodev_hw_access.h"
+#include "otx2_cryptodev_mbox.h"
+#include "otx2_cryptodev_ops.h"
+#include "otx2_dev.h"
#include "cpt_pmd_logs.h"
@@ -124,3 +128,98 @@ otx2_cpt_err_intr_register(const struct rte_cryptodev *dev)
*/
return 0;
}
+
+int
+otx2_cpt_iq_enable(const struct rte_cryptodev *dev,
+ const struct otx2_cpt_qp *qp, uint8_t grp_mask, uint8_t pri,
+ uint32_t size_div40)
+{
+ union otx2_cpt_af_lf_ctl af_lf_ctl;
+ union otx2_cpt_lf_inprog inprog;
+ union otx2_cpt_lf_q_base base;
+ union otx2_cpt_lf_q_size size;
+ union otx2_cpt_lf_ctl lf_ctl;
+ int ret;
+
+ /* Set engine group mask and priority */
+
+ ret = otx2_cpt_af_reg_read(dev, OTX2_CPT_AF_LF_CTL(qp->id),
+ &af_lf_ctl.u);
+ if (ret)
+ return ret;
+ af_lf_ctl.s.grp = grp_mask;
+ af_lf_ctl.s.pri = pri ? 1 : 0;
+ ret = otx2_cpt_af_reg_write(dev, OTX2_CPT_AF_LF_CTL(qp->id),
+ af_lf_ctl.u);
+ if (ret)
+ return ret;
+
+ /* Set instruction queue base address */
+
+ base.u = otx2_read64(qp->base + OTX2_CPT_LF_Q_BASE);
+ base.s.fault = 0;
+ base.s.stopped = 0;
+ base.s.addr = qp->iq_dma_addr >> 7;
+ otx2_write64(base.u, qp->base + OTX2_CPT_LF_Q_BASE);
+
+ /* Set instruction queue size */
+
+ size.u = otx2_read64(qp->base + OTX2_CPT_LF_Q_SIZE);
+ size.s.size_div40 = size_div40;
+ otx2_write64(size.u, qp->base + OTX2_CPT_LF_Q_SIZE);
+
+ /* Enable instruction queue */
+
+ lf_ctl.u = otx2_read64(qp->base + OTX2_CPT_LF_CTL);
+ lf_ctl.s.ena = 1;
+ otx2_write64(lf_ctl.u, qp->base + OTX2_CPT_LF_CTL);
+
+ /* Start instruction execution */
+
+ inprog.u = otx2_read64(qp->base + OTX2_CPT_LF_INPROG);
+ inprog.s.eena = 1;
+ otx2_write64(inprog.u, qp->base + OTX2_CPT_LF_INPROG);
+
+ return 0;
+}
+
+void
+otx2_cpt_iq_disable(struct otx2_cpt_qp *qp)
+{
+ union otx2_cpt_lf_q_grp_ptr grp_ptr;
+ union otx2_cpt_lf_inprog inprog;
+ union otx2_cpt_lf_ctl ctl;
+ int cnt;
+
+ /* Stop instruction execution */
+ inprog.u = otx2_read64(qp->base + OTX2_CPT_LF_INPROG);
+ inprog.s.eena = 0x0;
+ otx2_write64(inprog.u, qp->base + OTX2_CPT_LF_INPROG);
+
+ /* Disable instructions enqueuing */
+ ctl.u = otx2_read64(qp->base + OTX2_CPT_LF_CTL);
+ ctl.s.ena = 0;
+ otx2_write64(ctl.u, qp->base + OTX2_CPT_LF_CTL);
+
+ /* Wait for instruction queue to become empty */
+ cnt = 0;
+ do {
+ inprog.u = otx2_read64(qp->base + OTX2_CPT_LF_INPROG);
+ if (inprog.s.grb_partial)
+ cnt = 0;
+ else
+ cnt++;
+ grp_ptr.u = otx2_read64(qp->base + OTX2_CPT_LF_Q_GRP_PTR);
+ } while ((cnt < 10) && (grp_ptr.s.nq_ptr != grp_ptr.s.dq_ptr));
+
+ cnt = 0;
+ do {
+ inprog.u = otx2_read64(qp->base + OTX2_CPT_LF_INPROG);
+ if ((inprog.s.inflight == 0) &&
+ (inprog.s.gwb_cnt < 40) &&
+ ((inprog.s.grb_cnt == 0) || (inprog.s.grb_cnt == 40)))
+ cnt++;
+ else
+ cnt = 0;
+ } while (cnt < 10);
+}
diff --git a/drivers/crypto/octeontx2/otx2_cryptodev_hw_access.h b/drivers/crypto/octeontx2/otx2_cryptodev_hw_access.h
index 2af674d..87d4e77 100644
--- a/drivers/crypto/octeontx2/otx2_cryptodev_hw_access.h
+++ b/drivers/crypto/octeontx2/otx2_cryptodev_hw_access.h
@@ -5,23 +5,149 @@
#ifndef _OTX2_CRYPTODEV_HW_ACCESS_H_
#define _OTX2_CRYPTODEV_HW_ACCESS_H_
+#include <stdint.h>
+
#include <rte_cryptodev.h>
+#include <rte_memory.h>
+
+#include "cpt_common.h"
+#include "cpt_hw_types.h"
#include "otx2_dev.h"
+/* CPT instruction queue length */
+#define OTX2_CPT_IQ_LEN 8200
+
+#define OTX2_CPT_DEFAULT_CMD_QLEN OTX2_CPT_IQ_LEN
+
+/* Mask which selects all engine groups */
+#define OTX2_CPT_ENG_GRPS_MASK 0xFF
+
/* Register offsets */
+/* LMT LF registers */
+#define OTX2_LMT_LF_LMTLINE(a) (0x0ull | (uint64_t)(a) << 3)
+
/* CPT LF registers */
+#define OTX2_CPT_LF_CTL 0x10ull
+#define OTX2_CPT_LF_INPROG 0x40ull
#define OTX2_CPT_LF_MISC_INT 0xb0ull
#define OTX2_CPT_LF_MISC_INT_ENA_W1S 0xd0ull
#define OTX2_CPT_LF_MISC_INT_ENA_W1C 0xe0ull
+#define OTX2_CPT_LF_Q_BASE 0xf0ull
+#define OTX2_CPT_LF_Q_SIZE 0x100ull
+#define OTX2_CPT_LF_Q_GRP_PTR 0x120ull
+#define OTX2_CPT_LF_NQ(a) (0x400ull | (uint64_t)(a) << 3)
+
+#define OTX2_CPT_AF_LF_CTL(a) (0x27000ull | (uint64_t)(a) << 3)
#define OTX2_CPT_LF_BAR2(vf, q_id) \
((vf)->otx2_dev.bar2 + \
((RVU_BLOCK_ADDR_CPT0 << 20) | ((q_id) << 12)))
+#define OTX2_CPT_QUEUE_HI_PRIO 0x1
+
+union otx2_cpt_lf_ctl {
+ uint64_t u;
+ struct {
+ uint64_t ena : 1;
+ uint64_t fc_ena : 1;
+ uint64_t fc_up_crossing : 1;
+ uint64_t reserved_3_3 : 1;
+ uint64_t fc_hyst_bits : 4;
+ uint64_t reserved_8_63 : 56;
+ } s;
+};
+
+union otx2_cpt_lf_inprog {
+ uint64_t u;
+ struct {
+ uint64_t inflight : 9;
+ uint64_t reserved_9_15 : 7;
+ uint64_t eena : 1;
+ uint64_t grp_drp : 1;
+ uint64_t reserved_18_30 : 13;
+ uint64_t grb_partial : 1;
+ uint64_t grb_cnt : 8;
+ uint64_t gwb_cnt : 8;
+ uint64_t reserved_48_63 : 16;
+ } s;
+};
+
+union otx2_cpt_lf_q_base {
+ uint64_t u;
+ struct {
+ uint64_t fault : 1;
+ uint64_t stopped : 1;
+ uint64_t reserved_2_6 : 5;
+ uint64_t addr : 46;
+ uint64_t reserved_53_63 : 11;
+ } s;
+};
+
+union otx2_cpt_lf_q_size {
+ uint64_t u;
+ struct {
+ uint64_t size_div40 : 15;
+ uint64_t reserved_15_63 : 49;
+ } s;
+};
+
+union otx2_cpt_af_lf_ctl {
+ uint64_t u;
+ struct {
+ uint64_t pri : 1;
+ uint64_t reserved_1_8 : 8;
+ uint64_t pf_func_inst : 1;
+ uint64_t cont_err : 1;
+ uint64_t reserved_11_15 : 5;
+ uint64_t nixtx_en : 1;
+ uint64_t reserved_17_47 : 31;
+ uint64_t grp : 8;
+ uint64_t reserved_56_63 : 8;
+ } s;
+};
+
+union otx2_cpt_lf_q_grp_ptr {
+ uint64_t u;
+ struct {
+ uint64_t dq_ptr : 15;
+ uint64_t reserved_31_15 : 17;
+ uint64_t nq_ptr : 15;
+ uint64_t reserved_47_62 : 16;
+ uint64_t xq_xor : 1;
+ } s;
+};
+
+struct otx2_cpt_qp {
+ uint32_t id;
+ /**< Queue pair id */
+ uintptr_t base;
+ /**< Base address where BAR is mapped */
+ void *lmtline;
+ /**< Address of LMTLINE */
+ rte_iova_t lf_nq_reg;
+ /**< LF enqueue register address */
+ struct pending_queue pend_q;
+ /**< Pending queue */
+ struct rte_mempool *sess_mp;
+ /**< Session mempool */
+ struct rte_mempool *sess_mp_priv;
+ /**< Session private data mempool */
+ struct cpt_qp_meta_info meta_info;
+ /**< Metabuf info required to support operations on the queue pair */
+ rte_iova_t iq_dma_addr;
+ /**< Instruction queue address */
+};
+
void otx2_cpt_err_intr_unregister(const struct rte_cryptodev *dev);
int otx2_cpt_err_intr_register(const struct rte_cryptodev *dev);
+int otx2_cpt_iq_enable(const struct rte_cryptodev *dev,
+ const struct otx2_cpt_qp *qp, uint8_t grp_mask,
+ uint8_t pri, uint32_t size_div40);
+
+void otx2_cpt_iq_disable(struct otx2_cpt_qp *qp);
+
#endif /* _OTX2_CRYPTODEV_HW_ACCESS_H_ */
diff --git a/drivers/crypto/octeontx2/otx2_cryptodev_mbox.c b/drivers/crypto/octeontx2/otx2_cryptodev_mbox.c
index 9b0117a..b54e407 100644
--- a/drivers/crypto/octeontx2/otx2_cryptodev_mbox.c
+++ b/drivers/crypto/octeontx2/otx2_cryptodev_mbox.c
@@ -8,6 +8,8 @@
#include "otx2_dev.h"
#include "otx2_mbox.h"
+#include "cpt_pmd_logs.h"
+
int
otx2_cpt_available_queues_get(const struct rte_cryptodev *dev,
uint16_t *nb_queues)
@@ -90,3 +92,84 @@ otx2_cpt_msix_offsets_get(const struct rte_cryptodev *dev)
return 0;
}
+
+static int
+otx2_cpt_send_mbox_msg(struct otx2_cpt_vf *vf)
+{
+ struct otx2_mbox *mbox = vf->otx2_dev.mbox;
+ int ret;
+
+ otx2_mbox_msg_send(mbox, 0);
+
+ ret = otx2_mbox_wait_for_rsp(mbox, 0);
+ if (ret < 0) {
+ CPT_LOG_ERR("Could not get mailbox response");
+ return ret;
+ }
+
+ return 0;
+}
+
+int
+otx2_cpt_af_reg_read(const struct rte_cryptodev *dev, uint64_t reg,
+ uint64_t *val)
+{
+ struct otx2_cpt_vf *vf = dev->data->dev_private;
+ struct otx2_mbox *mbox = vf->otx2_dev.mbox;
+ struct otx2_mbox_dev *mdev = &mbox->dev[0];
+ struct cpt_rd_wr_reg_msg *msg;
+ int ret, off;
+
+ msg = (struct cpt_rd_wr_reg_msg *)
+ otx2_mbox_alloc_msg_rsp(mbox, 0, sizeof(*msg),
+ sizeof(*msg));
+ if (msg == NULL) {
+ CPT_LOG_ERR("Could not allocate mailbox message");
+ return -EFAULT;
+ }
+
+ msg->hdr.id = MBOX_MSG_CPT_RD_WR_REGISTER;
+ msg->hdr.sig = OTX2_MBOX_REQ_SIG;
+ msg->hdr.pcifunc = vf->otx2_dev.pf_func;
+ msg->is_write = 0;
+ msg->reg_offset = reg;
+ msg->ret_val = val;
+
+ ret = otx2_cpt_send_mbox_msg(vf);
+ if (ret < 0)
+ return ret;
+
+ off = mbox->rx_start +
+ RTE_ALIGN(sizeof(struct mbox_hdr), MBOX_MSG_ALIGN);
+ msg = (struct cpt_rd_wr_reg_msg *) ((uintptr_t)mdev->mbase + off);
+
+ *val = msg->val;
+
+ return 0;
+}
+
+int
+otx2_cpt_af_reg_write(const struct rte_cryptodev *dev, uint64_t reg,
+ uint64_t val)
+{
+ struct otx2_cpt_vf *vf = dev->data->dev_private;
+ struct otx2_mbox *mbox = vf->otx2_dev.mbox;
+ struct cpt_rd_wr_reg_msg *msg;
+
+ msg = (struct cpt_rd_wr_reg_msg *)
+ otx2_mbox_alloc_msg_rsp(mbox, 0, sizeof(*msg),
+ sizeof(*msg));
+ if (msg == NULL) {
+ CPT_LOG_ERR("Could not allocate mailbox message");
+ return -EFAULT;
+ }
+
+ msg->hdr.id = MBOX_MSG_CPT_RD_WR_REGISTER;
+ msg->hdr.sig = OTX2_MBOX_REQ_SIG;
+ msg->hdr.pcifunc = vf->otx2_dev.pf_func;
+ msg->is_write = 1;
+ msg->reg_offset = reg;
+ msg->val = val;
+
+ return otx2_cpt_send_mbox_msg(vf);
+}
diff --git a/drivers/crypto/octeontx2/otx2_cryptodev_mbox.h b/drivers/crypto/octeontx2/otx2_cryptodev_mbox.h
index 0a43061..a298718 100644
--- a/drivers/crypto/octeontx2/otx2_cryptodev_mbox.h
+++ b/drivers/crypto/octeontx2/otx2_cryptodev_mbox.h
@@ -16,4 +16,10 @@ int otx2_cpt_queues_detach(const struct rte_cryptodev *dev);
int otx2_cpt_msix_offsets_get(const struct rte_cryptodev *dev);
+int otx2_cpt_af_reg_read(const struct rte_cryptodev *dev, uint64_t reg,
+ uint64_t *val);
+
+int otx2_cpt_af_reg_write(const struct rte_cryptodev *dev, uint64_t reg,
+ uint64_t val);
+
#endif /* _OTX2_CRYPTODEV_MBOX_H_ */
diff --git a/drivers/crypto/octeontx2/otx2_cryptodev_ops.c b/drivers/crypto/octeontx2/otx2_cryptodev_ops.c
index ac84ed6..8419e27 100644
--- a/drivers/crypto/octeontx2/otx2_cryptodev_ops.c
+++ b/drivers/crypto/octeontx2/otx2_cryptodev_ops.c
@@ -2,7 +2,10 @@
* Copyright (C) 2019 Marvell International Ltd.
*/
+#include <unistd.h>
+
#include <rte_cryptodev_pmd.h>
+#include <rte_errno.h>
#include "otx2_cryptodev.h"
#include "otx2_cryptodev_hw_access.h"
@@ -12,6 +15,233 @@
#include "cpt_hw_types.h"
#include "cpt_pmd_logs.h"
+#include "cpt_pmd_ops_helper.h"
+
+#define METABUF_POOL_CACHE_SIZE 512
+
+/* Forward declarations */
+
+static int
+otx2_cpt_queue_pair_release(struct rte_cryptodev *dev, uint16_t qp_id);
+
+static void
+qp_memzone_name_get(char *name, int size, int dev_id, int qp_id)
+{
+ snprintf(name, size, "otx2_cpt_lf_mem_%u:%u", dev_id, qp_id);
+}
+
+static int
+otx2_cpt_metabuf_mempool_create(const struct rte_cryptodev *dev,
+ struct otx2_cpt_qp *qp, uint8_t qp_id,
+ int nb_elements)
+{
+ char mempool_name[RTE_MEMPOOL_NAMESIZE];
+ int sg_mlen, lb_mlen, max_mlen, ret;
+ struct cpt_qp_meta_info *meta_info;
+ struct rte_mempool *pool;
+
+ /* Get meta len for scatter gather mode */
+ sg_mlen = cpt_pmd_ops_helper_get_mlen_sg_mode();
+
+ /* Extra 32B saved for future considerations */
+ sg_mlen += 4 * sizeof(uint64_t);
+
+ /* Get meta len for linear buffer (direct) mode */
+ lb_mlen = cpt_pmd_ops_helper_get_mlen_direct_mode();
+
+ /* Extra 32B saved for future considerations */
+ lb_mlen += 4 * sizeof(uint64_t);
+
+ /* Check max requirement for meta buffer */
+ max_mlen = RTE_MAX(lb_mlen, sg_mlen);
+
+ /* Allocate mempool */
+
+ snprintf(mempool_name, RTE_MEMPOOL_NAMESIZE, "otx2_cpt_mb_%u:%u",
+ dev->data->dev_id, qp_id);
+
+ pool = rte_mempool_create_empty(mempool_name, nb_elements, max_mlen,
+ METABUF_POOL_CACHE_SIZE, 0,
+ rte_socket_id(), 0);
+
+ if (pool == NULL) {
+ CPT_LOG_ERR("Could not create mempool for metabuf");
+ return rte_errno;
+ }
+
+ ret = rte_mempool_set_ops_byname(pool, RTE_MBUF_DEFAULT_MEMPOOL_OPS,
+ NULL);
+ if (ret) {
+ CPT_LOG_ERR("Could not set mempool ops");
+ goto mempool_free;
+ }
+
+ ret = rte_mempool_populate_default(pool);
+ if (ret <= 0) {
+ CPT_LOG_ERR("Could not populate metabuf pool");
+ goto mempool_free;
+ }
+
+ meta_info = &qp->meta_info;
+
+ meta_info->pool = pool;
+ meta_info->lb_mlen = lb_mlen;
+ meta_info->sg_mlen = sg_mlen;
+
+ return 0;
+
+mempool_free:
+ rte_mempool_free(pool);
+ return ret;
+}
+
+static void
+otx2_cpt_metabuf_mempool_destroy(struct otx2_cpt_qp *qp)
+{
+ struct cpt_qp_meta_info *meta_info = &qp->meta_info;
+
+ rte_mempool_free(meta_info->pool);
+
+ meta_info->pool = NULL;
+ meta_info->lb_mlen = 0;
+ meta_info->sg_mlen = 0;
+}
+
+static struct otx2_cpt_qp *
+otx2_cpt_qp_create(const struct rte_cryptodev *dev, uint16_t qp_id,
+ uint8_t group)
+{
+ struct otx2_cpt_vf *vf = dev->data->dev_private;
+ uint64_t pg_sz = sysconf(_SC_PAGESIZE);
+ const struct rte_memzone *lf_mem;
+ uint32_t len, iq_len, size_div40;
+ char name[RTE_MEMZONE_NAMESIZE];
+ uint64_t used_len, iova;
+ struct otx2_cpt_qp *qp;
+ uint64_t lmtline;
+ uint8_t *va;
+ int ret;
+
+ /* Allocate queue pair */
+ qp = rte_zmalloc_socket("OCTEON TX2 Crypto PMD Queue Pair", sizeof(*qp),
+ OTX2_ALIGN, 0);
+ if (qp == NULL) {
+ CPT_LOG_ERR("Could not allocate queue pair");
+ return NULL;
+ }
+
+ iq_len = OTX2_CPT_IQ_LEN;
+
+ /*
+ * Queue size must be a multiple of 40 and effective queue size to
+ * software is (size_div40 - 1) * 40
+ */
+ size_div40 = (iq_len + 40 - 1) / 40 + 1;
+
+ /* For pending queue */
+ len = iq_len * RTE_ALIGN(sizeof(struct rid), 8);
+
+ /* Space for instruction group memory */
+ len += size_div40 * 16;
+
+ /* So that instruction queues start as pg size aligned */
+ len = RTE_ALIGN(len, pg_sz);
+
+ /* For instruction queues */
+ len += OTX2_CPT_IQ_LEN * sizeof(union cpt_inst_s);
+
+ /* Wastage after instruction queues */
+ len = RTE_ALIGN(len, pg_sz);
+
+ qp_memzone_name_get(name, RTE_MEMZONE_NAMESIZE, dev->data->dev_id,
+ qp_id);
+
+ lf_mem = rte_memzone_reserve_aligned(name, len, vf->otx2_dev.node,
+ RTE_MEMZONE_SIZE_HINT_ONLY | RTE_MEMZONE_256MB,
+ RTE_CACHE_LINE_SIZE);
+ if (lf_mem == NULL) {
+ CPT_LOG_ERR("Could not allocate reserved memzone");
+ goto qp_free;
+ }
+
+ va = lf_mem->addr;
+ iova = lf_mem->iova;
+
+ memset(va, 0, len);
+
+ ret = otx2_cpt_metabuf_mempool_create(dev, qp, qp_id, iq_len);
+ if (ret) {
+ CPT_LOG_ERR("Could not create mempool for metabuf");
+ goto lf_mem_free;
+ }
+
+ /* Initialize pending queue */
+ qp->pend_q.rid_queue = (struct rid *)va;
+ qp->pend_q.enq_tail = 0;
+ qp->pend_q.deq_head = 0;
+ qp->pend_q.pending_count = 0;
+
+ used_len = iq_len * RTE_ALIGN(sizeof(struct rid), 8);
+ used_len += size_div40 * 16;
+ used_len = RTE_ALIGN(used_len, pg_sz);
+ iova += used_len;
+
+ qp->iq_dma_addr = iova;
+ qp->id = qp_id;
+ qp->base = OTX2_CPT_LF_BAR2(vf, qp_id);
+
+ lmtline = vf->otx2_dev.bar2 +
+ (RVU_BLOCK_ADDR_LMT << 20 | qp_id << 12) +
+ OTX2_LMT_LF_LMTLINE(0);
+
+ qp->lmtline = (void *)lmtline;
+
+ qp->lf_nq_reg = qp->base + OTX2_CPT_LF_NQ(0);
+
+ otx2_cpt_iq_disable(qp);
+
+ ret = otx2_cpt_iq_enable(dev, qp, group, OTX2_CPT_QUEUE_HI_PRIO,
+ size_div40);
+ if (ret) {
+ CPT_LOG_ERR("Could not enable instruction queue");
+ goto mempool_destroy;
+ }
+
+ return qp;
+
+mempool_destroy:
+ otx2_cpt_metabuf_mempool_destroy(qp);
+lf_mem_free:
+ rte_memzone_free(lf_mem);
+qp_free:
+ rte_free(qp);
+ return NULL;
+}
+
+static int
+otx2_cpt_qp_destroy(const struct rte_cryptodev *dev, struct otx2_cpt_qp *qp)
+{
+ const struct rte_memzone *lf_mem;
+ char name[RTE_MEMZONE_NAMESIZE];
+ int ret;
+
+ otx2_cpt_iq_disable(qp);
+
+ otx2_cpt_metabuf_mempool_destroy(qp);
+
+ qp_memzone_name_get(name, RTE_MEMZONE_NAMESIZE, dev->data->dev_id,
+ qp->id);
+
+ lf_mem = rte_memzone_lookup(name);
+
+ ret = rte_memzone_free(lf_mem);
+ if (ret)
+ return ret;
+
+ rte_free(qp);
+
+ return 0;
+}
/* PMD ops */
@@ -92,7 +322,13 @@ static int
otx2_cpt_dev_close(struct rte_cryptodev *dev)
{
struct otx2_cpt_vf *vf = dev->data->dev_private;
- int ret = 0;
+ int i, ret = 0;
+
+ for (i = 0; i < dev->data->nb_queue_pairs; i++) {
+ ret = otx2_cpt_queue_pair_release(dev, i);
+ if (ret)
+ return ret;
+ }
/* Unregister error interrupts */
if (vf->err_intr_registered)
@@ -125,6 +361,70 @@ otx2_cpt_dev_info_get(struct rte_cryptodev *dev,
}
}
+static int
+otx2_cpt_queue_pair_setup(struct rte_cryptodev *dev, uint16_t qp_id,
+ const struct rte_cryptodev_qp_conf *conf,
+ int socket_id __rte_unused)
+{
+ uint8_t grp_mask = OTX2_CPT_ENG_GRPS_MASK;
+ struct rte_pci_device *pci_dev;
+ struct otx2_cpt_qp *qp;
+
+ CPT_PMD_INIT_FUNC_TRACE();
+
+ if (dev->data->queue_pairs[qp_id] != NULL)
+ otx2_cpt_queue_pair_release(dev, qp_id);
+
+ if (conf->nb_descriptors > OTX2_CPT_DEFAULT_CMD_QLEN) {
+ CPT_LOG_ERR("Could not setup queue pair for %u descriptors",
+ conf->nb_descriptors);
+ return -EINVAL;
+ }
+
+ pci_dev = RTE_DEV_TO_PCI(dev->device);
+
+ if (pci_dev->mem_resource[2].addr == NULL) {
+ CPT_LOG_ERR("Invalid PCI mem address");
+ return -EIO;
+ }
+
+ qp = otx2_cpt_qp_create(dev, qp_id, grp_mask);
+ if (qp == NULL) {
+ CPT_LOG_ERR("Could not create queue pair %d", qp_id);
+ return -ENOMEM;
+ }
+
+ qp->sess_mp = conf->mp_session;
+ qp->sess_mp_priv = conf->mp_session_private;
+ dev->data->queue_pairs[qp_id] = qp;
+
+ return 0;
+}
+
+static int
+otx2_cpt_queue_pair_release(struct rte_cryptodev *dev, uint16_t qp_id)
+{
+ struct otx2_cpt_qp *qp = dev->data->queue_pairs[qp_id];
+ int ret;
+
+ CPT_PMD_INIT_FUNC_TRACE();
+
+ if (qp == NULL)
+ return -EINVAL;
+
+ CPT_LOG_INFO("Releasing queue pair %d", qp_id);
+
+ ret = otx2_cpt_qp_destroy(dev, qp);
+ if (ret) {
+ CPT_LOG_ERR("Could not destroy queue pair %d", qp_id);
+ return ret;
+ }
+
+ dev->data->queue_pairs[qp_id] = NULL;
+
+ return 0;
+}
+
struct rte_cryptodev_ops otx2_cpt_ops = {
/* Device control ops */
.dev_configure = otx2_cpt_dev_config,
@@ -135,8 +435,8 @@ struct rte_cryptodev_ops otx2_cpt_ops = {
.stats_get = NULL,
.stats_reset = NULL,
- .queue_pair_setup = NULL,
- .queue_pair_release = NULL,
+ .queue_pair_setup = otx2_cpt_queue_pair_setup,
+ .queue_pair_release = otx2_cpt_queue_pair_release,
.queue_pair_count = NULL,
/* Symmetric crypto ops */
--
2.7.4
^ permalink raw reply related [flat|nested] 53+ messages in thread* [dpdk-dev] [PATCH v3 05/11] crypto/octeontx2: add symmetric capabilities
2019-10-16 15:25 ` [dpdk-dev] [PATCH v3 00/11] " Anoob Joseph
` (3 preceding siblings ...)
2019-10-16 15:25 ` [dpdk-dev] [PATCH v3 04/11] crypto/octeontx2: add queue pair functions Anoob Joseph
@ 2019-10-16 15:25 ` Anoob Joseph
2019-10-16 15:25 ` [dpdk-dev] [PATCH v3 06/11] crypto/octeontx2: add session related functions Anoob Joseph
` (6 subsequent siblings)
11 siblings, 0 replies; 53+ messages in thread
From: Anoob Joseph @ 2019-10-16 15:25 UTC (permalink / raw)
To: Akhil Goyal, Pablo de Lara
Cc: Anoob Joseph, Fiona Trahe, Jerin Jacob, Narayana Prasad,
Shally Verma, Ankur Dwivedi, Kanaka Durga Kotamarthy, Sunila Sahu,
Tejasree Kondoj, dev
This patch adds the symmetric capabilities for OCTEON TX2 crypto PMD.
Signed-off-by: Ankur Dwivedi <adwivedi@marvell.com>
Signed-off-by: Anoob Joseph <anoobj@marvell.com>
Signed-off-by: Tejasree Kondoj <ktejasree@marvell.com>
---
doc/guides/cryptodevs/features/octeontx2.ini | 59 ++
doc/guides/cryptodevs/octeontx2.rst | 41 ++
drivers/crypto/octeontx2/Makefile | 1 +
drivers/crypto/octeontx2/meson.build | 1 +
drivers/crypto/octeontx2/otx2_cryptodev.c | 6 +-
.../crypto/octeontx2/otx2_cryptodev_capabilities.c | 604 +++++++++++++++++++++
.../crypto/octeontx2/otx2_cryptodev_capabilities.h | 16 +
drivers/crypto/octeontx2/otx2_cryptodev_ops.c | 3 +-
8 files changed, 729 insertions(+), 2 deletions(-)
create mode 100644 drivers/crypto/octeontx2/otx2_cryptodev_capabilities.c
create mode 100644 drivers/crypto/octeontx2/otx2_cryptodev_capabilities.h
diff --git a/doc/guides/cryptodevs/features/octeontx2.ini b/doc/guides/cryptodevs/features/octeontx2.ini
index 35c9bee..4e82463 100644
--- a/doc/guides/cryptodevs/features/octeontx2.ini
+++ b/doc/guides/cryptodevs/features/octeontx2.ini
@@ -5,4 +5,63 @@
;
[Features]
Symmetric crypto = Y
+Sym operation chaining = Y
HW Accelerated = Y
+In Place SGL = Y
+OOP SGL In LB Out = Y
+OOP SGL In SGL Out = Y
+
+;
+; Supported crypto algorithms of 'octeontx2' crypto driver.
+;
+[Cipher]
+NULL = Y
+3DES CBC = Y
+3DES ECB = Y
+AES CBC (128) = Y
+AES CBC (192) = Y
+AES CBC (256) = Y
+AES CTR (128) = Y
+AES CTR (192) = Y
+AES CTR (256) = Y
+AES XTS (128) = Y
+AES XTS (256) = Y
+DES CBC = Y
+KASUMI F8 = Y
+SNOW3G UEA2 = Y
+ZUC EEA3 = Y
+
+;
+; Supported authentication algorithms of 'octeontx2' crypto driver.
+;
+[Auth]
+NULL = Y
+AES GMAC = Y
+KASUMI F9 = Y
+MD5 = Y
+MD5 HMAC = Y
+SHA1 = Y
+SHA1 HMAC = Y
+SHA224 = Y
+SHA224 HMAC = Y
+SHA256 = Y
+SHA256 HMAC = Y
+SHA384 = Y
+SHA384 HMAC = Y
+SHA512 = Y
+SHA512 HMAC = Y
+SNOW3G UIA2 = Y
+ZUC EIA3 = Y
+
+;
+; Supported AEAD algorithms of 'octeontx2' crypto driver.
+;
+[AEAD]
+AES GCM (128) = Y
+AES GCM (192) = Y
+AES GCM (256) = Y
+
+;
+; Supported Asymmetric algorithms of the 'octeontx2' crypto driver.
+;
+[Asymmetric]
diff --git a/doc/guides/cryptodevs/octeontx2.rst b/doc/guides/cryptodevs/octeontx2.rst
index 10f578a..47e9150 100644
--- a/doc/guides/cryptodevs/octeontx2.rst
+++ b/doc/guides/cryptodevs/octeontx2.rst
@@ -16,6 +16,47 @@ Features
The OCTEON TX2 crypto PMD has support for:
+Symmetric Crypto Algorithms
+~~~~~~~~~~~~~~~~~~~~~~~~~~~
+
+Cipher algorithms:
+
+* ``RTE_CRYPTO_CIPHER_NULL``
+* ``RTE_CRYPTO_CIPHER_3DES_CBC``
+* ``RTE_CRYPTO_CIPHER_3DES_ECB``
+* ``RTE_CRYPTO_CIPHER_AES_CBC``
+* ``RTE_CRYPTO_CIPHER_AES_CTR``
+* ``RTE_CRYPTO_CIPHER_AES_XTS``
+* ``RTE_CRYPTO_CIPHER_DES_CBC``
+* ``RTE_CRYPTO_CIPHER_KASUMI_F8``
+* ``RTE_CRYPTO_CIPHER_SNOW3G_UEA2``
+* ``RTE_CRYPTO_CIPHER_ZUC_EEA3``
+
+Hash algorithms:
+
+* ``RTE_CRYPTO_AUTH_NULL``
+* ``RTE_CRYPTO_AUTH_AES_GMAC``
+* ``RTE_CRYPTO_AUTH_KASUMI_F9``
+* ``RTE_CRYPTO_AUTH_MD5``
+* ``RTE_CRYPTO_AUTH_MD5_HMAC``
+* ``RTE_CRYPTO_AUTH_SHA1``
+* ``RTE_CRYPTO_AUTH_SHA1_HMAC``
+* ``RTE_CRYPTO_AUTH_SHA224``
+* ``RTE_CRYPTO_AUTH_SHA224_HMAC``
+* ``RTE_CRYPTO_AUTH_SHA256``
+* ``RTE_CRYPTO_AUTH_SHA256_HMAC``
+* ``RTE_CRYPTO_AUTH_SHA384``
+* ``RTE_CRYPTO_AUTH_SHA384_HMAC``
+* ``RTE_CRYPTO_AUTH_SHA512``
+* ``RTE_CRYPTO_AUTH_SHA512_HMAC``
+* ``RTE_CRYPTO_AUTH_SNOW3G_UIA2``
+* ``RTE_CRYPTO_AUTH_ZUC_EIA3``
+
+AEAD algorithms:
+
+* ``RTE_CRYPTO_AEAD_AES_GCM``
+
+
Installation
------------
diff --git a/drivers/crypto/octeontx2/Makefile b/drivers/crypto/octeontx2/Makefile
index 71bc4d1..968efac 100644
--- a/drivers/crypto/octeontx2/Makefile
+++ b/drivers/crypto/octeontx2/Makefile
@@ -35,6 +35,7 @@ endif
# PMD code
SRCS-$(CONFIG_RTE_LIBRTE_PMD_OCTEONTX2_CRYPTO) += otx2_cryptodev.c
+SRCS-$(CONFIG_RTE_LIBRTE_PMD_OCTEONTX2_CRYPTO) += otx2_cryptodev_capabilities.c
SRCS-$(CONFIG_RTE_LIBRTE_PMD_OCTEONTX2_CRYPTO) += otx2_cryptodev_hw_access.c
SRCS-$(CONFIG_RTE_LIBRTE_PMD_OCTEONTX2_CRYPTO) += otx2_cryptodev_mbox.c
SRCS-$(CONFIG_RTE_LIBRTE_PMD_OCTEONTX2_CRYPTO) += otx2_cryptodev_ops.c
diff --git a/drivers/crypto/octeontx2/meson.build b/drivers/crypto/octeontx2/meson.build
index 944fa2c..ee2e907 100644
--- a/drivers/crypto/octeontx2/meson.build
+++ b/drivers/crypto/octeontx2/meson.build
@@ -11,6 +11,7 @@ deps += ['common_octeontx2']
name = 'octeontx2_crypto'
sources = files('otx2_cryptodev.c',
+ 'otx2_cryptodev_capabilities.c',
'otx2_cryptodev_hw_access.c',
'otx2_cryptodev_mbox.c',
'otx2_cryptodev_ops.c')
diff --git a/drivers/crypto/octeontx2/otx2_cryptodev.c b/drivers/crypto/octeontx2/otx2_cryptodev.c
index efc17cb..32c0b48 100644
--- a/drivers/crypto/octeontx2/otx2_cryptodev.c
+++ b/drivers/crypto/octeontx2/otx2_cryptodev.c
@@ -95,7 +95,11 @@ otx2_cpt_pci_probe(struct rte_pci_driver *pci_drv __rte_unused,
CPT_LOG_INFO("Max queues supported by device: %d", vf->max_queues);
dev->feature_flags = RTE_CRYPTODEV_FF_SYMMETRIC_CRYPTO |
- RTE_CRYPTODEV_FF_HW_ACCELERATED;
+ RTE_CRYPTODEV_FF_HW_ACCELERATED |
+ RTE_CRYPTODEV_FF_SYM_OPERATION_CHAINING |
+ RTE_CRYPTODEV_FF_IN_PLACE_SGL |
+ RTE_CRYPTODEV_FF_OOP_SGL_IN_LB_OUT |
+ RTE_CRYPTODEV_FF_OOP_SGL_IN_SGL_OUT;
return 0;
diff --git a/drivers/crypto/octeontx2/otx2_cryptodev_capabilities.c b/drivers/crypto/octeontx2/otx2_cryptodev_capabilities.c
new file mode 100644
index 0000000..3a70470
--- /dev/null
+++ b/drivers/crypto/octeontx2/otx2_cryptodev_capabilities.c
@@ -0,0 +1,604 @@
+/* SPDX-License-Identifier: BSD-3-Clause
+ * Copyright (C) 2019 Marvell International Ltd.
+ */
+
+#include <rte_cryptodev.h>
+
+#include "otx2_cryptodev_capabilities.h"
+
+static const struct rte_cryptodev_capabilities otx2_cpt_sym_capabilities[] = {
+ /* Symmetric capabilities */
+ { /* NULL (AUTH) */
+ .op = RTE_CRYPTO_OP_TYPE_SYMMETRIC,
+ {.sym = {
+ .xform_type = RTE_CRYPTO_SYM_XFORM_AUTH,
+ {.auth = {
+ .algo = RTE_CRYPTO_AUTH_NULL,
+ .block_size = 1,
+ .key_size = {
+ .min = 0,
+ .max = 0,
+ .increment = 0
+ },
+ .digest_size = {
+ .min = 0,
+ .max = 0,
+ .increment = 0
+ },
+ }, },
+ }, },
+ },
+ { /* AES GMAC (AUTH) */
+ .op = RTE_CRYPTO_OP_TYPE_SYMMETRIC,
+ {.sym = {
+ .xform_type = RTE_CRYPTO_SYM_XFORM_AUTH,
+ {.auth = {
+ .algo = RTE_CRYPTO_AUTH_AES_GMAC,
+ .block_size = 16,
+ .key_size = {
+ .min = 16,
+ .max = 32,
+ .increment = 8
+ },
+ .digest_size = {
+ .min = 8,
+ .max = 16,
+ .increment = 4
+ },
+ .iv_size = {
+ .min = 12,
+ .max = 12,
+ .increment = 0
+ }
+ }, }
+ }, }
+ },
+ { /* KASUMI (F9) */
+ .op = RTE_CRYPTO_OP_TYPE_SYMMETRIC,
+ {.sym = {
+ .xform_type = RTE_CRYPTO_SYM_XFORM_AUTH,
+ {.auth = {
+ .algo = RTE_CRYPTO_AUTH_KASUMI_F9,
+ .block_size = 8,
+ .key_size = {
+ .min = 16,
+ .max = 16,
+ .increment = 0
+ },
+ .digest_size = {
+ .min = 4,
+ .max = 4,
+ .increment = 0
+ },
+ }, }
+ }, }
+ },
+ { /* MD5 */
+ .op = RTE_CRYPTO_OP_TYPE_SYMMETRIC,
+ {.sym = {
+ .xform_type = RTE_CRYPTO_SYM_XFORM_AUTH,
+ {.auth = {
+ .algo = RTE_CRYPTO_AUTH_MD5,
+ .block_size = 64,
+ .key_size = {
+ .min = 0,
+ .max = 0,
+ .increment = 0
+ },
+ .digest_size = {
+ .min = 16,
+ .max = 16,
+ .increment = 0
+ },
+ }, }
+ }, }
+ },
+ { /* MD5 HMAC */
+ .op = RTE_CRYPTO_OP_TYPE_SYMMETRIC,
+ {.sym = {
+ .xform_type = RTE_CRYPTO_SYM_XFORM_AUTH,
+ {.auth = {
+ .algo = RTE_CRYPTO_AUTH_MD5_HMAC,
+ .block_size = 64,
+ .key_size = {
+ .min = 8,
+ .max = 64,
+ .increment = 8
+ },
+ .digest_size = {
+ .min = 16,
+ .max = 16,
+ .increment = 0
+ },
+ }, }
+ }, }
+ },
+ { /* SHA1 */
+ .op = RTE_CRYPTO_OP_TYPE_SYMMETRIC,
+ {.sym = {
+ .xform_type = RTE_CRYPTO_SYM_XFORM_AUTH,
+ {.auth = {
+ .algo = RTE_CRYPTO_AUTH_SHA1,
+ .block_size = 64,
+ .key_size = {
+ .min = 0,
+ .max = 0,
+ .increment = 0
+ },
+ .digest_size = {
+ .min = 20,
+ .max = 20,
+ .increment = 0
+ },
+ }, }
+ }, }
+ },
+ { /* SHA1 HMAC */
+ .op = RTE_CRYPTO_OP_TYPE_SYMMETRIC,
+ {.sym = {
+ .xform_type = RTE_CRYPTO_SYM_XFORM_AUTH,
+ {.auth = {
+ .algo = RTE_CRYPTO_AUTH_SHA1_HMAC,
+ .block_size = 64,
+ .key_size = {
+ .min = 64,
+ .max = 64,
+ .increment = 0
+ },
+ .digest_size = {
+ .min = 20,
+ .max = 20,
+ .increment = 0
+ },
+ }, }
+ }, }
+ },
+ { /* SHA224 */
+ .op = RTE_CRYPTO_OP_TYPE_SYMMETRIC,
+ {.sym = {
+ .xform_type = RTE_CRYPTO_SYM_XFORM_AUTH,
+ {.auth = {
+ .algo = RTE_CRYPTO_AUTH_SHA224,
+ .block_size = 64,
+ .key_size = {
+ .min = 0,
+ .max = 0,
+ .increment = 0
+ },
+ .digest_size = {
+ .min = 28,
+ .max = 28,
+ .increment = 0
+ },
+ }, }
+ }, }
+ },
+ { /* SHA224 HMAC */
+ .op = RTE_CRYPTO_OP_TYPE_SYMMETRIC,
+ {.sym = {
+ .xform_type = RTE_CRYPTO_SYM_XFORM_AUTH,
+ {.auth = {
+ .algo = RTE_CRYPTO_AUTH_SHA224_HMAC,
+ .block_size = 64,
+ .key_size = {
+ .min = 64,
+ .max = 64,
+ .increment = 0
+ },
+ .digest_size = {
+ .min = 28,
+ .max = 28,
+ .increment = 0
+ },
+ }, }
+ }, }
+ },
+ { /* SHA256 */
+ .op = RTE_CRYPTO_OP_TYPE_SYMMETRIC,
+ {.sym = {
+ .xform_type = RTE_CRYPTO_SYM_XFORM_AUTH,
+ {.auth = {
+ .algo = RTE_CRYPTO_AUTH_SHA256,
+ .block_size = 64,
+ .key_size = {
+ .min = 0,
+ .max = 0,
+ .increment = 0
+ },
+ .digest_size = {
+ .min = 32,
+ .max = 32,
+ .increment = 0
+ },
+ }, }
+ }, }
+ },
+ { /* SHA256 HMAC */
+ .op = RTE_CRYPTO_OP_TYPE_SYMMETRIC,
+ {.sym = {
+ .xform_type = RTE_CRYPTO_SYM_XFORM_AUTH,
+ {.auth = {
+ .algo = RTE_CRYPTO_AUTH_SHA256_HMAC,
+ .block_size = 64,
+ .key_size = {
+ .min = 64,
+ .max = 64,
+ .increment = 0
+ },
+ .digest_size = {
+ .min = 32,
+ .max = 32,
+ .increment = 0
+ },
+ }, }
+ }, }
+ },
+ { /* SHA384 */
+ .op = RTE_CRYPTO_OP_TYPE_SYMMETRIC,
+ {.sym = {
+ .xform_type = RTE_CRYPTO_SYM_XFORM_AUTH,
+ {.auth = {
+ .algo = RTE_CRYPTO_AUTH_SHA384,
+ .block_size = 64,
+ .key_size = {
+ .min = 0,
+ .max = 0,
+ .increment = 0
+ },
+ .digest_size = {
+ .min = 48,
+ .max = 48,
+ .increment = 0
+ },
+ }, }
+ }, }
+ },
+ { /* SHA384 HMAC */
+ .op = RTE_CRYPTO_OP_TYPE_SYMMETRIC,
+ {.sym = {
+ .xform_type = RTE_CRYPTO_SYM_XFORM_AUTH,
+ {.auth = {
+ .algo = RTE_CRYPTO_AUTH_SHA384_HMAC,
+ .block_size = 64,
+ .key_size = {
+ .min = 64,
+ .max = 64,
+ .increment = 0
+ },
+ .digest_size = {
+ .min = 48,
+ .max = 48,
+ .increment = 0
+ },
+ }, }
+ }, }
+ },
+ { /* SHA512 */
+ .op = RTE_CRYPTO_OP_TYPE_SYMMETRIC,
+ {.sym = {
+ .xform_type = RTE_CRYPTO_SYM_XFORM_AUTH,
+ {.auth = {
+ .algo = RTE_CRYPTO_AUTH_SHA512,
+ .block_size = 128,
+ .key_size = {
+ .min = 0,
+ .max = 0,
+ .increment = 0
+ },
+ .digest_size = {
+ .min = 64,
+ .max = 64,
+ .increment = 0
+ },
+ }, }
+ }, }
+ },
+ { /* SHA512 HMAC */
+ .op = RTE_CRYPTO_OP_TYPE_SYMMETRIC,
+ {.sym = {
+ .xform_type = RTE_CRYPTO_SYM_XFORM_AUTH,
+ {.auth = {
+ .algo = RTE_CRYPTO_AUTH_SHA512_HMAC,
+ .block_size = 128,
+ .key_size = {
+ .min = 64,
+ .max = 64,
+ .increment = 0
+ },
+ .digest_size = {
+ .min = 64,
+ .max = 64,
+ .increment = 0
+ },
+ }, }
+ }, }
+ },
+ { /* SNOW 3G (UIA2) */
+ .op = RTE_CRYPTO_OP_TYPE_SYMMETRIC,
+ {.sym = {
+ .xform_type = RTE_CRYPTO_SYM_XFORM_AUTH,
+ {.auth = {
+ .algo = RTE_CRYPTO_AUTH_SNOW3G_UIA2,
+ .block_size = 16,
+ .key_size = {
+ .min = 16,
+ .max = 16,
+ .increment = 0
+ },
+ .digest_size = {
+ .min = 4,
+ .max = 4,
+ .increment = 0
+ },
+ .iv_size = {
+ .min = 16,
+ .max = 16,
+ .increment = 0
+ }
+ }, }
+ }, }
+ },
+ { /* ZUC (EIA3) */
+ .op = RTE_CRYPTO_OP_TYPE_SYMMETRIC,
+ {.sym = {
+ .xform_type = RTE_CRYPTO_SYM_XFORM_AUTH,
+ {.auth = {
+ .algo = RTE_CRYPTO_AUTH_ZUC_EIA3,
+ .block_size = 16,
+ .key_size = {
+ .min = 16,
+ .max = 16,
+ .increment = 0
+ },
+ .digest_size = {
+ .min = 4,
+ .max = 4,
+ .increment = 0
+ },
+ .iv_size = {
+ .min = 16,
+ .max = 16,
+ .increment = 0
+ }
+ }, }
+ }, }
+ },
+ { /* NULL (CIPHER) */
+ .op = RTE_CRYPTO_OP_TYPE_SYMMETRIC,
+ {.sym = {
+ .xform_type = RTE_CRYPTO_SYM_XFORM_CIPHER,
+ {.cipher = {
+ .algo = RTE_CRYPTO_CIPHER_NULL,
+ .block_size = 1,
+ .key_size = {
+ .min = 0,
+ .max = 0,
+ .increment = 0
+ },
+ .iv_size = {
+ .min = 0,
+ .max = 0,
+ .increment = 0
+ }
+ }, },
+ }, }
+ },
+ { /* 3DES CBC */
+ .op = RTE_CRYPTO_OP_TYPE_SYMMETRIC,
+ {.sym = {
+ .xform_type = RTE_CRYPTO_SYM_XFORM_CIPHER,
+ {.cipher = {
+ .algo = RTE_CRYPTO_CIPHER_3DES_CBC,
+ .block_size = 8,
+ .key_size = {
+ .min = 24,
+ .max = 24,
+ .increment = 0
+ },
+ .iv_size = {
+ .min = 8,
+ .max = 16,
+ .increment = 8
+ }
+ }, }
+ }, }
+ },
+ { /* 3DES ECB */
+ .op = RTE_CRYPTO_OP_TYPE_SYMMETRIC,
+ {.sym = {
+ .xform_type = RTE_CRYPTO_SYM_XFORM_CIPHER,
+ {.cipher = {
+ .algo = RTE_CRYPTO_CIPHER_3DES_ECB,
+ .block_size = 8,
+ .key_size = {
+ .min = 24,
+ .max = 24,
+ .increment = 0
+ },
+ .iv_size = {
+ .min = 0,
+ .max = 0,
+ .increment = 0
+ }
+ }, }
+ }, }
+ },
+ { /* AES CBC */
+ .op = RTE_CRYPTO_OP_TYPE_SYMMETRIC,
+ {.sym = {
+ .xform_type = RTE_CRYPTO_SYM_XFORM_CIPHER,
+ {.cipher = {
+ .algo = RTE_CRYPTO_CIPHER_AES_CBC,
+ .block_size = 16,
+ .key_size = {
+ .min = 16,
+ .max = 32,
+ .increment = 8
+ },
+ .iv_size = {
+ .min = 16,
+ .max = 16,
+ .increment = 0
+ }
+ }, }
+ }, }
+ },
+ { /* AES CTR */
+ .op = RTE_CRYPTO_OP_TYPE_SYMMETRIC,
+ {.sym = {
+ .xform_type = RTE_CRYPTO_SYM_XFORM_CIPHER,
+ {.cipher = {
+ .algo = RTE_CRYPTO_CIPHER_AES_CTR,
+ .block_size = 16,
+ .key_size = {
+ .min = 16,
+ .max = 32,
+ .increment = 8
+ },
+ .iv_size = {
+ .min = 12,
+ .max = 16,
+ .increment = 4
+ }
+ }, }
+ }, }
+ },
+ { /* AES XTS */
+ .op = RTE_CRYPTO_OP_TYPE_SYMMETRIC,
+ {.sym = {
+ .xform_type = RTE_CRYPTO_SYM_XFORM_CIPHER,
+ {.cipher = {
+ .algo = RTE_CRYPTO_CIPHER_AES_XTS,
+ .block_size = 16,
+ .key_size = {
+ .min = 32,
+ .max = 64,
+ .increment = 0
+ },
+ .iv_size = {
+ .min = 16,
+ .max = 16,
+ .increment = 0
+ }
+ }, }
+ }, }
+ },
+ { /* DES CBC */
+ .op = RTE_CRYPTO_OP_TYPE_SYMMETRIC,
+ {.sym = {
+ .xform_type = RTE_CRYPTO_SYM_XFORM_CIPHER,
+ {.cipher = {
+ .algo = RTE_CRYPTO_CIPHER_DES_CBC,
+ .block_size = 8,
+ .key_size = {
+ .min = 8,
+ .max = 8,
+ .increment = 0
+ },
+ .iv_size = {
+ .min = 8,
+ .max = 8,
+ .increment = 0
+ }
+ }, }
+ }, }
+ },
+ { /* KASUMI (F8) */
+ .op = RTE_CRYPTO_OP_TYPE_SYMMETRIC,
+ {.sym = {
+ .xform_type = RTE_CRYPTO_SYM_XFORM_CIPHER,
+ {.cipher = {
+ .algo = RTE_CRYPTO_CIPHER_KASUMI_F8,
+ .block_size = 8,
+ .key_size = {
+ .min = 16,
+ .max = 16,
+ .increment = 0
+ },
+ .iv_size = {
+ .min = 8,
+ .max = 8,
+ .increment = 0
+ }
+ }, }
+ }, }
+ },
+ { /* SNOW 3G (UEA2) */
+ .op = RTE_CRYPTO_OP_TYPE_SYMMETRIC,
+ {.sym = {
+ .xform_type = RTE_CRYPTO_SYM_XFORM_CIPHER,
+ {.cipher = {
+ .algo = RTE_CRYPTO_CIPHER_SNOW3G_UEA2,
+ .block_size = 16,
+ .key_size = {
+ .min = 16,
+ .max = 16,
+ .increment = 0
+ },
+ .iv_size = {
+ .min = 16,
+ .max = 16,
+ .increment = 0
+ }
+ }, }
+ }, }
+ },
+ { /* ZUC (EEA3) */
+ .op = RTE_CRYPTO_OP_TYPE_SYMMETRIC,
+ {.sym = {
+ .xform_type = RTE_CRYPTO_SYM_XFORM_CIPHER,
+ {.cipher = {
+ .algo = RTE_CRYPTO_CIPHER_ZUC_EEA3,
+ .block_size = 16,
+ .key_size = {
+ .min = 16,
+ .max = 16,
+ .increment = 0
+ },
+ .iv_size = {
+ .min = 16,
+ .max = 16,
+ .increment = 0
+ }
+ }, }
+ }, }
+ },
+ { /* AES GCM */
+ .op = RTE_CRYPTO_OP_TYPE_SYMMETRIC,
+ {.sym = {
+ .xform_type = RTE_CRYPTO_SYM_XFORM_AEAD,
+ {.aead = {
+ .algo = RTE_CRYPTO_AEAD_AES_GCM,
+ .block_size = 16,
+ .key_size = {
+ .min = 16,
+ .max = 32,
+ .increment = 8
+ },
+ .digest_size = {
+ .min = 8,
+ .max = 16,
+ .increment = 4
+ },
+ .aad_size = {
+ .min = 0,
+ .max = 1024,
+ .increment = 1
+ },
+ .iv_size = {
+ .min = 12,
+ .max = 12,
+ .increment = 0
+ }
+ }, }
+ }, }
+ },
+ /* End of symmetric capabilities */
+ RTE_CRYPTODEV_END_OF_CAPABILITIES_LIST()
+};
+
+const struct rte_cryptodev_capabilities *
+otx2_cpt_capabilities_get(void)
+{
+ return otx2_cpt_sym_capabilities;
+}
diff --git a/drivers/crypto/octeontx2/otx2_cryptodev_capabilities.h b/drivers/crypto/octeontx2/otx2_cryptodev_capabilities.h
new file mode 100644
index 0000000..f103c32
--- /dev/null
+++ b/drivers/crypto/octeontx2/otx2_cryptodev_capabilities.h
@@ -0,0 +1,16 @@
+/* SPDX-License-Identifier: BSD-3-Clause
+ * Copyright (C) 2019 Marvell International Ltd.
+ */
+
+#ifndef _OTX2_CRYPTODEV_CAPABILITIES_H_
+#define _OTX2_CRYPTODEV_CAPABILITIES_H_
+
+#include <rte_cryptodev.h>
+
+/*
+ * Get capabilities list for the device
+ *
+ */
+const struct rte_cryptodev_capabilities *otx2_cpt_capabilities_get(void);
+
+#endif /* _OTX2_CRYPTODEV_CAPABILITIES_H_ */
diff --git a/drivers/crypto/octeontx2/otx2_cryptodev_ops.c b/drivers/crypto/octeontx2/otx2_cryptodev_ops.c
index 8419e27..f2146ba 100644
--- a/drivers/crypto/octeontx2/otx2_cryptodev_ops.c
+++ b/drivers/crypto/octeontx2/otx2_cryptodev_ops.c
@@ -8,6 +8,7 @@
#include <rte_errno.h>
#include "otx2_cryptodev.h"
+#include "otx2_cryptodev_capabilities.h"
#include "otx2_cryptodev_hw_access.h"
#include "otx2_cryptodev_mbox.h"
#include "otx2_cryptodev_ops.h"
@@ -353,7 +354,7 @@ otx2_cpt_dev_info_get(struct rte_cryptodev *dev,
if (info != NULL) {
info->max_nb_queue_pairs = vf->max_queues;
info->feature_flags = dev->feature_flags;
- info->capabilities = NULL;
+ info->capabilities = otx2_cpt_capabilities_get();
info->sym.max_nb_sessions = 0;
info->driver_id = otx2_cryptodev_driver_id;
info->min_mbuf_headroom_req = OTX2_CPT_MIN_HEADROOM_REQ;
--
2.7.4
^ permalink raw reply related [flat|nested] 53+ messages in thread* [dpdk-dev] [PATCH v3 06/11] crypto/octeontx2: add session related functions
2019-10-16 15:25 ` [dpdk-dev] [PATCH v3 00/11] " Anoob Joseph
` (4 preceding siblings ...)
2019-10-16 15:25 ` [dpdk-dev] [PATCH v3 05/11] crypto/octeontx2: add symmetric capabilities Anoob Joseph
@ 2019-10-16 15:25 ` Anoob Joseph
2019-10-16 15:25 ` [dpdk-dev] [PATCH v3 07/11] crypto/octeontx2: add enqueue/dequeue ops Anoob Joseph
` (5 subsequent siblings)
11 siblings, 0 replies; 53+ messages in thread
From: Anoob Joseph @ 2019-10-16 15:25 UTC (permalink / raw)
To: Akhil Goyal, Pablo de Lara
Cc: Ankur Dwivedi, Fiona Trahe, Jerin Jacob, Narayana Prasad,
Shally Verma, Kanaka Durga Kotamarthy, Sunila Sahu,
Tejasree Kondoj, dev, Anoob Joseph
From: Ankur Dwivedi <adwivedi@marvell.com>
This patch adds the symmetric session related callbacks.
Signed-off-by: Ankur Dwivedi <adwivedi@marvell.com>
Signed-off-by: Anoob Joseph <anoobj@marvell.com>
Signed-off-by: Tejasree Kondoj <ktejasree@marvell.com>
---
drivers/common/cpt/cpt_mcode_defines.h | 2 +
drivers/crypto/octeontx2/otx2_cryptodev_ops.c | 117 +++++++++++++++++++++++++-
drivers/crypto/octeontx2/otx2_cryptodev_ops.h | 5 ++
3 files changed, 121 insertions(+), 3 deletions(-)
diff --git a/drivers/common/cpt/cpt_mcode_defines.h b/drivers/common/cpt/cpt_mcode_defines.h
index 91d30a5..f356e62 100644
--- a/drivers/common/cpt/cpt_mcode_defines.h
+++ b/drivers/common/cpt/cpt_mcode_defines.h
@@ -226,6 +226,8 @@ struct cpt_sess_misc {
uint16_t is_null:1;
/** Flag for GMAC */
uint16_t is_gmac:1;
+ /** Engine group */
+ uint16_t egrp:3;
/** AAD length */
uint16_t aad_length;
/** MAC len in bytes */
diff --git a/drivers/crypto/octeontx2/otx2_cryptodev_ops.c b/drivers/crypto/octeontx2/otx2_cryptodev_ops.c
index f2146ba..b06d8f3 100644
--- a/drivers/crypto/octeontx2/otx2_cryptodev_ops.c
+++ b/drivers/crypto/octeontx2/otx2_cryptodev_ops.c
@@ -17,6 +17,7 @@
#include "cpt_hw_types.h"
#include "cpt_pmd_logs.h"
#include "cpt_pmd_ops_helper.h"
+#include "cpt_ucode.h"
#define METABUF_POOL_CACHE_SIZE 512
@@ -244,6 +245,90 @@ otx2_cpt_qp_destroy(const struct rte_cryptodev *dev, struct otx2_cpt_qp *qp)
return 0;
}
+static int
+sym_session_configure(int driver_id, struct rte_crypto_sym_xform *xform,
+ struct rte_cryptodev_sym_session *sess,
+ struct rte_mempool *pool)
+{
+ struct cpt_sess_misc *misc;
+ void *priv;
+ int ret;
+
+ if (unlikely(cpt_is_algo_supported(xform))) {
+ CPT_LOG_ERR("Crypto xform not supported");
+ return -ENOTSUP;
+ }
+
+ if (unlikely(rte_mempool_get(pool, &priv))) {
+ CPT_LOG_ERR("Could not allocate session private data");
+ return -ENOMEM;
+ }
+
+ misc = priv;
+
+ for ( ; xform != NULL; xform = xform->next) {
+ switch (xform->type) {
+ case RTE_CRYPTO_SYM_XFORM_AEAD:
+ ret = fill_sess_aead(xform, misc);
+ break;
+ case RTE_CRYPTO_SYM_XFORM_CIPHER:
+ ret = fill_sess_cipher(xform, misc);
+ break;
+ case RTE_CRYPTO_SYM_XFORM_AUTH:
+ if (xform->auth.algo == RTE_CRYPTO_AUTH_AES_GMAC)
+ ret = fill_sess_gmac(xform, misc);
+ else
+ ret = fill_sess_auth(xform, misc);
+ break;
+ default:
+ ret = -1;
+ }
+
+ if (ret)
+ goto priv_put;
+ }
+
+ set_sym_session_private_data(sess, driver_id, misc);
+
+ misc->ctx_dma_addr = rte_mempool_virt2iova(misc) +
+ sizeof(struct cpt_sess_misc);
+
+ /*
+ * IE engines support IPsec operations
+ * SE engines support IPsec operations and Air-Crypto operations
+ */
+ if (misc->zsk_flag)
+ misc->egrp = OTX2_CPT_EGRP_SE;
+ else
+ misc->egrp = OTX2_CPT_EGRP_SE_IE;
+
+ return 0;
+
+priv_put:
+ rte_mempool_put(pool, priv);
+
+ CPT_LOG_ERR("Crypto xform not supported");
+ return -ENOTSUP;
+}
+
+static void
+sym_session_clear(int driver_id, struct rte_cryptodev_sym_session *sess)
+{
+ void *priv = get_sym_session_private_data(sess, driver_id);
+ struct rte_mempool *pool;
+
+ if (priv == NULL)
+ return;
+
+ memset(priv, 0, cpt_get_session_size());
+
+ pool = rte_mempool_from_obj(priv);
+
+ set_sym_session_private_data(sess, driver_id, NULL);
+
+ rte_mempool_put(pool, priv);
+}
+
/* PMD ops */
static int
@@ -426,6 +511,32 @@ otx2_cpt_queue_pair_release(struct rte_cryptodev *dev, uint16_t qp_id)
return 0;
}
+static unsigned int
+otx2_cpt_sym_session_get_size(struct rte_cryptodev *dev __rte_unused)
+{
+ return cpt_get_session_size();
+}
+
+static int
+otx2_cpt_sym_session_configure(struct rte_cryptodev *dev,
+ struct rte_crypto_sym_xform *xform,
+ struct rte_cryptodev_sym_session *sess,
+ struct rte_mempool *pool)
+{
+ CPT_PMD_INIT_FUNC_TRACE();
+
+ return sym_session_configure(dev->driver_id, xform, sess, pool);
+}
+
+static void
+otx2_cpt_sym_session_clear(struct rte_cryptodev *dev,
+ struct rte_cryptodev_sym_session *sess)
+{
+ CPT_PMD_INIT_FUNC_TRACE();
+
+ return sym_session_clear(dev->driver_id, sess);
+}
+
struct rte_cryptodev_ops otx2_cpt_ops = {
/* Device control ops */
.dev_configure = otx2_cpt_dev_config,
@@ -441,7 +552,7 @@ struct rte_cryptodev_ops otx2_cpt_ops = {
.queue_pair_count = NULL,
/* Symmetric crypto ops */
- .sym_session_get_size = NULL,
- .sym_session_configure = NULL,
- .sym_session_clear = NULL,
+ .sym_session_get_size = otx2_cpt_sym_session_get_size,
+ .sym_session_configure = otx2_cpt_sym_session_configure,
+ .sym_session_clear = otx2_cpt_sym_session_clear,
};
diff --git a/drivers/crypto/octeontx2/otx2_cryptodev_ops.h b/drivers/crypto/octeontx2/otx2_cryptodev_ops.h
index 9bd24e7..ba93a66 100644
--- a/drivers/crypto/octeontx2/otx2_cryptodev_ops.h
+++ b/drivers/crypto/octeontx2/otx2_cryptodev_ops.h
@@ -10,6 +10,11 @@
#define OTX2_CPT_MIN_HEADROOM_REQ 24
#define OTX2_CPT_MIN_TAILROOM_REQ 8
+enum otx2_cpt_egrp {
+ OTX2_CPT_EGRP_SE = 0,
+ OTX2_CPT_EGRP_SE_IE = 1,
+};
+
struct rte_cryptodev_ops otx2_cpt_ops;
#endif /* _OTX2_CRYPTODEV_OPS_H_ */
--
2.7.4
^ permalink raw reply related [flat|nested] 53+ messages in thread* [dpdk-dev] [PATCH v3 07/11] crypto/octeontx2: add enqueue/dequeue ops
2019-10-16 15:25 ` [dpdk-dev] [PATCH v3 00/11] " Anoob Joseph
` (5 preceding siblings ...)
2019-10-16 15:25 ` [dpdk-dev] [PATCH v3 06/11] crypto/octeontx2: add session related functions Anoob Joseph
@ 2019-10-16 15:25 ` Anoob Joseph
2019-10-16 15:25 ` [dpdk-dev] [PATCH v3 08/11] test: add OCTEON TX2 tests Anoob Joseph
` (4 subsequent siblings)
11 siblings, 0 replies; 53+ messages in thread
From: Anoob Joseph @ 2019-10-16 15:25 UTC (permalink / raw)
To: Akhil Goyal, Pablo de Lara
Cc: Anoob Joseph, Fiona Trahe, Jerin Jacob, Narayana Prasad,
Shally Verma, Ankur Dwivedi, Kanaka Durga Kotamarthy, Sunila Sahu,
Tejasree Kondoj, dev
This patch adds the enqueue burst and dequeue burst callbacks for the
OCTEON TX2 crypto driver.
Signed-off-by: Ankur Dwivedi <adwivedi@marvell.com>
Signed-off-by: Anoob Joseph <anoobj@marvell.com>
Signed-off-by: Tejasree Kondoj <ktejasree@marvell.com>
---
drivers/common/cpt/cpt_hw_types.h | 52 ++++
drivers/crypto/octeontx2/Makefile | 1 +
drivers/crypto/octeontx2/meson.build | 1 +
.../crypto/octeontx2/otx2_cryptodev_hw_access.h | 16 ++
drivers/crypto/octeontx2/otx2_cryptodev_ops.c | 289 +++++++++++++++++++++
5 files changed, 359 insertions(+)
diff --git a/drivers/common/cpt/cpt_hw_types.h b/drivers/common/cpt/cpt_hw_types.h
index 4c2893b..e2b127d 100644
--- a/drivers/common/cpt/cpt_hw_types.h
+++ b/drivers/common/cpt/cpt_hw_types.h
@@ -197,6 +197,44 @@ typedef union cpt_inst_s {
};
#endif /* Word 7 - End */
} s8x;
+ struct cpt_inst_s_9s {
+#if (RTE_BYTE_ORDER == RTE_BIG_ENDIAN) /* Word 0 - Big Endian */
+ uint64_t nixtx_addr : 60;
+ uint64_t doneint : 1;
+ uint64_t nixtxl : 3;
+#else /* Word 0 - Little Endian */
+ uint64_t nixtxl : 3;
+ uint64_t doneint : 1;
+ uint64_t nixtx_addr : 60;
+#endif /* Word 0 - End */
+ uint64_t res_addr;
+#if (RTE_BYTE_ORDER == RTE_BIG_ENDIAN) /* Word 2 - Big Endian */
+ uint64_t rvu_pf_func : 16;
+ uint64_t reserved_172_175 : 4;
+ uint64_t grp : 10;
+ uint64_t tt : 2;
+ uint64_t tag : 32;
+#else /* Word 2 - Little Endian */
+ uint64_t tag : 32;
+ uint64_t tt : 2;
+ uint64_t grp : 10;
+ uint64_t reserved_172_175 : 4;
+ uint64_t rvu_pf_func : 16;
+#endif /* Word 2 - End */
+#if (RTE_BYTE_ORDER == RTE_BIG_ENDIAN) /* Word 3 - Big Endian */
+ uint64_t wq_ptr : 61;
+ uint64_t reserved_194_193 : 2;
+ uint64_t qord : 1;
+#else /* Word 3 - Little Endian */
+ uint64_t qord : 1;
+ uint64_t reserved_194_193 : 2;
+ uint64_t wq_ptr : 61;
+#endif /* Word 3 - End */
+ uint64_t ei0;
+ uint64_t ei1;
+ uint64_t ei2;
+ uint64_t ei3;
+ } s9x;
} cpt_inst_s_t;
/**
@@ -243,6 +281,20 @@ typedef union cpt_res_s {
uint64_t reserved_64_127 : 64;
#endif /* Word 1 - End */
} s8x;
+ struct cpt_res_s_9s {
+#if (RTE_BYTE_ORDER == RTE_BIG_ENDIAN) /* Word 0 - Big Endian */
+ uint64_t reserved_17_63:47;
+ uint64_t doneint:1;
+ uint64_t uc_compcode:8;
+ uint64_t compcode:8;
+#else /* Word 0 - Little Endian */
+ uint64_t compcode:8;
+ uint64_t uc_compcode:8;
+ uint64_t doneint:1;
+ uint64_t reserved_17_63:47;
+#endif /* Word 0 - End */
+ uint64_t reserved_64_127;
+ } s9x;
} cpt_res_s_t;
/**
diff --git a/drivers/crypto/octeontx2/Makefile b/drivers/crypto/octeontx2/Makefile
index 968efac..ce116b8 100644
--- a/drivers/crypto/octeontx2/Makefile
+++ b/drivers/crypto/octeontx2/Makefile
@@ -24,6 +24,7 @@ CFLAGS += -O3
CFLAGS += -I$(RTE_SDK)/drivers/common/cpt
CFLAGS += -I$(RTE_SDK)/drivers/common/octeontx2
CFLAGS += -I$(RTE_SDK)/drivers/mempool/octeontx2
+CFLAGS += -DALLOW_EXPERIMENTAL_API
ifneq ($(CONFIG_RTE_ARCH_64),y)
CFLAGS += -Wno-int-to-pointer-cast
diff --git a/drivers/crypto/octeontx2/meson.build b/drivers/crypto/octeontx2/meson.build
index ee2e907..b6e5b73 100644
--- a/drivers/crypto/octeontx2/meson.build
+++ b/drivers/crypto/octeontx2/meson.build
@@ -10,6 +10,7 @@ deps += ['common_cpt']
deps += ['common_octeontx2']
name = 'octeontx2_crypto'
+allow_experimental_apis = true
sources = files('otx2_cryptodev.c',
'otx2_cryptodev_capabilities.c',
'otx2_cryptodev_hw_access.c',
diff --git a/drivers/crypto/octeontx2/otx2_cryptodev_hw_access.h b/drivers/crypto/octeontx2/otx2_cryptodev_hw_access.h
index 87d4e77..6f78aa4 100644
--- a/drivers/crypto/octeontx2/otx2_cryptodev_hw_access.h
+++ b/drivers/crypto/octeontx2/otx2_cryptodev_hw_access.h
@@ -12,6 +12,7 @@
#include "cpt_common.h"
#include "cpt_hw_types.h"
+#include "cpt_mcode_defines.h"
#include "otx2_dev.h"
@@ -119,6 +120,21 @@ union otx2_cpt_lf_q_grp_ptr {
} s;
};
+/*
+ * Enumeration cpt_9x_comp_e
+ *
+ * CPT 9X Completion Enumeration
+ * Enumerates the values of CPT_RES_S[COMPCODE].
+ */
+enum cpt_9x_comp_e {
+ CPT_9X_COMP_E_NOTDONE = 0x00,
+ CPT_9X_COMP_E_GOOD = 0x01,
+ CPT_9X_COMP_E_FAULT = 0x02,
+ CPT_9X_COMP_E_HWERR = 0x04,
+ CPT_9X_COMP_E_INSTERR = 0x05,
+ CPT_9X_COMP_E_LAST_ENTRY = 0x06
+};
+
struct otx2_cpt_qp {
uint32_t id;
/**< Queue pair id */
diff --git a/drivers/crypto/octeontx2/otx2_cryptodev_ops.c b/drivers/crypto/octeontx2/otx2_cryptodev_ops.c
index b06d8f3..818f0d9 100644
--- a/drivers/crypto/octeontx2/otx2_cryptodev_ops.c
+++ b/drivers/crypto/octeontx2/otx2_cryptodev_ops.c
@@ -329,6 +329,292 @@ sym_session_clear(int driver_id, struct rte_cryptodev_sym_session *sess)
rte_mempool_put(pool, priv);
}
+static __rte_always_inline int32_t __hot
+otx2_cpt_enqueue_req(const struct otx2_cpt_qp *qp,
+ struct pending_queue *pend_q,
+ struct cpt_request_info *req)
+{
+ void *lmtline = qp->lmtline;
+ union cpt_inst_s inst;
+ uint64_t lmt_status;
+
+ if (unlikely(pend_q->pending_count >= OTX2_CPT_DEFAULT_CMD_QLEN))
+ return -EAGAIN;
+
+ inst.u[0] = 0;
+ inst.s9x.res_addr = req->comp_baddr;
+ inst.u[2] = 0;
+ inst.u[3] = 0;
+
+ inst.s9x.ei0 = req->ist.ei0;
+ inst.s9x.ei1 = req->ist.ei1;
+ inst.s9x.ei2 = req->ist.ei2;
+ inst.s9x.ei3 = req->ist.ei3;
+
+ req->time_out = rte_get_timer_cycles() +
+ DEFAULT_COMMAND_TIMEOUT * rte_get_timer_hz();
+
+ do {
+ /* Copy CPT command to LMTLINE */
+ memcpy(lmtline, &inst, sizeof(inst));
+
+ /*
+ * Make sure compiler does not reorder memcpy and ldeor.
+ * LMTST transactions are always flushed from the write
+ * buffer immediately, a DMB is not required to push out
+ * LMTSTs.
+ */
+ rte_cio_wmb();
+ lmt_status = otx2_lmt_submit(qp->lf_nq_reg);
+ } while (lmt_status == 0);
+
+ pend_q->rid_queue[pend_q->enq_tail].rid = (uintptr_t)req;
+
+ /* We will use soft queue length here to limit requests */
+ MOD_INC(pend_q->enq_tail, OTX2_CPT_DEFAULT_CMD_QLEN);
+ pend_q->pending_count += 1;
+
+ return 0;
+}
+
+static __rte_always_inline int __hot
+otx2_cpt_enqueue_sym(struct otx2_cpt_qp *qp, struct rte_crypto_op *op,
+ struct pending_queue *pend_q)
+{
+ struct rte_crypto_sym_op *sym_op = op->sym;
+ struct cpt_request_info *req;
+ struct cpt_sess_misc *sess;
+ vq_cmd_word3_t *w3;
+ uint64_t cpt_op;
+ void *mdata;
+ int ret;
+
+ sess = get_sym_session_private_data(sym_op->session,
+ otx2_cryptodev_driver_id);
+
+ cpt_op = sess->cpt_op;
+
+ if (cpt_op & CPT_OP_CIPHER_MASK)
+ ret = fill_fc_params(op, sess, &qp->meta_info, &mdata,
+ (void **)&req);
+ else
+ ret = fill_digest_params(op, sess, &qp->meta_info, &mdata,
+ (void **)&req);
+
+ if (unlikely(ret)) {
+ CPT_LOG_DP_ERR("Crypto req : op %p, cpt_op 0x%x ret 0x%x",
+ op, (unsigned int)cpt_op, ret);
+ return ret;
+ }
+
+ w3 = ((vq_cmd_word3_t *)(&req->ist.ei3));
+ w3->s.grp = sess->egrp;
+
+ ret = otx2_cpt_enqueue_req(qp, pend_q, req);
+
+ if (unlikely(ret)) {
+ /* Free buffer allocated by fill params routines */
+ free_op_meta(mdata, qp->meta_info.pool);
+ }
+
+ return ret;
+}
+
+static __rte_always_inline int __hot
+otx2_cpt_enqueue_sym_sessless(struct otx2_cpt_qp *qp, struct rte_crypto_op *op,
+ struct pending_queue *pend_q)
+{
+ const int driver_id = otx2_cryptodev_driver_id;
+ struct rte_crypto_sym_op *sym_op = op->sym;
+ struct rte_cryptodev_sym_session *sess;
+ int ret;
+
+ /* Create temporary session */
+
+ if (rte_mempool_get(qp->sess_mp, (void **)&sess))
+ return -ENOMEM;
+
+ ret = sym_session_configure(driver_id, sym_op->xform, sess,
+ qp->sess_mp_priv);
+ if (ret)
+ goto sess_put;
+
+ sym_op->session = sess;
+
+ ret = otx2_cpt_enqueue_sym(qp, op, pend_q);
+
+ if (unlikely(ret))
+ goto priv_put;
+
+ return 0;
+
+priv_put:
+ sym_session_clear(driver_id, sess);
+sess_put:
+ rte_mempool_put(qp->sess_mp, sess);
+ return ret;
+}
+
+static uint16_t
+otx2_cpt_enqueue_burst(void *qptr, struct rte_crypto_op **ops, uint16_t nb_ops)
+{
+ uint16_t nb_allowed, count = 0;
+ struct otx2_cpt_qp *qp = qptr;
+ struct pending_queue *pend_q;
+ struct rte_crypto_op *op;
+ int ret;
+
+ pend_q = &qp->pend_q;
+
+ nb_allowed = OTX2_CPT_DEFAULT_CMD_QLEN - pend_q->pending_count;
+ if (nb_ops > nb_allowed)
+ nb_ops = nb_allowed;
+
+ for (count = 0; count < nb_ops; count++) {
+ op = ops[count];
+ if (op->type == RTE_CRYPTO_OP_TYPE_SYMMETRIC) {
+ if (op->sess_type == RTE_CRYPTO_OP_WITH_SESSION)
+ ret = otx2_cpt_enqueue_sym(qp, op, pend_q);
+ else
+ ret = otx2_cpt_enqueue_sym_sessless(qp, op,
+ pend_q);
+ } else
+ break;
+
+ if (unlikely(ret))
+ break;
+ }
+
+ return count;
+}
+
+static inline void
+otx2_cpt_dequeue_post_process(struct otx2_cpt_qp *qp, struct rte_crypto_op *cop,
+ uintptr_t *rsp, uint8_t cc)
+{
+ if (cop->type == RTE_CRYPTO_OP_TYPE_SYMMETRIC) {
+ if (likely(cc == NO_ERR)) {
+ /* Verify authentication data if required */
+ if (unlikely(rsp[2]))
+ compl_auth_verify(cop, (uint8_t *)rsp[2],
+ rsp[3]);
+ else
+ cop->status = RTE_CRYPTO_OP_STATUS_SUCCESS;
+ } else {
+ if (cc == ERR_GC_ICV_MISCOMPARE)
+ cop->status = RTE_CRYPTO_OP_STATUS_AUTH_FAILED;
+ else
+ cop->status = RTE_CRYPTO_OP_STATUS_ERROR;
+ }
+
+ if (unlikely(cop->sess_type == RTE_CRYPTO_OP_SESSIONLESS)) {
+ sym_session_clear(otx2_cryptodev_driver_id,
+ cop->sym->session);
+ rte_mempool_put(qp->sess_mp, cop->sym->session);
+ cop->sym->session = NULL;
+ }
+ }
+}
+
+static __rte_always_inline uint8_t
+otx2_cpt_compcode_get(struct cpt_request_info *req)
+{
+ volatile struct cpt_res_s_9s *res;
+ uint8_t ret;
+
+ res = (volatile struct cpt_res_s_9s *)req->completion_addr;
+
+ if (unlikely(res->compcode == CPT_9X_COMP_E_NOTDONE)) {
+ if (rte_get_timer_cycles() < req->time_out)
+ return ERR_REQ_PENDING;
+
+ CPT_LOG_DP_ERR("Request timed out");
+ return ERR_REQ_TIMEOUT;
+ }
+
+ if (likely(res->compcode == CPT_9X_COMP_E_GOOD)) {
+ ret = NO_ERR;
+ if (unlikely(res->uc_compcode)) {
+ ret = res->uc_compcode;
+ CPT_LOG_DP_DEBUG("Request failed with microcode error");
+ CPT_LOG_DP_DEBUG("MC completion code 0x%x",
+ res->uc_compcode);
+ }
+ } else {
+ CPT_LOG_DP_DEBUG("HW completion code 0x%x", res->compcode);
+
+ ret = res->compcode;
+ switch (res->compcode) {
+ case CPT_9X_COMP_E_INSTERR:
+ CPT_LOG_DP_ERR("Request failed with instruction error");
+ break;
+ case CPT_9X_COMP_E_FAULT:
+ CPT_LOG_DP_ERR("Request failed with DMA fault");
+ break;
+ case CPT_9X_COMP_E_HWERR:
+ CPT_LOG_DP_ERR("Request failed with hardware error");
+ break;
+ default:
+ CPT_LOG_DP_ERR("Request failed with unknown completion code");
+ }
+ }
+
+ return ret;
+}
+
+static uint16_t
+otx2_cpt_dequeue_burst(void *qptr, struct rte_crypto_op **ops, uint16_t nb_ops)
+{
+ int i, nb_pending, nb_completed;
+ struct otx2_cpt_qp *qp = qptr;
+ struct pending_queue *pend_q;
+ struct cpt_request_info *req;
+ struct rte_crypto_op *cop;
+ uint8_t cc[nb_ops];
+ struct rid *rid;
+ uintptr_t *rsp;
+ void *metabuf;
+
+ pend_q = &qp->pend_q;
+
+ nb_pending = pend_q->pending_count;
+
+ if (nb_ops > nb_pending)
+ nb_ops = nb_pending;
+
+ for (i = 0; i < nb_ops; i++) {
+ rid = &pend_q->rid_queue[pend_q->deq_head];
+ req = (struct cpt_request_info *)(rid->rid);
+
+ cc[i] = otx2_cpt_compcode_get(req);
+
+ if (unlikely(cc[i] == ERR_REQ_PENDING))
+ break;
+
+ ops[i] = req->op;
+
+ MOD_INC(pend_q->deq_head, OTX2_CPT_DEFAULT_CMD_QLEN);
+ pend_q->pending_count -= 1;
+ }
+
+ nb_completed = i;
+
+ for (i = 0; i < nb_completed; i++) {
+ rsp = (void *)ops[i];
+
+ metabuf = (void *)rsp[0];
+ cop = (void *)rsp[1];
+
+ ops[i] = cop;
+
+ otx2_cpt_dequeue_post_process(qp, cop, rsp, cc[i]);
+
+ free_op_meta(metabuf, qp->meta_info.pool);
+ }
+
+ return nb_completed;
+}
+
/* PMD ops */
static int
@@ -378,6 +664,9 @@ otx2_cpt_dev_config(struct rte_cryptodev *dev,
goto queues_detach;
}
+ dev->enqueue_burst = otx2_cpt_enqueue_burst;
+ dev->dequeue_burst = otx2_cpt_dequeue_burst;
+
rte_mb();
return 0;
--
2.7.4
^ permalink raw reply related [flat|nested] 53+ messages in thread* [dpdk-dev] [PATCH v3 08/11] test: add OCTEON TX2 tests
2019-10-16 15:25 ` [dpdk-dev] [PATCH v3 00/11] " Anoob Joseph
` (6 preceding siblings ...)
2019-10-16 15:25 ` [dpdk-dev] [PATCH v3 07/11] crypto/octeontx2: add enqueue/dequeue ops Anoob Joseph
@ 2019-10-16 15:25 ` Anoob Joseph
2019-10-16 15:25 ` [dpdk-dev] [PATCH v3 09/11] crypto/octeontx2: add asymmetric session operations Anoob Joseph
` (3 subsequent siblings)
11 siblings, 0 replies; 53+ messages in thread
From: Anoob Joseph @ 2019-10-16 15:25 UTC (permalink / raw)
To: Akhil Goyal, Pablo de Lara
Cc: Anoob Joseph, Fiona Trahe, Jerin Jacob, Narayana Prasad,
Shally Verma, Ankur Dwivedi, Kanaka Durga Kotamarthy, Sunila Sahu,
Tejasree Kondoj, dev
This patch adds the OCTEON TX2 crypto validation tests.
Signed-off-by: Ankur Dwivedi <adwivedi@marvell.com>
Signed-off-by: Anoob Joseph <anoobj@marvell.com>
Signed-off-by: Tejasree Kondoj <ktejasree@marvell.com>
---
app/test/meson.build | 1 +
app/test/test_cryptodev.c | 323 ++++++++++++++++++++++++++++
app/test/test_cryptodev.h | 1 +
app/test/test_cryptodev_aes_test_vectors.h | 114 ++++++----
app/test/test_cryptodev_blockcipher.c | 7 +
app/test/test_cryptodev_blockcipher.h | 1 +
app/test/test_cryptodev_des_test_vectors.h | 12 +-
app/test/test_cryptodev_hash_test_vectors.h | 75 ++++---
doc/guides/cryptodevs/octeontx2.rst | 11 +
9 files changed, 478 insertions(+), 67 deletions(-)
diff --git a/app/test/meson.build b/app/test/meson.build
index 2c23c63..a88b0eb 100644
--- a/app/test/meson.build
+++ b/app/test/meson.build
@@ -271,6 +271,7 @@ driver_test_names = [
'cryptodev_dpaa_sec_autotest',
'cryptodev_dpaa2_sec_autotest',
'cryptodev_null_autotest',
+ 'cryptodev_octeontx2_autotest',
'cryptodev_openssl_autotest',
'cryptodev_openssl_asym_autotest',
'cryptodev_qat_autotest',
diff --git a/app/test/test_cryptodev.c b/app/test/test_cryptodev.c
index a3ae2e2..65d8083 100644
--- a/app/test/test_cryptodev.c
+++ b/app/test/test_cryptodev.c
@@ -2404,6 +2404,101 @@ test_authonly_octeontx_all(void)
return TEST_SUCCESS;
}
+static int
+test_AES_chain_octeontx2_all(void)
+{
+ struct crypto_testsuite_params *ts_params = &testsuite_params;
+ int status;
+
+ status = test_blockcipher_all_tests(ts_params->mbuf_pool,
+ ts_params->op_mpool, ts_params->session_mpool,
+ ts_params->session_priv_mpool,
+ ts_params->valid_devs[0],
+ rte_cryptodev_driver_id_get(
+ RTE_STR(CRYPTODEV_NAME_OCTEONTX2_PMD)),
+ BLKCIPHER_AES_CHAIN_TYPE);
+
+ TEST_ASSERT_EQUAL(status, 0, "Test failed");
+
+ return TEST_SUCCESS;
+}
+
+static int
+test_AES_cipheronly_octeontx2_all(void)
+{
+ struct crypto_testsuite_params *ts_params = &testsuite_params;
+ int status;
+
+ status = test_blockcipher_all_tests(ts_params->mbuf_pool,
+ ts_params->op_mpool, ts_params->session_mpool,
+ ts_params->session_priv_mpool,
+ ts_params->valid_devs[0],
+ rte_cryptodev_driver_id_get(
+ RTE_STR(CRYPTODEV_NAME_OCTEONTX2_PMD)),
+ BLKCIPHER_AES_CIPHERONLY_TYPE);
+
+ TEST_ASSERT_EQUAL(status, 0, "Test failed");
+
+ return TEST_SUCCESS;
+}
+
+static int
+test_3DES_chain_octeontx2_all(void)
+{
+ struct crypto_testsuite_params *ts_params = &testsuite_params;
+ int status;
+
+ status = test_blockcipher_all_tests(ts_params->mbuf_pool,
+ ts_params->op_mpool, ts_params->session_mpool,
+ ts_params->session_priv_mpool,
+ ts_params->valid_devs[0],
+ rte_cryptodev_driver_id_get(
+ RTE_STR(CRYPTODEV_NAME_OCTEONTX2_PMD)),
+ BLKCIPHER_3DES_CHAIN_TYPE);
+
+ TEST_ASSERT_EQUAL(status, 0, "Test failed");
+
+ return TEST_SUCCESS;
+}
+
+static int
+test_3DES_cipheronly_octeontx2_all(void)
+{
+ struct crypto_testsuite_params *ts_params = &testsuite_params;
+ int status;
+
+ status = test_blockcipher_all_tests(ts_params->mbuf_pool,
+ ts_params->op_mpool, ts_params->session_mpool,
+ ts_params->session_priv_mpool,
+ ts_params->valid_devs[0],
+ rte_cryptodev_driver_id_get(
+ RTE_STR(CRYPTODEV_NAME_OCTEONTX2_PMD)),
+ BLKCIPHER_3DES_CIPHERONLY_TYPE);
+
+ TEST_ASSERT_EQUAL(status, 0, "Test failed");
+
+ return TEST_SUCCESS;
+}
+
+static int
+test_authonly_octeontx2_all(void)
+{
+ struct crypto_testsuite_params *ts_params = &testsuite_params;
+ int status;
+
+ status = test_blockcipher_all_tests(ts_params->mbuf_pool,
+ ts_params->op_mpool, ts_params->session_mpool,
+ ts_params->session_priv_mpool,
+ ts_params->valid_devs[0],
+ rte_cryptodev_driver_id_get(
+ RTE_STR(CRYPTODEV_NAME_OCTEONTX2_PMD)),
+ BLKCIPHER_AUTHONLY_TYPE);
+
+ TEST_ASSERT_EQUAL(status, 0, "Test failed");
+
+ return TEST_SUCCESS;
+}
+
/* ***** SNOW 3G Tests ***** */
static int
create_wireless_algo_hash_session(uint8_t dev_id,
@@ -13386,6 +13481,218 @@ static struct unit_test_suite cryptodev_nitrox_testsuite = {
}
};
+static struct unit_test_suite cryptodev_octeontx2_testsuite = {
+ .suite_name = "Crypto Device OCTEON TX2 Unit Test Suite",
+ .setup = testsuite_setup,
+ .teardown = testsuite_teardown,
+ .unit_test_cases = {
+ TEST_CASE_ST(ut_setup, ut_teardown,
+ test_AES_chain_octeontx2_all),
+ TEST_CASE_ST(ut_setup, ut_teardown,
+ test_AES_cipheronly_octeontx2_all),
+ TEST_CASE_ST(ut_setup, ut_teardown,
+ test_3DES_chain_octeontx2_all),
+ TEST_CASE_ST(ut_setup, ut_teardown,
+ test_3DES_cipheronly_octeontx2_all),
+ TEST_CASE_ST(ut_setup, ut_teardown,
+ test_authonly_octeontx2_all),
+
+ /** AES GCM Authenticated Encryption */
+ TEST_CASE_ST(ut_setup, ut_teardown,
+ test_AES_GCM_authenticated_encryption_test_case_1),
+ TEST_CASE_ST(ut_setup, ut_teardown,
+ test_AES_GCM_authenticated_encryption_test_case_2),
+ TEST_CASE_ST(ut_setup, ut_teardown,
+ test_AES_GCM_authenticated_encryption_test_case_3),
+ TEST_CASE_ST(ut_setup, ut_teardown,
+ test_AES_GCM_authenticated_encryption_test_case_4),
+ TEST_CASE_ST(ut_setup, ut_teardown,
+ test_AES_GCM_authenticated_encryption_test_case_5),
+ TEST_CASE_ST(ut_setup, ut_teardown,
+ test_AES_GCM_authenticated_encryption_test_case_6),
+ TEST_CASE_ST(ut_setup, ut_teardown,
+ test_AES_GCM_authenticated_encryption_test_case_7),
+
+ /** AES GCM Authenticated Decryption */
+ TEST_CASE_ST(ut_setup, ut_teardown,
+ test_AES_GCM_authenticated_decryption_test_case_1),
+ TEST_CASE_ST(ut_setup, ut_teardown,
+ test_AES_GCM_authenticated_decryption_test_case_2),
+ TEST_CASE_ST(ut_setup, ut_teardown,
+ test_AES_GCM_authenticated_decryption_test_case_3),
+ TEST_CASE_ST(ut_setup, ut_teardown,
+ test_AES_GCM_authenticated_decryption_test_case_4),
+ TEST_CASE_ST(ut_setup, ut_teardown,
+ test_AES_GCM_authenticated_decryption_test_case_5),
+ TEST_CASE_ST(ut_setup, ut_teardown,
+ test_AES_GCM_authenticated_decryption_test_case_6),
+ TEST_CASE_ST(ut_setup, ut_teardown,
+ test_AES_GCM_authenticated_decryption_test_case_7),
+ /** AES GMAC Authentication */
+ TEST_CASE_ST(ut_setup, ut_teardown,
+ test_AES_GMAC_authentication_test_case_1),
+ TEST_CASE_ST(ut_setup, ut_teardown,
+ test_AES_GMAC_authentication_verify_test_case_1),
+ TEST_CASE_ST(ut_setup, ut_teardown,
+ test_AES_GMAC_authentication_test_case_2),
+ TEST_CASE_ST(ut_setup, ut_teardown,
+ test_AES_GMAC_authentication_verify_test_case_2),
+ TEST_CASE_ST(ut_setup, ut_teardown,
+ test_AES_GMAC_authentication_test_case_3),
+ TEST_CASE_ST(ut_setup, ut_teardown,
+ test_AES_GMAC_authentication_verify_test_case_3),
+
+ /** SNOW 3G encrypt only (UEA2) */
+ TEST_CASE_ST(ut_setup, ut_teardown,
+ test_snow3g_encryption_test_case_1),
+ TEST_CASE_ST(ut_setup, ut_teardown,
+ test_snow3g_encryption_test_case_2),
+ TEST_CASE_ST(ut_setup, ut_teardown,
+ test_snow3g_encryption_test_case_3),
+ TEST_CASE_ST(ut_setup, ut_teardown,
+ test_snow3g_encryption_test_case_4),
+ TEST_CASE_ST(ut_setup, ut_teardown,
+ test_snow3g_encryption_test_case_5),
+
+ TEST_CASE_ST(ut_setup, ut_teardown,
+ test_snow3g_encryption_test_case_1_oop),
+ TEST_CASE_ST(ut_setup, ut_teardown,
+ test_snow3g_decryption_test_case_1_oop),
+ TEST_CASE_ST(ut_setup, ut_teardown,
+ test_snow3g_encryption_test_case_1_oop_sgl),
+
+ /** SNOW 3G decrypt only (UEA2) */
+ TEST_CASE_ST(ut_setup, ut_teardown,
+ test_snow3g_decryption_test_case_1),
+ TEST_CASE_ST(ut_setup, ut_teardown,
+ test_snow3g_decryption_test_case_2),
+ TEST_CASE_ST(ut_setup, ut_teardown,
+ test_snow3g_decryption_test_case_3),
+ TEST_CASE_ST(ut_setup, ut_teardown,
+ test_snow3g_decryption_test_case_4),
+ TEST_CASE_ST(ut_setup, ut_teardown,
+ test_snow3g_decryption_test_case_5),
+
+ TEST_CASE_ST(ut_setup, ut_teardown,
+ test_snow3g_hash_generate_test_case_1),
+ TEST_CASE_ST(ut_setup, ut_teardown,
+ test_snow3g_hash_generate_test_case_2),
+ TEST_CASE_ST(ut_setup, ut_teardown,
+ test_snow3g_hash_generate_test_case_3),
+ TEST_CASE_ST(ut_setup, ut_teardown,
+ test_snow3g_hash_verify_test_case_1),
+ TEST_CASE_ST(ut_setup, ut_teardown,
+ test_snow3g_hash_verify_test_case_2),
+ TEST_CASE_ST(ut_setup, ut_teardown,
+ test_snow3g_hash_verify_test_case_3),
+
+ /** ZUC encrypt only (EEA3) */
+ TEST_CASE_ST(ut_setup, ut_teardown,
+ test_zuc_encryption_test_case_1),
+ TEST_CASE_ST(ut_setup, ut_teardown,
+ test_zuc_encryption_test_case_2),
+ TEST_CASE_ST(ut_setup, ut_teardown,
+ test_zuc_encryption_test_case_3),
+ TEST_CASE_ST(ut_setup, ut_teardown,
+ test_zuc_encryption_test_case_4),
+ TEST_CASE_ST(ut_setup, ut_teardown,
+ test_zuc_encryption_test_case_5),
+ TEST_CASE_ST(ut_setup, ut_teardown,
+ test_zuc_hash_generate_test_case_1),
+ TEST_CASE_ST(ut_setup, ut_teardown,
+ test_zuc_hash_generate_test_case_2),
+ TEST_CASE_ST(ut_setup, ut_teardown,
+ test_zuc_hash_generate_test_case_3),
+ TEST_CASE_ST(ut_setup, ut_teardown,
+ test_zuc_hash_generate_test_case_4),
+ TEST_CASE_ST(ut_setup, ut_teardown,
+ test_zuc_hash_generate_test_case_5),
+ TEST_CASE_ST(ut_setup, ut_teardown,
+ test_zuc_encryption_test_case_6_sgl),
+
+ /** KASUMI encrypt only (UEA1) */
+ TEST_CASE_ST(ut_setup, ut_teardown,
+ test_kasumi_encryption_test_case_1),
+ TEST_CASE_ST(ut_setup, ut_teardown,
+ test_kasumi_encryption_test_case_2),
+ TEST_CASE_ST(ut_setup, ut_teardown,
+ test_kasumi_encryption_test_case_3),
+ TEST_CASE_ST(ut_setup, ut_teardown,
+ test_kasumi_encryption_test_case_4),
+ TEST_CASE_ST(ut_setup, ut_teardown,
+ test_kasumi_encryption_test_case_5),
+ TEST_CASE_ST(ut_setup, ut_teardown,
+ test_kasumi_encryption_test_case_1_sgl),
+ TEST_CASE_ST(ut_setup, ut_teardown,
+ test_kasumi_encryption_test_case_1_oop_sgl),
+ /** KASUMI decrypt only (UEA1) */
+ TEST_CASE_ST(ut_setup, ut_teardown,
+ test_kasumi_decryption_test_case_1),
+ TEST_CASE_ST(ut_setup, ut_teardown,
+ test_kasumi_decryption_test_case_2),
+ TEST_CASE_ST(ut_setup, ut_teardown,
+ test_kasumi_decryption_test_case_3),
+ TEST_CASE_ST(ut_setup, ut_teardown,
+ test_kasumi_decryption_test_case_4),
+ TEST_CASE_ST(ut_setup, ut_teardown,
+ test_kasumi_decryption_test_case_5),
+
+ TEST_CASE_ST(ut_setup, ut_teardown,
+ test_kasumi_encryption_test_case_1_oop),
+ TEST_CASE_ST(ut_setup, ut_teardown,
+ test_kasumi_decryption_test_case_1_oop),
+
+ /** KASUMI hash only (UIA1) */
+ TEST_CASE_ST(ut_setup, ut_teardown,
+ test_kasumi_hash_generate_test_case_1),
+ TEST_CASE_ST(ut_setup, ut_teardown,
+ test_kasumi_hash_generate_test_case_2),
+ TEST_CASE_ST(ut_setup, ut_teardown,
+ test_kasumi_hash_generate_test_case_3),
+ TEST_CASE_ST(ut_setup, ut_teardown,
+ test_kasumi_hash_generate_test_case_4),
+ TEST_CASE_ST(ut_setup, ut_teardown,
+ test_kasumi_hash_generate_test_case_5),
+ TEST_CASE_ST(ut_setup, ut_teardown,
+ test_kasumi_hash_generate_test_case_6),
+ TEST_CASE_ST(ut_setup, ut_teardown,
+ test_kasumi_hash_verify_test_case_1),
+ TEST_CASE_ST(ut_setup, ut_teardown,
+ test_kasumi_hash_verify_test_case_2),
+ TEST_CASE_ST(ut_setup, ut_teardown,
+ test_kasumi_hash_verify_test_case_3),
+ TEST_CASE_ST(ut_setup, ut_teardown,
+ test_kasumi_hash_verify_test_case_4),
+ TEST_CASE_ST(ut_setup, ut_teardown,
+ test_kasumi_hash_verify_test_case_5),
+
+ /** NULL tests */
+ TEST_CASE_ST(ut_setup, ut_teardown,
+ test_null_cipher_only_operation),
+ TEST_CASE_ST(ut_setup, ut_teardown,
+ test_null_auth_only_operation),
+ TEST_CASE_ST(ut_setup, ut_teardown,
+ test_null_cipher_auth_operation),
+ TEST_CASE_ST(ut_setup, ut_teardown,
+ test_null_auth_cipher_operation),
+
+ /** Negative tests */
+ TEST_CASE_ST(ut_setup, ut_teardown,
+ authentication_verify_HMAC_SHA1_fail_data_corrupt),
+ TEST_CASE_ST(ut_setup, ut_teardown,
+ authentication_verify_HMAC_SHA1_fail_tag_corrupt),
+ TEST_CASE_ST(ut_setup, ut_teardown,
+ authentication_verify_AES128_GMAC_fail_data_corrupt),
+ TEST_CASE_ST(ut_setup, ut_teardown,
+ authentication_verify_AES128_GMAC_fail_tag_corrupt),
+ TEST_CASE_ST(ut_setup, ut_teardown,
+ auth_decryption_AES128CBC_HMAC_SHA1_fail_data_corrupt),
+ TEST_CASE_ST(ut_setup, ut_teardown,
+ auth_decryption_AES128CBC_HMAC_SHA1_fail_tag_corrupt),
+ TEST_CASES_END() /**< NULL terminate unit test array */
+ }
+};
+
static int
test_cryptodev_qat(void /*argv __rte_unused, int argc __rte_unused*/)
{
@@ -13654,6 +13961,21 @@ test_cryptodev_octeontx(void)
}
static int
+test_cryptodev_octeontx2(void)
+{
+ gbl_driver_id = rte_cryptodev_driver_id_get(
+ RTE_STR(CRYPTODEV_NAME_OCTEONTX2_PMD));
+ if (gbl_driver_id == -1) {
+ RTE_LOG(ERR, USER1, "OCTEON TX2 PMD must be loaded. Check if "
+ "CONFIG_RTE_LIBRTE_PMD_OCTEONTX2_CRYPTO is "
+ "enabled in config file to run this "
+ "testsuite.\n");
+ return TEST_FAILED;
+ }
+ return unit_test_suite_runner(&cryptodev_octeontx2_testsuite);
+}
+
+static int
test_cryptodev_caam_jr(void /*argv __rte_unused, int argc __rte_unused*/)
{
gbl_driver_id = rte_cryptodev_driver_id_get(
@@ -13700,5 +14022,6 @@ REGISTER_TEST_COMMAND(cryptodev_dpaa_sec_autotest, test_cryptodev_dpaa_sec);
REGISTER_TEST_COMMAND(cryptodev_ccp_autotest, test_cryptodev_ccp);
REGISTER_TEST_COMMAND(cryptodev_virtio_autotest, test_cryptodev_virtio);
REGISTER_TEST_COMMAND(cryptodev_octeontx_autotest, test_cryptodev_octeontx);
+REGISTER_TEST_COMMAND(cryptodev_octeontx2_autotest, test_cryptodev_octeontx2);
REGISTER_TEST_COMMAND(cryptodev_caam_jr_autotest, test_cryptodev_caam_jr);
REGISTER_TEST_COMMAND(cryptodev_nitrox_autotest, test_cryptodev_nitrox);
diff --git a/app/test/test_cryptodev.h b/app/test/test_cryptodev.h
index d20586e..def304e 100644
--- a/app/test/test_cryptodev.h
+++ b/app/test/test_cryptodev.h
@@ -66,6 +66,7 @@
#define CRYPTODEV_NAME_CCP_PMD crypto_ccp
#define CRYPTODEV_NAME_VIRTIO_PMD crypto_virtio
#define CRYPTODEV_NAME_OCTEONTX_SYM_PMD crypto_octeontx
+#define CRYPTODEV_NAME_OCTEONTX2_PMD crypto_octeontx2
#define CRYPTODEV_NAME_CAAM_JR_PMD crypto_caam_jr
#define CRYPTODEV_NAME_NITROX_PMD crypto_nitrox_sym
diff --git a/app/test/test_cryptodev_aes_test_vectors.h b/app/test/test_cryptodev_aes_test_vectors.h
index 54a5d75..54a8082 100644
--- a/app/test/test_cryptodev_aes_test_vectors.h
+++ b/app/test/test_cryptodev_aes_test_vectors.h
@@ -1707,7 +1707,8 @@ static const struct blockcipher_test_case aes_chain_test_cases[] = {
BLOCKCIPHER_TEST_TARGET_PMD_MVSAM |
BLOCKCIPHER_TEST_TARGET_PMD_CCP |
BLOCKCIPHER_TEST_TARGET_PMD_OCTEONTX |
- BLOCKCIPHER_TEST_TARGET_PMD_NITROX
+ BLOCKCIPHER_TEST_TARGET_PMD_NITROX |
+ BLOCKCIPHER_TEST_TARGET_PMD_OCTEONTX2
},
{
.test_descr = "AES-128-CBC HMAC-SHA1 Encryption Digest "
@@ -1717,7 +1718,8 @@ static const struct blockcipher_test_case aes_chain_test_cases[] = {
.pmd_mask = BLOCKCIPHER_TEST_TARGET_PMD_ARMV8 |
BLOCKCIPHER_TEST_TARGET_PMD_MVSAM |
BLOCKCIPHER_TEST_TARGET_PMD_OCTEONTX |
- BLOCKCIPHER_TEST_TARGET_PMD_NITROX
+ BLOCKCIPHER_TEST_TARGET_PMD_NITROX |
+ BLOCKCIPHER_TEST_TARGET_PMD_OCTEONTX2
},
{
.test_descr = "AES-128-CBC HMAC-SHA1 Encryption Digest "
@@ -1734,7 +1736,8 @@ static const struct blockcipher_test_case aes_chain_test_cases[] = {
BLOCKCIPHER_TEST_TARGET_PMD_DPAA_SEC |
BLOCKCIPHER_TEST_TARGET_PMD_CAAM_JR |
BLOCKCIPHER_TEST_TARGET_PMD_OCTEONTX |
- BLOCKCIPHER_TEST_TARGET_PMD_NITROX
+ BLOCKCIPHER_TEST_TARGET_PMD_NITROX |
+ BLOCKCIPHER_TEST_TARGET_PMD_OCTEONTX2
},
{
.test_descr = "AES-128-CBC HMAC-SHA1 Decryption Digest "
@@ -1752,7 +1755,8 @@ static const struct blockcipher_test_case aes_chain_test_cases[] = {
BLOCKCIPHER_TEST_TARGET_PMD_MVSAM |
BLOCKCIPHER_TEST_TARGET_PMD_CCP |
BLOCKCIPHER_TEST_TARGET_PMD_OCTEONTX |
- BLOCKCIPHER_TEST_TARGET_PMD_NITROX
+ BLOCKCIPHER_TEST_TARGET_PMD_NITROX |
+ BLOCKCIPHER_TEST_TARGET_PMD_OCTEONTX2
},
{
.test_descr = "AES-128-CBC HMAC-SHA1 Decryption Digest "
@@ -1764,7 +1768,8 @@ static const struct blockcipher_test_case aes_chain_test_cases[] = {
BLOCKCIPHER_TEST_TARGET_PMD_DPAA_SEC |
BLOCKCIPHER_TEST_TARGET_PMD_CAAM_JR |
BLOCKCIPHER_TEST_TARGET_PMD_OCTEONTX |
- BLOCKCIPHER_TEST_TARGET_PMD_NITROX
+ BLOCKCIPHER_TEST_TARGET_PMD_NITROX |
+ BLOCKCIPHER_TEST_TARGET_PMD_OCTEONTX2
},
{
.test_descr = "AES-128-CBC HMAC-SHA1 Decryption Digest "
@@ -1774,7 +1779,8 @@ static const struct blockcipher_test_case aes_chain_test_cases[] = {
.pmd_mask = BLOCKCIPHER_TEST_TARGET_PMD_ARMV8 |
BLOCKCIPHER_TEST_TARGET_PMD_MVSAM |
BLOCKCIPHER_TEST_TARGET_PMD_OCTEONTX |
- BLOCKCIPHER_TEST_TARGET_PMD_NITROX
+ BLOCKCIPHER_TEST_TARGET_PMD_NITROX |
+ BLOCKCIPHER_TEST_TARGET_PMD_OCTEONTX2
},
{
.test_descr = "AES-128-CBC HMAC-SHA256 Encryption Digest",
@@ -1791,7 +1797,8 @@ static const struct blockcipher_test_case aes_chain_test_cases[] = {
BLOCKCIPHER_TEST_TARGET_PMD_MVSAM |
BLOCKCIPHER_TEST_TARGET_PMD_CCP |
BLOCKCIPHER_TEST_TARGET_PMD_OCTEONTX |
- BLOCKCIPHER_TEST_TARGET_PMD_NITROX
+ BLOCKCIPHER_TEST_TARGET_PMD_NITROX |
+ BLOCKCIPHER_TEST_TARGET_PMD_OCTEONTX2
},
{
.test_descr = "AES-128-CBC HMAC-SHA256 Encryption Digest "
@@ -1801,7 +1808,8 @@ static const struct blockcipher_test_case aes_chain_test_cases[] = {
.pmd_mask = BLOCKCIPHER_TEST_TARGET_PMD_ARMV8 |
BLOCKCIPHER_TEST_TARGET_PMD_MVSAM |
BLOCKCIPHER_TEST_TARGET_PMD_OCTEONTX |
- BLOCKCIPHER_TEST_TARGET_PMD_NITROX
+ BLOCKCIPHER_TEST_TARGET_PMD_NITROX |
+ BLOCKCIPHER_TEST_TARGET_PMD_OCTEONTX2
},
{
.test_descr = "AES-128-CBC HMAC-SHA256 Decryption Digest "
@@ -1818,7 +1826,8 @@ static const struct blockcipher_test_case aes_chain_test_cases[] = {
BLOCKCIPHER_TEST_TARGET_PMD_MVSAM |
BLOCKCIPHER_TEST_TARGET_PMD_CCP |
BLOCKCIPHER_TEST_TARGET_PMD_OCTEONTX |
- BLOCKCIPHER_TEST_TARGET_PMD_NITROX
+ BLOCKCIPHER_TEST_TARGET_PMD_NITROX |
+ BLOCKCIPHER_TEST_TARGET_PMD_OCTEONTX2
},
{
.test_descr = "AES-128-CBC HMAC-SHA256 Decryption Digest "
@@ -1828,7 +1837,8 @@ static const struct blockcipher_test_case aes_chain_test_cases[] = {
.pmd_mask = BLOCKCIPHER_TEST_TARGET_PMD_ARMV8 |
BLOCKCIPHER_TEST_TARGET_PMD_MVSAM |
BLOCKCIPHER_TEST_TARGET_PMD_OCTEONTX |
- BLOCKCIPHER_TEST_TARGET_PMD_NITROX
+ BLOCKCIPHER_TEST_TARGET_PMD_NITROX |
+ BLOCKCIPHER_TEST_TARGET_PMD_OCTEONTX2
},
{
.test_descr = "AES-128-CBC HMAC-SHA512 Encryption Digest",
@@ -1843,7 +1853,8 @@ static const struct blockcipher_test_case aes_chain_test_cases[] = {
BLOCKCIPHER_TEST_TARGET_PMD_CAAM_JR |
BLOCKCIPHER_TEST_TARGET_PMD_MVSAM |
BLOCKCIPHER_TEST_TARGET_PMD_CCP |
- BLOCKCIPHER_TEST_TARGET_PMD_OCTEONTX
+ BLOCKCIPHER_TEST_TARGET_PMD_OCTEONTX |
+ BLOCKCIPHER_TEST_TARGET_PMD_OCTEONTX2
},
{
.test_descr = "AES-128-CBC HMAC-SHA512 Encryption Digest "
@@ -1854,7 +1865,8 @@ static const struct blockcipher_test_case aes_chain_test_cases[] = {
.pmd_mask = BLOCKCIPHER_TEST_TARGET_PMD_MB |
BLOCKCIPHER_TEST_TARGET_PMD_OPENSSL |
BLOCKCIPHER_TEST_TARGET_PMD_CCP |
- BLOCKCIPHER_TEST_TARGET_PMD_OCTEONTX
+ BLOCKCIPHER_TEST_TARGET_PMD_OCTEONTX |
+ BLOCKCIPHER_TEST_TARGET_PMD_OCTEONTX2
},
{
.test_descr = "AES-128-CBC HMAC-SHA512 Encryption Digest "
@@ -1866,7 +1878,8 @@ static const struct blockcipher_test_case aes_chain_test_cases[] = {
BLOCKCIPHER_TEST_FEATURE_OOP,
.pmd_mask =
BLOCKCIPHER_TEST_TARGET_PMD_OPENSSL |
- BLOCKCIPHER_TEST_TARGET_PMD_OCTEONTX
+ BLOCKCIPHER_TEST_TARGET_PMD_OCTEONTX |
+ BLOCKCIPHER_TEST_TARGET_PMD_OCTEONTX2
},
{
.test_descr = "AES-128-CBC HMAC-SHA512 Decryption Digest "
@@ -1882,7 +1895,8 @@ static const struct blockcipher_test_case aes_chain_test_cases[] = {
BLOCKCIPHER_TEST_TARGET_PMD_CAAM_JR |
BLOCKCIPHER_TEST_TARGET_PMD_MVSAM |
BLOCKCIPHER_TEST_TARGET_PMD_CCP |
- BLOCKCIPHER_TEST_TARGET_PMD_OCTEONTX
+ BLOCKCIPHER_TEST_TARGET_PMD_OCTEONTX |
+ BLOCKCIPHER_TEST_TARGET_PMD_OCTEONTX2
},
{
.test_descr = "AES-128-CBC HMAC-SHA512 Decryption Digest "
@@ -1897,7 +1911,8 @@ static const struct blockcipher_test_case aes_chain_test_cases[] = {
BLOCKCIPHER_TEST_TARGET_PMD_DPAA2_SEC |
BLOCKCIPHER_TEST_TARGET_PMD_DPAA_SEC |
BLOCKCIPHER_TEST_TARGET_PMD_SCHEDULER |
- BLOCKCIPHER_TEST_TARGET_PMD_OCTEONTX
+ BLOCKCIPHER_TEST_TARGET_PMD_OCTEONTX |
+ BLOCKCIPHER_TEST_TARGET_PMD_OCTEONTX2
},
{
.test_descr = "AES-128-CBC XCBC Encryption Digest",
@@ -1929,7 +1944,8 @@ static const struct blockcipher_test_case aes_chain_test_cases[] = {
BLOCKCIPHER_TEST_TARGET_PMD_CAAM_JR |
BLOCKCIPHER_TEST_TARGET_PMD_MB |
BLOCKCIPHER_TEST_TARGET_PMD_OCTEONTX |
- BLOCKCIPHER_TEST_TARGET_PMD_NITROX
+ BLOCKCIPHER_TEST_TARGET_PMD_NITROX |
+ BLOCKCIPHER_TEST_TARGET_PMD_OCTEONTX2
},
{
.test_descr = "AES-128-CBC HMAC-SHA1 Encryption Digest "
@@ -1955,7 +1971,8 @@ static const struct blockcipher_test_case aes_chain_test_cases[] = {
BLOCKCIPHER_TEST_TARGET_PMD_CAAM_JR |
BLOCKCIPHER_TEST_TARGET_PMD_OCTEONTX |
BLOCKCIPHER_TEST_TARGET_PMD_MB |
- BLOCKCIPHER_TEST_TARGET_PMD_NITROX
+ BLOCKCIPHER_TEST_TARGET_PMD_NITROX |
+ BLOCKCIPHER_TEST_TARGET_PMD_OCTEONTX2
},
{
.test_descr = "AES-128-CBC HMAC-SHA224 Encryption Digest",
@@ -1970,7 +1987,8 @@ static const struct blockcipher_test_case aes_chain_test_cases[] = {
BLOCKCIPHER_TEST_TARGET_PMD_CAAM_JR |
BLOCKCIPHER_TEST_TARGET_PMD_CCP |
BLOCKCIPHER_TEST_TARGET_PMD_OCTEONTX |
- BLOCKCIPHER_TEST_TARGET_PMD_NITROX
+ BLOCKCIPHER_TEST_TARGET_PMD_NITROX |
+ BLOCKCIPHER_TEST_TARGET_PMD_OCTEONTX2
},
{
.test_descr = "AES-128-CBC HMAC-SHA224 Decryption Digest "
@@ -1986,7 +2004,8 @@ static const struct blockcipher_test_case aes_chain_test_cases[] = {
BLOCKCIPHER_TEST_TARGET_PMD_CAAM_JR |
BLOCKCIPHER_TEST_TARGET_PMD_CCP |
BLOCKCIPHER_TEST_TARGET_PMD_OCTEONTX |
- BLOCKCIPHER_TEST_TARGET_PMD_NITROX
+ BLOCKCIPHER_TEST_TARGET_PMD_NITROX |
+ BLOCKCIPHER_TEST_TARGET_PMD_OCTEONTX2
},
{
.test_descr = "AES-128-CBC HMAC-SHA384 Encryption Digest",
@@ -2026,7 +2045,8 @@ static const struct blockcipher_test_case aes_chain_test_cases[] = {
.pmd_mask = BLOCKCIPHER_TEST_TARGET_PMD_ARMV8 |
BLOCKCIPHER_TEST_TARGET_PMD_OPENSSL |
BLOCKCIPHER_TEST_TARGET_PMD_CCP |
- BLOCKCIPHER_TEST_TARGET_PMD_OCTEONTX
+ BLOCKCIPHER_TEST_TARGET_PMD_OCTEONTX |
+ BLOCKCIPHER_TEST_TARGET_PMD_OCTEONTX2
},
{
.test_descr =
@@ -2038,7 +2058,8 @@ static const struct blockcipher_test_case aes_chain_test_cases[] = {
.pmd_mask = BLOCKCIPHER_TEST_TARGET_PMD_ARMV8 |
BLOCKCIPHER_TEST_TARGET_PMD_OPENSSL |
BLOCKCIPHER_TEST_TARGET_PMD_CCP |
- BLOCKCIPHER_TEST_TARGET_PMD_OCTEONTX
+ BLOCKCIPHER_TEST_TARGET_PMD_OCTEONTX |
+ BLOCKCIPHER_TEST_TARGET_PMD_OCTEONTX2
},
{
.test_descr = "NULL-CIPHER-NULL-AUTH encrypt & gen x8byte",
@@ -2141,7 +2162,8 @@ static const struct blockcipher_test_case aes_cipheronly_test_cases[] = {
BLOCKCIPHER_TEST_TARGET_PMD_MVSAM |
BLOCKCIPHER_TEST_TARGET_PMD_CCP |
BLOCKCIPHER_TEST_TARGET_PMD_VIRTIO |
- BLOCKCIPHER_TEST_TARGET_PMD_OCTEONTX
+ BLOCKCIPHER_TEST_TARGET_PMD_OCTEONTX |
+ BLOCKCIPHER_TEST_TARGET_PMD_OCTEONTX2
},
{
.test_descr = "AES-128-CBC Decryption",
@@ -2157,7 +2179,8 @@ static const struct blockcipher_test_case aes_cipheronly_test_cases[] = {
BLOCKCIPHER_TEST_TARGET_PMD_MVSAM |
BLOCKCIPHER_TEST_TARGET_PMD_CCP |
BLOCKCIPHER_TEST_TARGET_PMD_VIRTIO |
- BLOCKCIPHER_TEST_TARGET_PMD_OCTEONTX
+ BLOCKCIPHER_TEST_TARGET_PMD_OCTEONTX |
+ BLOCKCIPHER_TEST_TARGET_PMD_OCTEONTX2
},
{
.test_descr = "AES-192-CBC Encryption",
@@ -2172,7 +2195,8 @@ static const struct blockcipher_test_case aes_cipheronly_test_cases[] = {
BLOCKCIPHER_TEST_TARGET_PMD_CAAM_JR |
BLOCKCIPHER_TEST_TARGET_PMD_CCP |
BLOCKCIPHER_TEST_TARGET_PMD_VIRTIO |
- BLOCKCIPHER_TEST_TARGET_PMD_OCTEONTX
+ BLOCKCIPHER_TEST_TARGET_PMD_OCTEONTX |
+ BLOCKCIPHER_TEST_TARGET_PMD_OCTEONTX2
},
{
.test_descr = "AES-192-CBC Encryption Scater gather",
@@ -2184,7 +2208,8 @@ static const struct blockcipher_test_case aes_cipheronly_test_cases[] = {
BLOCKCIPHER_TEST_TARGET_PMD_DPAA_SEC |
BLOCKCIPHER_TEST_TARGET_PMD_DPAA2_SEC |
BLOCKCIPHER_TEST_TARGET_PMD_CAAM_JR |
- BLOCKCIPHER_TEST_TARGET_PMD_OCTEONTX
+ BLOCKCIPHER_TEST_TARGET_PMD_OCTEONTX |
+ BLOCKCIPHER_TEST_TARGET_PMD_OCTEONTX2
},
{
.test_descr = "AES-192-CBC Decryption",
@@ -2199,7 +2224,8 @@ static const struct blockcipher_test_case aes_cipheronly_test_cases[] = {
BLOCKCIPHER_TEST_TARGET_PMD_CAAM_JR |
BLOCKCIPHER_TEST_TARGET_PMD_CCP |
BLOCKCIPHER_TEST_TARGET_PMD_VIRTIO |
- BLOCKCIPHER_TEST_TARGET_PMD_OCTEONTX
+ BLOCKCIPHER_TEST_TARGET_PMD_OCTEONTX |
+ BLOCKCIPHER_TEST_TARGET_PMD_OCTEONTX2
},
{
.test_descr = "AES-192-CBC Decryption Scatter Gather",
@@ -2209,7 +2235,8 @@ static const struct blockcipher_test_case aes_cipheronly_test_cases[] = {
.pmd_mask = BLOCKCIPHER_TEST_TARGET_PMD_DPAA2_SEC |
BLOCKCIPHER_TEST_TARGET_PMD_DPAA_SEC |
BLOCKCIPHER_TEST_TARGET_PMD_CAAM_JR |
- BLOCKCIPHER_TEST_TARGET_PMD_OCTEONTX
+ BLOCKCIPHER_TEST_TARGET_PMD_OCTEONTX |
+ BLOCKCIPHER_TEST_TARGET_PMD_OCTEONTX2
},
{
.test_descr = "AES-256-CBC Encryption",
@@ -2225,7 +2252,8 @@ static const struct blockcipher_test_case aes_cipheronly_test_cases[] = {
BLOCKCIPHER_TEST_TARGET_PMD_MVSAM |
BLOCKCIPHER_TEST_TARGET_PMD_CCP |
BLOCKCIPHER_TEST_TARGET_PMD_VIRTIO |
- BLOCKCIPHER_TEST_TARGET_PMD_OCTEONTX
+ BLOCKCIPHER_TEST_TARGET_PMD_OCTEONTX |
+ BLOCKCIPHER_TEST_TARGET_PMD_OCTEONTX2
},
{
.test_descr = "AES-256-CBC Decryption",
@@ -2241,7 +2269,8 @@ static const struct blockcipher_test_case aes_cipheronly_test_cases[] = {
BLOCKCIPHER_TEST_TARGET_PMD_MVSAM |
BLOCKCIPHER_TEST_TARGET_PMD_CCP |
BLOCKCIPHER_TEST_TARGET_PMD_VIRTIO |
- BLOCKCIPHER_TEST_TARGET_PMD_OCTEONTX
+ BLOCKCIPHER_TEST_TARGET_PMD_OCTEONTX |
+ BLOCKCIPHER_TEST_TARGET_PMD_OCTEONTX2
},
{
.test_descr = "AES-256-CBC OOP Encryption",
@@ -2284,7 +2313,8 @@ static const struct blockcipher_test_case aes_cipheronly_test_cases[] = {
BLOCKCIPHER_TEST_TARGET_PMD_CAAM_JR |
BLOCKCIPHER_TEST_TARGET_PMD_MVSAM |
BLOCKCIPHER_TEST_TARGET_PMD_CCP |
- BLOCKCIPHER_TEST_TARGET_PMD_OCTEONTX
+ BLOCKCIPHER_TEST_TARGET_PMD_OCTEONTX |
+ BLOCKCIPHER_TEST_TARGET_PMD_OCTEONTX2
},
{
.test_descr = "AES-128-CTR Decryption",
@@ -2299,7 +2329,8 @@ static const struct blockcipher_test_case aes_cipheronly_test_cases[] = {
BLOCKCIPHER_TEST_TARGET_PMD_CAAM_JR |
BLOCKCIPHER_TEST_TARGET_PMD_MVSAM |
BLOCKCIPHER_TEST_TARGET_PMD_CCP |
- BLOCKCIPHER_TEST_TARGET_PMD_OCTEONTX
+ BLOCKCIPHER_TEST_TARGET_PMD_OCTEONTX |
+ BLOCKCIPHER_TEST_TARGET_PMD_OCTEONTX2
},
{
.test_descr = "AES-192-CTR Encryption",
@@ -2313,7 +2344,8 @@ static const struct blockcipher_test_case aes_cipheronly_test_cases[] = {
BLOCKCIPHER_TEST_TARGET_PMD_DPAA_SEC |
BLOCKCIPHER_TEST_TARGET_PMD_CAAM_JR |
BLOCKCIPHER_TEST_TARGET_PMD_CCP |
- BLOCKCIPHER_TEST_TARGET_PMD_OCTEONTX
+ BLOCKCIPHER_TEST_TARGET_PMD_OCTEONTX |
+ BLOCKCIPHER_TEST_TARGET_PMD_OCTEONTX2
},
{
.test_descr = "AES-192-CTR Decryption",
@@ -2327,7 +2359,8 @@ static const struct blockcipher_test_case aes_cipheronly_test_cases[] = {
BLOCKCIPHER_TEST_TARGET_PMD_DPAA_SEC |
BLOCKCIPHER_TEST_TARGET_PMD_CAAM_JR |
BLOCKCIPHER_TEST_TARGET_PMD_CCP |
- BLOCKCIPHER_TEST_TARGET_PMD_OCTEONTX
+ BLOCKCIPHER_TEST_TARGET_PMD_OCTEONTX |
+ BLOCKCIPHER_TEST_TARGET_PMD_OCTEONTX2
},
{
.test_descr = "AES-256-CTR Encryption",
@@ -2342,7 +2375,8 @@ static const struct blockcipher_test_case aes_cipheronly_test_cases[] = {
BLOCKCIPHER_TEST_TARGET_PMD_CAAM_JR |
BLOCKCIPHER_TEST_TARGET_PMD_MVSAM |
BLOCKCIPHER_TEST_TARGET_PMD_CCP |
- BLOCKCIPHER_TEST_TARGET_PMD_OCTEONTX
+ BLOCKCIPHER_TEST_TARGET_PMD_OCTEONTX |
+ BLOCKCIPHER_TEST_TARGET_PMD_OCTEONTX2
},
{
.test_descr = "AES-256-CTR Decryption",
@@ -2357,28 +2391,32 @@ static const struct blockcipher_test_case aes_cipheronly_test_cases[] = {
BLOCKCIPHER_TEST_TARGET_PMD_CAAM_JR |
BLOCKCIPHER_TEST_TARGET_PMD_MVSAM |
BLOCKCIPHER_TEST_TARGET_PMD_CCP |
- BLOCKCIPHER_TEST_TARGET_PMD_OCTEONTX
+ BLOCKCIPHER_TEST_TARGET_PMD_OCTEONTX |
+ BLOCKCIPHER_TEST_TARGET_PMD_OCTEONTX2
},
{
.test_descr = "AES-128-CTR Encryption (12-byte IV)",
.test_data = &aes_test_data_1_IV_12_bytes,
.op_mask = BLOCKCIPHER_TEST_OP_ENCRYPT,
.pmd_mask = BLOCKCIPHER_TEST_TARGET_PMD_MB |
- BLOCKCIPHER_TEST_TARGET_PMD_OCTEONTX
+ BLOCKCIPHER_TEST_TARGET_PMD_OCTEONTX |
+ BLOCKCIPHER_TEST_TARGET_PMD_OCTEONTX2
},
{
.test_descr = "AES-192-CTR Encryption (12-byte IV)",
.test_data = &aes_test_data_2_IV_12_bytes,
.op_mask = BLOCKCIPHER_TEST_OP_ENCRYPT,
.pmd_mask = BLOCKCIPHER_TEST_TARGET_PMD_MB |
- BLOCKCIPHER_TEST_TARGET_PMD_OCTEONTX
+ BLOCKCIPHER_TEST_TARGET_PMD_OCTEONTX |
+ BLOCKCIPHER_TEST_TARGET_PMD_OCTEONTX2
},
{
.test_descr = "AES-256-CTR Encryption (12-byte IV)",
.test_data = &aes_test_data_3_IV_12_bytes,
.op_mask = BLOCKCIPHER_TEST_OP_ENCRYPT,
.pmd_mask = BLOCKCIPHER_TEST_TARGET_PMD_MB |
- BLOCKCIPHER_TEST_TARGET_PMD_OCTEONTX
+ BLOCKCIPHER_TEST_TARGET_PMD_OCTEONTX |
+ BLOCKCIPHER_TEST_TARGET_PMD_OCTEONTX2
},
{
.test_descr = "AES-128-XTS Encryption (16-byte plaintext)",
diff --git a/app/test/test_cryptodev_blockcipher.c b/app/test/test_cryptodev_blockcipher.c
index 885a20e..5bfe2d0 100644
--- a/app/test/test_cryptodev_blockcipher.c
+++ b/app/test/test_cryptodev_blockcipher.c
@@ -77,6 +77,8 @@ test_blockcipher_one_case(const struct blockcipher_test_case *t,
RTE_STR(CRYPTODEV_NAME_VIRTIO_PMD));
int octeontx_pmd = rte_cryptodev_driver_id_get(
RTE_STR(CRYPTODEV_NAME_OCTEONTX_SYM_PMD));
+ int octeontx2_pmd = rte_cryptodev_driver_id_get(
+ RTE_STR(CRYPTODEV_NAME_OCTEONTX2_PMD));
int null_pmd = rte_cryptodev_driver_id_get(
RTE_STR(CRYPTODEV_NAME_NULL_PMD));
int nitrox_pmd = rte_cryptodev_driver_id_get(
@@ -127,6 +129,7 @@ test_blockcipher_one_case(const struct blockcipher_test_case *t,
driver_id == ccp_pmd ||
driver_id == virtio_pmd ||
driver_id == octeontx_pmd ||
+ driver_id == octeontx2_pmd ||
driver_id == null_pmd ||
driver_id == nitrox_pmd) { /* Fall through */
digest_len = tdata->digest.len;
@@ -718,6 +721,8 @@ test_blockcipher_all_tests(struct rte_mempool *mbuf_pool,
RTE_STR(CRYPTODEV_NAME_VIRTIO_PMD));
int octeontx_pmd = rte_cryptodev_driver_id_get(
RTE_STR(CRYPTODEV_NAME_OCTEONTX_SYM_PMD));
+ int octeontx2_pmd = rte_cryptodev_driver_id_get(
+ RTE_STR(CRYPTODEV_NAME_OCTEONTX2_PMD));
int null_pmd = rte_cryptodev_driver_id_get(
RTE_STR(CRYPTODEV_NAME_NULL_PMD));
int nitrox_pmd = rte_cryptodev_driver_id_get(
@@ -792,6 +797,8 @@ test_blockcipher_all_tests(struct rte_mempool *mbuf_pool,
target_pmd_mask = BLOCKCIPHER_TEST_TARGET_PMD_VIRTIO;
else if (driver_id == octeontx_pmd)
target_pmd_mask = BLOCKCIPHER_TEST_TARGET_PMD_OCTEONTX;
+ else if (driver_id == octeontx2_pmd)
+ target_pmd_mask = BLOCKCIPHER_TEST_TARGET_PMD_OCTEONTX2;
else if (driver_id == null_pmd)
target_pmd_mask = BLOCKCIPHER_TEST_TARGET_PMD_NULL;
else if (driver_id == nitrox_pmd)
diff --git a/app/test/test_cryptodev_blockcipher.h b/app/test/test_cryptodev_blockcipher.h
index 1a65cda..204ba7b 100644
--- a/app/test/test_cryptodev_blockcipher.h
+++ b/app/test/test_cryptodev_blockcipher.h
@@ -33,6 +33,7 @@
#define BLOCKCIPHER_TEST_TARGET_PMD_CCP 0x0800 /* CCP flag */
#define BLOCKCIPHER_TEST_TARGET_PMD_NULL 0x1000 /* NULL flag */
#define BLOCKCIPHER_TEST_TARGET_PMD_NITROX 0x2000 /* NITROX flag */
+#define BLOCKCIPHER_TEST_TARGET_PMD_OCTEONTX2 0x4000 /* OCTEON TX2 flag */
#define BLOCKCIPHER_TEST_OP_CIPHER (BLOCKCIPHER_TEST_OP_ENCRYPT | \
BLOCKCIPHER_TEST_OP_DECRYPT)
diff --git a/app/test/test_cryptodev_des_test_vectors.h b/app/test/test_cryptodev_des_test_vectors.h
index a71b0e9..9d2d0e7 100644
--- a/app/test/test_cryptodev_des_test_vectors.h
+++ b/app/test/test_cryptodev_des_test_vectors.h
@@ -1114,7 +1114,8 @@ static const struct blockcipher_test_case triple_des_chain_test_cases[] = {
BLOCKCIPHER_TEST_TARGET_PMD_CAAM_JR |
BLOCKCIPHER_TEST_TARGET_PMD_MVSAM |
BLOCKCIPHER_TEST_TARGET_PMD_CCP |
- BLOCKCIPHER_TEST_TARGET_PMD_OCTEONTX
+ BLOCKCIPHER_TEST_TARGET_PMD_OCTEONTX |
+ BLOCKCIPHER_TEST_TARGET_PMD_OCTEONTX2
},
{
.test_descr = "3DES-192-CBC HMAC-SHA1 Decryption Digest Verify",
@@ -1127,7 +1128,8 @@ static const struct blockcipher_test_case triple_des_chain_test_cases[] = {
BLOCKCIPHER_TEST_TARGET_PMD_CAAM_JR |
BLOCKCIPHER_TEST_TARGET_PMD_MVSAM |
BLOCKCIPHER_TEST_TARGET_PMD_CCP |
- BLOCKCIPHER_TEST_TARGET_PMD_OCTEONTX
+ BLOCKCIPHER_TEST_TARGET_PMD_OCTEONTX |
+ BLOCKCIPHER_TEST_TARGET_PMD_OCTEONTX2
},
{
.test_descr = "3DES-192-CBC SHA1 Encryption Digest",
@@ -1296,7 +1298,8 @@ static const struct blockcipher_test_case triple_des_cipheronly_test_cases[] = {
BLOCKCIPHER_TEST_TARGET_PMD_MVSAM |
BLOCKCIPHER_TEST_TARGET_PMD_CCP |
BLOCKCIPHER_TEST_TARGET_PMD_MB |
- BLOCKCIPHER_TEST_TARGET_PMD_OCTEONTX
+ BLOCKCIPHER_TEST_TARGET_PMD_OCTEONTX |
+ BLOCKCIPHER_TEST_TARGET_PMD_OCTEONTX2
},
{
.test_descr = "3DES-192-CBC Decryption",
@@ -1310,7 +1313,8 @@ static const struct blockcipher_test_case triple_des_cipheronly_test_cases[] = {
BLOCKCIPHER_TEST_TARGET_PMD_MVSAM |
BLOCKCIPHER_TEST_TARGET_PMD_CCP |
BLOCKCIPHER_TEST_TARGET_PMD_MB |
- BLOCKCIPHER_TEST_TARGET_PMD_OCTEONTX
+ BLOCKCIPHER_TEST_TARGET_PMD_OCTEONTX |
+ BLOCKCIPHER_TEST_TARGET_PMD_OCTEONTX2
},
{
.test_descr = "3DES-128-CTR Encryption",
diff --git a/app/test/test_cryptodev_hash_test_vectors.h b/app/test/test_cryptodev_hash_test_vectors.h
index 6f201c0..cff2831 100644
--- a/app/test/test_cryptodev_hash_test_vectors.h
+++ b/app/test/test_cryptodev_hash_test_vectors.h
@@ -413,7 +413,8 @@ static const struct blockcipher_test_case hash_test_cases[] = {
.op_mask = BLOCKCIPHER_TEST_OP_AUTH_GEN,
.pmd_mask = BLOCKCIPHER_TEST_TARGET_PMD_OPENSSL |
BLOCKCIPHER_TEST_TARGET_PMD_MVSAM |
- BLOCKCIPHER_TEST_TARGET_PMD_OCTEONTX
+ BLOCKCIPHER_TEST_TARGET_PMD_OCTEONTX |
+ BLOCKCIPHER_TEST_TARGET_PMD_OCTEONTX2
},
{
.test_descr = "MD5 Digest Verify",
@@ -421,7 +422,8 @@ static const struct blockcipher_test_case hash_test_cases[] = {
.op_mask = BLOCKCIPHER_TEST_OP_AUTH_VERIFY,
.pmd_mask = BLOCKCIPHER_TEST_TARGET_PMD_OPENSSL |
BLOCKCIPHER_TEST_TARGET_PMD_MVSAM |
- BLOCKCIPHER_TEST_TARGET_PMD_OCTEONTX
+ BLOCKCIPHER_TEST_TARGET_PMD_OCTEONTX |
+ BLOCKCIPHER_TEST_TARGET_PMD_OCTEONTX2
},
{
.test_descr = "HMAC-MD5 Digest",
@@ -435,7 +437,8 @@ static const struct blockcipher_test_case hash_test_cases[] = {
BLOCKCIPHER_TEST_TARGET_PMD_CAAM_JR |
BLOCKCIPHER_TEST_TARGET_PMD_QAT |
BLOCKCIPHER_TEST_TARGET_PMD_MVSAM |
- BLOCKCIPHER_TEST_TARGET_PMD_OCTEONTX
+ BLOCKCIPHER_TEST_TARGET_PMD_OCTEONTX |
+ BLOCKCIPHER_TEST_TARGET_PMD_OCTEONTX2
},
{
.test_descr = "HMAC-MD5 Digest Verify",
@@ -449,7 +452,8 @@ static const struct blockcipher_test_case hash_test_cases[] = {
BLOCKCIPHER_TEST_TARGET_PMD_CAAM_JR |
BLOCKCIPHER_TEST_TARGET_PMD_QAT |
BLOCKCIPHER_TEST_TARGET_PMD_MVSAM |
- BLOCKCIPHER_TEST_TARGET_PMD_OCTEONTX
+ BLOCKCIPHER_TEST_TARGET_PMD_OCTEONTX |
+ BLOCKCIPHER_TEST_TARGET_PMD_OCTEONTX2
},
{
.test_descr = "SHA1 Digest",
@@ -461,7 +465,8 @@ static const struct blockcipher_test_case hash_test_cases[] = {
#if IMB_VERSION_NUM >= IMB_VERSION(0, 52, 0)
BLOCKCIPHER_TEST_TARGET_PMD_MB |
#endif
- BLOCKCIPHER_TEST_TARGET_PMD_OCTEONTX
+ BLOCKCIPHER_TEST_TARGET_PMD_OCTEONTX |
+ BLOCKCIPHER_TEST_TARGET_PMD_OCTEONTX2
},
{
.test_descr = "SHA1 Digest Verify",
@@ -473,7 +478,8 @@ static const struct blockcipher_test_case hash_test_cases[] = {
#if IMB_VERSION_NUM >= IMB_VERSION(0, 52, 0)
BLOCKCIPHER_TEST_TARGET_PMD_MB |
#endif
- BLOCKCIPHER_TEST_TARGET_PMD_OCTEONTX
+ BLOCKCIPHER_TEST_TARGET_PMD_OCTEONTX |
+ BLOCKCIPHER_TEST_TARGET_PMD_OCTEONTX2
},
{
.test_descr = "HMAC-SHA1 Digest",
@@ -488,7 +494,8 @@ static const struct blockcipher_test_case hash_test_cases[] = {
BLOCKCIPHER_TEST_TARGET_PMD_QAT |
BLOCKCIPHER_TEST_TARGET_PMD_CCP |
BLOCKCIPHER_TEST_TARGET_PMD_MVSAM |
- BLOCKCIPHER_TEST_TARGET_PMD_OCTEONTX
+ BLOCKCIPHER_TEST_TARGET_PMD_OCTEONTX |
+ BLOCKCIPHER_TEST_TARGET_PMD_OCTEONTX2
},
{
.test_descr = "HMAC-SHA1 Digest Scatter Gather",
@@ -498,7 +505,8 @@ static const struct blockcipher_test_case hash_test_cases[] = {
.pmd_mask = BLOCKCIPHER_TEST_TARGET_PMD_DPAA2_SEC |
BLOCKCIPHER_TEST_TARGET_PMD_DPAA_SEC |
BLOCKCIPHER_TEST_TARGET_PMD_CAAM_JR |
- BLOCKCIPHER_TEST_TARGET_PMD_OCTEONTX
+ BLOCKCIPHER_TEST_TARGET_PMD_OCTEONTX |
+ BLOCKCIPHER_TEST_TARGET_PMD_OCTEONTX2
},
{
.test_descr = "HMAC-SHA1 Digest Verify",
@@ -513,7 +521,8 @@ static const struct blockcipher_test_case hash_test_cases[] = {
BLOCKCIPHER_TEST_TARGET_PMD_QAT |
BLOCKCIPHER_TEST_TARGET_PMD_CCP |
BLOCKCIPHER_TEST_TARGET_PMD_MVSAM |
- BLOCKCIPHER_TEST_TARGET_PMD_OCTEONTX
+ BLOCKCIPHER_TEST_TARGET_PMD_OCTEONTX |
+ BLOCKCIPHER_TEST_TARGET_PMD_OCTEONTX2
},
{
.test_descr = "HMAC-SHA1 Digest Verify Scatter Gather",
@@ -523,7 +532,8 @@ static const struct blockcipher_test_case hash_test_cases[] = {
.pmd_mask = BLOCKCIPHER_TEST_TARGET_PMD_DPAA2_SEC |
BLOCKCIPHER_TEST_TARGET_PMD_DPAA_SEC |
BLOCKCIPHER_TEST_TARGET_PMD_CAAM_JR |
- BLOCKCIPHER_TEST_TARGET_PMD_OCTEONTX
+ BLOCKCIPHER_TEST_TARGET_PMD_OCTEONTX |
+ BLOCKCIPHER_TEST_TARGET_PMD_OCTEONTX2
},
{
.test_descr = "SHA224 Digest",
@@ -535,7 +545,8 @@ static const struct blockcipher_test_case hash_test_cases[] = {
#if IMB_VERSION_NUM >= IMB_VERSION(0, 52, 0)
BLOCKCIPHER_TEST_TARGET_PMD_MB |
#endif
- BLOCKCIPHER_TEST_TARGET_PMD_OCTEONTX
+ BLOCKCIPHER_TEST_TARGET_PMD_OCTEONTX |
+ BLOCKCIPHER_TEST_TARGET_PMD_OCTEONTX2
},
{
.test_descr = "SHA224 Digest Verify",
@@ -547,7 +558,8 @@ static const struct blockcipher_test_case hash_test_cases[] = {
#if IMB_VERSION_NUM >= IMB_VERSION(0, 52, 0)
BLOCKCIPHER_TEST_TARGET_PMD_MB |
#endif
- BLOCKCIPHER_TEST_TARGET_PMD_OCTEONTX
+ BLOCKCIPHER_TEST_TARGET_PMD_OCTEONTX |
+ BLOCKCIPHER_TEST_TARGET_PMD_OCTEONTX2
},
{
.test_descr = "HMAC-SHA224 Digest",
@@ -561,7 +573,8 @@ static const struct blockcipher_test_case hash_test_cases[] = {
BLOCKCIPHER_TEST_TARGET_PMD_CAAM_JR |
BLOCKCIPHER_TEST_TARGET_PMD_CCP |
BLOCKCIPHER_TEST_TARGET_PMD_QAT |
- BLOCKCIPHER_TEST_TARGET_PMD_OCTEONTX
+ BLOCKCIPHER_TEST_TARGET_PMD_OCTEONTX |
+ BLOCKCIPHER_TEST_TARGET_PMD_OCTEONTX2
},
{
.test_descr = "HMAC-SHA224 Digest Verify",
@@ -575,7 +588,8 @@ static const struct blockcipher_test_case hash_test_cases[] = {
BLOCKCIPHER_TEST_TARGET_PMD_CAAM_JR |
BLOCKCIPHER_TEST_TARGET_PMD_CCP |
BLOCKCIPHER_TEST_TARGET_PMD_QAT |
- BLOCKCIPHER_TEST_TARGET_PMD_OCTEONTX
+ BLOCKCIPHER_TEST_TARGET_PMD_OCTEONTX |
+ BLOCKCIPHER_TEST_TARGET_PMD_OCTEONTX2
},
{
.test_descr = "SHA256 Digest",
@@ -587,7 +601,8 @@ static const struct blockcipher_test_case hash_test_cases[] = {
#if IMB_VERSION_NUM >= IMB_VERSION(0, 52, 0)
BLOCKCIPHER_TEST_TARGET_PMD_MB |
#endif
- BLOCKCIPHER_TEST_TARGET_PMD_OCTEONTX
+ BLOCKCIPHER_TEST_TARGET_PMD_OCTEONTX |
+ BLOCKCIPHER_TEST_TARGET_PMD_OCTEONTX2
},
{
.test_descr = "SHA256 Digest Verify",
@@ -599,7 +614,8 @@ static const struct blockcipher_test_case hash_test_cases[] = {
#if IMB_VERSION_NUM >= IMB_VERSION(0, 52, 0)
BLOCKCIPHER_TEST_TARGET_PMD_MB |
#endif
- BLOCKCIPHER_TEST_TARGET_PMD_OCTEONTX
+ BLOCKCIPHER_TEST_TARGET_PMD_OCTEONTX |
+ BLOCKCIPHER_TEST_TARGET_PMD_OCTEONTX2
},
{
.test_descr = "HMAC-SHA256 Digest",
@@ -614,7 +630,8 @@ static const struct blockcipher_test_case hash_test_cases[] = {
BLOCKCIPHER_TEST_TARGET_PMD_QAT |
BLOCKCIPHER_TEST_TARGET_PMD_CCP |
BLOCKCIPHER_TEST_TARGET_PMD_MVSAM |
- BLOCKCIPHER_TEST_TARGET_PMD_OCTEONTX
+ BLOCKCIPHER_TEST_TARGET_PMD_OCTEONTX |
+ BLOCKCIPHER_TEST_TARGET_PMD_OCTEONTX2
},
{
.test_descr = "HMAC-SHA256 Digest Verify",
@@ -629,7 +646,8 @@ static const struct blockcipher_test_case hash_test_cases[] = {
BLOCKCIPHER_TEST_TARGET_PMD_QAT |
BLOCKCIPHER_TEST_TARGET_PMD_CCP |
BLOCKCIPHER_TEST_TARGET_PMD_MVSAM |
- BLOCKCIPHER_TEST_TARGET_PMD_OCTEONTX
+ BLOCKCIPHER_TEST_TARGET_PMD_OCTEONTX |
+ BLOCKCIPHER_TEST_TARGET_PMD_OCTEONTX2
},
{
.test_descr = "SHA384 Digest",
@@ -641,7 +659,8 @@ static const struct blockcipher_test_case hash_test_cases[] = {
#if IMB_VERSION_NUM >= IMB_VERSION(0, 52, 0)
BLOCKCIPHER_TEST_TARGET_PMD_MB |
#endif
- BLOCKCIPHER_TEST_TARGET_PMD_OCTEONTX
+ BLOCKCIPHER_TEST_TARGET_PMD_OCTEONTX |
+ BLOCKCIPHER_TEST_TARGET_PMD_OCTEONTX2
},
{
.test_descr = "SHA384 Digest Verify",
@@ -653,7 +672,8 @@ static const struct blockcipher_test_case hash_test_cases[] = {
#if IMB_VERSION_NUM >= IMB_VERSION(0, 52, 0)
BLOCKCIPHER_TEST_TARGET_PMD_MB |
#endif
- BLOCKCIPHER_TEST_TARGET_PMD_OCTEONTX
+ BLOCKCIPHER_TEST_TARGET_PMD_OCTEONTX |
+ BLOCKCIPHER_TEST_TARGET_PMD_OCTEONTX2
},
{
.test_descr = "HMAC-SHA384 Digest",
@@ -668,7 +688,8 @@ static const struct blockcipher_test_case hash_test_cases[] = {
BLOCKCIPHER_TEST_TARGET_PMD_QAT |
BLOCKCIPHER_TEST_TARGET_PMD_CCP |
BLOCKCIPHER_TEST_TARGET_PMD_MVSAM |
- BLOCKCIPHER_TEST_TARGET_PMD_OCTEONTX
+ BLOCKCIPHER_TEST_TARGET_PMD_OCTEONTX |
+ BLOCKCIPHER_TEST_TARGET_PMD_OCTEONTX2
},
{
.test_descr = "HMAC-SHA384 Digest Verify",
@@ -683,7 +704,8 @@ static const struct blockcipher_test_case hash_test_cases[] = {
BLOCKCIPHER_TEST_TARGET_PMD_QAT |
BLOCKCIPHER_TEST_TARGET_PMD_CCP |
BLOCKCIPHER_TEST_TARGET_PMD_MVSAM |
- BLOCKCIPHER_TEST_TARGET_PMD_OCTEONTX
+ BLOCKCIPHER_TEST_TARGET_PMD_OCTEONTX |
+ BLOCKCIPHER_TEST_TARGET_PMD_OCTEONTX2
},
{
.test_descr = "SHA512 Digest",
@@ -707,7 +729,8 @@ static const struct blockcipher_test_case hash_test_cases[] = {
#if IMB_VERSION_NUM >= IMB_VERSION(0, 52, 0)
BLOCKCIPHER_TEST_TARGET_PMD_MB |
#endif
- BLOCKCIPHER_TEST_TARGET_PMD_OCTEONTX
+ BLOCKCIPHER_TEST_TARGET_PMD_OCTEONTX |
+ BLOCKCIPHER_TEST_TARGET_PMD_OCTEONTX2
},
{
.test_descr = "HMAC-SHA512 Digest",
@@ -722,7 +745,8 @@ static const struct blockcipher_test_case hash_test_cases[] = {
BLOCKCIPHER_TEST_TARGET_PMD_QAT |
BLOCKCIPHER_TEST_TARGET_PMD_CCP |
BLOCKCIPHER_TEST_TARGET_PMD_MVSAM |
- BLOCKCIPHER_TEST_TARGET_PMD_OCTEONTX
+ BLOCKCIPHER_TEST_TARGET_PMD_OCTEONTX |
+ BLOCKCIPHER_TEST_TARGET_PMD_OCTEONTX2
},
{
.test_descr = "HMAC-SHA512 Digest Verify",
@@ -737,7 +761,8 @@ static const struct blockcipher_test_case hash_test_cases[] = {
BLOCKCIPHER_TEST_TARGET_PMD_QAT |
BLOCKCIPHER_TEST_TARGET_PMD_CCP |
BLOCKCIPHER_TEST_TARGET_PMD_MVSAM |
- BLOCKCIPHER_TEST_TARGET_PMD_OCTEONTX
+ BLOCKCIPHER_TEST_TARGET_PMD_OCTEONTX |
+ BLOCKCIPHER_TEST_TARGET_PMD_OCTEONTX2
},
{
.test_descr = "CMAC Digest 12B",
diff --git a/doc/guides/cryptodevs/octeontx2.rst b/doc/guides/cryptodevs/octeontx2.rst
index 47e9150..406d746 100644
--- a/doc/guides/cryptodevs/octeontx2.rst
+++ b/doc/guides/cryptodevs/octeontx2.rst
@@ -132,3 +132,14 @@ Debugging Options
+===+============+=======================================================+
| 1 | CPT | --log-level='pmd\.crypto\.octeontx2,8' |
+---+------------+-------------------------------------------------------+
+
+Testing
+-------
+
+The symmetric crypto operations on OCTEON TX2 crypto PMD may be verified by running the test
+application:
+
+.. code-block:: console
+
+ ./test
+ RTE>>cryptodev_octeontx2_autotest
--
2.7.4
^ permalink raw reply related [flat|nested] 53+ messages in thread* [dpdk-dev] [PATCH v3 09/11] crypto/octeontx2: add asymmetric session operations
2019-10-16 15:25 ` [dpdk-dev] [PATCH v3 00/11] " Anoob Joseph
` (7 preceding siblings ...)
2019-10-16 15:25 ` [dpdk-dev] [PATCH v3 08/11] test: add OCTEON TX2 tests Anoob Joseph
@ 2019-10-16 15:25 ` Anoob Joseph
2019-10-16 15:25 ` [dpdk-dev] [PATCH v3 10/11] crypto/octeontx2: add asymmetric in enqueue/dequeue ops Anoob Joseph
` (2 subsequent siblings)
11 siblings, 0 replies; 53+ messages in thread
From: Anoob Joseph @ 2019-10-16 15:25 UTC (permalink / raw)
To: Akhil Goyal, Pablo de Lara
Cc: Kanaka Durga Kotamarthy, Fiona Trahe, Jerin Jacob,
Narayana Prasad, Shally Verma, Ankur Dwivedi, Sunila Sahu,
Tejasree Kondoj, dev, Anoob Joseph
From: Kanaka Durga Kotamarthy <kkotamarthy@marvell.com>
This patch adds asymmetric session setup and free routines. RSA and
modexp operations are supported.
Signed-off-by: Anoob Joseph <anoobj@marvell.com>
Signed-off-by: Kanaka Durga Kotamarthy <kkotamarthy@marvell.com>
Signed-off-by: Sunila Sahu <ssahu@marvell.com>
---
doc/guides/cryptodevs/features/octeontx2.ini | 4 +
doc/guides/cryptodevs/octeontx2.rst | 6 ++
drivers/crypto/octeontx2/otx2_cryptodev.c | 4 +-
.../crypto/octeontx2/otx2_cryptodev_capabilities.c | 39 +++++++-
drivers/crypto/octeontx2/otx2_cryptodev_ops.c | 104 ++++++++++++++++++---
5 files changed, 143 insertions(+), 14 deletions(-)
diff --git a/doc/guides/cryptodevs/features/octeontx2.ini b/doc/guides/cryptodevs/features/octeontx2.ini
index 4e82463..7d07053 100644
--- a/doc/guides/cryptodevs/features/octeontx2.ini
+++ b/doc/guides/cryptodevs/features/octeontx2.ini
@@ -5,11 +5,13 @@
;
[Features]
Symmetric crypto = Y
+Asymmetric crypto = Y
Sym operation chaining = Y
HW Accelerated = Y
In Place SGL = Y
OOP SGL In LB Out = Y
OOP SGL In SGL Out = Y
+RSA PRIV OP KEY QT = Y
;
; Supported crypto algorithms of 'octeontx2' crypto driver.
@@ -65,3 +67,5 @@ AES GCM (256) = Y
; Supported Asymmetric algorithms of the 'octeontx2' crypto driver.
;
[Asymmetric]
+RSA = Y
+Modular Exponentiation = Y
diff --git a/doc/guides/cryptodevs/octeontx2.rst b/doc/guides/cryptodevs/octeontx2.rst
index 406d746..ad33c66 100644
--- a/doc/guides/cryptodevs/octeontx2.rst
+++ b/doc/guides/cryptodevs/octeontx2.rst
@@ -56,6 +56,12 @@ AEAD algorithms:
* ``RTE_CRYPTO_AEAD_AES_GCM``
+Asymmetric Crypto Algorithms
+~~~~~~~~~~~~~~~~~~~~~~~~~~~~
+
+* ``RTE_CRYPTO_ASYM_XFORM_RSA``
+* ``RTE_CRYPTO_ASYM_XFORM_MODEX``
+
Installation
------------
diff --git a/drivers/crypto/octeontx2/otx2_cryptodev.c b/drivers/crypto/octeontx2/otx2_cryptodev.c
index 32c0b48..7fd216b 100644
--- a/drivers/crypto/octeontx2/otx2_cryptodev.c
+++ b/drivers/crypto/octeontx2/otx2_cryptodev.c
@@ -99,7 +99,9 @@ otx2_cpt_pci_probe(struct rte_pci_driver *pci_drv __rte_unused,
RTE_CRYPTODEV_FF_SYM_OPERATION_CHAINING |
RTE_CRYPTODEV_FF_IN_PLACE_SGL |
RTE_CRYPTODEV_FF_OOP_SGL_IN_LB_OUT |
- RTE_CRYPTODEV_FF_OOP_SGL_IN_SGL_OUT;
+ RTE_CRYPTODEV_FF_OOP_SGL_IN_SGL_OUT |
+ RTE_CRYPTODEV_FF_ASYMMETRIC_CRYPTO |
+ RTE_CRYPTODEV_FF_RSA_PRIV_OP_KEY_QT;
return 0;
diff --git a/drivers/crypto/octeontx2/otx2_cryptodev_capabilities.c b/drivers/crypto/octeontx2/otx2_cryptodev_capabilities.c
index 3a70470..b9e3fe3 100644
--- a/drivers/crypto/octeontx2/otx2_cryptodev_capabilities.c
+++ b/drivers/crypto/octeontx2/otx2_cryptodev_capabilities.c
@@ -6,7 +6,8 @@
#include "otx2_cryptodev_capabilities.h"
-static const struct rte_cryptodev_capabilities otx2_cpt_sym_capabilities[] = {
+static const struct
+rte_cryptodev_capabilities otx2_cpt_capabilities[] = {
/* Symmetric capabilities */
{ /* NULL (AUTH) */
.op = RTE_CRYPTO_OP_TYPE_SYMMETRIC,
@@ -594,11 +595,45 @@ static const struct rte_cryptodev_capabilities otx2_cpt_sym_capabilities[] = {
}, }
},
/* End of symmetric capabilities */
+
+ /* Asymmetric capabilities */
+ { /* RSA */
+ .op = RTE_CRYPTO_OP_TYPE_ASYMMETRIC,
+ {.asym = {
+ .xform_capa = {
+ .xform_type = RTE_CRYPTO_ASYM_XFORM_RSA,
+ .op_types = ((1 << RTE_CRYPTO_ASYM_OP_SIGN) |
+ (1 << RTE_CRYPTO_ASYM_OP_VERIFY) |
+ (1 << RTE_CRYPTO_ASYM_OP_ENCRYPT) |
+ (1 << RTE_CRYPTO_ASYM_OP_DECRYPT)),
+ {.modlen = {
+ .min = 17,
+ .max = 1024,
+ .increment = 1
+ }, }
+ }
+ }, }
+ },
+ { /* MOD_EXP */
+ .op = RTE_CRYPTO_OP_TYPE_ASYMMETRIC,
+ {.asym = {
+ .xform_capa = {
+ .xform_type = RTE_CRYPTO_ASYM_XFORM_MODEX,
+ .op_types = 0,
+ {.modlen = {
+ .min = 17,
+ .max = 1024,
+ .increment = 1
+ }, }
+ }
+ }, }
+ },
+ /* End of asymmetric capabilities */
RTE_CRYPTODEV_END_OF_CAPABILITIES_LIST()
};
const struct rte_cryptodev_capabilities *
otx2_cpt_capabilities_get(void)
{
- return otx2_cpt_sym_capabilities;
+ return otx2_cpt_capabilities;
}
diff --git a/drivers/crypto/octeontx2/otx2_cryptodev_ops.c b/drivers/crypto/octeontx2/otx2_cryptodev_ops.c
index 818f0d9..f8d203e 100644
--- a/drivers/crypto/octeontx2/otx2_cryptodev_ops.c
+++ b/drivers/crypto/octeontx2/otx2_cryptodev_ops.c
@@ -18,6 +18,7 @@
#include "cpt_pmd_logs.h"
#include "cpt_pmd_ops_helper.h"
#include "cpt_ucode.h"
+#include "cpt_ucode_asym.h"
#define METABUF_POOL_CACHE_SIZE 512
@@ -38,24 +39,39 @@ otx2_cpt_metabuf_mempool_create(const struct rte_cryptodev *dev,
int nb_elements)
{
char mempool_name[RTE_MEMPOOL_NAMESIZE];
- int sg_mlen, lb_mlen, max_mlen, ret;
struct cpt_qp_meta_info *meta_info;
struct rte_mempool *pool;
+ int ret, max_mlen;
+ int asym_mlen = 0;
+ int lb_mlen = 0;
+ int sg_mlen = 0;
- /* Get meta len for scatter gather mode */
- sg_mlen = cpt_pmd_ops_helper_get_mlen_sg_mode();
+ if (dev->feature_flags & RTE_CRYPTODEV_FF_SYMMETRIC_CRYPTO) {
- /* Extra 32B saved for future considerations */
- sg_mlen += 4 * sizeof(uint64_t);
+ /* Get meta len for scatter gather mode */
+ sg_mlen = cpt_pmd_ops_helper_get_mlen_sg_mode();
- /* Get meta len for linear buffer (direct) mode */
- lb_mlen = cpt_pmd_ops_helper_get_mlen_direct_mode();
+ /* Extra 32B saved for future considerations */
+ sg_mlen += 4 * sizeof(uint64_t);
- /* Extra 32B saved for future considerations */
- lb_mlen += 4 * sizeof(uint64_t);
+ /* Get meta len for linear buffer (direct) mode */
+ lb_mlen = cpt_pmd_ops_helper_get_mlen_direct_mode();
- /* Check max requirement for meta buffer */
- max_mlen = RTE_MAX(lb_mlen, sg_mlen);
+ /* Extra 32B saved for future considerations */
+ lb_mlen += 4 * sizeof(uint64_t);
+ }
+
+ if (dev->feature_flags & RTE_CRYPTODEV_FF_ASYMMETRIC_CRYPTO) {
+
+ /* Get meta len required for asymmetric operations */
+ asym_mlen = cpt_pmd_ops_helper_asym_get_mlen();
+ }
+
+ /*
+ * Check max requirement for meta buffer to
+ * support crypto op of any type (sym/asym).
+ */
+ max_mlen = RTE_MAX(RTE_MAX(lb_mlen, sg_mlen), asym_mlen);
/* Allocate mempool */
@@ -826,6 +842,66 @@ otx2_cpt_sym_session_clear(struct rte_cryptodev *dev,
return sym_session_clear(dev->driver_id, sess);
}
+static unsigned int
+otx2_cpt_asym_session_size_get(struct rte_cryptodev *dev __rte_unused)
+{
+ return sizeof(struct cpt_asym_sess_misc);
+}
+
+static int
+otx2_cpt_asym_session_cfg(struct rte_cryptodev *dev,
+ struct rte_crypto_asym_xform *xform,
+ struct rte_cryptodev_asym_session *sess,
+ struct rte_mempool *pool)
+{
+ struct cpt_asym_sess_misc *priv;
+ int ret;
+
+ CPT_PMD_INIT_FUNC_TRACE();
+
+ if (rte_mempool_get(pool, (void **)&priv)) {
+ CPT_LOG_ERR("Could not allocate session_private_data");
+ return -ENOMEM;
+ }
+
+ memset(priv, 0, sizeof(struct cpt_asym_sess_misc));
+
+ ret = cpt_fill_asym_session_parameters(priv, xform);
+ if (ret) {
+ CPT_LOG_ERR("Could not configure session parameters");
+
+ /* Return session to mempool */
+ rte_mempool_put(pool, priv);
+ return ret;
+ }
+
+ set_asym_session_private_data(sess, dev->driver_id, priv);
+ return 0;
+}
+
+static void
+otx2_cpt_asym_session_clear(struct rte_cryptodev *dev,
+ struct rte_cryptodev_asym_session *sess)
+{
+ struct cpt_asym_sess_misc *priv;
+ struct rte_mempool *sess_mp;
+
+ CPT_PMD_INIT_FUNC_TRACE();
+
+ priv = get_asym_session_private_data(sess, dev->driver_id);
+ if (priv == NULL)
+ return;
+
+ /* Free resources allocated in session_cfg */
+ cpt_free_asym_session_parameters(priv);
+
+ /* Reset and free object back to pool */
+ memset(priv, 0, otx2_cpt_asym_session_size_get(dev));
+ sess_mp = rte_mempool_from_obj(priv);
+ set_asym_session_private_data(sess, dev->driver_id, NULL);
+ rte_mempool_put(sess_mp, priv);
+}
+
struct rte_cryptodev_ops otx2_cpt_ops = {
/* Device control ops */
.dev_configure = otx2_cpt_dev_config,
@@ -844,4 +920,10 @@ struct rte_cryptodev_ops otx2_cpt_ops = {
.sym_session_get_size = otx2_cpt_sym_session_get_size,
.sym_session_configure = otx2_cpt_sym_session_configure,
.sym_session_clear = otx2_cpt_sym_session_clear,
+
+ /* Asymmetric crypto ops */
+ .asym_session_get_size = otx2_cpt_asym_session_size_get,
+ .asym_session_configure = otx2_cpt_asym_session_cfg,
+ .asym_session_clear = otx2_cpt_asym_session_clear,
+
};
--
2.7.4
^ permalink raw reply related [flat|nested] 53+ messages in thread* [dpdk-dev] [PATCH v3 10/11] crypto/octeontx2: add asymmetric in enqueue/dequeue ops
2019-10-16 15:25 ` [dpdk-dev] [PATCH v3 00/11] " Anoob Joseph
` (8 preceding siblings ...)
2019-10-16 15:25 ` [dpdk-dev] [PATCH v3 09/11] crypto/octeontx2: add asymmetric session operations Anoob Joseph
@ 2019-10-16 15:25 ` Anoob Joseph
2019-10-16 15:25 ` [dpdk-dev] [PATCH v3 11/11] app/test: register octeontx2 PMD to asym testsuite Anoob Joseph
2019-10-17 9:48 ` [dpdk-dev] [PATCH v3 00/11] add OCTEON TX2 crypto PMD Akhil Goyal
11 siblings, 0 replies; 53+ messages in thread
From: Anoob Joseph @ 2019-10-16 15:25 UTC (permalink / raw)
To: Akhil Goyal, Pablo de Lara
Cc: Sunila Sahu, Fiona Trahe, Jerin Jacob, Narayana Prasad,
Shally Verma, Ankur Dwivedi, Kanaka Durga Kotamarthy,
Tejasree Kondoj, dev, Anoob Joseph
From: Sunila Sahu <ssahu@marvell.com>
This patch adds asymmetric support in enqueue/dequeue ops.
Signed-off-by: Anoob Joseph <anoobj@marvell.com>
Signed-off-by: Kanaka Durga Kotamarthy <kkotamarthy@marvell.com>
Signed-off-by: Sunila Sahu <ssahu@marvell.com>
---
drivers/crypto/octeontx2/otx2_cryptodev_ops.c | 177 ++++++++++++++++++++++++++
drivers/crypto/octeontx2/otx2_cryptodev_ops.h | 1 +
2 files changed, 178 insertions(+)
diff --git a/drivers/crypto/octeontx2/otx2_cryptodev_ops.c b/drivers/crypto/octeontx2/otx2_cryptodev_ops.c
index f8d203e..65101b0 100644
--- a/drivers/crypto/octeontx2/otx2_cryptodev_ops.c
+++ b/drivers/crypto/octeontx2/otx2_cryptodev_ops.c
@@ -393,6 +393,78 @@ otx2_cpt_enqueue_req(const struct otx2_cpt_qp *qp,
return 0;
}
+static __rte_always_inline int32_t __hot
+otx2_cpt_enqueue_asym(struct otx2_cpt_qp *qp,
+ struct rte_crypto_op *op,
+ struct pending_queue *pend_q)
+{
+ struct cpt_qp_meta_info *minfo = &qp->meta_info;
+ struct rte_crypto_asym_op *asym_op = op->asym;
+ struct asym_op_params params = {0};
+ struct cpt_asym_sess_misc *sess;
+ vq_cmd_word3_t *w3;
+ uintptr_t *cop;
+ void *mdata;
+ int ret;
+
+ if (unlikely(rte_mempool_get(minfo->pool, &mdata) < 0)) {
+ CPT_LOG_ERR("Could not allocate meta buffer for request");
+ return -ENOMEM;
+ }
+
+ sess = get_asym_session_private_data(asym_op->session,
+ otx2_cryptodev_driver_id);
+
+ /* Store IO address of the mdata to meta_buf */
+ params.meta_buf = rte_mempool_virt2iova(mdata);
+
+ cop = mdata;
+ cop[0] = (uintptr_t)mdata;
+ cop[1] = (uintptr_t)op;
+ cop[2] = cop[3] = 0ULL;
+
+ params.req = RTE_PTR_ADD(cop, 4 * sizeof(uintptr_t));
+ params.req->op = cop;
+
+ /* Adjust meta_buf to point to end of cpt_request_info structure */
+ params.meta_buf += (4 * sizeof(uintptr_t)) +
+ sizeof(struct cpt_request_info);
+ switch (sess->xfrm_type) {
+ case RTE_CRYPTO_ASYM_XFORM_MODEX:
+ ret = cpt_modex_prep(¶ms, &sess->mod_ctx);
+ if (unlikely(ret))
+ goto req_fail;
+ break;
+ case RTE_CRYPTO_ASYM_XFORM_RSA:
+ ret = cpt_enqueue_rsa_op(op, ¶ms, sess);
+ if (unlikely(ret))
+ goto req_fail;
+ break;
+ default:
+ op->status = RTE_CRYPTO_OP_STATUS_INVALID_ARGS;
+ ret = -EINVAL;
+ goto req_fail;
+ }
+
+ /* Set engine group of AE */
+ w3 = (vq_cmd_word3_t *)¶ms.req->ist.ei3;
+ w3->s.grp = OTX2_CPT_EGRP_AE;
+
+ ret = otx2_cpt_enqueue_req(qp, pend_q, params.req);
+
+ if (unlikely(ret)) {
+ CPT_LOG_DP_ERR("Could not enqueue crypto req");
+ goto req_fail;
+ }
+
+ return 0;
+
+req_fail:
+ free_op_meta(mdata, minfo->pool);
+
+ return ret;
+}
+
static __rte_always_inline int __hot
otx2_cpt_enqueue_sym(struct otx2_cpt_qp *qp, struct rte_crypto_op *op,
struct pending_queue *pend_q)
@@ -494,6 +566,11 @@ otx2_cpt_enqueue_burst(void *qptr, struct rte_crypto_op **ops, uint16_t nb_ops)
else
ret = otx2_cpt_enqueue_sym_sessless(qp, op,
pend_q);
+ } else if (op->type == RTE_CRYPTO_OP_TYPE_ASYMMETRIC) {
+ if (op->sess_type == RTE_CRYPTO_OP_WITH_SESSION)
+ ret = otx2_cpt_enqueue_asym(qp, op, pend_q);
+ else
+ break;
} else
break;
@@ -504,6 +581,92 @@ otx2_cpt_enqueue_burst(void *qptr, struct rte_crypto_op **ops, uint16_t nb_ops)
return count;
}
+static __rte_always_inline void
+otx2_cpt_asym_rsa_op(struct rte_crypto_op *cop, struct cpt_request_info *req,
+ struct rte_crypto_rsa_xform *rsa_ctx)
+{
+ struct rte_crypto_rsa_op_param *rsa = &cop->asym->rsa;
+
+ switch (rsa->op_type) {
+ case RTE_CRYPTO_ASYM_OP_ENCRYPT:
+ rsa->cipher.length = rsa_ctx->n.length;
+ memcpy(rsa->cipher.data, req->rptr, rsa->cipher.length);
+ break;
+ case RTE_CRYPTO_ASYM_OP_DECRYPT:
+ if (rsa->pad == RTE_CRYPTO_RSA_PADDING_NONE) {
+ rsa->message.length = rsa_ctx->n.length;
+ memcpy(rsa->message.data, req->rptr,
+ rsa->message.length);
+ } else {
+ /* Get length of decrypted output */
+ rsa->message.length = rte_cpu_to_be_16
+ (*((uint16_t *)req->rptr));
+ /*
+ * Offset output data pointer by length field
+ * (2 bytes) and copy decrypted data.
+ */
+ memcpy(rsa->message.data, req->rptr + 2,
+ rsa->message.length);
+ }
+ break;
+ case RTE_CRYPTO_ASYM_OP_SIGN:
+ rsa->sign.length = rsa_ctx->n.length;
+ memcpy(rsa->sign.data, req->rptr, rsa->sign.length);
+ break;
+ case RTE_CRYPTO_ASYM_OP_VERIFY:
+ if (rsa->pad == RTE_CRYPTO_RSA_PADDING_NONE) {
+ rsa->sign.length = rsa_ctx->n.length;
+ memcpy(rsa->sign.data, req->rptr, rsa->sign.length);
+ } else {
+ /* Get length of signed output */
+ rsa->sign.length = rte_cpu_to_be_16
+ (*((uint16_t *)req->rptr));
+ /*
+ * Offset output data pointer by length field
+ * (2 bytes) and copy signed data.
+ */
+ memcpy(rsa->sign.data, req->rptr + 2,
+ rsa->sign.length);
+ }
+ if (memcmp(rsa->sign.data, rsa->message.data,
+ rsa->message.length)) {
+ CPT_LOG_DP_ERR("RSA verification failed");
+ cop->status = RTE_CRYPTO_OP_STATUS_ERROR;
+ }
+ break;
+ default:
+ CPT_LOG_DP_DEBUG("Invalid RSA operation type");
+ cop->status = RTE_CRYPTO_OP_STATUS_INVALID_ARGS;
+ break;
+ }
+}
+
+static void
+otx2_cpt_asym_post_process(struct rte_crypto_op *cop,
+ struct cpt_request_info *req)
+{
+ struct rte_crypto_asym_op *op = cop->asym;
+ struct cpt_asym_sess_misc *sess;
+
+ sess = get_asym_session_private_data(op->session,
+ otx2_cryptodev_driver_id);
+
+ switch (sess->xfrm_type) {
+ case RTE_CRYPTO_ASYM_XFORM_RSA:
+ otx2_cpt_asym_rsa_op(cop, req, &sess->rsa_ctx);
+ break;
+ case RTE_CRYPTO_ASYM_XFORM_MODEX:
+ op->modex.result.length = sess->mod_ctx.modulus.length;
+ memcpy(op->modex.result.data, req->rptr,
+ op->modex.result.length);
+ break;
+ default:
+ CPT_LOG_DP_DEBUG("Invalid crypto xform type");
+ cop->status = RTE_CRYPTO_OP_STATUS_INVALID_ARGS;
+ break;
+ }
+}
+
static inline void
otx2_cpt_dequeue_post_process(struct otx2_cpt_qp *qp, struct rte_crypto_op *cop,
uintptr_t *rsp, uint8_t cc)
@@ -530,6 +693,20 @@ otx2_cpt_dequeue_post_process(struct otx2_cpt_qp *qp, struct rte_crypto_op *cop,
cop->sym->session = NULL;
}
}
+
+ if (cop->type == RTE_CRYPTO_OP_TYPE_ASYMMETRIC) {
+ if (likely(cc == NO_ERR)) {
+ cop->status = RTE_CRYPTO_OP_STATUS_SUCCESS;
+ /*
+ * Pass cpt_req_info stored in metabuf during
+ * enqueue.
+ */
+ rsp = RTE_PTR_ADD(rsp, 4 * sizeof(uintptr_t));
+ otx2_cpt_asym_post_process(cop,
+ (struct cpt_request_info *)rsp);
+ } else
+ cop->status = RTE_CRYPTO_OP_STATUS_ERROR;
+ }
}
static __rte_always_inline uint8_t
diff --git a/drivers/crypto/octeontx2/otx2_cryptodev_ops.h b/drivers/crypto/octeontx2/otx2_cryptodev_ops.h
index ba93a66..a2724f7 100644
--- a/drivers/crypto/octeontx2/otx2_cryptodev_ops.h
+++ b/drivers/crypto/octeontx2/otx2_cryptodev_ops.h
@@ -13,6 +13,7 @@
enum otx2_cpt_egrp {
OTX2_CPT_EGRP_SE = 0,
OTX2_CPT_EGRP_SE_IE = 1,
+ OTX2_CPT_EGRP_AE = 2
};
struct rte_cryptodev_ops otx2_cpt_ops;
--
2.7.4
^ permalink raw reply related [flat|nested] 53+ messages in thread* [dpdk-dev] [PATCH v3 11/11] app/test: register octeontx2 PMD to asym testsuite
2019-10-16 15:25 ` [dpdk-dev] [PATCH v3 00/11] " Anoob Joseph
` (9 preceding siblings ...)
2019-10-16 15:25 ` [dpdk-dev] [PATCH v3 10/11] crypto/octeontx2: add asymmetric in enqueue/dequeue ops Anoob Joseph
@ 2019-10-16 15:25 ` Anoob Joseph
2019-10-17 9:48 ` [dpdk-dev] [PATCH v3 00/11] add OCTEON TX2 crypto PMD Akhil Goyal
11 siblings, 0 replies; 53+ messages in thread
From: Anoob Joseph @ 2019-10-16 15:25 UTC (permalink / raw)
To: Akhil Goyal, Pablo de Lara
Cc: Sunila Sahu, Fiona Trahe, Jerin Jacob, Narayana Prasad,
Shally Verma, Ankur Dwivedi, Kanaka Durga Kotamarthy,
Tejasree Kondoj, dev, Anoob Joseph
From: Sunila Sahu <ssahu@marvell.com>
This patch updates asymmetric crypto unit-test application to
validate asymmetric crypto operation supported by octeontx2 PMD.
Signed-off-by: Anoob Joseph <anoobj@marvell.com>
Signed-off-by: Kanaka Durga Kotamarthy <kkotamarthy@marvell.com>
Signed-off-by: Sunila Sahu <ssahu@marvell.com>
---
app/test/test_cryptodev_asym.c | 20 ++++++++++++++++++++
doc/guides/cryptodevs/octeontx2.rst | 8 ++++++++
2 files changed, 28 insertions(+)
diff --git a/app/test/test_cryptodev_asym.c b/app/test/test_cryptodev_asym.c
index 241c384..6cc2f97 100644
--- a/app/test/test_cryptodev_asym.c
+++ b/app/test/test_cryptodev_asym.c
@@ -1851,6 +1851,23 @@ test_cryptodev_octeontx_asym(void)
return unit_test_suite_runner(&cryptodev_octeontx_asym_testsuite);
}
+static int
+test_cryptodev_octeontx2_asym(void)
+{
+ gbl_driver_id = rte_cryptodev_driver_id_get(
+ RTE_STR(CRYPTODEV_NAME_OCTEONTX2_PMD));
+ if (gbl_driver_id == -1) {
+ RTE_LOG(ERR, USER1, "OCTEONTX2 PMD must be loaded. Check if "
+ "CONFIG_RTE_LIBRTE_PMD_OCTEONTX2_CRYPTO is "
+ "enabled in config file to run this "
+ "testsuite.\n");
+ return TEST_FAILED;
+ }
+
+ /* Use test suite registered for crypto_octeontx PMD */
+ return unit_test_suite_runner(&cryptodev_octeontx_asym_testsuite);
+}
+
REGISTER_TEST_COMMAND(cryptodev_openssl_asym_autotest,
test_cryptodev_openssl_asym);
@@ -1858,3 +1875,6 @@ REGISTER_TEST_COMMAND(cryptodev_qat_asym_autotest, test_cryptodev_qat_asym);
REGISTER_TEST_COMMAND(cryptodev_octeontx_asym_autotest,
test_cryptodev_octeontx_asym);
+
+REGISTER_TEST_COMMAND(cryptodev_octeontx2_asym_autotest,
+ test_cryptodev_octeontx2_asym);
diff --git a/doc/guides/cryptodevs/octeontx2.rst b/doc/guides/cryptodevs/octeontx2.rst
index ad33c66..8bdb83f 100644
--- a/doc/guides/cryptodevs/octeontx2.rst
+++ b/doc/guides/cryptodevs/octeontx2.rst
@@ -149,3 +149,11 @@ application:
./test
RTE>>cryptodev_octeontx2_autotest
+
+The asymmetric crypto operations on OCTEON TX2 crypto PMD may be verified by running the test
+application:
+
+.. code-block:: console
+
+ ./test
+ RTE>>cryptodev_octeontx2_asym_autotest
--
2.7.4
^ permalink raw reply related [flat|nested] 53+ messages in thread* Re: [dpdk-dev] [PATCH v3 00/11] add OCTEON TX2 crypto PMD
2019-10-16 15:25 ` [dpdk-dev] [PATCH v3 00/11] " Anoob Joseph
` (10 preceding siblings ...)
2019-10-16 15:25 ` [dpdk-dev] [PATCH v3 11/11] app/test: register octeontx2 PMD to asym testsuite Anoob Joseph
@ 2019-10-17 9:48 ` Akhil Goyal
11 siblings, 0 replies; 53+ messages in thread
From: Akhil Goyal @ 2019-10-17 9:48 UTC (permalink / raw)
To: Anoob Joseph, Pablo de Lara
Cc: Fiona Trahe, Jerin Jacob, Narayana Prasad, Shally Verma,
Ankur Dwivedi, Kanaka Durga Kotamarthy, Sunila Sahu,
Tejasree Kondoj, dev@dpdk.org
>
> The series introduces poll mode driver to enable crypto offload engine
> on Marvell OCTEON TX2 SoC.
>
> Changes in v3:
> * Rebased on tip of dpdk-next-crypto("36112de91a44")
> * Updated version map to use right DPDK version
> * Added sanity checks in dev_close() routine.
>
> Changes in v2:
> * Merged series adding sym features and asym features into one.
> * Squashed patches as directed by Akhil.
> * Added check for ASYM SESSIONLESS (not supported currently)
> * Minor updates to documentation
>
> Ankur Dwivedi (3):
> crypto/octeontx2: add device control ops
> crypto/octeontx2: add queue pair functions
> crypto/octeontx2: add session related functions
>
> Anoob Joseph (5):
> crypto/octeontx2: add PMD skeleton
> crypto/octeontx2: add device init sequence in probe
> crypto/octeontx2: add symmetric capabilities
> crypto/octeontx2: add enqueue/dequeue ops
> test: add OCTEON TX2 tests
>
> Kanaka Durga Kotamarthy (1):
> crypto/octeontx2: add asymmetric session operations
>
> Sunila Sahu (2):
> crypto/octeontx2: add asymmetric in enqueue/dequeue ops
> app/test: register octeontx2 PMD to asym testsuite
>
> MAINTAINERS | 7 +
> app/test/meson.build | 1 +
> app/test/test_cryptodev.c | 323 ++++++
> app/test/test_cryptodev.h | 1 +
> app/test/test_cryptodev_aes_test_vectors.h | 114 +-
> app/test/test_cryptodev_asym.c | 20 +
> app/test/test_cryptodev_blockcipher.c | 7 +
> app/test/test_cryptodev_blockcipher.h | 1 +
> app/test/test_cryptodev_des_test_vectors.h | 12 +-
> app/test/test_cryptodev_hash_test_vectors.h | 75 +-
> config/common_base | 5 +
> doc/guides/cryptodevs/features/octeontx2.ini | 71 ++
> doc/guides/cryptodevs/index.rst | 1 +
> doc/guides/cryptodevs/octeontx2.rst | 159 +++
> doc/guides/platform/octeontx2.rst | 3 +
> doc/guides/rel_notes/release_19_11.rst | 6 +
> drivers/common/Makefile | 5 +-
> drivers/common/cpt/cpt_hw_types.h | 52 +
> drivers/common/cpt/cpt_mcode_defines.h | 2 +
> drivers/crypto/Makefile | 1 +
> drivers/crypto/meson.build | 21 +-
> drivers/crypto/octeontx2/Makefile | 50 +
> drivers/crypto/octeontx2/meson.build | 34 +
> drivers/crypto/octeontx2/otx2_cryptodev.c | 157 +++
> drivers/crypto/octeontx2/otx2_cryptodev.h | 43 +
> .../crypto/octeontx2/otx2_cryptodev_capabilities.c | 639 +++++++++++
> .../crypto/octeontx2/otx2_cryptodev_capabilities.h | 16 +
> .../crypto/octeontx2/otx2_cryptodev_hw_access.c | 225 ++++
> .../crypto/octeontx2/otx2_cryptodev_hw_access.h | 169 +++
> drivers/crypto/octeontx2/otx2_cryptodev_mbox.c | 175 ++++
> drivers/crypto/octeontx2/otx2_cryptodev_mbox.h | 25 +
> drivers/crypto/octeontx2/otx2_cryptodev_ops.c | 1106
> ++++++++++++++++++++
> drivers/crypto/octeontx2/otx2_cryptodev_ops.h | 21 +
> .../octeontx2/rte_pmd_octeontx2_crypto_version.map | 4 +
> mk/rte.app.mk | 6 +-
> 35 files changed, 3485 insertions(+), 72 deletions(-)
> create mode 100644 doc/guides/cryptodevs/features/octeontx2.ini
> create mode 100644 doc/guides/cryptodevs/octeontx2.rst
> create mode 100644 drivers/crypto/octeontx2/Makefile
> create mode 100644 drivers/crypto/octeontx2/meson.build
> create mode 100644 drivers/crypto/octeontx2/otx2_cryptodev.c
> create mode 100644 drivers/crypto/octeontx2/otx2_cryptodev.h
> create mode 100644 drivers/crypto/octeontx2/otx2_cryptodev_capabilities.c
> create mode 100644 drivers/crypto/octeontx2/otx2_cryptodev_capabilities.h
> create mode 100644 drivers/crypto/octeontx2/otx2_cryptodev_hw_access.c
> create mode 100644 drivers/crypto/octeontx2/otx2_cryptodev_hw_access.h
> create mode 100644 drivers/crypto/octeontx2/otx2_cryptodev_mbox.c
> create mode 100644 drivers/crypto/octeontx2/otx2_cryptodev_mbox.h
> create mode 100644 drivers/crypto/octeontx2/otx2_cryptodev_ops.c
> create mode 100644 drivers/crypto/octeontx2/otx2_cryptodev_ops.h
> create mode 100644
> drivers/crypto/octeontx2/rte_pmd_octeontx2_crypto_version.map
>
Acked-by: Akhil Goyal <akhil.goyal@nxp.com>
Applied to dpdk-next-crypto
Thanks.
^ permalink raw reply [flat|nested] 53+ messages in thread