From: Heiko Stuebner <heiko-4mtYJXux2i+zQB+pC5nmwQ@public.gmane.org>
To: Caesar Wang <wxt-TNX95d0MmH7DzftRWevZcw@public.gmane.org>
Cc: linux-rockchip-IAPFreCvJWM7uuMidbF8XUB+6BGkLq7r@public.gmane.org,
Douglas Anderson
<dianders-F7+t8E8rja9g9hUCZPvPmw@public.gmane.org>,
sonnyrao-F7+t8E8rja9g9hUCZPvPmw@public.gmane.org,
linux-arm-kernel-IAPFreCvJWM7uuMidbF8XUB+6BGkLq7r@public.gmane.org,
Will Deacon <will.deacon-5wv7dgnIgG8@public.gmane.org>,
Marc Zyngier <marc.zyngier-5wv7dgnIgG8@public.gmane.org>,
devicetree-u79uwXL29TY76Z2rM5mHXA@public.gmane.org,
David Wu <david.wu-TNX95d0MmH7DzftRWevZcw@public.gmane.org>,
Elaine Zhang <zhangqing-TNX95d0MmH7DzftRWevZcw@public.gmane.org>,
Brian Norris
<briannorris-F7+t8E8rja9g9hUCZPvPmw@public.gmane.org>,
linux-kernel-u79uwXL29TY76Z2rM5mHXA@public.gmane.org,
Huang Tao <huangtao-TNX95d0MmH7DzftRWevZcw@public.gmane.org>,
Shawn Lin <shawn.lin-TNX95d0MmH7DzftRWevZcw@public.gmane.org>,
Jianqun Xu <jay.xu-TNX95d0MmH7DzftRWevZcw@public.gmane.org>,
Mark Rutland <mark.rutland-5wv7dgnIgG8@public.gmane.org>,
Rob Herring <robh+dt-DgEjT+Ai2ygdnm+yROfE0A@public.gmane.org>,
Catalin Marinas <catalin.marinas-5wv7dgnIgG8@public.gmane.org>
Subject: Re: [PATCH v3 1/2] arm64: dts: rockchip: change all interrupts cells for 4 on rk3399 SoCs
Date: Tue, 06 Sep 2016 00:20:58 +0200 [thread overview]
Message-ID: <3069982.xePB5pcLZB@phil> (raw)
In-Reply-To: <1473099435-28198-2-git-send-email-wxt-TNX95d0MmH7DzftRWevZcw@public.gmane.org>
Am Dienstag, 6. September 2016, 02:17:14 CEST schrieb Caesar Wang:
> Add the interrupts cells value for 4, and the 4th cell is zero.
>
> Due to the doc[0] said:" the system requires describing PPI affinity,
> then the value must be at least 4"
> The 4th cell is a phandle to a node describing a set of CPUs this
> interrupt is affine to. The interrupt must be a PPI, and the node
> pointed must be a subnode of the "ppi-partitions" subnode. For
> interrupt types other than PPI or PPIs that are not partitionned,
> this cell must be zero. See the "ppi-partitions" node description
> below.
>
> [0]:
> Documentation/devicetree/bindings/interrupt-controller/arm,gic-v3.txt
>
> Signed-off-by: Caesar Wang <wxt-TNX95d0MmH7DzftRWevZcw@public.gmane.org>
> Acked-by: Mark Rutland <mark.rutland-5wv7dgnIgG8@public.gmane.org>
> Cc: Heiko Stuebner <heiko-4mtYJXux2i+zQB+pC5nmwQ@public.gmane.org>
> Cc: Will Deacon <will.deacon-5wv7dgnIgG8@public.gmane.org>
> Cc: Marc Zyngier <marc.zyngier-5wv7dgnIgG8@public.gmane.org>
> CC: linux-arm-kernel-IAPFreCvJWM7uuMidbF8XUB+6BGkLq7r@public.gmane.org
applied to my dts64 branch for 4.9
Thanks
Heiko
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WARNING: multiple messages have this Message-ID (diff)
From: heiko@sntech.de (Heiko Stuebner)
To: linux-arm-kernel@lists.infradead.org
Subject: [PATCH v3 1/2] arm64: dts: rockchip: change all interrupts cells for 4 on rk3399 SoCs
Date: Tue, 06 Sep 2016 00:20:58 +0200 [thread overview]
Message-ID: <3069982.xePB5pcLZB@phil> (raw)
In-Reply-To: <1473099435-28198-2-git-send-email-wxt@rock-chips.com>
Am Dienstag, 6. September 2016, 02:17:14 CEST schrieb Caesar Wang:
> Add the interrupts cells value for 4, and the 4th cell is zero.
>
> Due to the doc[0] said:" the system requires describing PPI affinity,
> then the value must be at least 4"
> The 4th cell is a phandle to a node describing a set of CPUs this
> interrupt is affine to. The interrupt must be a PPI, and the node
> pointed must be a subnode of the "ppi-partitions" subnode. For
> interrupt types other than PPI or PPIs that are not partitionned,
> this cell must be zero. See the "ppi-partitions" node description
> below.
>
> [0]:
> Documentation/devicetree/bindings/interrupt-controller/arm,gic-v3.txt
>
> Signed-off-by: Caesar Wang <wxt@rock-chips.com>
> Acked-by: Mark Rutland <mark.rutland@arm.com>
> Cc: Heiko Stuebner <heiko@sntech.de>
> Cc: Will Deacon <will.deacon@arm.com>
> Cc: Marc Zyngier <marc.zyngier@arm.com>
> CC: linux-arm-kernel at lists.infradead.org
applied to my dts64 branch for 4.9
Thanks
Heiko
WARNING: multiple messages have this Message-ID (diff)
From: Heiko Stuebner <heiko@sntech.de>
To: Caesar Wang <wxt@rock-chips.com>
Cc: linux-rockchip@lists.infradead.org,
Douglas Anderson <dianders@chromium.org>,
sonnyrao@chromium.org, linux-arm-kernel@lists.infradead.org,
Will Deacon <will.deacon@arm.com>,
Marc Zyngier <marc.zyngier@arm.com>,
devicetree@vger.kernel.org, David Wu <david.wu@rock-chips.com>,
Elaine Zhang <zhangqing@rock-chips.com>,
Brian Norris <briannorris@chromium.org>,
linux-kernel@vger.kernel.org, Huang Tao <huangtao@rock-chips.com>,
Shawn Lin <shawn.lin@rock-chips.com>,
Jianqun Xu <jay.xu@rock-chips.com>,
Mark Rutland <mark.rutland@arm.com>,
Rob Herring <robh+dt@kernel.org>,
Catalin Marinas <catalin.marinas@arm.com>
Subject: Re: [PATCH v3 1/2] arm64: dts: rockchip: change all interrupts cells for 4 on rk3399 SoCs
Date: Tue, 06 Sep 2016 00:20:58 +0200 [thread overview]
Message-ID: <3069982.xePB5pcLZB@phil> (raw)
In-Reply-To: <1473099435-28198-2-git-send-email-wxt@rock-chips.com>
Am Dienstag, 6. September 2016, 02:17:14 CEST schrieb Caesar Wang:
> Add the interrupts cells value for 4, and the 4th cell is zero.
>
> Due to the doc[0] said:" the system requires describing PPI affinity,
> then the value must be at least 4"
> The 4th cell is a phandle to a node describing a set of CPUs this
> interrupt is affine to. The interrupt must be a PPI, and the node
> pointed must be a subnode of the "ppi-partitions" subnode. For
> interrupt types other than PPI or PPIs that are not partitionned,
> this cell must be zero. See the "ppi-partitions" node description
> below.
>
> [0]:
> Documentation/devicetree/bindings/interrupt-controller/arm,gic-v3.txt
>
> Signed-off-by: Caesar Wang <wxt@rock-chips.com>
> Acked-by: Mark Rutland <mark.rutland@arm.com>
> Cc: Heiko Stuebner <heiko@sntech.de>
> Cc: Will Deacon <will.deacon@arm.com>
> Cc: Marc Zyngier <marc.zyngier@arm.com>
> CC: linux-arm-kernel@lists.infradead.org
applied to my dts64 branch for 4.9
Thanks
Heiko
next prev parent reply other threads:[~2016-09-05 22:20 UTC|newest]
Thread overview: 16+ messages / expand[flat|nested] mbox.gz Atom feed top
2016-09-05 18:17 [PATCH v3 0/2] arm64: dts: rockchip: Support PMU for rk3399 SoCs Caesar Wang
2016-09-05 18:17 ` Caesar Wang
2016-09-05 18:17 ` Caesar Wang
2016-09-05 18:17 ` [PATCH v3 1/2] arm64: dts: rockchip: change all interrupts cells for 4 on " Caesar Wang
2016-09-05 18:17 ` Caesar Wang
[not found] ` <1473099435-28198-2-git-send-email-wxt-TNX95d0MmH7DzftRWevZcw@public.gmane.org>
2016-09-05 22:20 ` Heiko Stuebner [this message]
2016-09-05 22:20 ` Heiko Stuebner
2016-09-05 22:20 ` Heiko Stuebner
[not found] ` <1473099435-28198-1-git-send-email-wxt-TNX95d0MmH7DzftRWevZcw@public.gmane.org>
2016-09-05 18:17 ` [PATCH v3 2/2] arm64: dts: rockchip: support the pmu node for rk3399 Caesar Wang
2016-09-05 18:17 ` Caesar Wang
2016-09-05 18:17 ` Caesar Wang
2016-09-05 22:27 ` Heiko Stuebner
2016-09-05 22:27 ` Heiko Stuebner
2016-09-05 23:27 ` Caesar Wang
2016-09-05 23:27 ` Caesar Wang
2016-09-05 23:27 ` Caesar Wang
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