[PATCH 0/7] ARM: dts: collected rockchip dtsi and board changes

[PATCH 0/7] ARM: dts: collected rockchip dtsi and board changes

[Heiko Stübner]

These are collected dtsi changes for drivers that made it into a tree
recently - except the saradc nodes, where the driver is still in-flight.
As everything depends on the clock controller series [0] anyway, I'll simply
strip off the last patch if necessary once the clocks land.

[0] http://www.spinics.net/lists/arm-kernel/msg343927.html

Beniamino Galvani (2):
  ARM: dts: add i2c and regulator nodes to rk3188-radxarock
  ARM: dts: rockchip: add pwm nodes

Heiko Stuebner (5):
  ARM: dts: add rk3066 and rk3188 i2c device nodes and pinctrl settings
  ARM: dts: rockchip: add tps65910 regulator for bqcurie2
  ARM: dts: rk3188-radxarock: enable sd-card slot
  ARM: dts: rockchip: add both clocks to uart nodes
  ARM: dts: rockchip: add saradc nodes

 arch/arm/boot/dts/rk3066a-bqcurie2.dts |  98 ++++++++++++++++++++++
 arch/arm/boot/dts/rk3066a.dtsi         |  59 +++++++++++++
 arch/arm/boot/dts/rk3188-radxarock.dts | 147 +++++++++++++++++++++++++++++++++
 arch/arm/boot/dts/rk3188.dtsi          |  79 ++++++++++++++++++
 arch/arm/boot/dts/rk3xxx.dtsi          | 139 ++++++++++++++++++++++++++++++-
 5 files changed, 518 insertions(+), 4 deletions(-)

-- 
1.9.0

[PATCH 1/7] ARM: dts: add rk3066 and rk3188 i2c device nodes and pinctrl settings

[Heiko Stübner]

The controller settings themself are identical, only the pinctrl settings differ.

Signed-off-by: Heiko Stuebner <heiko@sntech.de>
---
 arch/arm/boot/dts/rk3066a.dtsi | 35 ++++++++++++++++++
 arch/arm/boot/dts/rk3188.dtsi  | 55 +++++++++++++++++++++++++++
 arch/arm/boot/dts/rk3xxx.dtsi  | 84 ++++++++++++++++++++++++++++++++++++++++++
 3 files changed, 174 insertions(+)

diff --git a/arch/arm/boot/dts/rk3066a.dtsi b/arch/arm/boot/dts/rk3066a.dtsi
index b705a60..3cfdb43 100644
--- a/arch/arm/boot/dts/rk3066a.dtsi
+++ b/arch/arm/boot/dts/rk3066a.dtsi
@@ -181,6 +181,41 @@
 				bias-disable;
 			};
 
+			i2c0 {
+				i2c0_pins: i2c0-pins {
+					rockchip,pins = <RK_GPIO2 28 RK_FUNC_1 &pcfg_pull_none>,
+							<RK_GPIO2 29 RK_FUNC_1 &pcfg_pull_none>;
+				};
+			};
+
+			i2c1 {
+				i2c1_pins: i2c1-pins {
+					rockchip,pins = <RK_GPIO2 30 RK_FUNC_1 &pcfg_pull_none>,
+							<RK_GPIO2 31 RK_FUNC_1 &pcfg_pull_none>;
+				};
+			};
+
+			i2c2 {
+				i2c2_pins: i2c2-pins {
+					rockchip,pins = <RK_GPIO3 0 RK_FUNC_1 &pcfg_pull_none>,
+							<RK_GPIO3 1 RK_FUNC_1 &pcfg_pull_none>;
+				};
+			};
+
+			i2c3 {
+				i2c3_pins: i2c3-pins {
+					rockchip,pins = <RK_GPIO3 2 RK_FUNC_2 &pcfg_pull_none>,
+							<RK_GPIO3 3 RK_FUNC_2 &pcfg_pull_none>;
+				};
+			};
+
+			i2c4 {
+				i2c4_pins: i2c4-pins {
+					rockchip,pins = <RK_GPIO3 4 RK_FUNC_1 &pcfg_pull_none>,
+							<RK_GPIO3 5 RK_FUNC_1 &pcfg_pull_none>;
+				};
+			};
+
 			uart0 {
 				uart0_xfer: uart0-xfer {
 					rockchip,pins = <RK_GPIO1 0 RK_FUNC_1 &pcfg_pull_default>,
diff --git a/arch/arm/boot/dts/rk3188.dtsi b/arch/arm/boot/dts/rk3188.dtsi
index ddca355..fc3b0dd 100644
--- a/arch/arm/boot/dts/rk3188.dtsi
+++ b/arch/arm/boot/dts/rk3188.dtsi
@@ -156,6 +156,41 @@
 				bias-disable;
 			};
 
+			i2c0 {
+				i2c0_pins: i2c0-pins {
+					rockchip,pins = <RK_GPIO1 24 RK_FUNC_1 &pcfg_pull_none>,
+							<RK_GPIO1 25 RK_FUNC_1 &pcfg_pull_none>;
+				};
+			};
+
+			i2c1 {
+				i2c1_pins: i2c1-pins {
+					rockchip,pins = <RK_GPIO1 26 RK_FUNC_1 &pcfg_pull_none>,
+							<RK_GPIO1 27 RK_FUNC_1 &pcfg_pull_none>;
+				};
+			};
+
+			i2c2 {
+				i2c2_pins: i2c2-pins {
+					rockchip,pins = <RK_GPIO1 28 RK_FUNC_1 &pcfg_pull_none>,
+							<RK_GPIO1 29 RK_FUNC_1 &pcfg_pull_none>;
+				};
+			};
+
+			i2c3 {
+				i2c3_pins: i2c3-pins {
+					rockchip,pins = <RK_GPIO3 14 RK_FUNC_2 &pcfg_pull_none>,
+							<RK_GPIO3 15 RK_FUNC_2 &pcfg_pull_none>;
+				};
+			};
+
+			i2c4 {
+				i2c4_pins: i2c4-pins {
+					rockchip,pins = <RK_GPIO1 30 RK_FUNC_1 &pcfg_pull_none>,
+							<RK_GPIO1 31 RK_FUNC_1 &pcfg_pull_none>;
+				};
+			};
+
 			uart0 {
 				uart0_xfer: uart0-xfer {
 					rockchip,pins = <RK_GPIO1 0 RK_FUNC_1 &pcfg_pull_up>,
@@ -271,5 +306,25 @@
 				};
 			};
 		};
+
+		i2c0: i2c at 2002d000 {
+			compatible = "rockchip,rk3188-i2c";
+		};
+
+		i2c1: i2c at 2002f000 {
+			compatible = "rockchip,rk3188-i2c";
+		};
+
+		i2c2: i2c at 20056000 {
+			compatible = "rockchip,rk3188-i2c";
+		};
+
+		i2c3: i2c at 2005a000 {
+			compatible = "rockchip,rk3188-i2c";
+		};
+
+		i2c4: i2c at 2005e000 {
+			compatible = "rockchip,rk3188-i2c";
+		};
 	};
 };
diff --git a/arch/arm/boot/dts/rk3xxx.dtsi b/arch/arm/boot/dts/rk3xxx.dtsi
index 0de3f06..86062a0 100644
--- a/arch/arm/boot/dts/rk3xxx.dtsi
+++ b/arch/arm/boot/dts/rk3xxx.dtsi
@@ -20,6 +20,14 @@
 / {
 	interrupt-parent = <&gic>;
 
+	aliases {
+		i2c0 = &i2c0;
+		i2c1 = &i2c1;
+		i2c2 = &i2c2;
+		i2c3 = &i2c3;
+		i2c4 = &i2c4;
+	};
+
 	soc {
 		#address-cells = <1>;
 		#size-cells = <1>;
@@ -141,5 +149,81 @@
 
 			status = "disabled";
 		};
+
+		i2c0: i2c at 2002d000 {
+			compatible = "rockchip,rk3066-i2c";
+			reg = <0x2002d000 0x1000>;
+			interrupts = <GIC_SPI 40 IRQ_TYPE_LEVEL_HIGH>;
+			#address-cells = <1>;
+			#size-cells = <0>;
+
+			rockchip,grf = <&grf>;
+			rockchip,bus-index = <0>;
+
+			clock-names = "i2c";
+			clocks = <&cru PCLK_I2C0>;
+
+			status = "disabled";
+		};
+
+		i2c1: i2c at 2002f000 {
+			compatible = "rockchip,rk3066-i2c";
+			reg = <0x2002f000 0x1000>;
+			interrupts = <GIC_SPI 41 IRQ_TYPE_LEVEL_HIGH>;
+			#address-cells = <1>;
+			#size-cells = <0>;
+
+			rockchip,grf = <&grf>;
+
+			clocks = <&cru PCLK_I2C1>;
+			clock-names = "i2c";
+
+			status = "disabled";
+		};
+
+		i2c2: i2c at 20056000 {
+			compatible = "rockchip,rk3066-i2c";
+			reg = <0x20056000 0x1000>;
+			interrupts = <GIC_SPI 42 IRQ_TYPE_LEVEL_HIGH>;
+			#address-cells = <1>;
+			#size-cells = <0>;
+
+			rockchip,grf = <&grf>;
+
+			clocks = <&cru PCLK_I2C2>;
+			clock-names = "i2c";
+
+			status = "disabled";
+		};
+
+		i2c3: i2c at 2005a000 {
+			compatible = "rockchip,rk3066-i2c";
+			reg = <0x2005a000 0x1000>;
+			interrupts = <GIC_SPI 43 IRQ_TYPE_LEVEL_HIGH>;
+			#address-cells = <1>;
+			#size-cells = <0>;
+
+			rockchip,grf = <&grf>;
+
+			clocks = <&cru PCLK_I2C3>;
+			clock-names = "i2c";
+
+			status = "disabled";
+		};
+
+		i2c4: i2c at 2005e000 {
+			compatible = "rockchip,rk3066-i2c";
+			reg = <0x2005e000 0x1000>;
+			interrupts = <GIC_SPI 52 IRQ_TYPE_LEVEL_HIGH>;
+			#address-cells = <1>;
+			#size-cells = <0>;
+
+			rockchip,grf = <&grf>;
+
+			clocks = <&cru PCLK_I2C4>;
+			clock-names = "i2c";
+
+			status = "disabled";
+		};
 	};
 };
-- 
1.9.0

[PATCH 2/7] ARM: dts: rockchip: add tps65910 regulator for bqcurie2

[Heiko Stübner]

The Curie2 uses a tps659102 as its main pmic, so add the i2c1 and tps65910
node as well as define the used voltages and regulator-names according to
the schematics.

Also fix the supply of the sd0 regulator, as it is supplied by the vio reg.

Signed-off-by: Heiko Stuebner <heiko@sntech.de>
---
 arch/arm/boot/dts/rk3066a-bqcurie2.dts | 93 ++++++++++++++++++++++++++++++++++
 1 file changed, 93 insertions(+)

diff --git a/arch/arm/boot/dts/rk3066a-bqcurie2.dts b/arch/arm/boot/dts/rk3066a-bqcurie2.dts
index afb3273..4174ff8 100644
--- a/arch/arm/boot/dts/rk3066a-bqcurie2.dts
+++ b/arch/arm/boot/dts/rk3066a-bqcurie2.dts
@@ -50,6 +50,7 @@
 			regulator-max-microvolt = <3000000>;
 			gpio = <&gpio3 7 GPIO_ACTIVE_LOW>;
 			startup-delay-us = <100000>;
+			vin-supply = <&vio_reg>;
 		};
 
 		dwmmc at 10214000 { /* sdmmc */
@@ -108,3 +109,95 @@
 		};
 	};
 };
+
+&i2c1 {
+	pinctrl-names = "default";
+	pinctrl-0 = <&i2c1_pins>;
+
+	status = "okay";
+	clock-frequency = <400000>;
+
+	tps: tps at 2d {
+		reg = <0x2d>;
+
+		interrupt-parent = <&gpio6>;
+		interrupts = <6 IRQ_TYPE_LEVEL_LOW>;
+	};
+};
+
+#include "tps65910.dtsi"
+
+&tps {
+	vcc5-supply = <&vio_reg>;
+	vcc6-supply = <&vio_reg>;
+
+	regulators {
+		vrtc_reg: regulator at 0 {
+			regulator-name = "vcc_rtc";
+			regulator-always-on;
+		};
+
+		vio_reg: regulator at 1 {
+			regulator-name = "vcc_io";
+			regulator-always-on;
+		};
+
+		vdd1_reg: regulator at 2 {
+			regulator-name = "vdd_arm";
+			regulator-min-microvolt = <600000>;
+			regulator-max-microvolt = <1500000>;
+			regulator-boot-on;
+			regulator-always-on;
+		};
+
+		vdd2_reg: regulator at 3 {
+			regulator-name = "vcc_ddr";
+			regulator-min-microvolt = <600000>;
+			regulator-max-microvolt = <1500000>;
+			regulator-boot-on;
+			regulator-always-on;
+		};
+
+		/* vdd3_reg is not connected */
+
+		vdig1_reg: regulator at 5 {
+			regulator-name = "vcc18_cif";
+			regulator-always-on;
+		};
+
+		vdig2_reg: regulator at 6 {
+			regulator-name = "vdd_11";
+			regulator-always-on;
+		};
+
+		vpll_reg: regulator at 7 {
+			regulator-name = "vcc_25";
+			regulator-always-on;
+		};
+
+		vdac_reg: regulator at 8 {
+			regulator-name = "vcc_18";
+			regulator-always-on;
+		};
+
+		vaux1_reg: regulator at 9 {
+			regulator-name = "vcc25_hdmi";
+			regulator-always-on;
+		};
+
+		vaux2_reg: regulator at 10 {
+			regulator-name = "vcca_33";
+			regulator-always-on;
+		};
+
+		vaux33_reg: regulator at 11 {
+			regulator-name = "vcc_tp";
+			regulator-always-on;
+		};
+
+		vmmc_reg: regulator at 12 {
+			regulator-name = "vcc28_cif";
+			regulator-always-on;
+		};
+	};
+};
-- 
1.9.0

[PATCH 3/7] ARM: dts: add i2c and regulator nodes to rk3188-radxarock

[Heiko Stübner]

From: Beniamino Galvani <b.galvani@gmail.com>

This enables the 2nd i2c bus and adds the act8846 pmic as device.

Signed-off-by: Beniamino Galvani <b.galvani@gmail.com>
Signed-off-by: Heiko Stuebner <heiko@sntech.de>
---
 arch/arm/boot/dts/rk3188-radxarock.dts | 117 
+++++++++++++++++++++++++++++++++
 1 file changed, 117 insertions(+)

diff --git a/arch/arm/boot/dts/rk3188-radxarock.dts b/arch/arm/boot/dts/rk3188-
radxarock.dts
index a5eee55..d4d9f94 100644
--- a/arch/arm/boot/dts/rk3188-radxarock.dts
+++ b/arch/arm/boot/dts/rk3188-radxarock.dts
@@ -77,5 +77,122 @@
 			};
 		};
 
+		pinctrl at 20008000 {
+			pcfg_output_low: pcfg_output_low {
+				output-low;
+			};
+
+			act8846 {
+				act8846_dvs0_ctl: act8846-dvs0-ctl {
+					rockchip,pins = <RK_GPIO3 27 RK_FUNC_GPIO 
&pcfg_output_low>;
+				};
+			};
+		};
+
+	};
+};
+
+&i2c1 {
+	pinctrl-names = "default";
+	pinctrl-0 = <&i2c1_pins>;
+
+	status = "okay";
+	clock-frequency = <400000>;
+
+	act8846: act8846 at 5a {
+		compatible = "active-semi,act8846";
+		reg = <0x5a>;
+		status = "okay";
+
+		pinctrl-names = "default";
+		pinctrl-0 = <&act8846_dvs0_ctl>;
+	};
+};
+
+&act8846 {
+	regulators {
+		vcc_ddr: REG1 {
+			regulator-name = "VCC_DDR";
+			regulator-min-microvolt = <1200000>;
+			regulator-max-microvolt = <1200000>;
+			regulator-always-on;
+		};
+
+		vdd_log: REG2 {
+			regulator-name = "VDD_LOG";
+			regulator-min-microvolt = <1000000>;
+			regulator-max-microvolt = <1000000>;
+			regulator-always-on;
+		};
+
+		vdd_arm: REG3 {
+			regulator-name = "VDD_ARM";
+			regulator-min-microvolt = <875000>;
+			regulator-max-microvolt = <1300000>;
+			regulator-always-on;
+		};
+
+		vcc_io: REG4 {
+			regulator-name = "VCC_IO";
+			regulator-min-microvolt = <3300000>;
+			regulator-max-microvolt = <3300000>;
+			regulator-always-on;
+		};
+
+		vdd_10: REG5 {
+			regulator-name = "VDD_10";
+			regulator-min-microvolt = <1000000>;
+			regulator-max-microvolt = <1000000>;
+			regulator-always-on;
+		};
+
+		vdd_hdmi: REG6 {
+			regulator-name = "VDD_HDMI";
+			regulator-min-microvolt = <2500000>;
+			regulator-max-microvolt = <2500000>;
+			regulator-always-on;
+		};
+
+		vcc18: REG7 {
+			regulator-name = "VCC_18";
+			regulator-min-microvolt = <1800000>;
+			regulator-max-microvolt = <1800000>;
+			regulator-always-on;
+		};
+
+		vcca_33: REG8 {
+			regulator-name = "VCCA_33";
+			regulator-min-microvolt = <3300000>;
+			regulator-max-microvolt = <3300000>;
+			regulator-always-on;
+		};
+
+		vcc_rmii: REG9 {
+			regulator-name = "VCC_RMII";
+			regulator-min-microvolt = <3300000>;
+			regulator-max-microvolt = <3300000>;
+			regulator-always-on;
+		};
+
+		vccio_wl: REG10 {
+			regulator-name = "VCCIO_WL";
+			regulator-min-microvolt = <3300000>;
+			regulator-max-microvolt = <3300000>;
+			regulator-always-on;
+		};
+
+		vcc_18: REG11 {
+			regulator-name = "VCC18_IO";
+			regulator-min-microvolt = <1800000>;
+			regulator-max-microvolt = <1800000>;
+			regulator-always-on;
+		};
+
+		vcc28: REG12 {
+			regulator-name = "VCC_28";
+			regulator-min-microvolt = <2800000>;
+			regulator-max-microvolt = <2800000>;
+			regulator-always-on;
+		};
 	};
 };
-- 
1.9.0

[PATCH 4/7] ARM: dts: rk3188-radxarock: enable sd-card slot

[Heiko Stübner]

The Radxa Rock contains one sd-card slot. Add the supplying regulator
and enable its dw_mmc node.

Signed-off-by: Heiko Stuebner <heiko@sntech.de>
---
 arch/arm/boot/dts/rk3188-radxarock.dts | 25 +++++++++++++++++++++++++
 1 file changed, 25 insertions(+)

diff --git a/arch/arm/boot/dts/rk3188-radxarock.dts b/arch/arm/boot/dts/rk3188-radxarock.dts
index d4d9f94..f277237 100644
--- a/arch/arm/boot/dts/rk3188-radxarock.dts
+++ b/arch/arm/boot/dts/rk3188-radxarock.dts
@@ -42,6 +42,16 @@
 			status = "okay";
 		};
 
+		vcc_sd0: sdmmc-regulator {
+			compatible = "regulator-fixed";
+			regulator-name = "sdmmc-supply";
+			regulator-min-microvolt = <3300000>;
+			regulator-max-microvolt = <3300000>;
+			gpio = <&gpio3 1 GPIO_ACTIVE_LOW>;
+			startup-delay-us = <100000>;
+			vin-supply = <&vcc_io>;
+		};
+
 		gpio-keys {
 			compatible = "gpio-keys";
 			#address-cells = <1>;
@@ -77,6 +87,21 @@
 			};
 		};
 
+		dwmmc at 10214000 {
+			num-slots = <1>;
+			status = "okay";
+
+			pinctrl-names = "default";
+			pinctrl-0 = <&sd0_clk &sd0_cmd &sd0_cd &sd0_bus4>;
+			vmmc-supply = <&vcc_sd0>;
+
+			slot at 0 {
+				reg = <0>;
+				bus-width = <4>;
+				disable-wp;
+			};
+		};
+
 		pinctrl at 20008000 {
 			pcfg_output_low: pcfg_output_low {
 				output-low;
-- 
1.9.0

[PATCH 5/7] ARM: dts: rockchip: add both clocks to uart nodes

[Heiko Stübner]

Use the newly ammended dw_8250 clock binding to define both the baudclk as
well as the pclk supplying the ip.

Signed-off-by: Heiko Stuebner <heiko@sntech.de>
---
 arch/arm/boot/dts/rk3xxx.dtsi | 12 ++++++++----
 1 file changed, 8 insertions(+), 4 deletions(-)

diff --git a/arch/arm/boot/dts/rk3xxx.dtsi b/arch/arm/boot/dts/rk3xxx.dtsi
index 86062a0..8b083e8 100644
--- a/arch/arm/boot/dts/rk3xxx.dtsi
+++ b/arch/arm/boot/dts/rk3xxx.dtsi
@@ -90,7 +90,8 @@
 			interrupts = <GIC_SPI 34 IRQ_TYPE_LEVEL_HIGH>;
 			reg-shift = <2>;
 			reg-io-width = <1>;
-			clocks = <&cru SCLK_UART0>;
+			clock-names = "baudclk", "apb_pclk";
+			clocks = <&cru SCLK_UART0>, <&cru PCLK_UART0>;
 			status = "disabled";
 		};
 
@@ -100,7 +101,8 @@
 			interrupts = <GIC_SPI 35 IRQ_TYPE_LEVEL_HIGH>;
 			reg-shift = <2>;
 			reg-io-width = <1>;
-			clocks = <&cru SCLK_UART1>;
+			clock-names = "baudclk", "apb_pclk";
+			clocks = <&cru SCLK_UART1>, <&cru PCLK_UART1>;
 			status = "disabled";
 		};
 
@@ -110,7 +112,8 @@
 			interrupts = <GIC_SPI 36 IRQ_TYPE_LEVEL_HIGH>;
 			reg-shift = <2>;
 			reg-io-width = <1>;
-			clocks = <&cru SCLK_UART2>;
+			clock-names = "baudclk", "apb_pclk";
+			clocks = <&cru SCLK_UART2>, <&cru PCLK_UART2>;
 			status = "disabled";
 		};
 
@@ -120,7 +123,8 @@
 			interrupts = <GIC_SPI 37 IRQ_TYPE_LEVEL_HIGH>;
 			reg-shift = <2>;
 			reg-io-width = <1>;
-			clocks = <&cru SCLK_UART3>;
+			clock-names = "baudclk", "apb_pclk";
+			clocks = <&cru SCLK_UART3>, <&cru PCLK_UART3>;
 			status = "disabled";
 		};
 
-- 
1.9.0

[PATCH 6/7] ARM: dts: rockchip: add pwm nodes

[Heiko Stübner]

From: Beniamino Galvani <b.galvani@gmail.com>

This adds the necessary nodex and pinctrl settings for the Rockchip PWM-driver.

Signed-off-by: Beniamino Galvani <b.galvani@gmail.com>

Modified to use the new clock defines and added rk3066 pins.
Signed-off-by: Heiko Stuebner <heiko@sntech.de>
---
 arch/arm/boot/dts/rk3066a.dtsi | 24 ++++++++++++++++++++++++
 arch/arm/boot/dts/rk3188.dtsi  | 24 ++++++++++++++++++++++++
 arch/arm/boot/dts/rk3xxx.dtsi  | 32 ++++++++++++++++++++++++++++++++
 3 files changed, 80 insertions(+)

diff --git a/arch/arm/boot/dts/rk3066a.dtsi b/arch/arm/boot/dts/rk3066a.dtsi
index 3cfdb43..e8bbc29 100644
--- a/arch/arm/boot/dts/rk3066a.dtsi
+++ b/arch/arm/boot/dts/rk3066a.dtsi
@@ -216,6 +216,30 @@
 				};
 			};
 
+			pwm0 {
+				pwm0_pins: pwm0-pins {
+					rockchip,pins = <RK_GPIO0 3 RK_FUNC_1 &pcfg_pull_none>;
+				};
+			};
+
+			pwm1 {
+				pwm1_pins: pwm1-pins {
+					rockchip,pins = <RK_GPIO0 4 RK_FUNC_1 &pcfg_pull_none>;
+				};
+			};
+
+			pwm2 {
+				pwm2_pins: pwm2-pins {
+					rockchip,pins = <RK_GPIO0 30 RK_FUNC_1 &pcfg_pull_none>;
+				};
+			};
+
+			pwm3 {
+				pwm3_pins: pwm3-pins {
+					rockchip,pins = <RK_GPIO0 31 RK_FUNC_1 &pcfg_pull_none>;
+				};
+			};
+
 			uart0 {
 				uart0_xfer: uart0-xfer {
 					rockchip,pins = <RK_GPIO1 0 RK_FUNC_1 &pcfg_pull_default>,
diff --git a/arch/arm/boot/dts/rk3188.dtsi b/arch/arm/boot/dts/rk3188.dtsi
index fc3b0dd..004353d 100644
--- a/arch/arm/boot/dts/rk3188.dtsi
+++ b/arch/arm/boot/dts/rk3188.dtsi
@@ -191,6 +191,30 @@
 				};
 			};
 
+			pwm0 {
+				pwm0_pins: pwm0-pins {
+					rockchip,pins = <RK_GPIO3 27 RK_FUNC_1 &pcfg_pull_none>;
+				};
+			};
+
+			pwm1 {
+				pwm1_pins: pwm1-pins {
+					rockchip,pins = <RK_GPIO3 28 RK_FUNC_1 &pcfg_pull_none>;
+				};
+			};
+
+			pwm2 {
+				pwm2_pins: pwm2-pins {
+					rockchip,pins = <RK_GPIO3 29 RK_FUNC_1 &pcfg_pull_none>;
+				};
+			};
+
+			pwm3 {
+				pwm3_pins: pwm3-pins {
+					rockchip,pins = <RK_GPIO3 30 RK_FUNC_1 &pcfg_pull_none>;
+				};
+			};
+
 			uart0 {
 				uart0_xfer: uart0-xfer {
 					rockchip,pins = <RK_GPIO1 0 RK_FUNC_1 &pcfg_pull_up>,
diff --git a/arch/arm/boot/dts/rk3xxx.dtsi b/arch/arm/boot/dts/rk3xxx.dtsi
index 8b083e8..1623e21 100644
--- a/arch/arm/boot/dts/rk3xxx.dtsi
+++ b/arch/arm/boot/dts/rk3xxx.dtsi
@@ -229,5 +229,37 @@
 
 			status = "disabled";
 		};
+
+		pwm0: pwm at 20030000 {
+			compatible = "rockchip,rk2928-pwm";
+			reg = <0x20030000 0x10>;
+			#pwm-cells = <2>;
+			clocks = <&cru PCLK_PWM01>;
+			status = "disabled";
+		};
+
+		pwm1: pwm at 20030010 {
+			compatible = "rockchip,rk2928-pwm";
+			reg = <0x20030010 0x10>;
+			#pwm-cells = <2>;
+			clocks = <&cru PCLK_PWM01>;
+			status = "disabled";
+		};
+
+		pwm2: pwm at 20050020 {
+			compatible = "rockchip,rk2928-pwm";
+			reg = <0x20050020 0x10>;
+			#pwm-cells = <2>;
+			clocks = <&cru PCLK_PWM23>;
+			status = "disabled";
+		};
+
+		pwm3: pwm at 20050030 {
+			compatible = "rockchip,rk2928-pwm";
+			reg = <0x20050030 0x10>;
+			#pwm-cells = <2>;
+			clocks = <&cru PCLK_PWM23>;
+			status = "disabled";
+		};
 	};
 };
-- 
1.9.0

[PATCH 7/7] ARM: dts: rockchip: add saradc nodes

[Heiko Stübner]

This adds devicetree nodes for the SAR A/D converter including the board
specific regulator references for the two boards currently supported.

Signed-off-by: Heiko Stuebner <heiko@sntech.de>
---
 arch/arm/boot/dts/rk3066a-bqcurie2.dts |  5 +++++
 arch/arm/boot/dts/rk3188-radxarock.dts |  5 +++++
 arch/arm/boot/dts/rk3xxx.dtsi          | 11 +++++++++++
 3 files changed, 21 insertions(+)

diff --git a/arch/arm/boot/dts/rk3066a-bqcurie2.dts b/arch/arm/boot/dts/rk3066a-bqcurie2.dts
index 4174ff8..d90a058 100644
--- a/arch/arm/boot/dts/rk3066a-bqcurie2.dts
+++ b/arch/arm/boot/dts/rk3066a-bqcurie2.dts
@@ -83,6 +83,11 @@
 			};
 		};
 
+		saradc: saradc at 2006c000 {
+			status = "okay";
+			vref-supply = <&vpll_reg>;
+		};
+
 		gpio-keys {
 			compatible = "gpio-keys";
 			#address-cells = <1>;
diff --git a/arch/arm/boot/dts/rk3188-radxarock.dts b/arch/arm/boot/dts/rk3188-radxarock.dts
index f277237..19d45b4 100644
--- a/arch/arm/boot/dts/rk3188-radxarock.dts
+++ b/arch/arm/boot/dts/rk3188-radxarock.dts
@@ -52,6 +52,11 @@
 			vin-supply = <&vcc_io>;
 		};
 
+		saradc: saradc at 2006c000 {
+			status = "okay";
+			vref-supply = <&vcc18>;
+		};
+
 		gpio-keys {
 			compatible = "gpio-keys";
 			#address-cells = <1>;
diff --git a/arch/arm/boot/dts/rk3xxx.dtsi b/arch/arm/boot/dts/rk3xxx.dtsi
index 1623e21..69d866a 100644
--- a/arch/arm/boot/dts/rk3xxx.dtsi
+++ b/arch/arm/boot/dts/rk3xxx.dtsi
@@ -261,5 +261,16 @@
 			clocks = <&cru PCLK_PWM23>;
 			status = "disabled";
 		};
+
+		saradc at 2006c000 {
+			compatible = "rockchip,saradc";
+			reg = <0x2006c000 0x100>;
+			interrupts = <GIC_SPI 26 IRQ_TYPE_LEVEL_HIGH>;
+			clocks = <&cru SCLK_SARADC>, <&cru PCLK_SARADC>;
+			clock-names = "saradc", "apb_pclk";
+			#io-channel-cells = <1>;
+			clock-frequency = <1000000>;
+			status = "disabled";
+		};
 	};
 };
-- 
1.9.0