[PATCH 0/5] Power Related Fixes for Exynos5250

[PATCH 0/5] Power Related Fixes for Exynos5250

[Abhilash Kesavan]

Patch 1 prevents the gating of sysreg clock on Exynos5250.
Patch 2 is a re-send of an earlier patch.
(http://www.spinics.net/lists/linux-samsung-soc/msg15485.html)
Patches 3 and 4 are fixes for MAX77686 on Exynos5250 based Snow
board (boot-up issues).
Patch 5 implements a power-off call-back for Exynos5250 that can
be re-used for Exynos5420.

The patches have been tested on an SMDK5250 based Chromebook.

Abhilash Kesavan (4):
  clk: samsung: exynos5250: Add CLK_IGNORE_UNUSED flag for the sysreg
    clock
  ARM: EXYNOS5: Fix PMU register configuration for local power blocks
  clk: max77686: Replace is_enabled() with is_prepared call-back
  ARM: dts: Setup the interrupt parent for max77686

Olof Johansson (1):
  ARM: EXYNOS5250: Implement pm_power_off

 arch/arm/boot/dts/cros5250-common.dtsi       |   11 ++++
 arch/arm/mach-exynos/include/mach/regs-pmu.h |    3 +
 arch/arm/mach-exynos/pmu.c                   |   86 ++++++++++++++++++++------
 drivers/clk/clk-max77686.c                   |    4 +-
 drivers/clk/samsung/clk-exynos5250.c         |    3 +-
 5 files changed, 86 insertions(+), 21 deletions(-)

-- 
1.7.9.5

[PATCH 0/5] Power Related Fixes for Exynos5250

[Abhilash Kesavan]

Patch 1 prevents the gating of sysreg clock on Exynos5250.
Patch 2 is a re-send of an earlier patch.
(http://www.spinics.net/lists/linux-samsung-soc/msg15485.html)
Patches 3 and 4 are fixes for MAX77686 on Exynos5250 based Snow
board (boot-up issues).
Patch 5 implements a power-off call-back for Exynos5250 that can
be re-used for Exynos5420.

The patches have been tested on an SMDK5250 based Chromebook.

Abhilash Kesavan (4):
  clk: samsung: exynos5250: Add CLK_IGNORE_UNUSED flag for the sysreg
    clock
  ARM: EXYNOS5: Fix PMU register configuration for local power blocks
  clk: max77686: Replace is_enabled() with is_prepared call-back
  ARM: dts: Setup the interrupt parent for max77686

Olof Johansson (1):
  ARM: EXYNOS5250: Implement pm_power_off

 arch/arm/boot/dts/cros5250-common.dtsi       |   11 ++++
 arch/arm/mach-exynos/include/mach/regs-pmu.h |    3 +
 arch/arm/mach-exynos/pmu.c                   |   86 ++++++++++++++++++++------
 drivers/clk/clk-max77686.c                   |    4 +-
 drivers/clk/samsung/clk-exynos5250.c         |    3 +-
 5 files changed, 86 insertions(+), 21 deletions(-)

-- 
1.7.9.5

[PATCH 1/5] clk: samsung: exynos5250: Add CLK_IGNORE_UNUSED flag for the sysreg clock

[Abhilash Kesavan]

The sysreg (system register) generates control signals for various blocks
like disp1blk, i2c, mipi etc. However, it gets disabled as an unused clock
at boot-up.

Signed-off-by: Abhilash Kesavan <a.kesavan@samsung.com>
---
 drivers/clk/samsung/clk-exynos5250.c |    3 ++-
 1 file changed, 2 insertions(+), 1 deletion(-)

diff --git a/drivers/clk/samsung/clk-exynos5250.c b/drivers/clk/samsung/clk-exynos5250.c
index adf3234..0833501 100644
--- a/drivers/clk/samsung/clk-exynos5250.c
+++ b/drivers/clk/samsung/clk-exynos5250.c
@@ -406,7 +406,8 @@ static struct samsung_gate_clock exynos5250_gate_clks[] __initdata = {
 	GATE(hsi2c2, "hsi2c2", "aclk66", GATE_IP_PERIC, 30, 0, 0),
 	GATE(hsi2c3, "hsi2c3", "aclk66", GATE_IP_PERIC, 31, 0, 0),
 	GATE(chipid, "chipid", "aclk66", GATE_IP_PERIS, 0, 0, 0),
-	GATE(sysreg, "sysreg", "aclk66", GATE_IP_PERIS, 1, 0, 0),
+	GATE(sysreg, "sysreg", "aclk66",
+			GATE_IP_PERIS, 1, CLK_IGNORE_UNUSED, 0),
 	GATE(pmu, "pmu", "aclk66", GATE_IP_PERIS, 2, CLK_IGNORE_UNUSED, 0),
 	GATE(tzpc0, "tzpc0", "aclk66", GATE_IP_PERIS, 6, 0, 0),
 	GATE(tzpc1, "tzpc1", "aclk66", GATE_IP_PERIS, 7, 0, 0),
-- 
1.7.9.5

[PATCH 1/5] clk: samsung: exynos5250: Add CLK_IGNORE_UNUSED flag for the sysreg clock

[Abhilash Kesavan]

The sysreg (system register) generates control signals for various blocks
like disp1blk, i2c, mipi etc. However, it gets disabled as an unused clock
at boot-up.

Signed-off-by: Abhilash Kesavan <a.kesavan@samsung.com>
---
 drivers/clk/samsung/clk-exynos5250.c |    3 ++-
 1 file changed, 2 insertions(+), 1 deletion(-)

diff --git a/drivers/clk/samsung/clk-exynos5250.c b/drivers/clk/samsung/clk-exynos5250.c
index adf3234..0833501 100644
--- a/drivers/clk/samsung/clk-exynos5250.c
+++ b/drivers/clk/samsung/clk-exynos5250.c
@@ -406,7 +406,8 @@ static struct samsung_gate_clock exynos5250_gate_clks[] __initdata = {
 	GATE(hsi2c2, "hsi2c2", "aclk66", GATE_IP_PERIC, 30, 0, 0),
 	GATE(hsi2c3, "hsi2c3", "aclk66", GATE_IP_PERIC, 31, 0, 0),
 	GATE(chipid, "chipid", "aclk66", GATE_IP_PERIS, 0, 0, 0),
-	GATE(sysreg, "sysreg", "aclk66", GATE_IP_PERIS, 1, 0, 0),
+	GATE(sysreg, "sysreg", "aclk66",
+			GATE_IP_PERIS, 1, CLK_IGNORE_UNUSED, 0),
 	GATE(pmu, "pmu", "aclk66", GATE_IP_PERIS, 2, CLK_IGNORE_UNUSED, 0),
 	GATE(tzpc0, "tzpc0", "aclk66", GATE_IP_PERIS, 6, 0, 0),
 	GATE(tzpc1, "tzpc1", "aclk66", GATE_IP_PERIS, 7, 0, 0),
-- 
1.7.9.5

Re: [PATCH 1/5] clk: samsung: exynos5250: Add CLK_IGNORE_UNUSED flag for the sysreg clock

[Doug Anderson]

Abhilash,

On Wed, Dec 11, 2013 at 3:57 AM, Abhilash Kesavan <a.kesavan@samsung.com> wrote:
> The sysreg (system register) generates control signals for various blocks
> like disp1blk, i2c, mipi etc. However, it gets disabled as an unused clock
> at boot-up.
>
> Signed-off-by: Abhilash Kesavan <a.kesavan@samsung.com>
> ---
>  drivers/clk/samsung/clk-exynos5250.c |    3 ++-
>  1 file changed, 2 insertions(+), 1 deletion(-)
>
> diff --git a/drivers/clk/samsung/clk-exynos5250.c b/drivers/clk/samsung/clk-exynos5250.c
> index adf3234..0833501 100644
> --- a/drivers/clk/samsung/clk-exynos5250.c
> +++ b/drivers/clk/samsung/clk-exynos5250.c
> @@ -406,7 +406,8 @@ static struct samsung_gate_clock exynos5250_gate_clks[] __initdata = {
>         GATE(hsi2c2, "hsi2c2", "aclk66", GATE_IP_PERIC, 30, 0, 0),
>         GATE(hsi2c3, "hsi2c3", "aclk66", GATE_IP_PERIC, 31, 0, 0),
>         GATE(chipid, "chipid", "aclk66", GATE_IP_PERIS, 0, 0, 0),
> -       GATE(sysreg, "sysreg", "aclk66", GATE_IP_PERIS, 1, 0, 0),
> +       GATE(sysreg, "sysreg", "aclk66",
> +                       GATE_IP_PERIS, 1, CLK_IGNORE_UNUSED, 0),
>         GATE(pmu, "pmu", "aclk66", GATE_IP_PERIS, 2, CLK_IGNORE_UNUSED, 0),
>         GATE(tzpc0, "tzpc0", "aclk66", GATE_IP_PERIS, 6, 0, 0),
>         GATE(tzpc1, "tzpc1", "aclk66", GATE_IP_PERIS, 7, 0, 0),

This does match what's done in exynos4 and exynos5420 and it's not
terrible.  I'm always a fan of actually specifying clocks properly and
that's more possible now using the syscon stuff (see Leela Krishna's
watchdog patches).  You'd have to extend that to add a clock, but that
wouldn't be too hard.

That being said, I'd personally be OK with this solution for now (to
match the other exynos products), so:

Reviewed-by: Doug Anderson <dianders@chromium.org>

[PATCH 1/5] clk: samsung: exynos5250: Add CLK_IGNORE_UNUSED flag for the sysreg clock

[Doug Anderson]

Abhilash,

On Wed, Dec 11, 2013 at 3:57 AM, Abhilash Kesavan <a.kesavan@samsung.com> wrote:
> The sysreg (system register) generates control signals for various blocks
> like disp1blk, i2c, mipi etc. However, it gets disabled as an unused clock
> at boot-up.
>
> Signed-off-by: Abhilash Kesavan <a.kesavan@samsung.com>
> ---
>  drivers/clk/samsung/clk-exynos5250.c |    3 ++-
>  1 file changed, 2 insertions(+), 1 deletion(-)
>
> diff --git a/drivers/clk/samsung/clk-exynos5250.c b/drivers/clk/samsung/clk-exynos5250.c
> index adf3234..0833501 100644
> --- a/drivers/clk/samsung/clk-exynos5250.c
> +++ b/drivers/clk/samsung/clk-exynos5250.c
> @@ -406,7 +406,8 @@ static struct samsung_gate_clock exynos5250_gate_clks[] __initdata = {
>         GATE(hsi2c2, "hsi2c2", "aclk66", GATE_IP_PERIC, 30, 0, 0),
>         GATE(hsi2c3, "hsi2c3", "aclk66", GATE_IP_PERIC, 31, 0, 0),
>         GATE(chipid, "chipid", "aclk66", GATE_IP_PERIS, 0, 0, 0),
> -       GATE(sysreg, "sysreg", "aclk66", GATE_IP_PERIS, 1, 0, 0),
> +       GATE(sysreg, "sysreg", "aclk66",
> +                       GATE_IP_PERIS, 1, CLK_IGNORE_UNUSED, 0),
>         GATE(pmu, "pmu", "aclk66", GATE_IP_PERIS, 2, CLK_IGNORE_UNUSED, 0),
>         GATE(tzpc0, "tzpc0", "aclk66", GATE_IP_PERIS, 6, 0, 0),
>         GATE(tzpc1, "tzpc1", "aclk66", GATE_IP_PERIS, 7, 0, 0),

This does match what's done in exynos4 and exynos5420 and it's not
terrible.  I'm always a fan of actually specifying clocks properly and
that's more possible now using the syscon stuff (see Leela Krishna's
watchdog patches).  You'd have to extend that to add a clock, but that
wouldn't be too hard.

That being said, I'd personally be OK with this solution for now (to
match the other exynos products), so:

Reviewed-by: Doug Anderson <dianders@chromium.org>

Re: [PATCH 1/5] clk: samsung: exynos5250: Add CLK_IGNORE_UNUSED flag for the sysreg clock

[Tomasz Figa]

2013/12/12 Doug Anderson <dianders@chromium.org>:
> Abhilash,
>
> On Wed, Dec 11, 2013 at 3:57 AM, Abhilash Kesavan <a.kesavan@samsung.com> wrote:
>> The sysreg (system register) generates control signals for various blocks
>> like disp1blk, i2c, mipi etc. However, it gets disabled as an unused clock
>> at boot-up.
>>
>> Signed-off-by: Abhilash Kesavan <a.kesavan@samsung.com>
>> ---
>>  drivers/clk/samsung/clk-exynos5250.c |    3 ++-
>>  1 file changed, 2 insertions(+), 1 deletion(-)
>>
>> diff --git a/drivers/clk/samsung/clk-exynos5250.c b/drivers/clk/samsung/clk-exynos5250.c
>> index adf3234..0833501 100644
>> --- a/drivers/clk/samsung/clk-exynos5250.c
>> +++ b/drivers/clk/samsung/clk-exynos5250.c
>> @@ -406,7 +406,8 @@ static struct samsung_gate_clock exynos5250_gate_clks[] __initdata = {
>>         GATE(hsi2c2, "hsi2c2", "aclk66", GATE_IP_PERIC, 30, 0, 0),
>>         GATE(hsi2c3, "hsi2c3", "aclk66", GATE_IP_PERIC, 31, 0, 0),
>>         GATE(chipid, "chipid", "aclk66", GATE_IP_PERIS, 0, 0, 0),
>> -       GATE(sysreg, "sysreg", "aclk66", GATE_IP_PERIS, 1, 0, 0),
>> +       GATE(sysreg, "sysreg", "aclk66",
>> +                       GATE_IP_PERIS, 1, CLK_IGNORE_UNUSED, 0),
>>         GATE(pmu, "pmu", "aclk66", GATE_IP_PERIS, 2, CLK_IGNORE_UNUSED, 0),
>>         GATE(tzpc0, "tzpc0", "aclk66", GATE_IP_PERIS, 6, 0, 0),
>>         GATE(tzpc1, "tzpc1", "aclk66", GATE_IP_PERIS, 7, 0, 0),
>
> This does match what's done in exynos4 and exynos5420 and it's not
> terrible.  I'm always a fan of actually specifying clocks properly and
> that's more possible now using the syscon stuff (see Leela Krishna's
> watchdog patches).  You'd have to extend that to add a clock, but that
> wouldn't be too hard.

Leela's patches are about PMU, not sysreg, but that's not an issue, I guess,
as it's about adding a clock to the generic syscon driver.

Still, I discussed about such cases as this with Sylwester a bit today and
maybe a bit different approach would be better. There is a number of clocks
that need to be always on, such as PMU (but also a lot of currently undefined
ones). IMHO it would be nice to make sure they are enabled at boot time
and do one of following:
1) claim and enable them directly from the clock controller driver
2) define them with CLK_IGNORE_UNUSED flag and enable them directly from
   the clock controller driver (without increasing the refcount, so users could
   possibly disable them later),
3) add a generic flag, such as CLK_BOOT_ENABLE (or something), that would
   make the CCF enable such clock at bootup (in addition to implying
   CLK_IGNORE_UNUSED).

For me, the most sensible option would be 2) as it doesn't bloat the CCF with
yet another flag and doesn't encourage people to leave clocks always on
just because of laziness stopping them from implementing proper clock
support in drivers.

Still, for now, it's an OK from me, as we don't have the infrastructure yet.

Reviewed-by: Tomasz Figa <t.figa@samsung.com>

Best regards,
Tomasz

[PATCH 1/5] clk: samsung: exynos5250: Add CLK_IGNORE_UNUSED flag for the sysreg clock

[Tomasz Figa]

2013/12/12 Doug Anderson <dianders@chromium.org>:
> Abhilash,
>
> On Wed, Dec 11, 2013 at 3:57 AM, Abhilash Kesavan <a.kesavan@samsung.com> wrote:
>> The sysreg (system register) generates control signals for various blocks
>> like disp1blk, i2c, mipi etc. However, it gets disabled as an unused clock
>> at boot-up.
>>
>> Signed-off-by: Abhilash Kesavan <a.kesavan@samsung.com>
>> ---
>>  drivers/clk/samsung/clk-exynos5250.c |    3 ++-
>>  1 file changed, 2 insertions(+), 1 deletion(-)
>>
>> diff --git a/drivers/clk/samsung/clk-exynos5250.c b/drivers/clk/samsung/clk-exynos5250.c
>> index adf3234..0833501 100644
>> --- a/drivers/clk/samsung/clk-exynos5250.c
>> +++ b/drivers/clk/samsung/clk-exynos5250.c
>> @@ -406,7 +406,8 @@ static struct samsung_gate_clock exynos5250_gate_clks[] __initdata = {
>>         GATE(hsi2c2, "hsi2c2", "aclk66", GATE_IP_PERIC, 30, 0, 0),
>>         GATE(hsi2c3, "hsi2c3", "aclk66", GATE_IP_PERIC, 31, 0, 0),
>>         GATE(chipid, "chipid", "aclk66", GATE_IP_PERIS, 0, 0, 0),
>> -       GATE(sysreg, "sysreg", "aclk66", GATE_IP_PERIS, 1, 0, 0),
>> +       GATE(sysreg, "sysreg", "aclk66",
>> +                       GATE_IP_PERIS, 1, CLK_IGNORE_UNUSED, 0),
>>         GATE(pmu, "pmu", "aclk66", GATE_IP_PERIS, 2, CLK_IGNORE_UNUSED, 0),
>>         GATE(tzpc0, "tzpc0", "aclk66", GATE_IP_PERIS, 6, 0, 0),
>>         GATE(tzpc1, "tzpc1", "aclk66", GATE_IP_PERIS, 7, 0, 0),
>
> This does match what's done in exynos4 and exynos5420 and it's not
> terrible.  I'm always a fan of actually specifying clocks properly and
> that's more possible now using the syscon stuff (see Leela Krishna's
> watchdog patches).  You'd have to extend that to add a clock, but that
> wouldn't be too hard.

Leela's patches are about PMU, not sysreg, but that's not an issue, I guess,
as it's about adding a clock to the generic syscon driver.

Still, I discussed about such cases as this with Sylwester a bit today and
maybe a bit different approach would be better. There is a number of clocks
that need to be always on, such as PMU (but also a lot of currently undefined
ones). IMHO it would be nice to make sure they are enabled at boot time
and do one of following:
1) claim and enable them directly from the clock controller driver
2) define them with CLK_IGNORE_UNUSED flag and enable them directly from
   the clock controller driver (without increasing the refcount, so users could
   possibly disable them later),
3) add a generic flag, such as CLK_BOOT_ENABLE (or something), that would
   make the CCF enable such clock at bootup (in addition to implying
   CLK_IGNORE_UNUSED).

For me, the most sensible option would be 2) as it doesn't bloat the CCF with
yet another flag and doesn't encourage people to leave clocks always on
just because of laziness stopping them from implementing proper clock
support in drivers.

Still, for now, it's an OK from me, as we don't have the infrastructure yet.

Reviewed-by: Tomasz Figa <t.figa@samsung.com>

Best regards,
Tomasz

Re: [PATCH 1/5] clk: samsung: exynos5250: Add CLK_IGNORE_UNUSED flag for the sysreg clock

[Doug Anderson]

Tomasz,

On Wed, Dec 11, 2013 at 4:13 PM, Tomasz Figa <tomasz.figa@gmail.com> wrote:
> 2013/12/12 Doug Anderson <dianders@chromium.org>:
>> This does match what's done in exynos4 and exynos5420 and it's not
>> terrible.  I'm always a fan of actually specifying clocks properly and
>> that's more possible now using the syscon stuff (see Leela Krishna's
>> watchdog patches).  You'd have to extend that to add a clock, but that
>> wouldn't be too hard.
>
> Leela's patches are about PMU, not sysreg, but that's not an issue, I guess,
> as it's about adding a clock to the generic syscon driver.

Right.  I was proposing doing something similar to his, but for the
separate "sysreg" address range.  ...then adding a clock to the
generic syscon driver.

I _think_ the syscon clock doesn't really need to be always on--it
only needs to be on during the access of these registers, right?  I
make this statement based on the fact that exynos5250 boards currently
bootup and are very functional, but this clock is currently off.


> Still, I discussed about such cases as this with Sylwester a bit today and
> maybe a bit different approach would be better. There is a number of clocks
> that need to be always on, such as PMU (but also a lot of currently undefined
> ones). IMHO it would be nice to make sure they are enabled at boot time
> and do one of following:
> 1) claim and enable them directly from the clock controller driver
> 2) define them with CLK_IGNORE_UNUSED flag and enable them directly from
>    the clock controller driver (without increasing the refcount, so users could
>    possibly disable them later),
> 3) add a generic flag, such as CLK_BOOT_ENABLE (or something), that would
>    make the CCF enable such clock at bootup (in addition to implying
>    CLK_IGNORE_UNUSED).
>
> For me, the most sensible option would be 2) as it doesn't bloat the CCF with
> yet another flag and doesn't encourage people to leave clocks always on
> just because of laziness stopping them from implementing proper clock
> support in drivers.

Right, we're using #2 for this now, but one problem is that it's
possible that the firmware may turn off one of these misc-type clocks.
 On exynos5250-snow we ran into this.  The firmware actually gates the
clock needed for accessing the chip_id, though perhaps that's not one
of the clocks that needs to be on all the time.

-Doug

[PATCH 1/5] clk: samsung: exynos5250: Add CLK_IGNORE_UNUSED flag for the sysreg clock

[Doug Anderson]

Tomasz,

On Wed, Dec 11, 2013 at 4:13 PM, Tomasz Figa <tomasz.figa@gmail.com> wrote:
> 2013/12/12 Doug Anderson <dianders@chromium.org>:
>> This does match what's done in exynos4 and exynos5420 and it's not
>> terrible.  I'm always a fan of actually specifying clocks properly and
>> that's more possible now using the syscon stuff (see Leela Krishna's
>> watchdog patches).  You'd have to extend that to add a clock, but that
>> wouldn't be too hard.
>
> Leela's patches are about PMU, not sysreg, but that's not an issue, I guess,
> as it's about adding a clock to the generic syscon driver.

Right.  I was proposing doing something similar to his, but for the
separate "sysreg" address range.  ...then adding a clock to the
generic syscon driver.

I _think_ the syscon clock doesn't really need to be always on--it
only needs to be on during the access of these registers, right?  I
make this statement based on the fact that exynos5250 boards currently
bootup and are very functional, but this clock is currently off.


> Still, I discussed about such cases as this with Sylwester a bit today and
> maybe a bit different approach would be better. There is a number of clocks
> that need to be always on, such as PMU (but also a lot of currently undefined
> ones). IMHO it would be nice to make sure they are enabled at boot time
> and do one of following:
> 1) claim and enable them directly from the clock controller driver
> 2) define them with CLK_IGNORE_UNUSED flag and enable them directly from
>    the clock controller driver (without increasing the refcount, so users could
>    possibly disable them later),
> 3) add a generic flag, such as CLK_BOOT_ENABLE (or something), that would
>    make the CCF enable such clock at bootup (in addition to implying
>    CLK_IGNORE_UNUSED).
>
> For me, the most sensible option would be 2) as it doesn't bloat the CCF with
> yet another flag and doesn't encourage people to leave clocks always on
> just because of laziness stopping them from implementing proper clock
> support in drivers.

Right, we're using #2 for this now, but one problem is that it's
possible that the firmware may turn off one of these misc-type clocks.
 On exynos5250-snow we ran into this.  The firmware actually gates the
clock needed for accessing the chip_id, though perhaps that's not one
of the clocks that needs to be on all the time.

-Doug

Re: [PATCH 1/5] clk: samsung: exynos5250: Add CLK_IGNORE_UNUSED flag for the sysreg clock

[Abhilash Kesavan]

Hi Tomasz and Doug,

Thanks for the review.
On Thu, Dec 12, 2013 at 6:00 AM, Doug Anderson <dianders@chromium.org> wrote:
> Tomasz,
>
> On Wed, Dec 11, 2013 at 4:13 PM, Tomasz Figa <tomasz.figa@gmail.com> wrote:
>> 2013/12/12 Doug Anderson <dianders@chromium.org>:
>>> This does match what's done in exynos4 and exynos5420 and it's not
>>> terrible.  I'm always a fan of actually specifying clocks properly and
>>> that's more possible now using the syscon stuff (see Leela Krishna's
>>> watchdog patches).  You'd have to extend that to add a clock, but that
>>> wouldn't be too hard.
>>
>> Leela's patches are about PMU, not sysreg, but that's not an issue, I guess,
>> as it's about adding a clock to the generic syscon driver.
>
> Right.  I was proposing doing something similar to his, but for the
> separate "sysreg" address range.  ...then adding a clock to the
> generic syscon driver.
>
> I _think_ the syscon clock doesn't really need to be always on--it
> only needs to be on during the access of these registers, right?  I
> make this statement based on the fact that exynos5250 boards currently
> bootup and are very functional, but this clock is currently off.
I see USB2 currently using sysreg at boot-up, so I would assume that
it would fail if we have this clock turned off by the firmware. Have
not tested yet.
>
>
>> Still, I discussed about such cases as this with Sylwester a bit today and
>> maybe a bit different approach would be better. There is a number of clocks
>> that need to be always on, such as PMU (but also a lot of currently undefined
>> ones). IMHO it would be nice to make sure they are enabled at boot time
>> and do one of following:
>> 1) claim and enable them directly from the clock controller driver
>> 2) define them with CLK_IGNORE_UNUSED flag and enable them directly from
>>    the clock controller driver (without increasing the refcount, so users could
>>    possibly disable them later),
>> 3) add a generic flag, such as CLK_BOOT_ENABLE (or something), that would
>>    make the CCF enable such clock at bootup (in addition to implying
>>    CLK_IGNORE_UNUSED).
>>
>> For me, the most sensible option would be 2) as it doesn't bloat the CCF with
>> yet another flag and doesn't encourage people to leave clocks always on
>> just because of laziness stopping them from implementing proper clock
>> support in drivers.
>
> Right, we're using #2 for this now, but one problem is that it's
> possible that the firmware may turn off one of these misc-type clocks.
>  On exynos5250-snow we ran into this.  The firmware actually gates the
> clock needed for accessing the chip_id, though perhaps that's not one
> of the clocks that needs to be on all the time.

Yes, If the firmware gates sysreg then we should see failures at
boot-up or later.
Is this patch OK for now ? How would you guys like me to proceed on this ?
>
> -Doug

Regards,
Abhilash
>
> _______________________________________________
> linux-arm-kernel mailing list
> linux-arm-kernel@lists.infradead.org
> http://lists.infradead.org/mailman/listinfo/linux-arm-kernel

[PATCH 1/5] clk: samsung: exynos5250: Add CLK_IGNORE_UNUSED flag for the sysreg clock

[Abhilash Kesavan]

Hi Tomasz and Doug,

Thanks for the review.
On Thu, Dec 12, 2013 at 6:00 AM, Doug Anderson <dianders@chromium.org> wrote:
> Tomasz,
>
> On Wed, Dec 11, 2013 at 4:13 PM, Tomasz Figa <tomasz.figa@gmail.com> wrote:
>> 2013/12/12 Doug Anderson <dianders@chromium.org>:
>>> This does match what's done in exynos4 and exynos5420 and it's not
>>> terrible.  I'm always a fan of actually specifying clocks properly and
>>> that's more possible now using the syscon stuff (see Leela Krishna's
>>> watchdog patches).  You'd have to extend that to add a clock, but that
>>> wouldn't be too hard.
>>
>> Leela's patches are about PMU, not sysreg, but that's not an issue, I guess,
>> as it's about adding a clock to the generic syscon driver.
>
> Right.  I was proposing doing something similar to his, but for the
> separate "sysreg" address range.  ...then adding a clock to the
> generic syscon driver.
>
> I _think_ the syscon clock doesn't really need to be always on--it
> only needs to be on during the access of these registers, right?  I
> make this statement based on the fact that exynos5250 boards currently
> bootup and are very functional, but this clock is currently off.
I see USB2 currently using sysreg at boot-up, so I would assume that
it would fail if we have this clock turned off by the firmware. Have
not tested yet.
>
>
>> Still, I discussed about such cases as this with Sylwester a bit today and
>> maybe a bit different approach would be better. There is a number of clocks
>> that need to be always on, such as PMU (but also a lot of currently undefined
>> ones). IMHO it would be nice to make sure they are enabled at boot time
>> and do one of following:
>> 1) claim and enable them directly from the clock controller driver
>> 2) define them with CLK_IGNORE_UNUSED flag and enable them directly from
>>    the clock controller driver (without increasing the refcount, so users could
>>    possibly disable them later),
>> 3) add a generic flag, such as CLK_BOOT_ENABLE (or something), that would
>>    make the CCF enable such clock at bootup (in addition to implying
>>    CLK_IGNORE_UNUSED).
>>
>> For me, the most sensible option would be 2) as it doesn't bloat the CCF with
>> yet another flag and doesn't encourage people to leave clocks always on
>> just because of laziness stopping them from implementing proper clock
>> support in drivers.
>
> Right, we're using #2 for this now, but one problem is that it's
> possible that the firmware may turn off one of these misc-type clocks.
>  On exynos5250-snow we ran into this.  The firmware actually gates the
> clock needed for accessing the chip_id, though perhaps that's not one
> of the clocks that needs to be on all the time.

Yes, If the firmware gates sysreg then we should see failures at
boot-up or later.
Is this patch OK for now ? How would you guys like me to proceed on this ?
>
> -Doug

Regards,
Abhilash
>
> _______________________________________________
> linux-arm-kernel mailing list
> linux-arm-kernel at lists.infradead.org
> http://lists.infradead.org/mailman/listinfo/linux-arm-kernel

Re: [PATCH 1/5] clk: samsung: exynos5250: Add CLK_IGNORE_UNUSED flag for the sysreg clock

[Tomasz Figa]

On Thursday 12 of December 2013 10:06:36 Abhilash Kesavan wrote:
> Hi Tomasz and Doug,
> 
> Thanks for the review.
> On Thu, Dec 12, 2013 at 6:00 AM, Doug Anderson <dianders@chromium.org> wrote:
> > Tomasz,
> >
> > On Wed, Dec 11, 2013 at 4:13 PM, Tomasz Figa <tomasz.figa@gmail.com> wrote:
[snip]
> >> Still, I discussed about such cases as this with Sylwester a bit today and
> >> maybe a bit different approach would be better. There is a number of clocks
> >> that need to be always on, such as PMU (but also a lot of currently undefined
> >> ones). IMHO it would be nice to make sure they are enabled at boot time
> >> and do one of following:
> >> 1) claim and enable them directly from the clock controller driver
> >> 2) define them with CLK_IGNORE_UNUSED flag and enable them directly from
> >>    the clock controller driver (without increasing the refcount, so users could
> >>    possibly disable them later),
> >> 3) add a generic flag, such as CLK_BOOT_ENABLE (or something), that would
> >>    make the CCF enable such clock at bootup (in addition to implying
> >>    CLK_IGNORE_UNUSED).
> >>
> >> For me, the most sensible option would be 2) as it doesn't bloat the CCF with
> >> yet another flag and doesn't encourage people to leave clocks always on
> >> just because of laziness stopping them from implementing proper clock
> >> support in drivers.
> >
> > Right, we're using #2 for this now, but one problem is that it's
> > possible that the firmware may turn off one of these misc-type clocks.
> >  On exynos5250-snow we ran into this.  The firmware actually gates the
> > clock needed for accessing the chip_id, though perhaps that's not one
> > of the clocks that needs to be on all the time.
> 
> Yes, If the firmware gates sysreg then we should see failures at
> boot-up or later.
> Is this patch OK for now ? How would you guys like me to proceed on this ?

Yes, as I wrote in my original reply, for now your patch is fine as we
don't have the infrastructure for handling such clocks in a stricter
way yet.

Best regards,
Tomasz

[PATCH 1/5] clk: samsung: exynos5250: Add CLK_IGNORE_UNUSED flag for the sysreg clock

[Tomasz Figa]

On Thursday 12 of December 2013 10:06:36 Abhilash Kesavan wrote:
> Hi Tomasz and Doug,
> 
> Thanks for the review.
> On Thu, Dec 12, 2013 at 6:00 AM, Doug Anderson <dianders@chromium.org> wrote:
> > Tomasz,
> >
> > On Wed, Dec 11, 2013 at 4:13 PM, Tomasz Figa <tomasz.figa@gmail.com> wrote:
[snip]
> >> Still, I discussed about such cases as this with Sylwester a bit today and
> >> maybe a bit different approach would be better. There is a number of clocks
> >> that need to be always on, such as PMU (but also a lot of currently undefined
> >> ones). IMHO it would be nice to make sure they are enabled at boot time
> >> and do one of following:
> >> 1) claim and enable them directly from the clock controller driver
> >> 2) define them with CLK_IGNORE_UNUSED flag and enable them directly from
> >>    the clock controller driver (without increasing the refcount, so users could
> >>    possibly disable them later),
> >> 3) add a generic flag, such as CLK_BOOT_ENABLE (or something), that would
> >>    make the CCF enable such clock at bootup (in addition to implying
> >>    CLK_IGNORE_UNUSED).
> >>
> >> For me, the most sensible option would be 2) as it doesn't bloat the CCF with
> >> yet another flag and doesn't encourage people to leave clocks always on
> >> just because of laziness stopping them from implementing proper clock
> >> support in drivers.
> >
> > Right, we're using #2 for this now, but one problem is that it's
> > possible that the firmware may turn off one of these misc-type clocks.
> >  On exynos5250-snow we ran into this.  The firmware actually gates the
> > clock needed for accessing the chip_id, though perhaps that's not one
> > of the clocks that needs to be on all the time.
> 
> Yes, If the firmware gates sysreg then we should see failures at
> boot-up or later.
> Is this patch OK for now ? How would you guys like me to proceed on this ?

Yes, as I wrote in my original reply, for now your patch is fine as we
don't have the infrastructure for handling such clocks in a stricter
way yet.

Best regards,
Tomasz

Re: [PATCH 1/5] clk: samsung: exynos5250: Add CLK_IGNORE_UNUSED flag for the sysreg clock

[Tomasz Figa]

On Wednesday 11 of December 2013 17:27:05 Abhilash Kesavan wrote:
> The sysreg (system register) generates control signals for various blocks
> like disp1blk, i2c, mipi etc. However, it gets disabled as an unused clock
> at boot-up.
> 
> Signed-off-by: Abhilash Kesavan <a.kesavan@samsung.com>
> ---
>  drivers/clk/samsung/clk-exynos5250.c |    3 ++-
>  1 file changed, 2 insertions(+), 1 deletion(-)
> 
> diff --git a/drivers/clk/samsung/clk-exynos5250.c b/drivers/clk/samsung/clk-exynos5250.c
> index adf3234..0833501 100644
> --- a/drivers/clk/samsung/clk-exynos5250.c
> +++ b/drivers/clk/samsung/clk-exynos5250.c
> @@ -406,7 +406,8 @@ static struct samsung_gate_clock exynos5250_gate_clks[] __initdata = {
>  	GATE(hsi2c2, "hsi2c2", "aclk66", GATE_IP_PERIC, 30, 0, 0),
>  	GATE(hsi2c3, "hsi2c3", "aclk66", GATE_IP_PERIC, 31, 0, 0),
>  	GATE(chipid, "chipid", "aclk66", GATE_IP_PERIS, 0, 0, 0),
> -	GATE(sysreg, "sysreg", "aclk66", GATE_IP_PERIS, 1, 0, 0),
> +	GATE(sysreg, "sysreg", "aclk66",
> +			GATE_IP_PERIS, 1, CLK_IGNORE_UNUSED, 0),
>  	GATE(pmu, "pmu", "aclk66", GATE_IP_PERIS, 2, CLK_IGNORE_UNUSED, 0),
>  	GATE(tzpc0, "tzpc0", "aclk66", GATE_IP_PERIS, 6, 0, 0),
>  	GATE(tzpc1, "tzpc1", "aclk66", GATE_IP_PERIS, 7, 0, 0),
> 

Applied to samsung-clk tree, since this patch seems not to depend or be
a dependency of other patches.

Best regards,
Tomasz

[PATCH 1/5] clk: samsung: exynos5250: Add CLK_IGNORE_UNUSED flag for the sysreg clock

[Tomasz Figa]

On Wednesday 11 of December 2013 17:27:05 Abhilash Kesavan wrote:
> The sysreg (system register) generates control signals for various blocks
> like disp1blk, i2c, mipi etc. However, it gets disabled as an unused clock
> at boot-up.
> 
> Signed-off-by: Abhilash Kesavan <a.kesavan@samsung.com>
> ---
>  drivers/clk/samsung/clk-exynos5250.c |    3 ++-
>  1 file changed, 2 insertions(+), 1 deletion(-)
> 
> diff --git a/drivers/clk/samsung/clk-exynos5250.c b/drivers/clk/samsung/clk-exynos5250.c
> index adf3234..0833501 100644
> --- a/drivers/clk/samsung/clk-exynos5250.c
> +++ b/drivers/clk/samsung/clk-exynos5250.c
> @@ -406,7 +406,8 @@ static struct samsung_gate_clock exynos5250_gate_clks[] __initdata = {
>  	GATE(hsi2c2, "hsi2c2", "aclk66", GATE_IP_PERIC, 30, 0, 0),
>  	GATE(hsi2c3, "hsi2c3", "aclk66", GATE_IP_PERIC, 31, 0, 0),
>  	GATE(chipid, "chipid", "aclk66", GATE_IP_PERIS, 0, 0, 0),
> -	GATE(sysreg, "sysreg", "aclk66", GATE_IP_PERIS, 1, 0, 0),
> +	GATE(sysreg, "sysreg", "aclk66",
> +			GATE_IP_PERIS, 1, CLK_IGNORE_UNUSED, 0),
>  	GATE(pmu, "pmu", "aclk66", GATE_IP_PERIS, 2, CLK_IGNORE_UNUSED, 0),
>  	GATE(tzpc0, "tzpc0", "aclk66", GATE_IP_PERIS, 6, 0, 0),
>  	GATE(tzpc1, "tzpc1", "aclk66", GATE_IP_PERIS, 7, 0, 0),
> 

Applied to samsung-clk tree, since this patch seems not to depend or be
a dependency of other patches.

Best regards,
Tomasz

[PATCH 2/5] ARM: EXYNOS5: Fix PMU register configuration for local power blocks

[Abhilash Kesavan]

For the six local power blocks - MFC, DISP1, GSC, MAU, G3D and ISP
the respective CMU_RESET, CMU_SYSCLK and CMU_CLKSTOP registers need
to be low initially for normal mode on Exynos5250.
Also fix the corresponding AFTR and LPA configurations.

Signed-off-by: Abhilash Kesavan <a.kesavan@samsung.com>
---
 arch/arm/mach-exynos/pmu.c |   66 ++++++++++++++++++++++++++++++++------------
 1 file changed, 48 insertions(+), 18 deletions(-)

diff --git a/arch/arm/mach-exynos/pmu.c b/arch/arm/mach-exynos/pmu.c
index 97d6885..5f4d26b 100644
--- a/arch/arm/mach-exynos/pmu.c
+++ b/arch/arm/mach-exynos/pmu.c
@@ -296,24 +296,24 @@ static struct exynos_pmu_conf exynos5250_pmu_config[] = {
 	{ EXYNOS5_G3D_SYS_PWR_REG,			{ 0x7, 0x0, 0x0} },
 	{ EXYNOS5_DISP1_SYS_PWR_REG,			{ 0x7, 0x0, 0x0} },
 	{ EXYNOS5_MAU_SYS_PWR_REG,			{ 0x7, 0x7, 0x0} },
-	{ EXYNOS5_CMU_CLKSTOP_GSCL_SYS_PWR_REG,		{ 0x1, 0x0, 0x0} },
-	{ EXYNOS5_CMU_CLKSTOP_ISP_SYS_PWR_REG,		{ 0x1, 0x0, 0x0} },
-	{ EXYNOS5_CMU_CLKSTOP_MFC_SYS_PWR_REG,		{ 0x1, 0x0, 0x0} },
-	{ EXYNOS5_CMU_CLKSTOP_G3D_SYS_PWR_REG,		{ 0x1, 0x0, 0x0} },
-	{ EXYNOS5_CMU_CLKSTOP_DISP1_SYS_PWR_REG,	{ 0x1, 0x0, 0x0} },
-	{ EXYNOS5_CMU_CLKSTOP_MAU_SYS_PWR_REG,		{ 0x1, 0x1, 0x0} },
-	{ EXYNOS5_CMU_SYSCLK_GSCL_SYS_PWR_REG,		{ 0x1, 0x0, 0x0} },
-	{ EXYNOS5_CMU_SYSCLK_ISP_SYS_PWR_REG,		{ 0x1, 0x0, 0x0} },
-	{ EXYNOS5_CMU_SYSCLK_MFC_SYS_PWR_REG,		{ 0x1, 0x0, 0x0} },
-	{ EXYNOS5_CMU_SYSCLK_G3D_SYS_PWR_REG,		{ 0x1, 0x0, 0x0} },
-	{ EXYNOS5_CMU_SYSCLK_DISP1_SYS_PWR_REG,		{ 0x1, 0x0, 0x0} },
-	{ EXYNOS5_CMU_SYSCLK_MAU_SYS_PWR_REG,		{ 0x1, 0x1, 0x0} },
-	{ EXYNOS5_CMU_RESET_GSCL_SYS_PWR_REG,		{ 0x1, 0x0, 0x0} },
-	{ EXYNOS5_CMU_RESET_ISP_SYS_PWR_REG,		{ 0x1, 0x0, 0x0} },
-	{ EXYNOS5_CMU_RESET_MFC_SYS_PWR_REG,		{ 0x1, 0x0, 0x0} },
-	{ EXYNOS5_CMU_RESET_G3D_SYS_PWR_REG,		{ 0x1, 0x0, 0x0} },
-	{ EXYNOS5_CMU_RESET_DISP1_SYS_PWR_REG,		{ 0x1, 0x0, 0x0} },
-	{ EXYNOS5_CMU_RESET_MAU_SYS_PWR_REG,		{ 0x1, 0x1, 0x0} },
+	{ EXYNOS5_CMU_CLKSTOP_GSCL_SYS_PWR_REG,		{ 0x0, 0x0, 0x0} },
+	{ EXYNOS5_CMU_CLKSTOP_ISP_SYS_PWR_REG,		{ 0x0, 0x0, 0x0} },
+	{ EXYNOS5_CMU_CLKSTOP_MFC_SYS_PWR_REG,		{ 0x0, 0x0, 0x0} },
+	{ EXYNOS5_CMU_CLKSTOP_G3D_SYS_PWR_REG,		{ 0x0, 0x0, 0x0} },
+	{ EXYNOS5_CMU_CLKSTOP_DISP1_SYS_PWR_REG,	{ 0x0, 0x0, 0x0} },
+	{ EXYNOS5_CMU_CLKSTOP_MAU_SYS_PWR_REG,		{ 0x0, 0x0, 0x0} },
+	{ EXYNOS5_CMU_SYSCLK_GSCL_SYS_PWR_REG,		{ 0x0, 0x0, 0x0} },
+	{ EXYNOS5_CMU_SYSCLK_ISP_SYS_PWR_REG,		{ 0x0, 0x0, 0x0} },
+	{ EXYNOS5_CMU_SYSCLK_MFC_SYS_PWR_REG,		{ 0x0, 0x0, 0x0} },
+	{ EXYNOS5_CMU_SYSCLK_G3D_SYS_PWR_REG,		{ 0x0, 0x0, 0x0} },
+	{ EXYNOS5_CMU_SYSCLK_DISP1_SYS_PWR_REG,		{ 0x0, 0x0, 0x0} },
+	{ EXYNOS5_CMU_SYSCLK_MAU_SYS_PWR_REG,		{ 0x0, 0x0, 0x0} },
+	{ EXYNOS5_CMU_RESET_GSCL_SYS_PWR_REG,		{ 0x0, 0x0, 0x0} },
+	{ EXYNOS5_CMU_RESET_ISP_SYS_PWR_REG,		{ 0x0, 0x0, 0x0} },
+	{ EXYNOS5_CMU_RESET_MFC_SYS_PWR_REG,		{ 0x0, 0x0, 0x0} },
+	{ EXYNOS5_CMU_RESET_G3D_SYS_PWR_REG,		{ 0x0, 0x0, 0x0} },
+	{ EXYNOS5_CMU_RESET_DISP1_SYS_PWR_REG,		{ 0x0, 0x0, 0x0} },
+	{ EXYNOS5_CMU_RESET_MAU_SYS_PWR_REG,		{ 0x0, 0x0, 0x0} },
 	{ PMU_TABLE_END,},
 };
 
@@ -337,6 +337,27 @@ static void __iomem *exynos5_list_diable_wfi_wfe[] = {
 	EXYNOS5_ISP_ARM_OPTION,
 };
 
+void __iomem *exynos5_list_disable_pmu_reg[] = {
+	EXYNOS5_CMU_CLKSTOP_GSCL_SYS_PWR_REG,
+	EXYNOS5_CMU_CLKSTOP_ISP_SYS_PWR_REG,
+	EXYNOS5_CMU_CLKSTOP_MFC_SYS_PWR_REG,
+	EXYNOS5_CMU_CLKSTOP_G3D_SYS_PWR_REG,
+	EXYNOS5_CMU_CLKSTOP_DISP1_SYS_PWR_REG,
+	EXYNOS5_CMU_CLKSTOP_MAU_SYS_PWR_REG,
+	EXYNOS5_CMU_SYSCLK_GSCL_SYS_PWR_REG,
+	EXYNOS5_CMU_SYSCLK_ISP_SYS_PWR_REG,
+	EXYNOS5_CMU_SYSCLK_MFC_SYS_PWR_REG,
+	EXYNOS5_CMU_SYSCLK_G3D_SYS_PWR_REG,
+	EXYNOS5_CMU_SYSCLK_DISP1_SYS_PWR_REG,
+	EXYNOS5_CMU_SYSCLK_MAU_SYS_PWR_REG,
+	EXYNOS5_CMU_RESET_GSCL_SYS_PWR_REG,
+	EXYNOS5_CMU_RESET_ISP_SYS_PWR_REG,
+	EXYNOS5_CMU_RESET_MFC_SYS_PWR_REG,
+	EXYNOS5_CMU_RESET_G3D_SYS_PWR_REG,
+	EXYNOS5_CMU_RESET_DISP1_SYS_PWR_REG,
+	EXYNOS5_CMU_RESET_MAU_SYS_PWR_REG,
+};
+
 static void exynos5_init_pmu(void)
 {
 	unsigned int i;
@@ -391,6 +412,7 @@ void exynos_sys_powerdown_conf(enum sys_powerdown mode)
 static int __init exynos_pmu_init(void)
 {
 	unsigned int value;
+	unsigned int i;
 
 	exynos_pmu_config = exynos4210_pmu_config;
 
@@ -413,6 +435,14 @@ static int __init exynos_pmu_init(void)
 		value &= ~EXYNOS5_SYS_WDTRESET;
 		__raw_writel(value, EXYNOS5_MASK_WDTRESET_REQUEST);
 
+		/*
+		 * Set the CMU_RESET, CMU_SYSCLK and CMU_CLKSTOP registers for
+		 * local power blocks to Low initially as per the "System-Level
+		 * Power-Down Configuration Registers" table.
+		 */
+		for (i = 0; i < ARRAY_SIZE(exynos5_list_disable_pmu_reg); i++)
+			__raw_writel(0x0, exynos5_list_disable_pmu_reg[i]);
+
 		exynos_pmu_config = exynos5250_pmu_config;
 		pr_info("EXYNOS5250 PMU Initialize\n");
 	} else {
-- 
1.7.9.5

[PATCH 2/5] ARM: EXYNOS5: Fix PMU register configuration for local power blocks

[Abhilash Kesavan]

For the six local power blocks - MFC, DISP1, GSC, MAU, G3D and ISP
the respective CMU_RESET, CMU_SYSCLK and CMU_CLKSTOP registers need
to be low initially for normal mode on Exynos5250.
Also fix the corresponding AFTR and LPA configurations.

Signed-off-by: Abhilash Kesavan <a.kesavan@samsung.com>
---
 arch/arm/mach-exynos/pmu.c |   66 ++++++++++++++++++++++++++++++++------------
 1 file changed, 48 insertions(+), 18 deletions(-)

diff --git a/arch/arm/mach-exynos/pmu.c b/arch/arm/mach-exynos/pmu.c
index 97d6885..5f4d26b 100644
--- a/arch/arm/mach-exynos/pmu.c
+++ b/arch/arm/mach-exynos/pmu.c
@@ -296,24 +296,24 @@ static struct exynos_pmu_conf exynos5250_pmu_config[] = {
 	{ EXYNOS5_G3D_SYS_PWR_REG,			{ 0x7, 0x0, 0x0} },
 	{ EXYNOS5_DISP1_SYS_PWR_REG,			{ 0x7, 0x0, 0x0} },
 	{ EXYNOS5_MAU_SYS_PWR_REG,			{ 0x7, 0x7, 0x0} },
-	{ EXYNOS5_CMU_CLKSTOP_GSCL_SYS_PWR_REG,		{ 0x1, 0x0, 0x0} },
-	{ EXYNOS5_CMU_CLKSTOP_ISP_SYS_PWR_REG,		{ 0x1, 0x0, 0x0} },
-	{ EXYNOS5_CMU_CLKSTOP_MFC_SYS_PWR_REG,		{ 0x1, 0x0, 0x0} },
-	{ EXYNOS5_CMU_CLKSTOP_G3D_SYS_PWR_REG,		{ 0x1, 0x0, 0x0} },
-	{ EXYNOS5_CMU_CLKSTOP_DISP1_SYS_PWR_REG,	{ 0x1, 0x0, 0x0} },
-	{ EXYNOS5_CMU_CLKSTOP_MAU_SYS_PWR_REG,		{ 0x1, 0x1, 0x0} },
-	{ EXYNOS5_CMU_SYSCLK_GSCL_SYS_PWR_REG,		{ 0x1, 0x0, 0x0} },
-	{ EXYNOS5_CMU_SYSCLK_ISP_SYS_PWR_REG,		{ 0x1, 0x0, 0x0} },
-	{ EXYNOS5_CMU_SYSCLK_MFC_SYS_PWR_REG,		{ 0x1, 0x0, 0x0} },
-	{ EXYNOS5_CMU_SYSCLK_G3D_SYS_PWR_REG,		{ 0x1, 0x0, 0x0} },
-	{ EXYNOS5_CMU_SYSCLK_DISP1_SYS_PWR_REG,		{ 0x1, 0x0, 0x0} },
-	{ EXYNOS5_CMU_SYSCLK_MAU_SYS_PWR_REG,		{ 0x1, 0x1, 0x0} },
-	{ EXYNOS5_CMU_RESET_GSCL_SYS_PWR_REG,		{ 0x1, 0x0, 0x0} },
-	{ EXYNOS5_CMU_RESET_ISP_SYS_PWR_REG,		{ 0x1, 0x0, 0x0} },
-	{ EXYNOS5_CMU_RESET_MFC_SYS_PWR_REG,		{ 0x1, 0x0, 0x0} },
-	{ EXYNOS5_CMU_RESET_G3D_SYS_PWR_REG,		{ 0x1, 0x0, 0x0} },
-	{ EXYNOS5_CMU_RESET_DISP1_SYS_PWR_REG,		{ 0x1, 0x0, 0x0} },
-	{ EXYNOS5_CMU_RESET_MAU_SYS_PWR_REG,		{ 0x1, 0x1, 0x0} },
+	{ EXYNOS5_CMU_CLKSTOP_GSCL_SYS_PWR_REG,		{ 0x0, 0x0, 0x0} },
+	{ EXYNOS5_CMU_CLKSTOP_ISP_SYS_PWR_REG,		{ 0x0, 0x0, 0x0} },
+	{ EXYNOS5_CMU_CLKSTOP_MFC_SYS_PWR_REG,		{ 0x0, 0x0, 0x0} },
+	{ EXYNOS5_CMU_CLKSTOP_G3D_SYS_PWR_REG,		{ 0x0, 0x0, 0x0} },
+	{ EXYNOS5_CMU_CLKSTOP_DISP1_SYS_PWR_REG,	{ 0x0, 0x0, 0x0} },
+	{ EXYNOS5_CMU_CLKSTOP_MAU_SYS_PWR_REG,		{ 0x0, 0x0, 0x0} },
+	{ EXYNOS5_CMU_SYSCLK_GSCL_SYS_PWR_REG,		{ 0x0, 0x0, 0x0} },
+	{ EXYNOS5_CMU_SYSCLK_ISP_SYS_PWR_REG,		{ 0x0, 0x0, 0x0} },
+	{ EXYNOS5_CMU_SYSCLK_MFC_SYS_PWR_REG,		{ 0x0, 0x0, 0x0} },
+	{ EXYNOS5_CMU_SYSCLK_G3D_SYS_PWR_REG,		{ 0x0, 0x0, 0x0} },
+	{ EXYNOS5_CMU_SYSCLK_DISP1_SYS_PWR_REG,		{ 0x0, 0x0, 0x0} },
+	{ EXYNOS5_CMU_SYSCLK_MAU_SYS_PWR_REG,		{ 0x0, 0x0, 0x0} },
+	{ EXYNOS5_CMU_RESET_GSCL_SYS_PWR_REG,		{ 0x0, 0x0, 0x0} },
+	{ EXYNOS5_CMU_RESET_ISP_SYS_PWR_REG,		{ 0x0, 0x0, 0x0} },
+	{ EXYNOS5_CMU_RESET_MFC_SYS_PWR_REG,		{ 0x0, 0x0, 0x0} },
+	{ EXYNOS5_CMU_RESET_G3D_SYS_PWR_REG,		{ 0x0, 0x0, 0x0} },
+	{ EXYNOS5_CMU_RESET_DISP1_SYS_PWR_REG,		{ 0x0, 0x0, 0x0} },
+	{ EXYNOS5_CMU_RESET_MAU_SYS_PWR_REG,		{ 0x0, 0x0, 0x0} },
 	{ PMU_TABLE_END,},
 };
 
@@ -337,6 +337,27 @@ static void __iomem *exynos5_list_diable_wfi_wfe[] = {
 	EXYNOS5_ISP_ARM_OPTION,
 };
 
+void __iomem *exynos5_list_disable_pmu_reg[] = {
+	EXYNOS5_CMU_CLKSTOP_GSCL_SYS_PWR_REG,
+	EXYNOS5_CMU_CLKSTOP_ISP_SYS_PWR_REG,
+	EXYNOS5_CMU_CLKSTOP_MFC_SYS_PWR_REG,
+	EXYNOS5_CMU_CLKSTOP_G3D_SYS_PWR_REG,
+	EXYNOS5_CMU_CLKSTOP_DISP1_SYS_PWR_REG,
+	EXYNOS5_CMU_CLKSTOP_MAU_SYS_PWR_REG,
+	EXYNOS5_CMU_SYSCLK_GSCL_SYS_PWR_REG,
+	EXYNOS5_CMU_SYSCLK_ISP_SYS_PWR_REG,
+	EXYNOS5_CMU_SYSCLK_MFC_SYS_PWR_REG,
+	EXYNOS5_CMU_SYSCLK_G3D_SYS_PWR_REG,
+	EXYNOS5_CMU_SYSCLK_DISP1_SYS_PWR_REG,
+	EXYNOS5_CMU_SYSCLK_MAU_SYS_PWR_REG,
+	EXYNOS5_CMU_RESET_GSCL_SYS_PWR_REG,
+	EXYNOS5_CMU_RESET_ISP_SYS_PWR_REG,
+	EXYNOS5_CMU_RESET_MFC_SYS_PWR_REG,
+	EXYNOS5_CMU_RESET_G3D_SYS_PWR_REG,
+	EXYNOS5_CMU_RESET_DISP1_SYS_PWR_REG,
+	EXYNOS5_CMU_RESET_MAU_SYS_PWR_REG,
+};
+
 static void exynos5_init_pmu(void)
 {
 	unsigned int i;
@@ -391,6 +412,7 @@ void exynos_sys_powerdown_conf(enum sys_powerdown mode)
 static int __init exynos_pmu_init(void)
 {
 	unsigned int value;
+	unsigned int i;
 
 	exynos_pmu_config = exynos4210_pmu_config;
 
@@ -413,6 +435,14 @@ static int __init exynos_pmu_init(void)
 		value &= ~EXYNOS5_SYS_WDTRESET;
 		__raw_writel(value, EXYNOS5_MASK_WDTRESET_REQUEST);
 
+		/*
+		 * Set the CMU_RESET, CMU_SYSCLK and CMU_CLKSTOP registers for
+		 * local power blocks to Low initially as per the "System-Level
+		 * Power-Down Configuration Registers" table.
+		 */
+		for (i = 0; i < ARRAY_SIZE(exynos5_list_disable_pmu_reg); i++)
+			__raw_writel(0x0, exynos5_list_disable_pmu_reg[i]);
+
 		exynos_pmu_config = exynos5250_pmu_config;
 		pr_info("EXYNOS5250 PMU Initialize\n");
 	} else {
-- 
1.7.9.5

Re: [PATCH 2/5] ARM: EXYNOS5: Fix PMU register configuration for local power blocks

[Tomasz Figa]

Hi Abhilash,

[dropping invalid address of DT mailing list]

Please see my comments inline.

On Wednesday 11 of December 2013 17:27:06 Abhilash Kesavan wrote:
> For the six local power blocks - MFC, DISP1, GSC, MAU, G3D and ISP
> the respective CMU_RESET, CMU_SYSCLK and CMU_CLKSTOP registers need
> to be low initially for normal mode on Exynos5250.
> Also fix the corresponding AFTR and LPA configurations.
> 
> Signed-off-by: Abhilash Kesavan <a.kesavan@samsung.com>
> ---
>  arch/arm/mach-exynos/pmu.c |   66 ++++++++++++++++++++++++++++++++------------
>  1 file changed, 48 insertions(+), 18 deletions(-)
> 
> diff --git a/arch/arm/mach-exynos/pmu.c b/arch/arm/mach-exynos/pmu.c
> index 97d6885..5f4d26b 100644
> --- a/arch/arm/mach-exynos/pmu.c
> +++ b/arch/arm/mach-exynos/pmu.c
> @@ -296,24 +296,24 @@ static struct exynos_pmu_conf exynos5250_pmu_config[] = {
>  	{ EXYNOS5_G3D_SYS_PWR_REG,			{ 0x7, 0x0, 0x0} },
>  	{ EXYNOS5_DISP1_SYS_PWR_REG,			{ 0x7, 0x0, 0x0} },
>  	{ EXYNOS5_MAU_SYS_PWR_REG,			{ 0x7, 0x7, 0x0} },
> -	{ EXYNOS5_CMU_CLKSTOP_GSCL_SYS_PWR_REG,		{ 0x1, 0x0, 0x0} },
> -	{ EXYNOS5_CMU_CLKSTOP_ISP_SYS_PWR_REG,		{ 0x1, 0x0, 0x0} },
> -	{ EXYNOS5_CMU_CLKSTOP_MFC_SYS_PWR_REG,		{ 0x1, 0x0, 0x0} },
> -	{ EXYNOS5_CMU_CLKSTOP_G3D_SYS_PWR_REG,		{ 0x1, 0x0, 0x0} },
> -	{ EXYNOS5_CMU_CLKSTOP_DISP1_SYS_PWR_REG,	{ 0x1, 0x0, 0x0} },
> -	{ EXYNOS5_CMU_CLKSTOP_MAU_SYS_PWR_REG,		{ 0x1, 0x1, 0x0} },
> -	{ EXYNOS5_CMU_SYSCLK_GSCL_SYS_PWR_REG,		{ 0x1, 0x0, 0x0} },
> -	{ EXYNOS5_CMU_SYSCLK_ISP_SYS_PWR_REG,		{ 0x1, 0x0, 0x0} },
> -	{ EXYNOS5_CMU_SYSCLK_MFC_SYS_PWR_REG,		{ 0x1, 0x0, 0x0} },
> -	{ EXYNOS5_CMU_SYSCLK_G3D_SYS_PWR_REG,		{ 0x1, 0x0, 0x0} },
> -	{ EXYNOS5_CMU_SYSCLK_DISP1_SYS_PWR_REG,		{ 0x1, 0x0, 0x0} },
> -	{ EXYNOS5_CMU_SYSCLK_MAU_SYS_PWR_REG,		{ 0x1, 0x1, 0x0} },
> -	{ EXYNOS5_CMU_RESET_GSCL_SYS_PWR_REG,		{ 0x1, 0x0, 0x0} },
> -	{ EXYNOS5_CMU_RESET_ISP_SYS_PWR_REG,		{ 0x1, 0x0, 0x0} },
> -	{ EXYNOS5_CMU_RESET_MFC_SYS_PWR_REG,		{ 0x1, 0x0, 0x0} },
> -	{ EXYNOS5_CMU_RESET_G3D_SYS_PWR_REG,		{ 0x1, 0x0, 0x0} },
> -	{ EXYNOS5_CMU_RESET_DISP1_SYS_PWR_REG,		{ 0x1, 0x0, 0x0} },
> -	{ EXYNOS5_CMU_RESET_MAU_SYS_PWR_REG,		{ 0x1, 0x1, 0x0} },
> +	{ EXYNOS5_CMU_CLKSTOP_GSCL_SYS_PWR_REG,		{ 0x0, 0x0, 0x0} },
> +	{ EXYNOS5_CMU_CLKSTOP_ISP_SYS_PWR_REG,		{ 0x0, 0x0, 0x0} },
> +	{ EXYNOS5_CMU_CLKSTOP_MFC_SYS_PWR_REG,		{ 0x0, 0x0, 0x0} },
> +	{ EXYNOS5_CMU_CLKSTOP_G3D_SYS_PWR_REG,		{ 0x0, 0x0, 0x0} },
> +	{ EXYNOS5_CMU_CLKSTOP_DISP1_SYS_PWR_REG,	{ 0x0, 0x0, 0x0} },
> +	{ EXYNOS5_CMU_CLKSTOP_MAU_SYS_PWR_REG,		{ 0x0, 0x0, 0x0} },
> +	{ EXYNOS5_CMU_SYSCLK_GSCL_SYS_PWR_REG,		{ 0x0, 0x0, 0x0} },
> +	{ EXYNOS5_CMU_SYSCLK_ISP_SYS_PWR_REG,		{ 0x0, 0x0, 0x0} },
> +	{ EXYNOS5_CMU_SYSCLK_MFC_SYS_PWR_REG,		{ 0x0, 0x0, 0x0} },
> +	{ EXYNOS5_CMU_SYSCLK_G3D_SYS_PWR_REG,		{ 0x0, 0x0, 0x0} },
> +	{ EXYNOS5_CMU_SYSCLK_DISP1_SYS_PWR_REG,		{ 0x0, 0x0, 0x0} },
> +	{ EXYNOS5_CMU_SYSCLK_MAU_SYS_PWR_REG,		{ 0x0, 0x0, 0x0} },
> +	{ EXYNOS5_CMU_RESET_GSCL_SYS_PWR_REG,		{ 0x0, 0x0, 0x0} },
> +	{ EXYNOS5_CMU_RESET_ISP_SYS_PWR_REG,		{ 0x0, 0x0, 0x0} },
> +	{ EXYNOS5_CMU_RESET_MFC_SYS_PWR_REG,		{ 0x0, 0x0, 0x0} },
> +	{ EXYNOS5_CMU_RESET_G3D_SYS_PWR_REG,		{ 0x0, 0x0, 0x0} },
> +	{ EXYNOS5_CMU_RESET_DISP1_SYS_PWR_REG,		{ 0x0, 0x0, 0x0} },
> +	{ EXYNOS5_CMU_RESET_MAU_SYS_PWR_REG,		{ 0x0, 0x0, 0x0} },
>  	{ PMU_TABLE_END,},
>  };
>  
> @@ -337,6 +337,27 @@ static void __iomem *exynos5_list_diable_wfi_wfe[] = {
>  	EXYNOS5_ISP_ARM_OPTION,
>  };
>  
> +void __iomem *exynos5_list_disable_pmu_reg[] = {

static void __iomem * const exynos5_list_disable_pmu_reg[] = {

Best regards,
Tomasz

[PATCH 2/5] ARM: EXYNOS5: Fix PMU register configuration for local power blocks

[Tomasz Figa]

Hi Abhilash,

[dropping invalid address of DT mailing list]

Please see my comments inline.

On Wednesday 11 of December 2013 17:27:06 Abhilash Kesavan wrote:
> For the six local power blocks - MFC, DISP1, GSC, MAU, G3D and ISP
> the respective CMU_RESET, CMU_SYSCLK and CMU_CLKSTOP registers need
> to be low initially for normal mode on Exynos5250.
> Also fix the corresponding AFTR and LPA configurations.
> 
> Signed-off-by: Abhilash Kesavan <a.kesavan@samsung.com>
> ---
>  arch/arm/mach-exynos/pmu.c |   66 ++++++++++++++++++++++++++++++++------------
>  1 file changed, 48 insertions(+), 18 deletions(-)
> 
> diff --git a/arch/arm/mach-exynos/pmu.c b/arch/arm/mach-exynos/pmu.c
> index 97d6885..5f4d26b 100644
> --- a/arch/arm/mach-exynos/pmu.c
> +++ b/arch/arm/mach-exynos/pmu.c
> @@ -296,24 +296,24 @@ static struct exynos_pmu_conf exynos5250_pmu_config[] = {
>  	{ EXYNOS5_G3D_SYS_PWR_REG,			{ 0x7, 0x0, 0x0} },
>  	{ EXYNOS5_DISP1_SYS_PWR_REG,			{ 0x7, 0x0, 0x0} },
>  	{ EXYNOS5_MAU_SYS_PWR_REG,			{ 0x7, 0x7, 0x0} },
> -	{ EXYNOS5_CMU_CLKSTOP_GSCL_SYS_PWR_REG,		{ 0x1, 0x0, 0x0} },
> -	{ EXYNOS5_CMU_CLKSTOP_ISP_SYS_PWR_REG,		{ 0x1, 0x0, 0x0} },
> -	{ EXYNOS5_CMU_CLKSTOP_MFC_SYS_PWR_REG,		{ 0x1, 0x0, 0x0} },
> -	{ EXYNOS5_CMU_CLKSTOP_G3D_SYS_PWR_REG,		{ 0x1, 0x0, 0x0} },
> -	{ EXYNOS5_CMU_CLKSTOP_DISP1_SYS_PWR_REG,	{ 0x1, 0x0, 0x0} },
> -	{ EXYNOS5_CMU_CLKSTOP_MAU_SYS_PWR_REG,		{ 0x1, 0x1, 0x0} },
> -	{ EXYNOS5_CMU_SYSCLK_GSCL_SYS_PWR_REG,		{ 0x1, 0x0, 0x0} },
> -	{ EXYNOS5_CMU_SYSCLK_ISP_SYS_PWR_REG,		{ 0x1, 0x0, 0x0} },
> -	{ EXYNOS5_CMU_SYSCLK_MFC_SYS_PWR_REG,		{ 0x1, 0x0, 0x0} },
> -	{ EXYNOS5_CMU_SYSCLK_G3D_SYS_PWR_REG,		{ 0x1, 0x0, 0x0} },
> -	{ EXYNOS5_CMU_SYSCLK_DISP1_SYS_PWR_REG,		{ 0x1, 0x0, 0x0} },
> -	{ EXYNOS5_CMU_SYSCLK_MAU_SYS_PWR_REG,		{ 0x1, 0x1, 0x0} },
> -	{ EXYNOS5_CMU_RESET_GSCL_SYS_PWR_REG,		{ 0x1, 0x0, 0x0} },
> -	{ EXYNOS5_CMU_RESET_ISP_SYS_PWR_REG,		{ 0x1, 0x0, 0x0} },
> -	{ EXYNOS5_CMU_RESET_MFC_SYS_PWR_REG,		{ 0x1, 0x0, 0x0} },
> -	{ EXYNOS5_CMU_RESET_G3D_SYS_PWR_REG,		{ 0x1, 0x0, 0x0} },
> -	{ EXYNOS5_CMU_RESET_DISP1_SYS_PWR_REG,		{ 0x1, 0x0, 0x0} },
> -	{ EXYNOS5_CMU_RESET_MAU_SYS_PWR_REG,		{ 0x1, 0x1, 0x0} },
> +	{ EXYNOS5_CMU_CLKSTOP_GSCL_SYS_PWR_REG,		{ 0x0, 0x0, 0x0} },
> +	{ EXYNOS5_CMU_CLKSTOP_ISP_SYS_PWR_REG,		{ 0x0, 0x0, 0x0} },
> +	{ EXYNOS5_CMU_CLKSTOP_MFC_SYS_PWR_REG,		{ 0x0, 0x0, 0x0} },
> +	{ EXYNOS5_CMU_CLKSTOP_G3D_SYS_PWR_REG,		{ 0x0, 0x0, 0x0} },
> +	{ EXYNOS5_CMU_CLKSTOP_DISP1_SYS_PWR_REG,	{ 0x0, 0x0, 0x0} },
> +	{ EXYNOS5_CMU_CLKSTOP_MAU_SYS_PWR_REG,		{ 0x0, 0x0, 0x0} },
> +	{ EXYNOS5_CMU_SYSCLK_GSCL_SYS_PWR_REG,		{ 0x0, 0x0, 0x0} },
> +	{ EXYNOS5_CMU_SYSCLK_ISP_SYS_PWR_REG,		{ 0x0, 0x0, 0x0} },
> +	{ EXYNOS5_CMU_SYSCLK_MFC_SYS_PWR_REG,		{ 0x0, 0x0, 0x0} },
> +	{ EXYNOS5_CMU_SYSCLK_G3D_SYS_PWR_REG,		{ 0x0, 0x0, 0x0} },
> +	{ EXYNOS5_CMU_SYSCLK_DISP1_SYS_PWR_REG,		{ 0x0, 0x0, 0x0} },
> +	{ EXYNOS5_CMU_SYSCLK_MAU_SYS_PWR_REG,		{ 0x0, 0x0, 0x0} },
> +	{ EXYNOS5_CMU_RESET_GSCL_SYS_PWR_REG,		{ 0x0, 0x0, 0x0} },
> +	{ EXYNOS5_CMU_RESET_ISP_SYS_PWR_REG,		{ 0x0, 0x0, 0x0} },
> +	{ EXYNOS5_CMU_RESET_MFC_SYS_PWR_REG,		{ 0x0, 0x0, 0x0} },
> +	{ EXYNOS5_CMU_RESET_G3D_SYS_PWR_REG,		{ 0x0, 0x0, 0x0} },
> +	{ EXYNOS5_CMU_RESET_DISP1_SYS_PWR_REG,		{ 0x0, 0x0, 0x0} },
> +	{ EXYNOS5_CMU_RESET_MAU_SYS_PWR_REG,		{ 0x0, 0x0, 0x0} },
>  	{ PMU_TABLE_END,},
>  };
>  
> @@ -337,6 +337,27 @@ static void __iomem *exynos5_list_diable_wfi_wfe[] = {
>  	EXYNOS5_ISP_ARM_OPTION,
>  };
>  
> +void __iomem *exynos5_list_disable_pmu_reg[] = {

static void __iomem * const exynos5_list_disable_pmu_reg[] = {

Best regards,
Tomasz

Re: [PATCH 2/5] ARM: EXYNOS5: Fix PMU register configuration for local power blocks

[Abhilash Kesavan]

Hi Tomasz,

On Wed, Dec 11, 2013 at 5:59 PM, Tomasz Figa <t.figa@samsung.com> wrote:
> Hi Abhilash,
>
> [dropping invalid address of DT mailing list]
>
> Please see my comments inline.
>
> On Wednesday 11 of December 2013 17:27:06 Abhilash Kesavan wrote:
>> For the six local power blocks - MFC, DISP1, GSC, MAU, G3D and ISP
>> the respective CMU_RESET, CMU_SYSCLK and CMU_CLKSTOP registers need
>> to be low initially for normal mode on Exynos5250.
>> Also fix the corresponding AFTR and LPA configurations.
>>
>> Signed-off-by: Abhilash Kesavan <a.kesavan@samsung.com>
>> ---
>>  arch/arm/mach-exynos/pmu.c |   66 ++++++++++++++++++++++++++++++++------------
>>  1 file changed, 48 insertions(+), 18 deletions(-)
>>
>> diff --git a/arch/arm/mach-exynos/pmu.c b/arch/arm/mach-exynos/pmu.c
>> index 97d6885..5f4d26b 100644
>> --- a/arch/arm/mach-exynos/pmu.c
>> +++ b/arch/arm/mach-exynos/pmu.c
>> @@ -296,24 +296,24 @@ static struct exynos_pmu_conf exynos5250_pmu_config[] = {
>>       { EXYNOS5_G3D_SYS_PWR_REG,                      { 0x7, 0x0, 0x0} },
>>       { EXYNOS5_DISP1_SYS_PWR_REG,                    { 0x7, 0x0, 0x0} },
>>       { EXYNOS5_MAU_SYS_PWR_REG,                      { 0x7, 0x7, 0x0} },
>> -     { EXYNOS5_CMU_CLKSTOP_GSCL_SYS_PWR_REG,         { 0x1, 0x0, 0x0} },
>> -     { EXYNOS5_CMU_CLKSTOP_ISP_SYS_PWR_REG,          { 0x1, 0x0, 0x0} },
>> -     { EXYNOS5_CMU_CLKSTOP_MFC_SYS_PWR_REG,          { 0x1, 0x0, 0x0} },
>> -     { EXYNOS5_CMU_CLKSTOP_G3D_SYS_PWR_REG,          { 0x1, 0x0, 0x0} },
>> -     { EXYNOS5_CMU_CLKSTOP_DISP1_SYS_PWR_REG,        { 0x1, 0x0, 0x0} },
>> -     { EXYNOS5_CMU_CLKSTOP_MAU_SYS_PWR_REG,          { 0x1, 0x1, 0x0} },
>> -     { EXYNOS5_CMU_SYSCLK_GSCL_SYS_PWR_REG,          { 0x1, 0x0, 0x0} },
>> -     { EXYNOS5_CMU_SYSCLK_ISP_SYS_PWR_REG,           { 0x1, 0x0, 0x0} },
>> -     { EXYNOS5_CMU_SYSCLK_MFC_SYS_PWR_REG,           { 0x1, 0x0, 0x0} },
>> -     { EXYNOS5_CMU_SYSCLK_G3D_SYS_PWR_REG,           { 0x1, 0x0, 0x0} },
>> -     { EXYNOS5_CMU_SYSCLK_DISP1_SYS_PWR_REG,         { 0x1, 0x0, 0x0} },
>> -     { EXYNOS5_CMU_SYSCLK_MAU_SYS_PWR_REG,           { 0x1, 0x1, 0x0} },
>> -     { EXYNOS5_CMU_RESET_GSCL_SYS_PWR_REG,           { 0x1, 0x0, 0x0} },
>> -     { EXYNOS5_CMU_RESET_ISP_SYS_PWR_REG,            { 0x1, 0x0, 0x0} },
>> -     { EXYNOS5_CMU_RESET_MFC_SYS_PWR_REG,            { 0x1, 0x0, 0x0} },
>> -     { EXYNOS5_CMU_RESET_G3D_SYS_PWR_REG,            { 0x1, 0x0, 0x0} },
>> -     { EXYNOS5_CMU_RESET_DISP1_SYS_PWR_REG,          { 0x1, 0x0, 0x0} },
>> -     { EXYNOS5_CMU_RESET_MAU_SYS_PWR_REG,            { 0x1, 0x1, 0x0} },
>> +     { EXYNOS5_CMU_CLKSTOP_GSCL_SYS_PWR_REG,         { 0x0, 0x0, 0x0} },
>> +     { EXYNOS5_CMU_CLKSTOP_ISP_SYS_PWR_REG,          { 0x0, 0x0, 0x0} },
>> +     { EXYNOS5_CMU_CLKSTOP_MFC_SYS_PWR_REG,          { 0x0, 0x0, 0x0} },
>> +     { EXYNOS5_CMU_CLKSTOP_G3D_SYS_PWR_REG,          { 0x0, 0x0, 0x0} },
>> +     { EXYNOS5_CMU_CLKSTOP_DISP1_SYS_PWR_REG,        { 0x0, 0x0, 0x0} },
>> +     { EXYNOS5_CMU_CLKSTOP_MAU_SYS_PWR_REG,          { 0x0, 0x0, 0x0} },
>> +     { EXYNOS5_CMU_SYSCLK_GSCL_SYS_PWR_REG,          { 0x0, 0x0, 0x0} },
>> +     { EXYNOS5_CMU_SYSCLK_ISP_SYS_PWR_REG,           { 0x0, 0x0, 0x0} },
>> +     { EXYNOS5_CMU_SYSCLK_MFC_SYS_PWR_REG,           { 0x0, 0x0, 0x0} },
>> +     { EXYNOS5_CMU_SYSCLK_G3D_SYS_PWR_REG,           { 0x0, 0x0, 0x0} },
>> +     { EXYNOS5_CMU_SYSCLK_DISP1_SYS_PWR_REG,         { 0x0, 0x0, 0x0} },
>> +     { EXYNOS5_CMU_SYSCLK_MAU_SYS_PWR_REG,           { 0x0, 0x0, 0x0} },
>> +     { EXYNOS5_CMU_RESET_GSCL_SYS_PWR_REG,           { 0x0, 0x0, 0x0} },
>> +     { EXYNOS5_CMU_RESET_ISP_SYS_PWR_REG,            { 0x0, 0x0, 0x0} },
>> +     { EXYNOS5_CMU_RESET_MFC_SYS_PWR_REG,            { 0x0, 0x0, 0x0} },
>> +     { EXYNOS5_CMU_RESET_G3D_SYS_PWR_REG,            { 0x0, 0x0, 0x0} },
>> +     { EXYNOS5_CMU_RESET_DISP1_SYS_PWR_REG,          { 0x0, 0x0, 0x0} },
>> +     { EXYNOS5_CMU_RESET_MAU_SYS_PWR_REG,            { 0x0, 0x0, 0x0} },
>>       { PMU_TABLE_END,},
>>  };
>>
>> @@ -337,6 +337,27 @@ static void __iomem *exynos5_list_diable_wfi_wfe[] = {
>>       EXYNOS5_ISP_ARM_OPTION,
>>  };
>>
>> +void __iomem *exynos5_list_disable_pmu_reg[] = {
>
> static void __iomem * const exynos5_list_disable_pmu_reg[] = {

Will fix and re-post.
>
> Best regards,
> Tomasz
>
>
> _______________________________________________
> linux-arm-kernel mailing list
> linux-arm-kernel@lists.infradead.org
> http://lists.infradead.org/mailman/listinfo/linux-arm-kernel

[PATCH 2/5] ARM: EXYNOS5: Fix PMU register configuration for local power blocks

[Abhilash Kesavan]

Hi Tomasz,

On Wed, Dec 11, 2013 at 5:59 PM, Tomasz Figa <t.figa@samsung.com> wrote:
> Hi Abhilash,
>
> [dropping invalid address of DT mailing list]
>
> Please see my comments inline.
>
> On Wednesday 11 of December 2013 17:27:06 Abhilash Kesavan wrote:
>> For the six local power blocks - MFC, DISP1, GSC, MAU, G3D and ISP
>> the respective CMU_RESET, CMU_SYSCLK and CMU_CLKSTOP registers need
>> to be low initially for normal mode on Exynos5250.
>> Also fix the corresponding AFTR and LPA configurations.
>>
>> Signed-off-by: Abhilash Kesavan <a.kesavan@samsung.com>
>> ---
>>  arch/arm/mach-exynos/pmu.c |   66 ++++++++++++++++++++++++++++++++------------
>>  1 file changed, 48 insertions(+), 18 deletions(-)
>>
>> diff --git a/arch/arm/mach-exynos/pmu.c b/arch/arm/mach-exynos/pmu.c
>> index 97d6885..5f4d26b 100644
>> --- a/arch/arm/mach-exynos/pmu.c
>> +++ b/arch/arm/mach-exynos/pmu.c
>> @@ -296,24 +296,24 @@ static struct exynos_pmu_conf exynos5250_pmu_config[] = {
>>       { EXYNOS5_G3D_SYS_PWR_REG,                      { 0x7, 0x0, 0x0} },
>>       { EXYNOS5_DISP1_SYS_PWR_REG,                    { 0x7, 0x0, 0x0} },
>>       { EXYNOS5_MAU_SYS_PWR_REG,                      { 0x7, 0x7, 0x0} },
>> -     { EXYNOS5_CMU_CLKSTOP_GSCL_SYS_PWR_REG,         { 0x1, 0x0, 0x0} },
>> -     { EXYNOS5_CMU_CLKSTOP_ISP_SYS_PWR_REG,          { 0x1, 0x0, 0x0} },
>> -     { EXYNOS5_CMU_CLKSTOP_MFC_SYS_PWR_REG,          { 0x1, 0x0, 0x0} },
>> -     { EXYNOS5_CMU_CLKSTOP_G3D_SYS_PWR_REG,          { 0x1, 0x0, 0x0} },
>> -     { EXYNOS5_CMU_CLKSTOP_DISP1_SYS_PWR_REG,        { 0x1, 0x0, 0x0} },
>> -     { EXYNOS5_CMU_CLKSTOP_MAU_SYS_PWR_REG,          { 0x1, 0x1, 0x0} },
>> -     { EXYNOS5_CMU_SYSCLK_GSCL_SYS_PWR_REG,          { 0x1, 0x0, 0x0} },
>> -     { EXYNOS5_CMU_SYSCLK_ISP_SYS_PWR_REG,           { 0x1, 0x0, 0x0} },
>> -     { EXYNOS5_CMU_SYSCLK_MFC_SYS_PWR_REG,           { 0x1, 0x0, 0x0} },
>> -     { EXYNOS5_CMU_SYSCLK_G3D_SYS_PWR_REG,           { 0x1, 0x0, 0x0} },
>> -     { EXYNOS5_CMU_SYSCLK_DISP1_SYS_PWR_REG,         { 0x1, 0x0, 0x0} },
>> -     { EXYNOS5_CMU_SYSCLK_MAU_SYS_PWR_REG,           { 0x1, 0x1, 0x0} },
>> -     { EXYNOS5_CMU_RESET_GSCL_SYS_PWR_REG,           { 0x1, 0x0, 0x0} },
>> -     { EXYNOS5_CMU_RESET_ISP_SYS_PWR_REG,            { 0x1, 0x0, 0x0} },
>> -     { EXYNOS5_CMU_RESET_MFC_SYS_PWR_REG,            { 0x1, 0x0, 0x0} },
>> -     { EXYNOS5_CMU_RESET_G3D_SYS_PWR_REG,            { 0x1, 0x0, 0x0} },
>> -     { EXYNOS5_CMU_RESET_DISP1_SYS_PWR_REG,          { 0x1, 0x0, 0x0} },
>> -     { EXYNOS5_CMU_RESET_MAU_SYS_PWR_REG,            { 0x1, 0x1, 0x0} },
>> +     { EXYNOS5_CMU_CLKSTOP_GSCL_SYS_PWR_REG,         { 0x0, 0x0, 0x0} },
>> +     { EXYNOS5_CMU_CLKSTOP_ISP_SYS_PWR_REG,          { 0x0, 0x0, 0x0} },
>> +     { EXYNOS5_CMU_CLKSTOP_MFC_SYS_PWR_REG,          { 0x0, 0x0, 0x0} },
>> +     { EXYNOS5_CMU_CLKSTOP_G3D_SYS_PWR_REG,          { 0x0, 0x0, 0x0} },
>> +     { EXYNOS5_CMU_CLKSTOP_DISP1_SYS_PWR_REG,        { 0x0, 0x0, 0x0} },
>> +     { EXYNOS5_CMU_CLKSTOP_MAU_SYS_PWR_REG,          { 0x0, 0x0, 0x0} },
>> +     { EXYNOS5_CMU_SYSCLK_GSCL_SYS_PWR_REG,          { 0x0, 0x0, 0x0} },
>> +     { EXYNOS5_CMU_SYSCLK_ISP_SYS_PWR_REG,           { 0x0, 0x0, 0x0} },
>> +     { EXYNOS5_CMU_SYSCLK_MFC_SYS_PWR_REG,           { 0x0, 0x0, 0x0} },
>> +     { EXYNOS5_CMU_SYSCLK_G3D_SYS_PWR_REG,           { 0x0, 0x0, 0x0} },
>> +     { EXYNOS5_CMU_SYSCLK_DISP1_SYS_PWR_REG,         { 0x0, 0x0, 0x0} },
>> +     { EXYNOS5_CMU_SYSCLK_MAU_SYS_PWR_REG,           { 0x0, 0x0, 0x0} },
>> +     { EXYNOS5_CMU_RESET_GSCL_SYS_PWR_REG,           { 0x0, 0x0, 0x0} },
>> +     { EXYNOS5_CMU_RESET_ISP_SYS_PWR_REG,            { 0x0, 0x0, 0x0} },
>> +     { EXYNOS5_CMU_RESET_MFC_SYS_PWR_REG,            { 0x0, 0x0, 0x0} },
>> +     { EXYNOS5_CMU_RESET_G3D_SYS_PWR_REG,            { 0x0, 0x0, 0x0} },
>> +     { EXYNOS5_CMU_RESET_DISP1_SYS_PWR_REG,          { 0x0, 0x0, 0x0} },
>> +     { EXYNOS5_CMU_RESET_MAU_SYS_PWR_REG,            { 0x0, 0x0, 0x0} },
>>       { PMU_TABLE_END,},
>>  };
>>
>> @@ -337,6 +337,27 @@ static void __iomem *exynos5_list_diable_wfi_wfe[] = {
>>       EXYNOS5_ISP_ARM_OPTION,
>>  };
>>
>> +void __iomem *exynos5_list_disable_pmu_reg[] = {
>
> static void __iomem * const exynos5_list_disable_pmu_reg[] = {

Will fix and re-post.
>
> Best regards,
> Tomasz
>
>
> _______________________________________________
> linux-arm-kernel mailing list
> linux-arm-kernel at lists.infradead.org
> http://lists.infradead.org/mailman/listinfo/linux-arm-kernel

[PATCH 3/5] clk: max77686: Replace is_enabled() with is_prepared call-back

[Abhilash Kesavan]

Following messages are observed when unused PMIC clocks are being
disabled during boot-up:
[ 2921.969560] BUG: scheduling while atomic: swapper/0/1/0x00000002
[ 2921.974080] Modules linked in:
[ 2921.977120] CPU: 0 PID: 1 Comm: swapper/0 Not tainted 3.13.0-rc1-00018-g8465d57 #27
[ 2921.984772] [<c0013c80>] (unwind_backtrace+0x0/0xf8) from [<c00110cc>] (show_stack+0x10/0x14)
[ 2921.993269] [<c00110cc>] (show_stack+0x10/0x14) from [<c032c10c>] (dump_stack+0x64/0xa4)
[ 2922.001340] [<c032c10c>] (dump_stack+0x64/0xa4) from [<c0329b00>] (__schedule_bug+0x48/0x60)
[ 2922.009758] [<c0329b00>] (__schedule_bug+0x48/0x60) from [<c032d414>] (__schedule+0x468/0x504)
[ 2922.018351] [<c032d414>] (__schedule+0x468/0x504) from [<c032caac>] (schedule_timeout+0x114/0x19c)
[ 2922.027294] [<c032caac>] (schedule_timeout+0x114/0x19c) from [<c0255c00>] (s3c24xx_i2c_xfer+0x1cc/0x320)
[ 2922.036754] [<c0255c00>] (s3c24xx_i2c_xfer+0x1cc/0x320) from [<c0252e08>] (__i2c_transfer+0x44/0x7c)
[ 2922.045868] [<c0252e08>] (__i2c_transfer+0x44/0x7c) from [<c025416c>] (i2c_transfer+0x74/0x98)
[ 2922.054462] [<c025416c>] (i2c_transfer+0x74/0x98) from [<c021ed38>] (regmap_i2c_read+0x48/0x64)
[ 2922.063142] [<c021ed38>] (regmap_i2c_read+0x48/0x64) from [<c021b41c>] (_regmap_raw_read+0xa8/0xfc)
[ 2922.072168] [<c021b41c>] (_regmap_raw_read+0xa8/0xfc) from [<c021b780>] (_regmap_bus_read+0x28/0x48)
[ 2922.081281] [<c021b780>] (_regmap_bus_read+0x28/0x48) from [<c0219d30>] (_regmap_read+0x5c/0xc4)
[ 2922.090048] [<c0219d30>] (_regmap_read+0x5c/0xc4) from [<c0219ddc>] (regmap_read+0x44/0x5c)
[ 2922.098383] [<c0219ddc>] (regmap_read+0x44/0x5c) from [<c0290bdc>] (max77686_clk_is_enabled+0x20/0x3c)
[ 2922.107670] [<c0290bdc>] (max77686_clk_is_enabled+0x20/0x3c) from [<c028cfdc>] (clk_disable_unused_subtree+0x6c/0xa8)
[ 2922.118258] [<c028cfdc>] (clk_disable_unused_subtree+0x6c/0xa8) from [<c028dc90>] (clk_disable_unused+0x30/0xd8)
[ 2922.128414] [<c028dc90>] (clk_disable_unused+0x30/0xd8) from [<c00087a8>] (do_one_initcall+0x38/0x160)

Fix it by replacing is_enabled call-back with is_prepared as the i2c driver may
sleep during a transfer.

Signed-off-by: Abhilash Kesavan <a.kesavan@samsung.com>
---
 drivers/clk/clk-max77686.c |    4 ++--
 1 file changed, 2 insertions(+), 2 deletions(-)

diff --git a/drivers/clk/clk-max77686.c b/drivers/clk/clk-max77686.c
index 9f57bc3..e39d463 100644
--- a/drivers/clk/clk-max77686.c
+++ b/drivers/clk/clk-max77686.c
@@ -66,7 +66,7 @@ static void max77686_clk_unprepare(struct clk_hw *hw)
 		MAX77686_REG_32KHZ, max77686->mask, ~max77686->mask);
 }
 
-static int max77686_clk_is_enabled(struct clk_hw *hw)
+static int max77686_clk_is_prepared(struct clk_hw *hw)
 {
 	struct max77686_clk *max77686 = to_max77686_clk(hw);
 	int ret;
@@ -84,7 +84,7 @@ static int max77686_clk_is_enabled(struct clk_hw *hw)
 static struct clk_ops max77686_clk_ops = {
 	.prepare	= max77686_clk_prepare,
 	.unprepare	= max77686_clk_unprepare,
-	.is_enabled	= max77686_clk_is_enabled,
+	.is_prepared	= max77686_clk_is_prepared,
 };
 
 static struct clk_init_data max77686_clks_init[MAX77686_CLKS_NUM] = {
-- 
1.7.9.5

[PATCH 3/5] clk: max77686: Replace is_enabled() with is_prepared call-back

[Abhilash Kesavan]

Following messages are observed when unused PMIC clocks are being
disabled during boot-up:
[ 2921.969560] BUG: scheduling while atomic: swapper/0/1/0x00000002
[ 2921.974080] Modules linked in:
[ 2921.977120] CPU: 0 PID: 1 Comm: swapper/0 Not tainted 3.13.0-rc1-00018-g8465d57 #27
[ 2921.984772] [<c0013c80>] (unwind_backtrace+0x0/0xf8) from [<c00110cc>] (show_stack+0x10/0x14)
[ 2921.993269] [<c00110cc>] (show_stack+0x10/0x14) from [<c032c10c>] (dump_stack+0x64/0xa4)
[ 2922.001340] [<c032c10c>] (dump_stack+0x64/0xa4) from [<c0329b00>] (__schedule_bug+0x48/0x60)
[ 2922.009758] [<c0329b00>] (__schedule_bug+0x48/0x60) from [<c032d414>] (__schedule+0x468/0x504)
[ 2922.018351] [<c032d414>] (__schedule+0x468/0x504) from [<c032caac>] (schedule_timeout+0x114/0x19c)
[ 2922.027294] [<c032caac>] (schedule_timeout+0x114/0x19c) from [<c0255c00>] (s3c24xx_i2c_xfer+0x1cc/0x320)
[ 2922.036754] [<c0255c00>] (s3c24xx_i2c_xfer+0x1cc/0x320) from [<c0252e08>] (__i2c_transfer+0x44/0x7c)
[ 2922.045868] [<c0252e08>] (__i2c_transfer+0x44/0x7c) from [<c025416c>] (i2c_transfer+0x74/0x98)
[ 2922.054462] [<c025416c>] (i2c_transfer+0x74/0x98) from [<c021ed38>] (regmap_i2c_read+0x48/0x64)
[ 2922.063142] [<c021ed38>] (regmap_i2c_read+0x48/0x64) from [<c021b41c>] (_regmap_raw_read+0xa8/0xfc)
[ 2922.072168] [<c021b41c>] (_regmap_raw_read+0xa8/0xfc) from [<c021b780>] (_regmap_bus_read+0x28/0x48)
[ 2922.081281] [<c021b780>] (_regmap_bus_read+0x28/0x48) from [<c0219d30>] (_regmap_read+0x5c/0xc4)
[ 2922.090048] [<c0219d30>] (_regmap_read+0x5c/0xc4) from [<c0219ddc>] (regmap_read+0x44/0x5c)
[ 2922.098383] [<c0219ddc>] (regmap_read+0x44/0x5c) from [<c0290bdc>] (max77686_clk_is_enabled+0x20/0x3c)
[ 2922.107670] [<c0290bdc>] (max77686_clk_is_enabled+0x20/0x3c) from [<c028cfdc>] (clk_disable_unused_subtree+0x6c/0xa8)
[ 2922.118258] [<c028cfdc>] (clk_disable_unused_subtree+0x6c/0xa8) from [<c028dc90>] (clk_disable_unused+0x30/0xd8)
[ 2922.128414] [<c028dc90>] (clk_disable_unused+0x30/0xd8) from [<c00087a8>] (do_one_initcall+0x38/0x160)

Fix it by replacing is_enabled call-back with is_prepared as the i2c driver may
sleep during a transfer.

Signed-off-by: Abhilash Kesavan <a.kesavan@samsung.com>
---
 drivers/clk/clk-max77686.c |    4 ++--
 1 file changed, 2 insertions(+), 2 deletions(-)

diff --git a/drivers/clk/clk-max77686.c b/drivers/clk/clk-max77686.c
index 9f57bc3..e39d463 100644
--- a/drivers/clk/clk-max77686.c
+++ b/drivers/clk/clk-max77686.c
@@ -66,7 +66,7 @@ static void max77686_clk_unprepare(struct clk_hw *hw)
 		MAX77686_REG_32KHZ, max77686->mask, ~max77686->mask);
 }
 
-static int max77686_clk_is_enabled(struct clk_hw *hw)
+static int max77686_clk_is_prepared(struct clk_hw *hw)
 {
 	struct max77686_clk *max77686 = to_max77686_clk(hw);
 	int ret;
@@ -84,7 +84,7 @@ static int max77686_clk_is_enabled(struct clk_hw *hw)
 static struct clk_ops max77686_clk_ops = {
 	.prepare	= max77686_clk_prepare,
 	.unprepare	= max77686_clk_unprepare,
-	.is_enabled	= max77686_clk_is_enabled,
+	.is_prepared	= max77686_clk_is_prepared,
 };
 
 static struct clk_init_data max77686_clks_init[MAX77686_CLKS_NUM] = {
-- 
1.7.9.5

Re: [PATCH 3/5] clk: max77686: Replace is_enabled() with is_prepared call-back

[Tomasz Figa]

Hi Abhilash,

On Wednesday 11 of December 2013 17:27:07 Abhilash Kesavan wrote:
> Following messages are observed when unused PMIC clocks are being
> disabled during boot-up:
> [ 2921.969560] BUG: scheduling while atomic: swapper/0/1/0x00000002
> [ 2921.974080] Modules linked in:
> [ 2921.977120] CPU: 0 PID: 1 Comm: swapper/0 Not tainted 3.13.0-rc1-00018-g8465d57 #27
> [ 2921.984772] [<c0013c80>] (unwind_backtrace+0x0/0xf8) from [<c00110cc>] (show_stack+0x10/0x14)
> [ 2921.993269] [<c00110cc>] (show_stack+0x10/0x14) from [<c032c10c>] (dump_stack+0x64/0xa4)
> [ 2922.001340] [<c032c10c>] (dump_stack+0x64/0xa4) from [<c0329b00>] (__schedule_bug+0x48/0x60)
> [ 2922.009758] [<c0329b00>] (__schedule_bug+0x48/0x60) from [<c032d414>] (__schedule+0x468/0x504)
> [ 2922.018351] [<c032d414>] (__schedule+0x468/0x504) from [<c032caac>] (schedule_timeout+0x114/0x19c)
> [ 2922.027294] [<c032caac>] (schedule_timeout+0x114/0x19c) from [<c0255c00>] (s3c24xx_i2c_xfer+0x1cc/0x320)
> [ 2922.036754] [<c0255c00>] (s3c24xx_i2c_xfer+0x1cc/0x320) from [<c0252e08>] (__i2c_transfer+0x44/0x7c)
> [ 2922.045868] [<c0252e08>] (__i2c_transfer+0x44/0x7c) from [<c025416c>] (i2c_transfer+0x74/0x98)
> [ 2922.054462] [<c025416c>] (i2c_transfer+0x74/0x98) from [<c021ed38>] (regmap_i2c_read+0x48/0x64)
> [ 2922.063142] [<c021ed38>] (regmap_i2c_read+0x48/0x64) from [<c021b41c>] (_regmap_raw_read+0xa8/0xfc)
> [ 2922.072168] [<c021b41c>] (_regmap_raw_read+0xa8/0xfc) from [<c021b780>] (_regmap_bus_read+0x28/0x48)
> [ 2922.081281] [<c021b780>] (_regmap_bus_read+0x28/0x48) from [<c0219d30>] (_regmap_read+0x5c/0xc4)
> [ 2922.090048] [<c0219d30>] (_regmap_read+0x5c/0xc4) from [<c0219ddc>] (regmap_read+0x44/0x5c)
> [ 2922.098383] [<c0219ddc>] (regmap_read+0x44/0x5c) from [<c0290bdc>] (max77686_clk_is_enabled+0x20/0x3c)
> [ 2922.107670] [<c0290bdc>] (max77686_clk_is_enabled+0x20/0x3c) from [<c028cfdc>] (clk_disable_unused_subtree+0x6c/0xa8)
> [ 2922.118258] [<c028cfdc>] (clk_disable_unused_subtree+0x6c/0xa8) from [<c028dc90>] (clk_disable_unused+0x30/0xd8)
> [ 2922.128414] [<c028dc90>] (clk_disable_unused+0x30/0xd8) from [<c00087a8>] (do_one_initcall+0x38/0x160)
> 
> Fix it by replacing is_enabled call-back with is_prepared as the i2c driver may
> sleep during a transfer.
> 
> Signed-off-by: Abhilash Kesavan <a.kesavan@samsung.com>
> ---
>  drivers/clk/clk-max77686.c |    4 ++--
>  1 file changed, 2 insertions(+), 2 deletions(-)

This has been already fixed as a part of series I sent a while ago to
fix max77686 clock driver. Unfortunately nobody seems to have applied
it.

Please refer to following thread:
http://thread.gmane.org/gmane.linux.kernel.samsung-soc/24153

I plan to rebase and resent the series soon.

Best regards,
Tomasz

[PATCH 3/5] clk: max77686: Replace is_enabled() with is_prepared call-back

[Tomasz Figa]

Hi Abhilash,

On Wednesday 11 of December 2013 17:27:07 Abhilash Kesavan wrote:
> Following messages are observed when unused PMIC clocks are being
> disabled during boot-up:
> [ 2921.969560] BUG: scheduling while atomic: swapper/0/1/0x00000002
> [ 2921.974080] Modules linked in:
> [ 2921.977120] CPU: 0 PID: 1 Comm: swapper/0 Not tainted 3.13.0-rc1-00018-g8465d57 #27
> [ 2921.984772] [<c0013c80>] (unwind_backtrace+0x0/0xf8) from [<c00110cc>] (show_stack+0x10/0x14)
> [ 2921.993269] [<c00110cc>] (show_stack+0x10/0x14) from [<c032c10c>] (dump_stack+0x64/0xa4)
> [ 2922.001340] [<c032c10c>] (dump_stack+0x64/0xa4) from [<c0329b00>] (__schedule_bug+0x48/0x60)
> [ 2922.009758] [<c0329b00>] (__schedule_bug+0x48/0x60) from [<c032d414>] (__schedule+0x468/0x504)
> [ 2922.018351] [<c032d414>] (__schedule+0x468/0x504) from [<c032caac>] (schedule_timeout+0x114/0x19c)
> [ 2922.027294] [<c032caac>] (schedule_timeout+0x114/0x19c) from [<c0255c00>] (s3c24xx_i2c_xfer+0x1cc/0x320)
> [ 2922.036754] [<c0255c00>] (s3c24xx_i2c_xfer+0x1cc/0x320) from [<c0252e08>] (__i2c_transfer+0x44/0x7c)
> [ 2922.045868] [<c0252e08>] (__i2c_transfer+0x44/0x7c) from [<c025416c>] (i2c_transfer+0x74/0x98)
> [ 2922.054462] [<c025416c>] (i2c_transfer+0x74/0x98) from [<c021ed38>] (regmap_i2c_read+0x48/0x64)
> [ 2922.063142] [<c021ed38>] (regmap_i2c_read+0x48/0x64) from [<c021b41c>] (_regmap_raw_read+0xa8/0xfc)
> [ 2922.072168] [<c021b41c>] (_regmap_raw_read+0xa8/0xfc) from [<c021b780>] (_regmap_bus_read+0x28/0x48)
> [ 2922.081281] [<c021b780>] (_regmap_bus_read+0x28/0x48) from [<c0219d30>] (_regmap_read+0x5c/0xc4)
> [ 2922.090048] [<c0219d30>] (_regmap_read+0x5c/0xc4) from [<c0219ddc>] (regmap_read+0x44/0x5c)
> [ 2922.098383] [<c0219ddc>] (regmap_read+0x44/0x5c) from [<c0290bdc>] (max77686_clk_is_enabled+0x20/0x3c)
> [ 2922.107670] [<c0290bdc>] (max77686_clk_is_enabled+0x20/0x3c) from [<c028cfdc>] (clk_disable_unused_subtree+0x6c/0xa8)
> [ 2922.118258] [<c028cfdc>] (clk_disable_unused_subtree+0x6c/0xa8) from [<c028dc90>] (clk_disable_unused+0x30/0xd8)
> [ 2922.128414] [<c028dc90>] (clk_disable_unused+0x30/0xd8) from [<c00087a8>] (do_one_initcall+0x38/0x160)
> 
> Fix it by replacing is_enabled call-back with is_prepared as the i2c driver may
> sleep during a transfer.
> 
> Signed-off-by: Abhilash Kesavan <a.kesavan@samsung.com>
> ---
>  drivers/clk/clk-max77686.c |    4 ++--
>  1 file changed, 2 insertions(+), 2 deletions(-)

This has been already fixed as a part of series I sent a while ago to
fix max77686 clock driver. Unfortunately nobody seems to have applied
it.

Please refer to following thread:
http://thread.gmane.org/gmane.linux.kernel.samsung-soc/24153

I plan to rebase and resent the series soon.

Best regards,
Tomasz

Re: [PATCH 3/5] clk: max77686: Replace is_enabled() with is_prepared call-back

[Abhilash Kesavan]

Hi Tomasz,

On Wed, Dec 11, 2013 at 5:54 PM, Tomasz Figa <t.figa@samsung.com> wrote:
> Hi Abhilash,
>
> On Wednesday 11 of December 2013 17:27:07 Abhilash Kesavan wrote:
>> Following messages are observed when unused PMIC clocks are being
>> disabled during boot-up:
>> [ 2921.969560] BUG: scheduling while atomic: swapper/0/1/0x00000002
>> [ 2921.974080] Modules linked in:
>> [ 2921.977120] CPU: 0 PID: 1 Comm: swapper/0 Not tainted 3.13.0-rc1-00018-g8465d57 #27
>> [ 2921.984772] [<c0013c80>] (unwind_backtrace+0x0/0xf8) from [<c00110cc>] (show_stack+0x10/0x14)
>> [ 2921.993269] [<c00110cc>] (show_stack+0x10/0x14) from [<c032c10c>] (dump_stack+0x64/0xa4)
>> [ 2922.001340] [<c032c10c>] (dump_stack+0x64/0xa4) from [<c0329b00>] (__schedule_bug+0x48/0x60)
>> [ 2922.009758] [<c0329b00>] (__schedule_bug+0x48/0x60) from [<c032d414>] (__schedule+0x468/0x504)
>> [ 2922.018351] [<c032d414>] (__schedule+0x468/0x504) from [<c032caac>] (schedule_timeout+0x114/0x19c)
>> [ 2922.027294] [<c032caac>] (schedule_timeout+0x114/0x19c) from [<c0255c00>] (s3c24xx_i2c_xfer+0x1cc/0x320)
>> [ 2922.036754] [<c0255c00>] (s3c24xx_i2c_xfer+0x1cc/0x320) from [<c0252e08>] (__i2c_transfer+0x44/0x7c)
>> [ 2922.045868] [<c0252e08>] (__i2c_transfer+0x44/0x7c) from [<c025416c>] (i2c_transfer+0x74/0x98)
>> [ 2922.054462] [<c025416c>] (i2c_transfer+0x74/0x98) from [<c021ed38>] (regmap_i2c_read+0x48/0x64)
>> [ 2922.063142] [<c021ed38>] (regmap_i2c_read+0x48/0x64) from [<c021b41c>] (_regmap_raw_read+0xa8/0xfc)
>> [ 2922.072168] [<c021b41c>] (_regmap_raw_read+0xa8/0xfc) from [<c021b780>] (_regmap_bus_read+0x28/0x48)
>> [ 2922.081281] [<c021b780>] (_regmap_bus_read+0x28/0x48) from [<c0219d30>] (_regmap_read+0x5c/0xc4)
>> [ 2922.090048] [<c0219d30>] (_regmap_read+0x5c/0xc4) from [<c0219ddc>] (regmap_read+0x44/0x5c)
>> [ 2922.098383] [<c0219ddc>] (regmap_read+0x44/0x5c) from [<c0290bdc>] (max77686_clk_is_enabled+0x20/0x3c)
>> [ 2922.107670] [<c0290bdc>] (max77686_clk_is_enabled+0x20/0x3c) from [<c028cfdc>] (clk_disable_unused_subtree+0x6c/0xa8)
>> [ 2922.118258] [<c028cfdc>] (clk_disable_unused_subtree+0x6c/0xa8) from [<c028dc90>] (clk_disable_unused+0x30/0xd8)
>> [ 2922.128414] [<c028dc90>] (clk_disable_unused+0x30/0xd8) from [<c00087a8>] (do_one_initcall+0x38/0x160)
>>
>> Fix it by replacing is_enabled call-back with is_prepared as the i2c driver may
>> sleep during a transfer.
>>
>> Signed-off-by: Abhilash Kesavan <a.kesavan@samsung.com>
>> ---
>>  drivers/clk/clk-max77686.c |    4 ++--
>>  1 file changed, 2 insertions(+), 2 deletions(-)
>
> This has been already fixed as a part of series I sent a while ago to
> fix max77686 clock driver. Unfortunately nobody seems to have applied
> it.
>
> Please refer to following thread:
> http://thread.gmane.org/gmane.linux.kernel.samsung-soc/24153
>
> I plan to rebase and resent the series soon.

Great, your patchset also adds OF support which was what I was looking
to do next. I'll wait for the rebased patchset.
>
> Best regards,
> Tomasz

Thanks,
Abhilash

[PATCH 3/5] clk: max77686: Replace is_enabled() with is_prepared call-back

[Abhilash Kesavan]

Hi Tomasz,

On Wed, Dec 11, 2013 at 5:54 PM, Tomasz Figa <t.figa@samsung.com> wrote:
> Hi Abhilash,
>
> On Wednesday 11 of December 2013 17:27:07 Abhilash Kesavan wrote:
>> Following messages are observed when unused PMIC clocks are being
>> disabled during boot-up:
>> [ 2921.969560] BUG: scheduling while atomic: swapper/0/1/0x00000002
>> [ 2921.974080] Modules linked in:
>> [ 2921.977120] CPU: 0 PID: 1 Comm: swapper/0 Not tainted 3.13.0-rc1-00018-g8465d57 #27
>> [ 2921.984772] [<c0013c80>] (unwind_backtrace+0x0/0xf8) from [<c00110cc>] (show_stack+0x10/0x14)
>> [ 2921.993269] [<c00110cc>] (show_stack+0x10/0x14) from [<c032c10c>] (dump_stack+0x64/0xa4)
>> [ 2922.001340] [<c032c10c>] (dump_stack+0x64/0xa4) from [<c0329b00>] (__schedule_bug+0x48/0x60)
>> [ 2922.009758] [<c0329b00>] (__schedule_bug+0x48/0x60) from [<c032d414>] (__schedule+0x468/0x504)
>> [ 2922.018351] [<c032d414>] (__schedule+0x468/0x504) from [<c032caac>] (schedule_timeout+0x114/0x19c)
>> [ 2922.027294] [<c032caac>] (schedule_timeout+0x114/0x19c) from [<c0255c00>] (s3c24xx_i2c_xfer+0x1cc/0x320)
>> [ 2922.036754] [<c0255c00>] (s3c24xx_i2c_xfer+0x1cc/0x320) from [<c0252e08>] (__i2c_transfer+0x44/0x7c)
>> [ 2922.045868] [<c0252e08>] (__i2c_transfer+0x44/0x7c) from [<c025416c>] (i2c_transfer+0x74/0x98)
>> [ 2922.054462] [<c025416c>] (i2c_transfer+0x74/0x98) from [<c021ed38>] (regmap_i2c_read+0x48/0x64)
>> [ 2922.063142] [<c021ed38>] (regmap_i2c_read+0x48/0x64) from [<c021b41c>] (_regmap_raw_read+0xa8/0xfc)
>> [ 2922.072168] [<c021b41c>] (_regmap_raw_read+0xa8/0xfc) from [<c021b780>] (_regmap_bus_read+0x28/0x48)
>> [ 2922.081281] [<c021b780>] (_regmap_bus_read+0x28/0x48) from [<c0219d30>] (_regmap_read+0x5c/0xc4)
>> [ 2922.090048] [<c0219d30>] (_regmap_read+0x5c/0xc4) from [<c0219ddc>] (regmap_read+0x44/0x5c)
>> [ 2922.098383] [<c0219ddc>] (regmap_read+0x44/0x5c) from [<c0290bdc>] (max77686_clk_is_enabled+0x20/0x3c)
>> [ 2922.107670] [<c0290bdc>] (max77686_clk_is_enabled+0x20/0x3c) from [<c028cfdc>] (clk_disable_unused_subtree+0x6c/0xa8)
>> [ 2922.118258] [<c028cfdc>] (clk_disable_unused_subtree+0x6c/0xa8) from [<c028dc90>] (clk_disable_unused+0x30/0xd8)
>> [ 2922.128414] [<c028dc90>] (clk_disable_unused+0x30/0xd8) from [<c00087a8>] (do_one_initcall+0x38/0x160)
>>
>> Fix it by replacing is_enabled call-back with is_prepared as the i2c driver may
>> sleep during a transfer.
>>
>> Signed-off-by: Abhilash Kesavan <a.kesavan@samsung.com>
>> ---
>>  drivers/clk/clk-max77686.c |    4 ++--
>>  1 file changed, 2 insertions(+), 2 deletions(-)
>
> This has been already fixed as a part of series I sent a while ago to
> fix max77686 clock driver. Unfortunately nobody seems to have applied
> it.
>
> Please refer to following thread:
> http://thread.gmane.org/gmane.linux.kernel.samsung-soc/24153
>
> I plan to rebase and resent the series soon.

Great, your patchset also adds OF support which was what I was looking
to do next. I'll wait for the rebased patchset.
>
> Best regards,
> Tomasz

Thanks,
Abhilash

[PATCH 4/5] ARM: EXYNOS5250: Implement pm_power_off

[Abhilash Kesavan]

From: Olof Johansson <olofj@chromium.org>

Add pm_power_off callback function for exynos5250 to make soft
power off work properly.

Signed-off-by: Abhilash Kesavan <a.kesavan@samsung.com>
Signed-off-by: Olof Johansson <olofj@chromium.org>
---
 arch/arm/mach-exynos/include/mach/regs-pmu.h |    3 +++
 arch/arm/mach-exynos/pmu.c                   |   20 ++++++++++++++++++++
 2 files changed, 23 insertions(+)

diff --git a/arch/arm/mach-exynos/include/mach/regs-pmu.h b/arch/arm/mach-exynos/include/mach/regs-pmu.h
index 2cdb63e..da2fab0 100644
--- a/arch/arm/mach-exynos/include/mach/regs-pmu.h
+++ b/arch/arm/mach-exynos/include/mach/regs-pmu.h
@@ -343,6 +343,7 @@
 #define EXYNOS5_TOP_PWR_OPTION					S5P_PMUREG(0x2C48)
 #define EXYNOS5_TOP_PWR_SYSMEM_OPTION				S5P_PMUREG(0x2CC8)
 #define EXYNOS5_JPEG_MEM_OPTION					S5P_PMUREG(0x2F48)
+#define EXYNOS5_PS_HOLD_CONTROL					S5P_PMUREG(0x330C)
 #define EXYNOS5_GSCL_STATUS					S5P_PMUREG(0x4004)
 #define EXYNOS5_ISP_STATUS					S5P_PMUREG(0x4024)
 #define EXYNOS5_GSCL_OPTION					S5P_PMUREG(0x4008)
@@ -365,4 +366,6 @@
 
 #define EXYNOS5_OPTION_USE_RETENTION				(1 << 4)
 
+#define EXYNOS5_PS_HOLD_CONTROL_DATA				(1 << 8)
+
 #endif /* __ASM_ARCH_REGS_PMU_H */
diff --git a/arch/arm/mach-exynos/pmu.c b/arch/arm/mach-exynos/pmu.c
index 5f4d26b..9053b6c 100644
--- a/arch/arm/mach-exynos/pmu.c
+++ b/arch/arm/mach-exynos/pmu.c
@@ -12,6 +12,8 @@
 #include <linux/io.h>
 #include <linux/kernel.h>
 #include <linux/bug.h>
+#include <linux/delay.h>
+#include <linux/pm.h>
 
 #include <mach/regs-clock.h>
 
@@ -409,6 +411,23 @@ void exynos_sys_powerdown_conf(enum sys_powerdown mode)
 	}
 }
 
+static void exynos5_power_off(void)
+{
+	unsigned int tmp;
+
+	pr_info("Power down\n");
+	tmp = __raw_readl(EXYNOS5_PS_HOLD_CONTROL);
+	tmp &= ~EXYNOS5_PS_HOLD_CONTROL_DATA;
+	__raw_writel(tmp, EXYNOS5_PS_HOLD_CONTROL);
+
+	/* Wait a little so we don't give a false warning below */
+	mdelay(100);
+
+	pr_err("Power down failed, please power off system manually.\n");
+	while (1)
+		;
+}
+
 static int __init exynos_pmu_init(void)
 {
 	unsigned int value;
@@ -444,6 +463,7 @@ static int __init exynos_pmu_init(void)
 			__raw_writel(0x0, exynos5_list_disable_pmu_reg[i]);
 
 		exynos_pmu_config = exynos5250_pmu_config;
+		pm_power_off = exynos5_power_off;
 		pr_info("EXYNOS5250 PMU Initialize\n");
 	} else {
 		pr_info("EXYNOS: PMU not supported\n");
-- 
1.7.9.5

[PATCH 4/5] ARM: EXYNOS5250: Implement pm_power_off

[Abhilash Kesavan]

From: Olof Johansson <olofj@chromium.org>

Add pm_power_off callback function for exynos5250 to make soft
power off work properly.

Signed-off-by: Abhilash Kesavan <a.kesavan@samsung.com>
Signed-off-by: Olof Johansson <olofj@chromium.org>
---
 arch/arm/mach-exynos/include/mach/regs-pmu.h |    3 +++
 arch/arm/mach-exynos/pmu.c                   |   20 ++++++++++++++++++++
 2 files changed, 23 insertions(+)

diff --git a/arch/arm/mach-exynos/include/mach/regs-pmu.h b/arch/arm/mach-exynos/include/mach/regs-pmu.h
index 2cdb63e..da2fab0 100644
--- a/arch/arm/mach-exynos/include/mach/regs-pmu.h
+++ b/arch/arm/mach-exynos/include/mach/regs-pmu.h
@@ -343,6 +343,7 @@
 #define EXYNOS5_TOP_PWR_OPTION					S5P_PMUREG(0x2C48)
 #define EXYNOS5_TOP_PWR_SYSMEM_OPTION				S5P_PMUREG(0x2CC8)
 #define EXYNOS5_JPEG_MEM_OPTION					S5P_PMUREG(0x2F48)
+#define EXYNOS5_PS_HOLD_CONTROL					S5P_PMUREG(0x330C)
 #define EXYNOS5_GSCL_STATUS					S5P_PMUREG(0x4004)
 #define EXYNOS5_ISP_STATUS					S5P_PMUREG(0x4024)
 #define EXYNOS5_GSCL_OPTION					S5P_PMUREG(0x4008)
@@ -365,4 +366,6 @@
 
 #define EXYNOS5_OPTION_USE_RETENTION				(1 << 4)
 
+#define EXYNOS5_PS_HOLD_CONTROL_DATA				(1 << 8)
+
 #endif /* __ASM_ARCH_REGS_PMU_H */
diff --git a/arch/arm/mach-exynos/pmu.c b/arch/arm/mach-exynos/pmu.c
index 5f4d26b..9053b6c 100644
--- a/arch/arm/mach-exynos/pmu.c
+++ b/arch/arm/mach-exynos/pmu.c
@@ -12,6 +12,8 @@
 #include <linux/io.h>
 #include <linux/kernel.h>
 #include <linux/bug.h>
+#include <linux/delay.h>
+#include <linux/pm.h>
 
 #include <mach/regs-clock.h>
 
@@ -409,6 +411,23 @@ void exynos_sys_powerdown_conf(enum sys_powerdown mode)
 	}
 }
 
+static void exynos5_power_off(void)
+{
+	unsigned int tmp;
+
+	pr_info("Power down\n");
+	tmp = __raw_readl(EXYNOS5_PS_HOLD_CONTROL);
+	tmp &= ~EXYNOS5_PS_HOLD_CONTROL_DATA;
+	__raw_writel(tmp, EXYNOS5_PS_HOLD_CONTROL);
+
+	/* Wait a little so we don't give a false warning below */
+	mdelay(100);
+
+	pr_err("Power down failed, please power off system manually.\n");
+	while (1)
+		;
+}
+
 static int __init exynos_pmu_init(void)
 {
 	unsigned int value;
@@ -444,6 +463,7 @@ static int __init exynos_pmu_init(void)
 			__raw_writel(0x0, exynos5_list_disable_pmu_reg[i]);
 
 		exynos_pmu_config = exynos5250_pmu_config;
+		pm_power_off = exynos5_power_off;
 		pr_info("EXYNOS5250 PMU Initialize\n");
 	} else {
 		pr_info("EXYNOS: PMU not supported\n");
-- 
1.7.9.5

[PATCH 5/5] ARM: dts: Setup the interrupt parent for max77686

[Abhilash Kesavan]

Fix the following warning message:
[ 2921.671238] WARNING: CPU: 0 PID: 1 at kernel/irq/irqdomain.c:399 irq_create_mapping+0xe4/0xfc()
[ 2921.679907] irq_create_mapping(, b) called with NULL domain
[ 2921.685462] Modules linked in:
[ 2921.688498] CPU: 0 PID: 1 Comm: swapper/0 Not tainted 3.13.0-rc1-00026-g36cc776 #67
[ 2921.696154] [<c0013c80>] (unwind_backtrace+0x0/0xf8) from [<c00110cc>] (show_stack+0x10/0x14)
[ 2921.704654] [<c00110cc>] (show_stack+0x10/0x14) from [<c03779fc>] (dump_stack+0x64/0xa4)
[ 2921.712725] [<c03779fc>] (dump_stack+0x64/0xa4) from [<c001c830>] (warn_slowpath_common+0x64/0x84)
[ 2921.721663] [<c001c830>] (warn_slowpath_common+0x64/0x84) from [<c001c8e4>] (warn_slowpath_fmt+0x30/0x40)
[ 2921.731210] [<c001c8e4>] (warn_slowpath_fmt+0x30/0x40) from [<c005a564>] (irq_create_mapping+0xe4/0xfc)
[ 2921.740590] [<c005a564>] (irq_create_mapping+0xe4/0xfc) from [<c029c85c>] (max77686_rtc_probe+0x110/0x21c)
[ 2921.750221] [<c029c85c>] (max77686_rtc_probe+0x110/0x21c) from [<c02253a8>] (platform_drv_probe+0x18/0x48)

Also setup the default state of the max77686 irq line.

Signed-off-by: Abhilash Kesavan <a.kesavan@samsung.com>
---
 arch/arm/boot/dts/cros5250-common.dtsi |   11 +++++++++++
 1 file changed, 11 insertions(+)

diff --git a/arch/arm/boot/dts/cros5250-common.dtsi b/arch/arm/boot/dts/cros5250-common.dtsi
index 6470536..dc853b9 100644
--- a/arch/arm/boot/dts/cros5250-common.dtsi
+++ b/arch/arm/boot/dts/cros5250-common.dtsi
@@ -27,6 +27,13 @@
 		i2c2_bus: i2c2-bus {
 			samsung,pin-pud = <0>;
 		};
+
+		max77686_irq: max77686-irq {
+			samsung,pins = "gpx3-2";
+			samsung,pin-function = <0>;
+			samsung,pin-pud = <0>;
+			samsung,pin-drv = <0>;
+		};
 	};
 
 	i2c@12C60000 {
@@ -36,6 +43,10 @@
 		max77686@09 {
 			compatible = "maxim,max77686";
 			reg = <0x09>;
+			interrupt-parent = <&gpx3>;
+			interrupts = <2 0>;
+			pinctrl-names = "default";
+			pinctrl-0 = <&max77686_irq>;
 
 			voltage-regulators {
 				ldo1_reg: LDO1 {
-- 
1.7.9.5

[PATCH 5/5] ARM: dts: Setup the interrupt parent for max77686

[Abhilash Kesavan]

Fix the following warning message:
[ 2921.671238] WARNING: CPU: 0 PID: 1 at kernel/irq/irqdomain.c:399 irq_create_mapping+0xe4/0xfc()
[ 2921.679907] irq_create_mapping(, b) called with NULL domain
[ 2921.685462] Modules linked in:
[ 2921.688498] CPU: 0 PID: 1 Comm: swapper/0 Not tainted 3.13.0-rc1-00026-g36cc776 #67
[ 2921.696154] [<c0013c80>] (unwind_backtrace+0x0/0xf8) from [<c00110cc>] (show_stack+0x10/0x14)
[ 2921.704654] [<c00110cc>] (show_stack+0x10/0x14) from [<c03779fc>] (dump_stack+0x64/0xa4)
[ 2921.712725] [<c03779fc>] (dump_stack+0x64/0xa4) from [<c001c830>] (warn_slowpath_common+0x64/0x84)
[ 2921.721663] [<c001c830>] (warn_slowpath_common+0x64/0x84) from [<c001c8e4>] (warn_slowpath_fmt+0x30/0x40)
[ 2921.731210] [<c001c8e4>] (warn_slowpath_fmt+0x30/0x40) from [<c005a564>] (irq_create_mapping+0xe4/0xfc)
[ 2921.740590] [<c005a564>] (irq_create_mapping+0xe4/0xfc) from [<c029c85c>] (max77686_rtc_probe+0x110/0x21c)
[ 2921.750221] [<c029c85c>] (max77686_rtc_probe+0x110/0x21c) from [<c02253a8>] (platform_drv_probe+0x18/0x48)

Also setup the default state of the max77686 irq line.

Signed-off-by: Abhilash Kesavan <a.kesavan@samsung.com>
---
 arch/arm/boot/dts/cros5250-common.dtsi |   11 +++++++++++
 1 file changed, 11 insertions(+)

diff --git a/arch/arm/boot/dts/cros5250-common.dtsi b/arch/arm/boot/dts/cros5250-common.dtsi
index 6470536..dc853b9 100644
--- a/arch/arm/boot/dts/cros5250-common.dtsi
+++ b/arch/arm/boot/dts/cros5250-common.dtsi
@@ -27,6 +27,13 @@
 		i2c2_bus: i2c2-bus {
 			samsung,pin-pud = <0>;
 		};
+
+		max77686_irq: max77686-irq {
+			samsung,pins = "gpx3-2";
+			samsung,pin-function = <0>;
+			samsung,pin-pud = <0>;
+			samsung,pin-drv = <0>;
+		};
 	};
 
 	i2c at 12C60000 {
@@ -36,6 +43,10 @@
 		max77686 at 09 {
 			compatible = "maxim,max77686";
 			reg = <0x09>;
+			interrupt-parent = <&gpx3>;
+			interrupts = <2 0>;
+			pinctrl-names = "default";
+			pinctrl-0 = <&max77686_irq>;
 
 			voltage-regulators {
 				ldo1_reg: LDO1 {
-- 
1.7.9.5

Re: [PATCH 5/5] ARM: dts: Setup the interrupt parent for max77686

[Doug Anderson]

Abhliash,

On Wed, Dec 11, 2013 at 3:57 AM, Abhilash Kesavan <a.kesavan@samsung.com> wrote:
> Fix the following warning message:
> [ 2921.671238] WARNING: CPU: 0 PID: 1 at kernel/irq/irqdomain.c:399 irq_create_mapping+0xe4/0xfc()
> [ 2921.679907] irq_create_mapping(, b) called with NULL domain
> [ 2921.685462] Modules linked in:
> [ 2921.688498] CPU: 0 PID: 1 Comm: swapper/0 Not tainted 3.13.0-rc1-00026-g36cc776 #67
> [ 2921.696154] [<c0013c80>] (unwind_backtrace+0x0/0xf8) from [<c00110cc>] (show_stack+0x10/0x14)
> [ 2921.704654] [<c00110cc>] (show_stack+0x10/0x14) from [<c03779fc>] (dump_stack+0x64/0xa4)
> [ 2921.712725] [<c03779fc>] (dump_stack+0x64/0xa4) from [<c001c830>] (warn_slowpath_common+0x64/0x84)
> [ 2921.721663] [<c001c830>] (warn_slowpath_common+0x64/0x84) from [<c001c8e4>] (warn_slowpath_fmt+0x30/0x40)
> [ 2921.731210] [<c001c8e4>] (warn_slowpath_fmt+0x30/0x40) from [<c005a564>] (irq_create_mapping+0xe4/0xfc)
> [ 2921.740590] [<c005a564>] (irq_create_mapping+0xe4/0xfc) from [<c029c85c>] (max77686_rtc_probe+0x110/0x21c)
> [ 2921.750221] [<c029c85c>] (max77686_rtc_probe+0x110/0x21c) from [<c02253a8>] (platform_drv_probe+0x18/0x48)
>
> Also setup the default state of the max77686 irq line.
>
> Signed-off-by: Abhilash Kesavan <a.kesavan@samsung.com>
> ---
>  arch/arm/boot/dts/cros5250-common.dtsi |   11 +++++++++++
>  1 file changed, 11 insertions(+)

Thank you for sending stuff upstream, but I'm afraid this patch has
already landed:

c61248a ARM: dts: Add max77686 RTC interrupt to cros5250-common

My patch matches yours but also includes the "wakeup-source" property.

[PATCH 5/5] ARM: dts: Setup the interrupt parent for max77686

[Doug Anderson]

Abhliash,

On Wed, Dec 11, 2013 at 3:57 AM, Abhilash Kesavan <a.kesavan@samsung.com> wrote:
> Fix the following warning message:
> [ 2921.671238] WARNING: CPU: 0 PID: 1 at kernel/irq/irqdomain.c:399 irq_create_mapping+0xe4/0xfc()
> [ 2921.679907] irq_create_mapping(, b) called with NULL domain
> [ 2921.685462] Modules linked in:
> [ 2921.688498] CPU: 0 PID: 1 Comm: swapper/0 Not tainted 3.13.0-rc1-00026-g36cc776 #67
> [ 2921.696154] [<c0013c80>] (unwind_backtrace+0x0/0xf8) from [<c00110cc>] (show_stack+0x10/0x14)
> [ 2921.704654] [<c00110cc>] (show_stack+0x10/0x14) from [<c03779fc>] (dump_stack+0x64/0xa4)
> [ 2921.712725] [<c03779fc>] (dump_stack+0x64/0xa4) from [<c001c830>] (warn_slowpath_common+0x64/0x84)
> [ 2921.721663] [<c001c830>] (warn_slowpath_common+0x64/0x84) from [<c001c8e4>] (warn_slowpath_fmt+0x30/0x40)
> [ 2921.731210] [<c001c8e4>] (warn_slowpath_fmt+0x30/0x40) from [<c005a564>] (irq_create_mapping+0xe4/0xfc)
> [ 2921.740590] [<c005a564>] (irq_create_mapping+0xe4/0xfc) from [<c029c85c>] (max77686_rtc_probe+0x110/0x21c)
> [ 2921.750221] [<c029c85c>] (max77686_rtc_probe+0x110/0x21c) from [<c02253a8>] (platform_drv_probe+0x18/0x48)
>
> Also setup the default state of the max77686 irq line.
>
> Signed-off-by: Abhilash Kesavan <a.kesavan@samsung.com>
> ---
>  arch/arm/boot/dts/cros5250-common.dtsi |   11 +++++++++++
>  1 file changed, 11 insertions(+)

Thank you for sending stuff upstream, but I'm afraid this patch has
already landed:

c61248a ARM: dts: Add max77686 RTC interrupt to cros5250-common

My patch matches yours but also includes the "wakeup-source" property.

Re: [PATCH 5/5] ARM: dts: Setup the interrupt parent for max77686

[Abhilash Kesavan]

Hi Doug,

On Thu, Dec 12, 2013 at 5:27 AM, Doug Anderson <dianders@chromium.org> wrote:
> Abhliash,
>
> On Wed, Dec 11, 2013 at 3:57 AM, Abhilash Kesavan <a.kesavan@samsung.com> wrote:
>> Fix the following warning message:
>> [ 2921.671238] WARNING: CPU: 0 PID: 1 at kernel/irq/irqdomain.c:399 irq_create_mapping+0xe4/0xfc()
>> [ 2921.679907] irq_create_mapping(, b) called with NULL domain
>> [ 2921.685462] Modules linked in:
>> [ 2921.688498] CPU: 0 PID: 1 Comm: swapper/0 Not tainted 3.13.0-rc1-00026-g36cc776 #67
>> [ 2921.696154] [<c0013c80>] (unwind_backtrace+0x0/0xf8) from [<c00110cc>] (show_stack+0x10/0x14)
>> [ 2921.704654] [<c00110cc>] (show_stack+0x10/0x14) from [<c03779fc>] (dump_stack+0x64/0xa4)
>> [ 2921.712725] [<c03779fc>] (dump_stack+0x64/0xa4) from [<c001c830>] (warn_slowpath_common+0x64/0x84)
>> [ 2921.721663] [<c001c830>] (warn_slowpath_common+0x64/0x84) from [<c001c8e4>] (warn_slowpath_fmt+0x30/0x40)
>> [ 2921.731210] [<c001c8e4>] (warn_slowpath_fmt+0x30/0x40) from [<c005a564>] (irq_create_mapping+0xe4/0xfc)
>> [ 2921.740590] [<c005a564>] (irq_create_mapping+0xe4/0xfc) from [<c029c85c>] (max77686_rtc_probe+0x110/0x21c)
>> [ 2921.750221] [<c029c85c>] (max77686_rtc_probe+0x110/0x21c) from [<c02253a8>] (platform_drv_probe+0x18/0x48)
>>
>> Also setup the default state of the max77686 irq line.
>>
>> Signed-off-by: Abhilash Kesavan <a.kesavan@samsung.com>
>> ---
>>  arch/arm/boot/dts/cros5250-common.dtsi |   11 +++++++++++
>>  1 file changed, 11 insertions(+)
>
> Thank you for sending stuff upstream, but I'm afraid this patch has
> already landed:
>
> c61248a ARM: dts: Add max77686 RTC interrupt to cros5250-common
>
> My patch matches yours but also includes the "wakeup-source" property.

I was working on Kgene's for-next; I do see your patch in linux-next.

Regards,
Abhilash

[PATCH 5/5] ARM: dts: Setup the interrupt parent for max77686

[Abhilash Kesavan]

Hi Doug,

On Thu, Dec 12, 2013 at 5:27 AM, Doug Anderson <dianders@chromium.org> wrote:
> Abhliash,
>
> On Wed, Dec 11, 2013 at 3:57 AM, Abhilash Kesavan <a.kesavan@samsung.com> wrote:
>> Fix the following warning message:
>> [ 2921.671238] WARNING: CPU: 0 PID: 1 at kernel/irq/irqdomain.c:399 irq_create_mapping+0xe4/0xfc()
>> [ 2921.679907] irq_create_mapping(, b) called with NULL domain
>> [ 2921.685462] Modules linked in:
>> [ 2921.688498] CPU: 0 PID: 1 Comm: swapper/0 Not tainted 3.13.0-rc1-00026-g36cc776 #67
>> [ 2921.696154] [<c0013c80>] (unwind_backtrace+0x0/0xf8) from [<c00110cc>] (show_stack+0x10/0x14)
>> [ 2921.704654] [<c00110cc>] (show_stack+0x10/0x14) from [<c03779fc>] (dump_stack+0x64/0xa4)
>> [ 2921.712725] [<c03779fc>] (dump_stack+0x64/0xa4) from [<c001c830>] (warn_slowpath_common+0x64/0x84)
>> [ 2921.721663] [<c001c830>] (warn_slowpath_common+0x64/0x84) from [<c001c8e4>] (warn_slowpath_fmt+0x30/0x40)
>> [ 2921.731210] [<c001c8e4>] (warn_slowpath_fmt+0x30/0x40) from [<c005a564>] (irq_create_mapping+0xe4/0xfc)
>> [ 2921.740590] [<c005a564>] (irq_create_mapping+0xe4/0xfc) from [<c029c85c>] (max77686_rtc_probe+0x110/0x21c)
>> [ 2921.750221] [<c029c85c>] (max77686_rtc_probe+0x110/0x21c) from [<c02253a8>] (platform_drv_probe+0x18/0x48)
>>
>> Also setup the default state of the max77686 irq line.
>>
>> Signed-off-by: Abhilash Kesavan <a.kesavan@samsung.com>
>> ---
>>  arch/arm/boot/dts/cros5250-common.dtsi |   11 +++++++++++
>>  1 file changed, 11 insertions(+)
>
> Thank you for sending stuff upstream, but I'm afraid this patch has
> already landed:
>
> c61248a ARM: dts: Add max77686 RTC interrupt to cros5250-common
>
> My patch matches yours but also includes the "wakeup-source" property.

I was working on Kgene's for-next; I do see your patch in linux-next.

Regards,
Abhilash

Re: [PATCH 0/5] Power Related Fixes for Exynos5250

[Tomasz Figa]

Hi Abhilash,

On Wednesday 11 of December 2013 17:27:04 Abhilash Kesavan wrote:
> Patch 1 prevents the gating of sysreg clock on Exynos5250.
> Patch 2 is a re-send of an earlier patch.
> (http://www.spinics.net/lists/linux-samsung-soc/msg15485.html)
> Patches 3 and 4 are fixes for MAX77686 on Exynos5250 based Snow
> board (boot-up issues).
> Patch 5 implements a power-off call-back for Exynos5250 that can
> be re-used for Exynos5420.
> 
> The patches have been tested on an SMDK5250 based Chromebook.
> 
> Abhilash Kesavan (4):
>   clk: samsung: exynos5250: Add CLK_IGNORE_UNUSED flag for the sysreg
>     clock
>   ARM: EXYNOS5: Fix PMU register configuration for local power blocks
>   clk: max77686: Replace is_enabled() with is_prepared call-back
>   ARM: dts: Setup the interrupt parent for max77686
> 
> Olof Johansson (1):
>   ARM: EXYNOS5250: Implement pm_power_off
> 
>  arch/arm/boot/dts/cros5250-common.dtsi       |   11 ++++
>  arch/arm/mach-exynos/include/mach/regs-pmu.h |    3 +
>  arch/arm/mach-exynos/pmu.c                   |   86 ++++++++++++++++++++------
>  drivers/clk/clk-max77686.c                   |    4 +-
>  drivers/clk/samsung/clk-exynos5250.c         |    3 +-
>  5 files changed, 86 insertions(+), 21 deletions(-)

You used the old and now invalid address of DT mailing list.

Anyway, there is no need to send patches for .dts* files to DT mailing
list anymore. Just changes in drivers that affect how they handle data
from DT and binding documentation (Documentation/devicetree/.*). So
please drop the DT mailing list in next iteration of the series.

Best regards,
Tomasz

[PATCH 0/5] Power Related Fixes for Exynos5250

[Tomasz Figa]

Hi Abhilash,

On Wednesday 11 of December 2013 17:27:04 Abhilash Kesavan wrote:
> Patch 1 prevents the gating of sysreg clock on Exynos5250.
> Patch 2 is a re-send of an earlier patch.
> (http://www.spinics.net/lists/linux-samsung-soc/msg15485.html)
> Patches 3 and 4 are fixes for MAX77686 on Exynos5250 based Snow
> board (boot-up issues).
> Patch 5 implements a power-off call-back for Exynos5250 that can
> be re-used for Exynos5420.
> 
> The patches have been tested on an SMDK5250 based Chromebook.
> 
> Abhilash Kesavan (4):
>   clk: samsung: exynos5250: Add CLK_IGNORE_UNUSED flag for the sysreg
>     clock
>   ARM: EXYNOS5: Fix PMU register configuration for local power blocks
>   clk: max77686: Replace is_enabled() with is_prepared call-back
>   ARM: dts: Setup the interrupt parent for max77686
> 
> Olof Johansson (1):
>   ARM: EXYNOS5250: Implement pm_power_off
> 
>  arch/arm/boot/dts/cros5250-common.dtsi       |   11 ++++
>  arch/arm/mach-exynos/include/mach/regs-pmu.h |    3 +
>  arch/arm/mach-exynos/pmu.c                   |   86 ++++++++++++++++++++------
>  drivers/clk/clk-max77686.c                   |    4 +-
>  drivers/clk/samsung/clk-exynos5250.c         |    3 +-
>  5 files changed, 86 insertions(+), 21 deletions(-)

You used the old and now invalid address of DT mailing list.

Anyway, there is no need to send patches for .dts* files to DT mailing
list anymore. Just changes in drivers that affect how they handle data
from DT and binding documentation (Documentation/devicetree/.*). So
please drop the DT mailing list in next iteration of the series.

Best regards,
Tomasz

Re: [PATCH 0/5] Power Related Fixes for Exynos5250

[Abhilash Kesavan]

Hi Tomasz,

On Wed, Dec 11, 2013 at 6:11 PM, Tomasz Figa <t.figa@samsung.com> wrote:
> Hi Abhilash,
>
> On Wednesday 11 of December 2013 17:27:04 Abhilash Kesavan wrote:
>> Patch 1 prevents the gating of sysreg clock on Exynos5250.
>> Patch 2 is a re-send of an earlier patch.
>> (http://www.spinics.net/lists/linux-samsung-soc/msg15485.html)
>> Patches 3 and 4 are fixes for MAX77686 on Exynos5250 based Snow
>> board (boot-up issues).
>> Patch 5 implements a power-off call-back for Exynos5250 that can
>> be re-used for Exynos5420.
>>
>> The patches have been tested on an SMDK5250 based Chromebook.
>>
>> Abhilash Kesavan (4):
>>   clk: samsung: exynos5250: Add CLK_IGNORE_UNUSED flag for the sysreg
>>     clock
>>   ARM: EXYNOS5: Fix PMU register configuration for local power blocks
>>   clk: max77686: Replace is_enabled() with is_prepared call-back
>>   ARM: dts: Setup the interrupt parent for max77686
>>
>> Olof Johansson (1):
>>   ARM: EXYNOS5250: Implement pm_power_off
>>
>>  arch/arm/boot/dts/cros5250-common.dtsi       |   11 ++++
>>  arch/arm/mach-exynos/include/mach/regs-pmu.h |    3 +
>>  arch/arm/mach-exynos/pmu.c                   |   86 ++++++++++++++++++++------
>>  drivers/clk/clk-max77686.c                   |    4 +-
>>  drivers/clk/samsung/clk-exynos5250.c         |    3 +-
>>  5 files changed, 86 insertions(+), 21 deletions(-)
>
> You used the old and now invalid address of DT mailing list.
>
> Anyway, there is no need to send patches for .dts* files to DT mailing
> list anymore. Just changes in drivers that affect how they handle data
> from DT and binding documentation (Documentation/devicetree/.*). So
> please drop the DT mailing list in next iteration of the series.

Thanks for the pointer. I'll take care in the future.
>
> Best regards,
> Tomasz
>
>
> _______________________________________________
> linux-arm-kernel mailing list
> linux-arm-kernel@lists.infradead.org
> http://lists.infradead.org/mailman/listinfo/linux-arm-kernel

[PATCH 0/5] Power Related Fixes for Exynos5250

[Abhilash Kesavan]

Hi Tomasz,

On Wed, Dec 11, 2013 at 6:11 PM, Tomasz Figa <t.figa@samsung.com> wrote:
> Hi Abhilash,
>
> On Wednesday 11 of December 2013 17:27:04 Abhilash Kesavan wrote:
>> Patch 1 prevents the gating of sysreg clock on Exynos5250.
>> Patch 2 is a re-send of an earlier patch.
>> (http://www.spinics.net/lists/linux-samsung-soc/msg15485.html)
>> Patches 3 and 4 are fixes for MAX77686 on Exynos5250 based Snow
>> board (boot-up issues).
>> Patch 5 implements a power-off call-back for Exynos5250 that can
>> be re-used for Exynos5420.
>>
>> The patches have been tested on an SMDK5250 based Chromebook.
>>
>> Abhilash Kesavan (4):
>>   clk: samsung: exynos5250: Add CLK_IGNORE_UNUSED flag for the sysreg
>>     clock
>>   ARM: EXYNOS5: Fix PMU register configuration for local power blocks
>>   clk: max77686: Replace is_enabled() with is_prepared call-back
>>   ARM: dts: Setup the interrupt parent for max77686
>>
>> Olof Johansson (1):
>>   ARM: EXYNOS5250: Implement pm_power_off
>>
>>  arch/arm/boot/dts/cros5250-common.dtsi       |   11 ++++
>>  arch/arm/mach-exynos/include/mach/regs-pmu.h |    3 +
>>  arch/arm/mach-exynos/pmu.c                   |   86 ++++++++++++++++++++------
>>  drivers/clk/clk-max77686.c                   |    4 +-
>>  drivers/clk/samsung/clk-exynos5250.c         |    3 +-
>>  5 files changed, 86 insertions(+), 21 deletions(-)
>
> You used the old and now invalid address of DT mailing list.
>
> Anyway, there is no need to send patches for .dts* files to DT mailing
> list anymore. Just changes in drivers that affect how they handle data
> from DT and binding documentation (Documentation/devicetree/.*). So
> please drop the DT mailing list in next iteration of the series.

Thanks for the pointer. I'll take care in the future.
>
> Best regards,
> Tomasz
>
>
> _______________________________________________
> linux-arm-kernel mailing list
> linux-arm-kernel at lists.infradead.org
> http://lists.infradead.org/mailman/listinfo/linux-arm-kernel