* [PATCH v3 0/2] Improve CCS save restore series
@ 2025-08-06 8:29 Satyanarayana K V P
2025-08-06 8:19 ` ✓ CI.KUnit: success for Improve CCS save restore series (rev3) Patchwork
` (4 more replies)
0 siblings, 5 replies; 15+ messages in thread
From: Satyanarayana K V P @ 2025-08-06 8:29 UTC (permalink / raw)
To: intel-xe; +Cc: Satyanarayana K V P
Previously, CCS save/restore operations created separate migration
contexts with new VM memory allocations, resulting in significant
overhead.
This series eliminates redundant context creation reusing the default
migration context by registering new execution queues for CCS save and
restore on the existing migrate VM.
Also fixed corruption issue with save/restore followed by S3/S4 cycle.
V2 -> V3:
- Fixed review comments.
- Added new commit "Scale mmio send/recv timeout for CCS save/restore with
smem size"
- Squashed "Re-register CCS save/restore contexts post S3/S4 resume" into
"Refactor CCS save/restore to use default migration context" commit as per
review comments.
V1 -> V2:
- Fix kernel-doc issues reported by patchworks.
- Added new commit "Re-register CCS save/restore contexts post S3/S4
resume"
Satyanarayana K V P (2):
drm/xe/vf: Refactor CCS save/restore to use default migration context
drm/xe/guc: Scale mmio send/recv timeout for CCS save/restore with
smem size
drivers/gpu/drm/xe/xe_guc.c | 33 ++++++++++++++-
drivers/gpu/drm/xe/xe_migrate.c | 18 ++++----
drivers/gpu/drm/xe/xe_migrate.h | 2 +-
drivers/gpu/drm/xe/xe_pm.c | 3 ++
drivers/gpu/drm/xe/xe_sriov_vf_ccs.c | 49 ++++++++++++----------
drivers/gpu/drm/xe/xe_sriov_vf_ccs_types.h | 6 +--
6 files changed, 75 insertions(+), 36 deletions(-)
--
2.43.0
^ permalink raw reply [flat|nested] 15+ messages in thread* ✓ CI.KUnit: success for Improve CCS save restore series (rev3) 2025-08-06 8:29 [PATCH v3 0/2] Improve CCS save restore series Satyanarayana K V P @ 2025-08-06 8:19 ` Patchwork 2025-08-06 8:29 ` [PATCH v3 1/2] drm/xe/vf: Refactor CCS save/restore to use default migration context Satyanarayana K V P ` (3 subsequent siblings) 4 siblings, 0 replies; 15+ messages in thread From: Patchwork @ 2025-08-06 8:19 UTC (permalink / raw) To: Satyanarayana K V P; +Cc: intel-xe == Series Details == Series: Improve CCS save restore series (rev3) URL : https://patchwork.freedesktop.org/series/152316/ State : success == Summary == + trap cleanup EXIT + /kernel/tools/testing/kunit/kunit.py run --kunitconfig /kernel/drivers/gpu/drm/xe/.kunitconfig [08:18:01] Configuring KUnit Kernel ... Generating .config ... Populating config with: $ make ARCH=um O=.kunit olddefconfig [08:18:05] Building KUnit Kernel ... Populating config with: $ make ARCH=um O=.kunit olddefconfig Building with: $ make all compile_commands.json scripts_gdb ARCH=um O=.kunit --jobs=48 [08:18:32] Starting KUnit Kernel (1/1)... [08:18:32] ============================================================ Running tests with: $ .kunit/linux kunit.enable=1 mem=1G console=tty kunit_shutdown=halt [08:18:33] ================== guc_buf (11 subtests) =================== [08:18:33] [PASSED] test_smallest [08:18:33] [PASSED] test_largest [08:18:33] [PASSED] test_granular [08:18:33] [PASSED] test_unique [08:18:33] [PASSED] test_overlap [08:18:33] [PASSED] test_reusable [08:18:33] [PASSED] test_too_big [08:18:33] [PASSED] test_flush [08:18:33] [PASSED] test_lookup [08:18:33] [PASSED] test_data [08:18:33] [PASSED] test_class [08:18:33] ===================== [PASSED] guc_buf ===================== [08:18:33] =================== guc_dbm (7 subtests) =================== [08:18:33] [PASSED] test_empty [08:18:33] [PASSED] test_default [08:18:33] ======================== test_size ======================== [08:18:33] [PASSED] 4 [08:18:33] [PASSED] 8 [08:18:33] [PASSED] 32 [08:18:33] [PASSED] 256 [08:18:33] ==================== [PASSED] test_size ==================== [08:18:33] ======================= test_reuse ======================== [08:18:33] [PASSED] 4 [08:18:33] [PASSED] 8 [08:18:33] [PASSED] 32 [08:18:33] [PASSED] 256 [08:18:33] =================== [PASSED] test_reuse ==================== [08:18:33] =================== test_range_overlap ==================== [08:18:33] [PASSED] 4 [08:18:33] [PASSED] 8 [08:18:33] [PASSED] 32 [08:18:33] [PASSED] 256 [08:18:33] =============== [PASSED] test_range_overlap ================ [08:18:33] =================== test_range_compact ==================== [08:18:33] [PASSED] 4 [08:18:33] [PASSED] 8 [08:18:33] [PASSED] 32 [08:18:33] [PASSED] 256 [08:18:33] =============== [PASSED] test_range_compact ================ [08:18:33] ==================== test_range_spare ===================== [08:18:33] [PASSED] 4 [08:18:33] [PASSED] 8 [08:18:33] [PASSED] 32 [08:18:33] [PASSED] 256 [08:18:33] ================ [PASSED] test_range_spare ================= [08:18:33] ===================== [PASSED] guc_dbm ===================== [08:18:33] =================== guc_idm (6 subtests) =================== [08:18:33] [PASSED] bad_init [08:18:33] [PASSED] no_init [08:18:33] [PASSED] init_fini [08:18:33] [PASSED] check_used [08:18:33] [PASSED] check_quota [08:18:33] [PASSED] check_all [08:18:33] ===================== [PASSED] guc_idm ===================== [08:18:33] ================== no_relay (3 subtests) =================== [08:18:33] [PASSED] xe_drops_guc2pf_if_not_ready [08:18:33] [PASSED] xe_drops_guc2vf_if_not_ready [08:18:33] [PASSED] xe_rejects_send_if_not_ready [08:18:33] ==================== [PASSED] no_relay ===================== [08:18:33] ================== pf_relay (14 subtests) ================== [08:18:33] [PASSED] pf_rejects_guc2pf_too_short [08:18:33] [PASSED] pf_rejects_guc2pf_too_long [08:18:33] [PASSED] pf_rejects_guc2pf_no_payload [08:18:33] [PASSED] pf_fails_no_payload [08:18:33] [PASSED] pf_fails_bad_origin [08:18:33] [PASSED] pf_fails_bad_type [08:18:33] [PASSED] pf_txn_reports_error [08:18:33] [PASSED] pf_txn_sends_pf2guc [08:18:33] [PASSED] pf_sends_pf2guc [08:18:33] [SKIPPED] pf_loopback_nop [08:18:33] [SKIPPED] pf_loopback_echo [08:18:33] [SKIPPED] pf_loopback_fail [08:18:33] [SKIPPED] pf_loopback_busy [08:18:33] [SKIPPED] pf_loopback_retry [08:18:33] ==================== [PASSED] pf_relay ===================== [08:18:33] ================== vf_relay (3 subtests) =================== [08:18:33] [PASSED] vf_rejects_guc2vf_too_short [08:18:33] [PASSED] vf_rejects_guc2vf_too_long [08:18:33] [PASSED] vf_rejects_guc2vf_no_payload [08:18:33] ==================== [PASSED] vf_relay ===================== [08:18:33] ===================== lmtt (1 subtest) ===================== [08:18:33] ======================== test_ops ========================= [08:18:33] [PASSED] 2-level [08:18:33] [PASSED] multi-level [08:18:33] ==================== [PASSED] test_ops ===================== [08:18:33] ====================== [PASSED] lmtt ======================= [08:18:33] ================= pf_service (11 subtests) ================= [08:18:33] [PASSED] pf_negotiate_any [08:18:33] [PASSED] pf_negotiate_base_match [08:18:33] [PASSED] pf_negotiate_base_newer [08:18:33] [PASSED] pf_negotiate_base_next [08:18:33] [SKIPPED] pf_negotiate_base_older [08:18:33] [PASSED] pf_negotiate_base_prev [08:18:33] [PASSED] pf_negotiate_latest_match [08:18:33] [PASSED] pf_negotiate_latest_newer [08:18:33] [PASSED] pf_negotiate_latest_next [08:18:33] [SKIPPED] pf_negotiate_latest_older [08:18:33] [SKIPPED] pf_negotiate_latest_prev [08:18:33] =================== [PASSED] pf_service ==================== [08:18:33] =================== xe_mocs (2 subtests) =================== [08:18:33] ================ xe_live_mocs_kernel_kunit ================ [08:18:33] =========== [SKIPPED] xe_live_mocs_kernel_kunit ============ [08:18:33] ================ xe_live_mocs_reset_kunit ================= [08:18:33] ============ [SKIPPED] xe_live_mocs_reset_kunit ============ [08:18:33] ==================== [SKIPPED] xe_mocs ===================== [08:18:33] ================= xe_migrate (2 subtests) ================== [08:18:33] ================= xe_migrate_sanity_kunit ================= [08:18:33] ============ [SKIPPED] xe_migrate_sanity_kunit ============= [08:18:33] ================== xe_validate_ccs_kunit ================== [08:18:33] ============= [SKIPPED] xe_validate_ccs_kunit ============== [08:18:33] =================== [SKIPPED] xe_migrate =================== [08:18:33] ================== xe_dma_buf (1 subtest) ================== [08:18:33] ==================== xe_dma_buf_kunit ===================== [08:18:33] ================ [SKIPPED] xe_dma_buf_kunit ================ [08:18:33] =================== [SKIPPED] xe_dma_buf =================== [08:18:33] ================= xe_bo_shrink (1 subtest) ================= [08:18:33] =================== xe_bo_shrink_kunit ==================== [08:18:33] =============== [SKIPPED] xe_bo_shrink_kunit =============== [08:18:33] ================== [SKIPPED] xe_bo_shrink ================== [08:18:33] ==================== xe_bo (2 subtests) ==================== [08:18:33] ================== xe_ccs_migrate_kunit =================== [08:18:33] ============== [SKIPPED] xe_ccs_migrate_kunit ============== [08:18:33] ==================== xe_bo_evict_kunit ==================== [08:18:33] =============== [SKIPPED] xe_bo_evict_kunit ================ [08:18:33] ===================== [SKIPPED] xe_bo ====================== [08:18:33] ==================== args (11 subtests) ==================== [08:18:33] [PASSED] count_args_test [08:18:33] [PASSED] call_args_example [08:18:33] [PASSED] call_args_test [08:18:33] [PASSED] drop_first_arg_example [08:18:33] [PASSED] drop_first_arg_test [08:18:33] [PASSED] first_arg_example [08:18:33] [PASSED] first_arg_test [08:18:33] [PASSED] last_arg_example [08:18:33] [PASSED] last_arg_test [08:18:33] [PASSED] pick_arg_example [08:18:33] [PASSED] sep_comma_example [08:18:33] ====================== [PASSED] args ======================= [08:18:33] =================== xe_pci (3 subtests) ==================== [08:18:33] ==================== check_graphics_ip ==================== [08:18:33] [PASSED] 12.70 Xe_LPG [08:18:33] [PASSED] 12.71 Xe_LPG [08:18:33] [PASSED] 12.74 Xe_LPG+ [08:18:33] [PASSED] 20.01 Xe2_HPG [08:18:33] [PASSED] 20.02 Xe2_HPG [08:18:33] [PASSED] 20.04 Xe2_LPG [08:18:33] [PASSED] 30.00 Xe3_LPG [08:18:33] [PASSED] 30.01 Xe3_LPG [08:18:33] [PASSED] 30.03 Xe3_LPG [08:18:33] ================ [PASSED] check_graphics_ip ================ [08:18:33] ===================== check_media_ip ====================== [08:18:33] [PASSED] 13.00 Xe_LPM+ [08:18:33] [PASSED] 13.01 Xe2_HPM [08:18:33] [PASSED] 20.00 Xe2_LPM [08:18:33] [PASSED] 30.00 Xe3_LPM [08:18:33] [PASSED] 30.02 Xe3_LPM [08:18:33] ================= [PASSED] check_media_ip ================== [08:18:33] ================= check_platform_gt_count ================= [08:18:33] [PASSED] 0x9A60 (TIGERLAKE) [08:18:33] [PASSED] 0x9A68 (TIGERLAKE) [08:18:33] [PASSED] 0x9A70 (TIGERLAKE) [08:18:33] [PASSED] 0x9A40 (TIGERLAKE) [08:18:33] [PASSED] 0x9A49 (TIGERLAKE) [08:18:33] [PASSED] 0x9A59 (TIGERLAKE) [08:18:33] [PASSED] 0x9A78 (TIGERLAKE) [08:18:33] [PASSED] 0x9AC0 (TIGERLAKE) [08:18:33] [PASSED] 0x9AC9 (TIGERLAKE) [08:18:33] [PASSED] 0x9AD9 (TIGERLAKE) [08:18:33] [PASSED] 0x9AF8 (TIGERLAKE) [08:18:33] [PASSED] 0x4C80 (ROCKETLAKE) [08:18:33] [PASSED] 0x4C8A (ROCKETLAKE) [08:18:33] [PASSED] 0x4C8B (ROCKETLAKE) [08:18:33] [PASSED] 0x4C8C (ROCKETLAKE) [08:18:33] [PASSED] 0x4C90 (ROCKETLAKE) [08:18:33] [PASSED] 0x4C9A (ROCKETLAKE) [08:18:33] [PASSED] 0x4680 (ALDERLAKE_S) [08:18:33] [PASSED] 0x4682 (ALDERLAKE_S) [08:18:33] [PASSED] 0x4688 (ALDERLAKE_S) [08:18:33] [PASSED] 0x468A (ALDERLAKE_S) [08:18:33] [PASSED] 0x468B (ALDERLAKE_S) [08:18:33] [PASSED] 0x4690 (ALDERLAKE_S) [08:18:33] [PASSED] 0x4692 (ALDERLAKE_S) [08:18:33] [PASSED] 0x4693 (ALDERLAKE_S) [08:18:33] [PASSED] 0x46A0 (ALDERLAKE_P) [08:18:33] [PASSED] 0x46A1 (ALDERLAKE_P) [08:18:33] [PASSED] 0x46A2 (ALDERLAKE_P) [08:18:33] [PASSED] 0x46A3 (ALDERLAKE_P) [08:18:33] [PASSED] 0x46A6 (ALDERLAKE_P) [08:18:33] [PASSED] 0x46A8 (ALDERLAKE_P) [08:18:33] [PASSED] 0x46AA (ALDERLAKE_P) [08:18:33] [PASSED] 0x462A (ALDERLAKE_P) [08:18:33] [PASSED] 0x4626 (ALDERLAKE_P) [08:18:33] [PASSED] 0x4628 (ALDERLAKE_P) [08:18:33] [PASSED] 0x46B0 (ALDERLAKE_P) [08:18:33] [PASSED] 0x46B1 (ALDERLAKE_P) [08:18:33] [PASSED] 0x46B2 (ALDERLAKE_P) [08:18:33] [PASSED] 0x46B3 (ALDERLAKE_P) [08:18:33] [PASSED] 0x46C0 (ALDERLAKE_P) [08:18:33] [PASSED] 0x46C1 (ALDERLAKE_P) [08:18:33] [PASSED] 0x46C2 (ALDERLAKE_P) [08:18:33] [PASSED] 0x46C3 (ALDERLAKE_P) [08:18:33] [PASSED] 0x46D0 (ALDERLAKE_N) [08:18:33] [PASSED] 0x46D1 (ALDERLAKE_N) [08:18:33] [PASSED] 0x46D2 (ALDERLAKE_N) [08:18:33] [PASSED] 0x46D3 (ALDERLAKE_N) [08:18:33] [PASSED] 0x46D4 (ALDERLAKE_N) [08:18:33] [PASSED] 0xA721 (ALDERLAKE_P) [08:18:33] [PASSED] 0xA7A1 (ALDERLAKE_P) [08:18:33] [PASSED] 0xA7A9 (ALDERLAKE_P) [08:18:33] [PASSED] 0xA7AC (ALDERLAKE_P) [08:18:33] [PASSED] 0xA7AD (ALDERLAKE_P) [08:18:33] [PASSED] 0xA720 (ALDERLAKE_P) [08:18:33] [PASSED] 0xA7A0 (ALDERLAKE_P) [08:18:33] [PASSED] 0xA7A8 (ALDERLAKE_P) [08:18:33] [PASSED] 0xA7AA (ALDERLAKE_P) [08:18:33] [PASSED] 0xA7AB (ALDERLAKE_P) [08:18:33] [PASSED] 0xA780 (ALDERLAKE_S) [08:18:33] [PASSED] 0xA781 (ALDERLAKE_S) [08:18:33] [PASSED] 0xA782 (ALDERLAKE_S) [08:18:33] [PASSED] 0xA783 (ALDERLAKE_S) [08:18:33] [PASSED] 0xA788 (ALDERLAKE_S) [08:18:33] [PASSED] 0xA789 (ALDERLAKE_S) [08:18:33] [PASSED] 0xA78A (ALDERLAKE_S) [08:18:33] [PASSED] 0xA78B (ALDERLAKE_S) [08:18:33] [PASSED] 0x4905 (DG1) [08:18:33] [PASSED] 0x4906 (DG1) [08:18:33] [PASSED] 0x4907 (DG1) [08:18:33] [PASSED] 0x4908 (DG1) [08:18:33] [PASSED] 0x4909 (DG1) [08:18:33] [PASSED] 0x56C0 (DG2) [08:18:33] [PASSED] 0x56C2 (DG2) [08:18:33] [PASSED] 0x56C1 (DG2) [08:18:33] [PASSED] 0x7D51 (METEORLAKE) [08:18:33] [PASSED] 0x7DD1 (METEORLAKE) [08:18:33] [PASSED] 0x7D41 (METEORLAKE) [08:18:33] [PASSED] 0x7D67 (METEORLAKE) [08:18:33] [PASSED] 0xB640 (METEORLAKE) [08:18:33] [PASSED] 0x56A0 (DG2) [08:18:33] [PASSED] 0x56A1 (DG2) [08:18:33] [PASSED] 0x56A2 (DG2) [08:18:33] [PASSED] 0x56BE (DG2) [08:18:33] [PASSED] 0x56BF (DG2) [08:18:33] [PASSED] 0x5690 (DG2) [08:18:33] [PASSED] 0x5691 (DG2) [08:18:33] [PASSED] 0x5692 (DG2) [08:18:33] [PASSED] 0x56A5 (DG2) [08:18:33] [PASSED] 0x56A6 (DG2) [08:18:33] [PASSED] 0x56B0 (DG2) [08:18:33] [PASSED] 0x56B1 (DG2) [08:18:33] [PASSED] 0x56BA (DG2) [08:18:33] [PASSED] 0x56BB (DG2) [08:18:33] [PASSED] 0x56BC (DG2) [08:18:33] [PASSED] 0x56BD (DG2) [08:18:33] [PASSED] 0x5693 (DG2) [08:18:33] [PASSED] 0x5694 (DG2) [08:18:33] [PASSED] 0x5695 (DG2) [08:18:33] [PASSED] 0x56A3 (DG2) [08:18:33] [PASSED] 0x56A4 (DG2) [08:18:33] [PASSED] 0x56B2 (DG2) [08:18:33] [PASSED] 0x56B3 (DG2) [08:18:33] [PASSED] 0x5696 (DG2) [08:18:33] [PASSED] 0x5697 (DG2) [08:18:33] [PASSED] 0xB69 (PVC) [08:18:33] [PASSED] 0xB6E (PVC) [08:18:33] [PASSED] 0xBD4 (PVC) [08:18:33] [PASSED] 0xBD5 (PVC) [08:18:33] [PASSED] 0xBD6 (PVC) [08:18:33] [PASSED] 0xBD7 (PVC) [08:18:33] [PASSED] 0xBD8 (PVC) [08:18:33] [PASSED] 0xBD9 (PVC) [08:18:33] [PASSED] 0xBDA (PVC) [08:18:33] [PASSED] 0xBDB (PVC) [08:18:33] [PASSED] 0xBE0 (PVC) [08:18:33] [PASSED] 0xBE1 (PVC) [08:18:33] [PASSED] 0xBE5 (PVC) [08:18:33] [PASSED] 0x7D40 (METEORLAKE) [08:18:33] [PASSED] 0x7D45 (METEORLAKE) [08:18:33] [PASSED] 0x7D55 (METEORLAKE) [08:18:33] [PASSED] 0x7D60 (METEORLAKE) [08:18:33] [PASSED] 0x7DD5 (METEORLAKE) [08:18:33] [PASSED] 0x6420 (LUNARLAKE) [08:18:33] [PASSED] 0x64A0 (LUNARLAKE) [08:18:33] [PASSED] 0x64B0 (LUNARLAKE) [08:18:33] [PASSED] 0xE202 (BATTLEMAGE) [08:18:33] [PASSED] 0xE209 (BATTLEMAGE) [08:18:33] [PASSED] 0xE20B (BATTLEMAGE) [08:18:33] [PASSED] 0xE20C (BATTLEMAGE) [08:18:33] [PASSED] 0xE20D (BATTLEMAGE) [08:18:33] [PASSED] 0xE210 (BATTLEMAGE) [08:18:33] [PASSED] 0xE211 (BATTLEMAGE) [08:18:33] [PASSED] 0xE212 (BATTLEMAGE) [08:18:33] [PASSED] 0xE216 (BATTLEMAGE) [08:18:33] [PASSED] 0xE220 (BATTLEMAGE) [08:18:33] [PASSED] 0xE221 (BATTLEMAGE) [08:18:33] [PASSED] 0xE222 (BATTLEMAGE) [08:18:33] [PASSED] 0xE223 (BATTLEMAGE) [08:18:33] [PASSED] 0xB080 (PANTHERLAKE) [08:18:33] [PASSED] 0xB081 (PANTHERLAKE) [08:18:33] [PASSED] 0xB082 (PANTHERLAKE) [08:18:33] [PASSED] 0xB083 (PANTHERLAKE) [08:18:33] [PASSED] 0xB084 (PANTHERLAKE) [08:18:33] [PASSED] 0xB085 (PANTHERLAKE) [08:18:33] [PASSED] 0xB086 (PANTHERLAKE) [08:18:33] [PASSED] 0xB087 (PANTHERLAKE) [08:18:33] [PASSED] 0xB08F (PANTHERLAKE) [08:18:33] [PASSED] 0xB090 (PANTHERLAKE) [08:18:33] [PASSED] 0xB0A0 (PANTHERLAKE) [08:18:33] [PASSED] 0xB0B0 (PANTHERLAKE) [08:18:33] [PASSED] 0xFD80 (PANTHERLAKE) [08:18:33] [PASSED] 0xFD81 (PANTHERLAKE) [08:18:33] ============= [PASSED] check_platform_gt_count ============= [08:18:33] ===================== [PASSED] xe_pci ====================== [08:18:33] =================== xe_rtp (2 subtests) ==================== [08:18:33] =============== xe_rtp_process_to_sr_tests ================ [08:18:33] [PASSED] coalesce-same-reg [08:18:33] [PASSED] no-match-no-add [08:18:33] [PASSED] match-or [08:18:33] [PASSED] match-or-xfail [08:18:33] [PASSED] no-match-no-add-multiple-rules [08:18:33] [PASSED] two-regs-two-entries [08:18:33] [PASSED] clr-one-set-other [08:18:33] [PASSED] set-field [08:18:33] [PASSED] conflict-duplicate [08:18:33] [PASSED] conflict-not-disjoint [08:18:33] [PASSED] conflict-reg-type [08:18:33] =========== [PASSED] xe_rtp_process_to_sr_tests ============ [08:18:33] ================== xe_rtp_process_tests =================== [08:18:33] [PASSED] active1 [08:18:33] [PASSED] active2 [08:18:33] [PASSED] active-inactive [08:18:33] [PASSED] inactive-active [08:18:33] [PASSED] inactive-1st_or_active-inactive [08:18:33] [PASSED] inactive-2nd_or_active-inactive [08:18:33] [PASSED] inactive-last_or_active-inactive [08:18:33] [PASSED] inactive-no_or_active-inactive [08:18:33] ============== [PASSED] xe_rtp_process_tests =============== [08:18:33] ===================== [PASSED] xe_rtp ====================== [08:18:33] ==================== xe_wa (1 subtest) ===================== [08:18:33] ======================== xe_wa_gt ========================= [08:18:33] [PASSED] TIGERLAKE (B0) [08:18:33] [PASSED] DG1 (A0) [08:18:33] [PASSED] DG1 (B0) [08:18:33] [PASSED] ALDERLAKE_S (A0) [08:18:33] [PASSED] ALDERLAKE_S (B0) [08:18:33] [PASSED] ALDERLAKE_S (C0) [08:18:33] [PASSED] ALDERLAKE_S (D0) [08:18:33] [PASSED] ALDERLAKE_P (A0) [08:18:33] [PASSED] ALDERLAKE_P (B0) [08:18:33] [PASSED] ALDERLAKE_P (C0) [08:18:33] [PASSED] ALDERLAKE_S_RPLS (D0) [08:18:33] [PASSED] ALDERLAKE_P_RPLU (E0) [08:18:33] [PASSED] DG2_G10 (C0) [08:18:33] [PASSED] DG2_G11 (B1) [08:18:33] [PASSED] DG2_G12 (A1) [08:18:33] [PASSED] METEORLAKE (g:A0, m:A0) [08:18:33] [PASSED] METEORLAKE (g:A0, m:A0) [08:18:33] [PASSED] METEORLAKE (g:A0, m:A0) [08:18:33] [PASSED] LUNARLAKE (g:A0, m:A0) [08:18:33] [PASSED] LUNARLAKE (g:B0, m:A0) stty: 'standard input': Inappropriate ioctl for device [08:18:33] [PASSED] BATTLEMAGE (g:A0, m:A1) [08:18:33] ==================== [PASSED] xe_wa_gt ===================== [08:18:33] ====================== [PASSED] xe_wa ====================== [08:18:33] ============================================================ [08:18:33] Testing complete. Ran 297 tests: passed: 281, skipped: 16 [08:18:33] Elapsed time: 31.770s total, 4.141s configuring, 27.262s building, 0.324s running + /kernel/tools/testing/kunit/kunit.py run --kunitconfig /kernel/drivers/gpu/drm/tests/.kunitconfig [08:18:33] Configuring KUnit Kernel ... Regenerating .config ... Populating config with: $ make ARCH=um O=.kunit olddefconfig [08:18:34] Building KUnit Kernel ... Populating config with: $ make ARCH=um O=.kunit olddefconfig Building with: $ make all compile_commands.json scripts_gdb ARCH=um O=.kunit --jobs=48 [08:18:56] Starting KUnit Kernel (1/1)... [08:18:56] ============================================================ Running tests with: $ .kunit/linux kunit.enable=1 mem=1G console=tty kunit_shutdown=halt [08:18:56] == drm_test_atomic_get_connector_for_encoder (1 subtest) === [08:18:56] [PASSED] drm_test_drm_atomic_get_connector_for_encoder [08:18:56] ==== [PASSED] drm_test_atomic_get_connector_for_encoder ==== [08:18:56] =========== drm_validate_clone_mode (2 subtests) =========== [08:18:56] ============== drm_test_check_in_clone_mode =============== [08:18:56] [PASSED] in_clone_mode [08:18:56] [PASSED] not_in_clone_mode [08:18:56] ========== [PASSED] drm_test_check_in_clone_mode =========== [08:18:56] =============== drm_test_check_valid_clones =============== [08:18:56] [PASSED] not_in_clone_mode [08:18:56] [PASSED] valid_clone [08:18:56] [PASSED] invalid_clone [08:18:56] =========== [PASSED] drm_test_check_valid_clones =========== [08:18:56] ============= [PASSED] drm_validate_clone_mode ============= [08:18:56] ============= drm_validate_modeset (1 subtest) ============= [08:18:56] [PASSED] drm_test_check_connector_changed_modeset [08:18:56] ============== [PASSED] drm_validate_modeset =============== [08:18:56] ====== drm_test_bridge_get_current_state (2 subtests) ====== [08:18:56] [PASSED] drm_test_drm_bridge_get_current_state_atomic [08:18:56] [PASSED] drm_test_drm_bridge_get_current_state_legacy [08:18:56] ======== [PASSED] drm_test_bridge_get_current_state ======== [08:18:56] ====== drm_test_bridge_helper_reset_crtc (3 subtests) ====== [08:18:56] [PASSED] drm_test_drm_bridge_helper_reset_crtc_atomic [08:18:56] [PASSED] drm_test_drm_bridge_helper_reset_crtc_atomic_disabled [08:18:56] [PASSED] drm_test_drm_bridge_helper_reset_crtc_legacy [08:18:56] ======== [PASSED] drm_test_bridge_helper_reset_crtc ======== [08:18:56] ============== drm_bridge_alloc (2 subtests) =============== [08:18:56] [PASSED] drm_test_drm_bridge_alloc_basic [08:18:56] [PASSED] drm_test_drm_bridge_alloc_get_put [08:18:56] ================ [PASSED] drm_bridge_alloc ================= [08:18:56] ================== drm_buddy (7 subtests) ================== [08:18:56] [PASSED] drm_test_buddy_alloc_limit [08:18:56] [PASSED] drm_test_buddy_alloc_optimistic [08:18:56] [PASSED] drm_test_buddy_alloc_pessimistic [08:18:56] [PASSED] drm_test_buddy_alloc_pathological [08:18:56] [PASSED] drm_test_buddy_alloc_contiguous [08:18:56] [PASSED] drm_test_buddy_alloc_clear [08:18:56] [PASSED] drm_test_buddy_alloc_range_bias [08:18:56] ==================== [PASSED] drm_buddy ==================== [08:18:56] ============= drm_cmdline_parser (40 subtests) ============= [08:18:56] [PASSED] drm_test_cmdline_force_d_only [08:18:56] [PASSED] drm_test_cmdline_force_D_only_dvi [08:18:56] [PASSED] drm_test_cmdline_force_D_only_hdmi [08:18:56] [PASSED] drm_test_cmdline_force_D_only_not_digital [08:18:56] [PASSED] drm_test_cmdline_force_e_only [08:18:56] [PASSED] drm_test_cmdline_res [08:18:56] [PASSED] drm_test_cmdline_res_vesa [08:18:56] [PASSED] drm_test_cmdline_res_vesa_rblank [08:18:56] [PASSED] drm_test_cmdline_res_rblank [08:18:56] [PASSED] drm_test_cmdline_res_bpp [08:18:56] [PASSED] drm_test_cmdline_res_refresh [08:18:56] [PASSED] drm_test_cmdline_res_bpp_refresh [08:18:56] [PASSED] drm_test_cmdline_res_bpp_refresh_interlaced [08:18:56] [PASSED] drm_test_cmdline_res_bpp_refresh_margins [08:18:56] [PASSED] drm_test_cmdline_res_bpp_refresh_force_off [08:18:56] [PASSED] drm_test_cmdline_res_bpp_refresh_force_on [08:18:56] [PASSED] drm_test_cmdline_res_bpp_refresh_force_on_analog [08:18:56] [PASSED] drm_test_cmdline_res_bpp_refresh_force_on_digital [08:18:56] [PASSED] drm_test_cmdline_res_bpp_refresh_interlaced_margins_force_on [08:18:56] [PASSED] drm_test_cmdline_res_margins_force_on [08:18:56] [PASSED] drm_test_cmdline_res_vesa_margins [08:18:56] [PASSED] drm_test_cmdline_name [08:18:56] [PASSED] drm_test_cmdline_name_bpp [08:18:56] [PASSED] drm_test_cmdline_name_option [08:18:56] [PASSED] drm_test_cmdline_name_bpp_option [08:18:56] [PASSED] drm_test_cmdline_rotate_0 [08:18:56] [PASSED] drm_test_cmdline_rotate_90 [08:18:56] [PASSED] drm_test_cmdline_rotate_180 [08:18:56] [PASSED] drm_test_cmdline_rotate_270 [08:18:56] [PASSED] drm_test_cmdline_hmirror [08:18:56] [PASSED] drm_test_cmdline_vmirror [08:18:56] [PASSED] drm_test_cmdline_margin_options [08:18:56] [PASSED] drm_test_cmdline_multiple_options [08:18:56] [PASSED] drm_test_cmdline_bpp_extra_and_option [08:18:56] [PASSED] drm_test_cmdline_extra_and_option [08:18:56] [PASSED] drm_test_cmdline_freestanding_options [08:18:56] [PASSED] drm_test_cmdline_freestanding_force_e_and_options [08:18:56] [PASSED] drm_test_cmdline_panel_orientation [08:18:56] ================ drm_test_cmdline_invalid ================= [08:18:56] [PASSED] margin_only [08:18:56] [PASSED] interlace_only [08:18:56] [PASSED] res_missing_x [08:18:56] [PASSED] res_missing_y [08:18:56] [PASSED] res_bad_y [08:18:56] [PASSED] res_missing_y_bpp [08:18:56] [PASSED] res_bad_bpp [08:18:56] [PASSED] res_bad_refresh [08:18:56] [PASSED] res_bpp_refresh_force_on_off [08:18:56] [PASSED] res_invalid_mode [08:18:56] [PASSED] res_bpp_wrong_place_mode [08:18:56] [PASSED] name_bpp_refresh [08:18:56] [PASSED] name_refresh [08:18:56] [PASSED] name_refresh_wrong_mode [08:18:56] [PASSED] name_refresh_invalid_mode [08:18:56] [PASSED] rotate_multiple [08:18:56] [PASSED] rotate_invalid_val [08:18:56] [PASSED] rotate_truncated [08:18:56] [PASSED] invalid_option [08:18:56] [PASSED] invalid_tv_option [08:18:56] [PASSED] truncated_tv_option [08:18:56] ============ [PASSED] drm_test_cmdline_invalid ============= [08:18:56] =============== drm_test_cmdline_tv_options =============== [08:18:56] [PASSED] NTSC [08:18:56] [PASSED] NTSC_443 [08:18:56] [PASSED] NTSC_J [08:18:56] [PASSED] PAL [08:18:56] [PASSED] PAL_M [08:18:56] [PASSED] PAL_N [08:18:56] [PASSED] SECAM [08:18:56] [PASSED] MONO_525 [08:18:56] [PASSED] MONO_625 [08:18:56] =========== [PASSED] drm_test_cmdline_tv_options =========== [08:18:56] =============== [PASSED] drm_cmdline_parser ================ [08:18:56] ========== drmm_connector_hdmi_init (20 subtests) ========== [08:18:56] [PASSED] drm_test_connector_hdmi_init_valid [08:18:56] [PASSED] drm_test_connector_hdmi_init_bpc_8 [08:18:56] [PASSED] drm_test_connector_hdmi_init_bpc_10 [08:18:56] [PASSED] drm_test_connector_hdmi_init_bpc_12 [08:18:56] [PASSED] drm_test_connector_hdmi_init_bpc_invalid [08:18:56] [PASSED] drm_test_connector_hdmi_init_bpc_null [08:18:56] [PASSED] drm_test_connector_hdmi_init_formats_empty [08:18:56] [PASSED] drm_test_connector_hdmi_init_formats_no_rgb [08:18:56] === drm_test_connector_hdmi_init_formats_yuv420_allowed === [08:18:56] [PASSED] supported_formats=0x9 yuv420_allowed=1 [08:18:56] [PASSED] supported_formats=0x9 yuv420_allowed=0 [08:18:56] [PASSED] supported_formats=0x3 yuv420_allowed=1 [08:18:56] [PASSED] supported_formats=0x3 yuv420_allowed=0 [08:18:56] === [PASSED] drm_test_connector_hdmi_init_formats_yuv420_allowed === [08:18:56] [PASSED] drm_test_connector_hdmi_init_null_ddc [08:18:56] [PASSED] drm_test_connector_hdmi_init_null_product [08:18:56] [PASSED] drm_test_connector_hdmi_init_null_vendor [08:18:56] [PASSED] drm_test_connector_hdmi_init_product_length_exact [08:18:56] [PASSED] drm_test_connector_hdmi_init_product_length_too_long [08:18:56] [PASSED] drm_test_connector_hdmi_init_product_valid [08:18:56] [PASSED] drm_test_connector_hdmi_init_vendor_length_exact [08:18:56] [PASSED] drm_test_connector_hdmi_init_vendor_length_too_long [08:18:56] [PASSED] drm_test_connector_hdmi_init_vendor_valid [08:18:56] ========= drm_test_connector_hdmi_init_type_valid ========= [08:18:56] [PASSED] HDMI-A [08:18:56] [PASSED] HDMI-B [08:18:56] ===== [PASSED] drm_test_connector_hdmi_init_type_valid ===== [08:18:56] ======== drm_test_connector_hdmi_init_type_invalid ======== [08:18:56] [PASSED] Unknown [08:18:56] [PASSED] VGA [08:18:56] [PASSED] DVI-I [08:18:56] [PASSED] DVI-D [08:18:56] [PASSED] DVI-A [08:18:56] [PASSED] Composite [08:18:56] [PASSED] SVIDEO [08:18:56] [PASSED] LVDS [08:18:56] [PASSED] Component [08:18:56] [PASSED] DIN [08:18:56] [PASSED] DP [08:18:56] [PASSED] TV [08:18:56] [PASSED] eDP [08:18:56] [PASSED] Virtual [08:18:56] [PASSED] DSI [08:18:56] [PASSED] DPI [08:18:56] [PASSED] Writeback [08:18:56] [PASSED] SPI [08:18:56] [PASSED] USB [08:18:56] ==== [PASSED] drm_test_connector_hdmi_init_type_invalid ==== [08:18:56] ============ [PASSED] drmm_connector_hdmi_init ============= [08:18:56] ============= drmm_connector_init (3 subtests) ============= [08:18:56] [PASSED] drm_test_drmm_connector_init [08:18:56] [PASSED] drm_test_drmm_connector_init_null_ddc [08:18:56] ========= drm_test_drmm_connector_init_type_valid ========= [08:18:56] [PASSED] Unknown [08:18:56] [PASSED] VGA [08:18:56] [PASSED] DVI-I [08:18:56] [PASSED] DVI-D [08:18:56] [PASSED] DVI-A [08:18:56] [PASSED] Composite [08:18:56] [PASSED] SVIDEO [08:18:56] [PASSED] LVDS [08:18:56] [PASSED] Component [08:18:56] [PASSED] DIN [08:18:56] [PASSED] DP [08:18:56] [PASSED] HDMI-A [08:18:56] [PASSED] HDMI-B [08:18:56] [PASSED] TV [08:18:56] [PASSED] eDP [08:18:56] [PASSED] Virtual [08:18:56] [PASSED] DSI [08:18:56] [PASSED] DPI [08:18:56] [PASSED] Writeback [08:18:56] [PASSED] SPI [08:18:56] [PASSED] USB [08:18:56] ===== [PASSED] drm_test_drmm_connector_init_type_valid ===== [08:18:56] =============== [PASSED] drmm_connector_init =============== [08:18:56] ========= drm_connector_dynamic_init (6 subtests) ========== [08:18:56] [PASSED] drm_test_drm_connector_dynamic_init [08:18:56] [PASSED] drm_test_drm_connector_dynamic_init_null_ddc [08:18:56] [PASSED] drm_test_drm_connector_dynamic_init_not_added [08:18:56] [PASSED] drm_test_drm_connector_dynamic_init_properties [08:18:56] ===== drm_test_drm_connector_dynamic_init_type_valid ====== [08:18:56] [PASSED] Unknown [08:18:56] [PASSED] VGA [08:18:56] [PASSED] DVI-I [08:18:56] [PASSED] DVI-D [08:18:56] [PASSED] DVI-A [08:18:56] [PASSED] Composite [08:18:56] [PASSED] SVIDEO [08:18:56] [PASSED] LVDS [08:18:56] [PASSED] Component [08:18:56] [PASSED] DIN [08:18:56] [PASSED] DP [08:18:56] [PASSED] HDMI-A [08:18:56] [PASSED] HDMI-B [08:18:56] [PASSED] TV [08:18:56] [PASSED] eDP [08:18:56] [PASSED] Virtual [08:18:56] [PASSED] DSI [08:18:56] [PASSED] DPI [08:18:56] [PASSED] Writeback [08:18:56] [PASSED] SPI [08:18:56] [PASSED] USB [08:18:56] = [PASSED] drm_test_drm_connector_dynamic_init_type_valid == [08:18:56] ======== drm_test_drm_connector_dynamic_init_name ========= [08:18:56] [PASSED] Unknown [08:18:56] [PASSED] VGA [08:18:56] [PASSED] DVI-I [08:18:56] [PASSED] DVI-D [08:18:56] [PASSED] DVI-A [08:18:56] [PASSED] Composite [08:18:56] [PASSED] SVIDEO [08:18:56] [PASSED] LVDS [08:18:56] [PASSED] Component [08:18:56] [PASSED] DIN [08:18:56] [PASSED] DP [08:18:56] [PASSED] HDMI-A [08:18:56] [PASSED] HDMI-B [08:18:56] [PASSED] TV [08:18:56] [PASSED] eDP [08:18:56] [PASSED] Virtual [08:18:56] [PASSED] DSI [08:18:56] [PASSED] DPI [08:18:56] [PASSED] Writeback [08:18:56] [PASSED] SPI [08:18:56] [PASSED] USB [08:18:56] ==== [PASSED] drm_test_drm_connector_dynamic_init_name ===== [08:18:56] =========== [PASSED] drm_connector_dynamic_init ============ [08:18:56] ==== drm_connector_dynamic_register_early (4 subtests) ===== [08:18:56] [PASSED] drm_test_drm_connector_dynamic_register_early_on_list [08:18:56] [PASSED] drm_test_drm_connector_dynamic_register_early_defer [08:18:56] [PASSED] drm_test_drm_connector_dynamic_register_early_no_init [08:18:56] [PASSED] drm_test_drm_connector_dynamic_register_early_no_mode_object [08:18:56] ====== [PASSED] drm_connector_dynamic_register_early ======= [08:18:56] ======= drm_connector_dynamic_register (7 subtests) ======== [08:18:56] [PASSED] drm_test_drm_connector_dynamic_register_on_list [08:18:56] [PASSED] drm_test_drm_connector_dynamic_register_no_defer [08:18:56] [PASSED] drm_test_drm_connector_dynamic_register_no_init [08:18:56] [PASSED] drm_test_drm_connector_dynamic_register_mode_object [08:18:56] [PASSED] drm_test_drm_connector_dynamic_register_sysfs [08:18:56] [PASSED] drm_test_drm_connector_dynamic_register_sysfs_name [08:18:56] [PASSED] drm_test_drm_connector_dynamic_register_debugfs [08:18:56] ========= [PASSED] drm_connector_dynamic_register ========== [08:18:56] = drm_connector_attach_broadcast_rgb_property (2 subtests) = [08:18:56] [PASSED] drm_test_drm_connector_attach_broadcast_rgb_property [08:18:56] [PASSED] drm_test_drm_connector_attach_broadcast_rgb_property_hdmi_connector [08:18:56] === [PASSED] drm_connector_attach_broadcast_rgb_property === [08:18:56] ========== drm_get_tv_mode_from_name (2 subtests) ========== [08:18:56] ========== drm_test_get_tv_mode_from_name_valid =========== [08:18:56] [PASSED] NTSC [08:18:56] [PASSED] NTSC-443 [08:18:56] [PASSED] NTSC-J [08:18:56] [PASSED] PAL [08:18:56] [PASSED] PAL-M [08:18:56] [PASSED] PAL-N [08:18:56] [PASSED] SECAM [08:18:56] [PASSED] Mono [08:18:56] ====== [PASSED] drm_test_get_tv_mode_from_name_valid ======= [08:18:56] [PASSED] drm_test_get_tv_mode_from_name_truncated [08:18:56] ============ [PASSED] drm_get_tv_mode_from_name ============ [08:18:56] = drm_test_connector_hdmi_compute_mode_clock (12 subtests) = [08:18:56] [PASSED] drm_test_drm_hdmi_compute_mode_clock_rgb [08:18:56] [PASSED] drm_test_drm_hdmi_compute_mode_clock_rgb_10bpc [08:18:56] [PASSED] drm_test_drm_hdmi_compute_mode_clock_rgb_10bpc_vic_1 [08:18:56] [PASSED] drm_test_drm_hdmi_compute_mode_clock_rgb_12bpc [08:18:56] [PASSED] drm_test_drm_hdmi_compute_mode_clock_rgb_12bpc_vic_1 [08:18:56] [PASSED] drm_test_drm_hdmi_compute_mode_clock_rgb_double [08:18:56] = drm_test_connector_hdmi_compute_mode_clock_yuv420_valid = [08:18:56] [PASSED] VIC 96 [08:18:56] [PASSED] VIC 97 [08:18:56] [PASSED] VIC 101 [08:18:56] [PASSED] VIC 102 [08:18:56] [PASSED] VIC 106 [08:18:56] [PASSED] VIC 107 [08:18:56] === [PASSED] drm_test_connector_hdmi_compute_mode_clock_yuv420_valid === [08:18:56] [PASSED] drm_test_connector_hdmi_compute_mode_clock_yuv420_10_bpc [08:18:56] [PASSED] drm_test_connector_hdmi_compute_mode_clock_yuv420_12_bpc [08:18:56] [PASSED] drm_test_connector_hdmi_compute_mode_clock_yuv422_8_bpc [08:18:56] [PASSED] drm_test_connector_hdmi_compute_mode_clock_yuv422_10_bpc [08:18:56] [PASSED] drm_test_connector_hdmi_compute_mode_clock_yuv422_12_bpc [08:18:56] === [PASSED] drm_test_connector_hdmi_compute_mode_clock ==== [08:18:56] == drm_hdmi_connector_get_broadcast_rgb_name (2 subtests) == [08:18:56] === drm_test_drm_hdmi_connector_get_broadcast_rgb_name ==== [08:18:56] [PASSED] Automatic [08:18:56] [PASSED] Full [08:18:56] [PASSED] Limited 16:235 [08:18:56] === [PASSED] drm_test_drm_hdmi_connector_get_broadcast_rgb_name === [08:18:56] [PASSED] drm_test_drm_hdmi_connector_get_broadcast_rgb_name_invalid [08:18:56] ==== [PASSED] drm_hdmi_connector_get_broadcast_rgb_name ==== [08:18:56] == drm_hdmi_connector_get_output_format_name (2 subtests) == [08:18:56] === drm_test_drm_hdmi_connector_get_output_format_name ==== [08:18:56] [PASSED] RGB [08:18:56] [PASSED] YUV 4:2:0 [08:18:56] [PASSED] YUV 4:2:2 [08:18:56] [PASSED] YUV 4:4:4 [08:18:56] === [PASSED] drm_test_drm_hdmi_connector_get_output_format_name === [08:18:56] [PASSED] drm_test_drm_hdmi_connector_get_output_format_name_invalid [08:18:56] ==== [PASSED] drm_hdmi_connector_get_output_format_name ==== [08:18:56] ============= drm_damage_helper (21 subtests) ============== [08:18:56] [PASSED] drm_test_damage_iter_no_damage [08:18:56] [PASSED] drm_test_damage_iter_no_damage_fractional_src [08:18:56] [PASSED] drm_test_damage_iter_no_damage_src_moved [08:18:56] [PASSED] drm_test_damage_iter_no_damage_fractional_src_moved [08:18:56] [PASSED] drm_test_damage_iter_no_damage_not_visible [08:18:56] [PASSED] drm_test_damage_iter_no_damage_no_crtc [08:18:56] [PASSED] drm_test_damage_iter_no_damage_no_fb [08:18:56] [PASSED] drm_test_damage_iter_simple_damage [08:18:56] [PASSED] drm_test_damage_iter_single_damage [08:18:56] [PASSED] drm_test_damage_iter_single_damage_intersect_src [08:18:56] [PASSED] drm_test_damage_iter_single_damage_outside_src [08:18:56] [PASSED] drm_test_damage_iter_single_damage_fractional_src [08:18:56] [PASSED] drm_test_damage_iter_single_damage_intersect_fractional_src [08:18:56] [PASSED] drm_test_damage_iter_single_damage_outside_fractional_src [08:18:56] [PASSED] drm_test_damage_iter_single_damage_src_moved [08:18:56] [PASSED] drm_test_damage_iter_single_damage_fractional_src_moved [08:18:56] [PASSED] drm_test_damage_iter_damage [08:18:56] [PASSED] drm_test_damage_iter_damage_one_intersect [08:18:56] [PASSED] drm_test_damage_iter_damage_one_outside [08:18:56] [PASSED] drm_test_damage_iter_damage_src_moved [08:18:56] [PASSED] drm_test_damage_iter_damage_not_visible [08:18:56] ================ [PASSED] drm_damage_helper ================ [08:18:56] ============== drm_dp_mst_helper (3 subtests) ============== [08:18:56] ============== drm_test_dp_mst_calc_pbn_mode ============== [08:18:56] [PASSED] Clock 154000 BPP 30 DSC disabled [08:18:56] [PASSED] Clock 234000 BPP 30 DSC disabled [08:18:56] [PASSED] Clock 297000 BPP 24 DSC disabled [08:18:56] [PASSED] Clock 332880 BPP 24 DSC enabled [08:18:56] [PASSED] Clock 324540 BPP 24 DSC enabled [08:18:56] ========== [PASSED] drm_test_dp_mst_calc_pbn_mode ========== [08:18:56] ============== drm_test_dp_mst_calc_pbn_div =============== [08:18:56] [PASSED] Link rate 2000000 lane count 4 [08:18:56] [PASSED] Link rate 2000000 lane count 2 [08:18:56] [PASSED] Link rate 2000000 lane count 1 [08:18:56] [PASSED] Link rate 1350000 lane count 4 [08:18:56] [PASSED] Link rate 1350000 lane count 2 [08:18:56] [PASSED] Link rate 1350000 lane count 1 [08:18:56] [PASSED] Link rate 1000000 lane count 4 [08:18:56] [PASSED] Link rate 1000000 lane count 2 [08:18:56] [PASSED] Link rate 1000000 lane count 1 [08:18:56] [PASSED] Link rate 810000 lane count 4 [08:18:56] [PASSED] Link rate 810000 lane count 2 [08:18:56] [PASSED] Link rate 810000 lane count 1 [08:18:56] [PASSED] Link rate 540000 lane count 4 [08:18:56] [PASSED] Link rate 540000 lane count 2 [08:18:56] [PASSED] Link rate 540000 lane count 1 [08:18:56] [PASSED] Link rate 270000 lane count 4 [08:18:56] [PASSED] Link rate 270000 lane count 2 [08:18:56] [PASSED] Link rate 270000 lane count 1 [08:18:56] [PASSED] Link rate 162000 lane count 4 [08:18:56] [PASSED] Link rate 162000 lane count 2 [08:18:56] [PASSED] Link rate 162000 lane count 1 [08:18:56] ========== [PASSED] drm_test_dp_mst_calc_pbn_div =========== [08:18:56] ========= drm_test_dp_mst_sideband_msg_req_decode ========= [08:18:56] [PASSED] DP_ENUM_PATH_RESOURCES with port number [08:18:56] [PASSED] DP_POWER_UP_PHY with port number [08:18:56] [PASSED] DP_POWER_DOWN_PHY with port number [08:18:56] [PASSED] DP_ALLOCATE_PAYLOAD with SDP stream sinks [08:18:56] [PASSED] DP_ALLOCATE_PAYLOAD with port number [08:18:56] [PASSED] DP_ALLOCATE_PAYLOAD with VCPI [08:18:56] [PASSED] DP_ALLOCATE_PAYLOAD with PBN [08:18:56] [PASSED] DP_QUERY_PAYLOAD with port number [08:18:56] [PASSED] DP_QUERY_PAYLOAD with VCPI [08:18:56] [PASSED] DP_REMOTE_DPCD_READ with port number [08:18:56] [PASSED] DP_REMOTE_DPCD_READ with DPCD address [08:18:56] [PASSED] DP_REMOTE_DPCD_READ with max number of bytes [08:18:56] [PASSED] DP_REMOTE_DPCD_WRITE with port number [08:18:56] [PASSED] DP_REMOTE_DPCD_WRITE with DPCD address [08:18:56] [PASSED] DP_REMOTE_DPCD_WRITE with data array [08:18:56] [PASSED] DP_REMOTE_I2C_READ with port number [08:18:56] [PASSED] DP_REMOTE_I2C_READ with I2C device ID [08:18:56] [PASSED] DP_REMOTE_I2C_READ with transactions array [08:18:56] [PASSED] DP_REMOTE_I2C_WRITE with port number [08:18:56] [PASSED] DP_REMOTE_I2C_WRITE with I2C device ID [08:18:56] [PASSED] DP_REMOTE_I2C_WRITE with data array [08:18:56] [PASSED] DP_QUERY_STREAM_ENC_STATUS with stream ID [08:18:56] [PASSED] DP_QUERY_STREAM_ENC_STATUS with client ID [08:18:56] [PASSED] DP_QUERY_STREAM_ENC_STATUS with stream event [08:18:56] [PASSED] DP_QUERY_STREAM_ENC_STATUS with valid stream event [08:18:56] [PASSED] DP_QUERY_STREAM_ENC_STATUS with stream behavior [08:18:56] [PASSED] DP_QUERY_STREAM_ENC_STATUS with a valid stream behavior [08:18:56] ===== [PASSED] drm_test_dp_mst_sideband_msg_req_decode ===== [08:18:56] ================ [PASSED] drm_dp_mst_helper ================ [08:18:56] ================== drm_exec (7 subtests) =================== [08:18:56] [PASSED] sanitycheck [08:18:56] [PASSED] test_lock [08:18:56] [PASSED] test_lock_unlock [08:18:56] [PASSED] test_duplicates [08:18:56] [PASSED] test_prepare [08:18:56] [PASSED] test_prepare_array [08:18:56] [PASSED] test_multiple_loops [08:18:56] ==================== [PASSED] drm_exec ===================== [08:18:56] =========== drm_format_helper_test (17 subtests) =========== [08:18:56] ============== drm_test_fb_xrgb8888_to_gray8 ============== [08:18:56] [PASSED] single_pixel_source_buffer [08:18:56] [PASSED] single_pixel_clip_rectangle [08:18:56] [PASSED] well_known_colors [08:18:56] [PASSED] destination_pitch [08:18:56] ========== [PASSED] drm_test_fb_xrgb8888_to_gray8 ========== [08:18:56] ============= drm_test_fb_xrgb8888_to_rgb332 ============== [08:18:56] [PASSED] single_pixel_source_buffer [08:18:56] [PASSED] single_pixel_clip_rectangle [08:18:56] [PASSED] well_known_colors [08:18:56] [PASSED] destination_pitch [08:18:56] ========= [PASSED] drm_test_fb_xrgb8888_to_rgb332 ========== [08:18:56] ============= drm_test_fb_xrgb8888_to_rgb565 ============== [08:18:56] [PASSED] single_pixel_source_buffer [08:18:56] [PASSED] single_pixel_clip_rectangle [08:18:56] [PASSED] well_known_colors [08:18:56] [PASSED] destination_pitch [08:18:56] ========= [PASSED] drm_test_fb_xrgb8888_to_rgb565 ========== [08:18:56] ============ drm_test_fb_xrgb8888_to_xrgb1555 ============= [08:18:56] [PASSED] single_pixel_source_buffer [08:18:56] [PASSED] single_pixel_clip_rectangle [08:18:56] [PASSED] well_known_colors [08:18:56] [PASSED] destination_pitch [08:18:56] ======== [PASSED] drm_test_fb_xrgb8888_to_xrgb1555 ========= [08:18:56] ============ drm_test_fb_xrgb8888_to_argb1555 ============= [08:18:56] [PASSED] single_pixel_source_buffer [08:18:56] [PASSED] single_pixel_clip_rectangle [08:18:56] [PASSED] well_known_colors [08:18:56] [PASSED] destination_pitch [08:18:56] ======== [PASSED] drm_test_fb_xrgb8888_to_argb1555 ========= [08:18:56] ============ drm_test_fb_xrgb8888_to_rgba5551 ============= [08:18:56] [PASSED] single_pixel_source_buffer [08:18:56] [PASSED] single_pixel_clip_rectangle [08:18:56] [PASSED] well_known_colors [08:18:56] [PASSED] destination_pitch [08:18:56] ======== [PASSED] drm_test_fb_xrgb8888_to_rgba5551 ========= [08:18:56] ============= drm_test_fb_xrgb8888_to_rgb888 ============== [08:18:56] [PASSED] single_pixel_source_buffer [08:18:56] [PASSED] single_pixel_clip_rectangle [08:18:56] [PASSED] well_known_colors [08:18:56] [PASSED] destination_pitch [08:18:56] ========= [PASSED] drm_test_fb_xrgb8888_to_rgb888 ========== [08:18:56] ============= drm_test_fb_xrgb8888_to_bgr888 ============== [08:18:56] [PASSED] single_pixel_source_buffer [08:18:56] [PASSED] single_pixel_clip_rectangle [08:18:56] [PASSED] well_known_colors [08:18:56] [PASSED] destination_pitch [08:18:56] ========= [PASSED] drm_test_fb_xrgb8888_to_bgr888 ========== [08:18:56] ============ drm_test_fb_xrgb8888_to_argb8888 ============= [08:18:56] [PASSED] single_pixel_source_buffer [08:18:56] [PASSED] single_pixel_clip_rectangle [08:18:56] [PASSED] well_known_colors [08:18:56] [PASSED] destination_pitch [08:18:56] ======== [PASSED] drm_test_fb_xrgb8888_to_argb8888 ========= [08:18:56] =========== drm_test_fb_xrgb8888_to_xrgb2101010 =========== [08:18:56] [PASSED] single_pixel_source_buffer [08:18:56] [PASSED] single_pixel_clip_rectangle [08:18:56] [PASSED] well_known_colors [08:18:56] [PASSED] destination_pitch [08:18:56] ======= [PASSED] drm_test_fb_xrgb8888_to_xrgb2101010 ======= [08:18:56] =========== drm_test_fb_xrgb8888_to_argb2101010 =========== [08:18:56] [PASSED] single_pixel_source_buffer [08:18:56] [PASSED] single_pixel_clip_rectangle [08:18:56] [PASSED] well_known_colors [08:18:56] [PASSED] destination_pitch [08:18:56] ======= [PASSED] drm_test_fb_xrgb8888_to_argb2101010 ======= [08:18:56] ============== drm_test_fb_xrgb8888_to_mono =============== [08:18:56] [PASSED] single_pixel_source_buffer [08:18:56] [PASSED] single_pixel_clip_rectangle [08:18:56] [PASSED] well_known_colors [08:18:56] [PASSED] destination_pitch [08:18:56] ========== [PASSED] drm_test_fb_xrgb8888_to_mono =========== [08:18:56] ==================== drm_test_fb_swab ===================== [08:18:56] [PASSED] single_pixel_source_buffer [08:18:56] [PASSED] single_pixel_clip_rectangle [08:18:56] [PASSED] well_known_colors [08:18:56] [PASSED] destination_pitch [08:18:56] ================ [PASSED] drm_test_fb_swab ================= [08:18:56] ============ drm_test_fb_xrgb8888_to_xbgr8888 ============= [08:18:56] [PASSED] single_pixel_source_buffer [08:18:56] [PASSED] single_pixel_clip_rectangle [08:18:56] [PASSED] well_known_colors [08:18:56] [PASSED] destination_pitch [08:18:56] ======== [PASSED] drm_test_fb_xrgb8888_to_xbgr8888 ========= [08:18:56] ============ drm_test_fb_xrgb8888_to_abgr8888 ============= [08:18:56] [PASSED] single_pixel_source_buffer [08:18:56] [PASSED] single_pixel_clip_rectangle [08:18:56] [PASSED] well_known_colors [08:18:56] [PASSED] destination_pitch [08:18:56] ======== [PASSED] drm_test_fb_xrgb8888_to_abgr8888 ========= [08:18:56] ================= drm_test_fb_clip_offset ================= [08:18:56] [PASSED] pass through [08:18:56] [PASSED] horizontal offset [08:18:56] [PASSED] vertical offset [08:18:56] [PASSED] horizontal and vertical offset [08:18:56] [PASSED] horizontal offset (custom pitch) [08:18:56] [PASSED] vertical offset (custom pitch) [08:18:56] [PASSED] horizontal and vertical offset (custom pitch) [08:18:56] ============= [PASSED] drm_test_fb_clip_offset ============= [08:18:56] =================== drm_test_fb_memcpy ==================== [08:18:56] [PASSED] single_pixel_source_buffer: XR24 little-endian (0x34325258) [08:18:56] [PASSED] single_pixel_source_buffer: XRA8 little-endian (0x38415258) [08:18:56] [PASSED] single_pixel_source_buffer: YU24 little-endian (0x34325559) [08:18:56] [PASSED] single_pixel_clip_rectangle: XB24 little-endian (0x34324258) [08:18:56] [PASSED] single_pixel_clip_rectangle: XRA8 little-endian (0x38415258) [08:18:56] [PASSED] single_pixel_clip_rectangle: YU24 little-endian (0x34325559) [08:18:56] [PASSED] well_known_colors: XB24 little-endian (0x34324258) [08:18:56] [PASSED] well_known_colors: XRA8 little-endian (0x38415258) [08:18:56] [PASSED] well_known_colors: YU24 little-endian (0x34325559) [08:18:56] [PASSED] destination_pitch: XB24 little-endian (0x34324258) [08:18:56] [PASSED] destination_pitch: XRA8 little-endian (0x38415258) [08:18:56] [PASSED] destination_pitch: YU24 little-endian (0x34325559) [08:18:56] =============== [PASSED] drm_test_fb_memcpy ================ [08:18:56] ============= [PASSED] drm_format_helper_test ============== [08:18:56] ================= drm_format (18 subtests) ================= [08:18:56] [PASSED] drm_test_format_block_width_invalid [08:18:56] [PASSED] drm_test_format_block_width_one_plane [08:18:56] [PASSED] drm_test_format_block_width_two_plane [08:18:56] [PASSED] drm_test_format_block_width_three_plane [08:18:56] [PASSED] drm_test_format_block_width_tiled [08:18:56] [PASSED] drm_test_format_block_height_invalid [08:18:56] [PASSED] drm_test_format_block_height_one_plane [08:18:56] [PASSED] drm_test_format_block_height_two_plane [08:18:56] [PASSED] drm_test_format_block_height_three_plane [08:18:56] [PASSED] drm_test_format_block_height_tiled [08:18:56] [PASSED] drm_test_format_min_pitch_invalid [08:18:56] [PASSED] drm_test_format_min_pitch_one_plane_8bpp [08:18:56] [PASSED] drm_test_format_min_pitch_one_plane_16bpp [08:18:56] [PASSED] drm_test_format_min_pitch_one_plane_24bpp [08:18:56] [PASSED] drm_test_format_min_pitch_one_plane_32bpp [08:18:56] [PASSED] drm_test_format_min_pitch_two_plane [08:18:56] [PASSED] drm_test_format_min_pitch_three_plane_8bpp [08:18:56] [PASSED] drm_test_format_min_pitch_tiled [08:18:56] =================== [PASSED] drm_format ==================== [08:18:56] ============== drm_framebuffer (10 subtests) =============== [08:18:56] ========== drm_test_framebuffer_check_src_coords ========== [08:18:56] [PASSED] Success: source fits into fb [08:18:56] [PASSED] Fail: overflowing fb with x-axis coordinate [08:18:56] [PASSED] Fail: overflowing fb with y-axis coordinate [08:18:56] [PASSED] Fail: overflowing fb with source width [08:18:56] [PASSED] Fail: overflowing fb with source height [08:18:56] ====== [PASSED] drm_test_framebuffer_check_src_coords ====== [08:18:56] [PASSED] drm_test_framebuffer_cleanup [08:18:56] =============== drm_test_framebuffer_create =============== [08:18:56] [PASSED] ABGR8888 normal sizes [08:18:56] [PASSED] ABGR8888 max sizes [08:18:56] [PASSED] ABGR8888 pitch greater than min required [08:18:56] [PASSED] ABGR8888 pitch less than min required [08:18:56] [PASSED] ABGR8888 Invalid width [08:18:56] [PASSED] ABGR8888 Invalid buffer handle [08:18:56] [PASSED] No pixel format [08:18:56] [PASSED] ABGR8888 Width 0 [08:18:56] [PASSED] ABGR8888 Height 0 [08:18:56] [PASSED] ABGR8888 Out of bound height * pitch combination [08:18:56] [PASSED] ABGR8888 Large buffer offset [08:18:56] [PASSED] ABGR8888 Buffer offset for inexistent plane [08:18:56] [PASSED] ABGR8888 Invalid flag [08:18:56] [PASSED] ABGR8888 Set DRM_MODE_FB_MODIFIERS without modifiers [08:18:56] [PASSED] ABGR8888 Valid buffer modifier [08:18:56] [PASSED] ABGR8888 Invalid buffer modifier(DRM_FORMAT_MOD_SAMSUNG_64_32_TILE) [08:18:56] [PASSED] ABGR8888 Extra pitches without DRM_MODE_FB_MODIFIERS [08:18:56] [PASSED] ABGR8888 Extra pitches with DRM_MODE_FB_MODIFIERS [08:18:56] [PASSED] NV12 Normal sizes [08:18:56] [PASSED] NV12 Max sizes [08:18:56] [PASSED] NV12 Invalid pitch [08:18:56] [PASSED] NV12 Invalid modifier/missing DRM_MODE_FB_MODIFIERS flag [08:18:56] [PASSED] NV12 different modifier per-plane [08:18:56] [PASSED] NV12 with DRM_FORMAT_MOD_SAMSUNG_64_32_TILE [08:18:56] [PASSED] NV12 Valid modifiers without DRM_MODE_FB_MODIFIERS [08:18:56] [PASSED] NV12 Modifier for inexistent plane [08:18:56] [PASSED] NV12 Handle for inexistent plane [08:18:56] [PASSED] NV12 Handle for inexistent plane without DRM_MODE_FB_MODIFIERS [08:18:56] [PASSED] YVU420 DRM_MODE_FB_MODIFIERS set without modifier [08:18:56] [PASSED] YVU420 Normal sizes [08:18:56] [PASSED] YVU420 Max sizes [08:18:56] [PASSED] YVU420 Invalid pitch [08:18:56] [PASSED] YVU420 Different pitches [08:18:56] [PASSED] YVU420 Different buffer offsets/pitches [08:18:56] [PASSED] YVU420 Modifier set just for plane 0, without DRM_MODE_FB_MODIFIERS [08:18:56] [PASSED] YVU420 Modifier set just for planes 0, 1, without DRM_MODE_FB_MODIFIERS [08:18:56] [PASSED] YVU420 Modifier set just for plane 0, 1, with DRM_MODE_FB_MODIFIERS [08:18:56] [PASSED] YVU420 Valid modifier [08:18:56] [PASSED] YVU420 Different modifiers per plane [08:18:56] [PASSED] YVU420 Modifier for inexistent plane [08:18:56] [PASSED] YUV420_10BIT Invalid modifier(DRM_FORMAT_MOD_LINEAR) [08:18:56] [PASSED] X0L2 Normal sizes [08:18:56] [PASSED] X0L2 Max sizes [08:18:56] [PASSED] X0L2 Invalid pitch [08:18:56] [PASSED] X0L2 Pitch greater than minimum required [08:18:56] [PASSED] X0L2 Handle for inexistent plane [08:18:56] [PASSED] X0L2 Offset for inexistent plane, without DRM_MODE_FB_MODIFIERS set [08:18:56] [PASSED] X0L2 Modifier without DRM_MODE_FB_MODIFIERS set [08:18:56] [PASSED] X0L2 Valid modifier [08:18:56] [PASSED] X0L2 Modifier for inexistent plane [08:18:56] =========== [PASSED] drm_test_framebuffer_create =========== [08:18:56] [PASSED] drm_test_framebuffer_free [08:18:56] [PASSED] drm_test_framebuffer_init [08:18:56] [PASSED] drm_test_framebuffer_init_bad_format [08:18:56] [PASSED] drm_test_framebuffer_init_dev_mismatch [08:18:56] [PASSED] drm_test_framebuffer_lookup [08:18:56] [PASSED] drm_test_framebuffer_lookup_inexistent [08:18:56] [PASSED] drm_test_framebuffer_modifiers_not_supported [08:18:56] ================= [PASSED] drm_framebuffer ================= [08:18:56] ================ drm_gem_shmem (8 subtests) ================ [08:18:56] [PASSED] drm_gem_shmem_test_obj_create [08:18:56] [PASSED] drm_gem_shmem_test_obj_create_private [08:18:56] [PASSED] drm_gem_shmem_test_pin_pages [08:18:56] [PASSED] drm_gem_shmem_test_vmap [08:18:56] [PASSED] drm_gem_shmem_test_get_pages_sgt [08:18:56] [PASSED] drm_gem_shmem_test_get_sg_table [08:18:56] [PASSED] drm_gem_shmem_test_madvise [08:18:56] [PASSED] drm_gem_shmem_test_purge [08:18:56] ================== [PASSED] drm_gem_shmem ================== [08:18:56] === drm_atomic_helper_connector_hdmi_check (27 subtests) === [08:18:56] [PASSED] drm_test_check_broadcast_rgb_auto_cea_mode [08:18:56] [PASSED] drm_test_check_broadcast_rgb_auto_cea_mode_vic_1 [08:18:56] [PASSED] drm_test_check_broadcast_rgb_full_cea_mode [08:18:56] [PASSED] drm_test_check_broadcast_rgb_full_cea_mode_vic_1 [08:18:56] [PASSED] drm_test_check_broadcast_rgb_limited_cea_mode [08:18:56] [PASSED] drm_test_check_broadcast_rgb_limited_cea_mode_vic_1 [08:18:56] ====== drm_test_check_broadcast_rgb_cea_mode_yuv420 ======= [08:18:56] [PASSED] Automatic [08:18:56] [PASSED] Full [08:18:56] [PASSED] Limited 16:235 [08:18:56] == [PASSED] drm_test_check_broadcast_rgb_cea_mode_yuv420 === [08:18:56] [PASSED] drm_test_check_broadcast_rgb_crtc_mode_changed [08:18:56] [PASSED] drm_test_check_broadcast_rgb_crtc_mode_not_changed [08:18:56] [PASSED] drm_test_check_disable_connector [08:18:56] [PASSED] drm_test_check_hdmi_funcs_reject_rate [08:18:56] [PASSED] drm_test_check_max_tmds_rate_bpc_fallback_rgb [08:18:56] [PASSED] drm_test_check_max_tmds_rate_bpc_fallback_yuv420 [08:18:56] [PASSED] drm_test_check_max_tmds_rate_bpc_fallback_ignore_yuv422 [08:18:56] [PASSED] drm_test_check_max_tmds_rate_bpc_fallback_ignore_yuv420 [08:18:56] [PASSED] drm_test_check_driver_unsupported_fallback_yuv420 [08:18:56] [PASSED] drm_test_check_output_bpc_crtc_mode_changed [08:18:56] [PASSED] drm_test_check_output_bpc_crtc_mode_not_changed [08:18:56] [PASSED] drm_test_check_output_bpc_dvi [08:18:56] [PASSED] drm_test_check_output_bpc_format_vic_1 [08:18:56] [PASSED] drm_test_check_output_bpc_format_display_8bpc_only [08:18:56] [PASSED] drm_test_check_output_bpc_format_display_rgb_only [08:18:56] [PASSED] drm_test_check_output_bpc_format_driver_8bpc_only [08:18:56] [PASSED] drm_test_check_output_bpc_format_driver_rgb_only [08:18:56] [PASSED] drm_test_check_tmds_char_rate_rgb_8bpc [08:18:56] [PASSED] drm_test_check_tmds_char_rate_rgb_10bpc [08:18:56] [PASSED] drm_test_check_tmds_char_rate_rgb_12bpc [08:18:56] ===== [PASSED] drm_atomic_helper_connector_hdmi_check ====== [08:18:56] === drm_atomic_helper_connector_hdmi_reset (6 subtests) ==== [08:18:56] [PASSED] drm_test_check_broadcast_rgb_value [08:18:56] [PASSED] drm_test_check_bpc_8_value [08:18:56] [PASSED] drm_test_check_bpc_10_value [08:18:56] [PASSED] drm_test_check_bpc_12_value [08:18:56] [PASSED] drm_test_check_format_value [08:18:56] [PASSED] drm_test_check_tmds_char_value [08:18:56] ===== [PASSED] drm_atomic_helper_connector_hdmi_reset ====== [08:18:56] = drm_atomic_helper_connector_hdmi_mode_valid (4 subtests) = [08:18:56] [PASSED] drm_test_check_mode_valid [08:18:56] [PASSED] drm_test_check_mode_valid_reject [08:18:56] [PASSED] drm_test_check_mode_valid_reject_rate [08:18:56] [PASSED] drm_test_check_mode_valid_reject_max_clock [08:18:56] === [PASSED] drm_atomic_helper_connector_hdmi_mode_valid === [08:18:56] ================= drm_managed (2 subtests) ================= [08:18:56] [PASSED] drm_test_managed_release_action [08:18:56] [PASSED] drm_test_managed_run_action [08:18:56] =================== [PASSED] drm_managed =================== [08:18:56] =================== drm_mm (6 subtests) ==================== [08:18:56] [PASSED] drm_test_mm_init [08:18:56] [PASSED] drm_test_mm_debug [08:18:56] [PASSED] drm_test_mm_align32 [08:18:56] [PASSED] drm_test_mm_align64 [08:18:56] [PASSED] drm_test_mm_lowest [08:18:56] [PASSED] drm_test_mm_highest [08:18:56] ===================== [PASSED] drm_mm ====================== [08:18:56] ============= drm_modes_analog_tv (5 subtests) ============= [08:18:56] [PASSED] drm_test_modes_analog_tv_mono_576i [08:18:56] [PASSED] drm_test_modes_analog_tv_ntsc_480i [08:18:56] [PASSED] drm_test_modes_analog_tv_ntsc_480i_inlined [08:18:56] [PASSED] drm_test_modes_analog_tv_pal_576i [08:18:56] [PASSED] drm_test_modes_analog_tv_pal_576i_inlined [08:18:56] =============== [PASSED] drm_modes_analog_tv =============== [08:18:56] ============== drm_plane_helper (2 subtests) =============== [08:18:56] =============== drm_test_check_plane_state ================ [08:18:56] [PASSED] clipping_simple [08:18:56] [PASSED] clipping_rotate_reflect [08:18:56] [PASSED] positioning_simple [08:18:56] [PASSED] upscaling [08:18:56] [PASSED] downscaling [08:18:56] [PASSED] rounding1 [08:18:56] [PASSED] rounding2 [08:18:56] [PASSED] rounding3 [08:18:56] [PASSED] rounding4 [08:18:56] =========== [PASSED] drm_test_check_plane_state ============ [08:18:56] =========== drm_test_check_invalid_plane_state ============ [08:18:56] [PASSED] positioning_invalid [08:18:56] [PASSED] upscaling_invalid [08:18:56] [PASSED] downscaling_invalid [08:18:56] ======= [PASSED] drm_test_check_invalid_plane_state ======== [08:18:56] ================ [PASSED] drm_plane_helper ================= [08:18:56] ====== drm_connector_helper_tv_get_modes (1 subtest) ======= [08:18:56] ====== drm_test_connector_helper_tv_get_modes_check ======= [08:18:56] [PASSED] None [08:18:56] [PASSED] PAL [08:18:56] [PASSED] NTSC [08:18:56] [PASSED] Both, NTSC Default [08:18:56] [PASSED] Both, PAL Default [08:18:56] [PASSED] Both, NTSC Default, with PAL on command-line [08:18:56] [PASSED] Both, PAL Default, with NTSC on command-line [08:18:56] == [PASSED] drm_test_connector_helper_tv_get_modes_check === [08:18:56] ======== [PASSED] drm_connector_helper_tv_get_modes ======== [08:18:56] ================== drm_rect (9 subtests) =================== [08:18:56] [PASSED] drm_test_rect_clip_scaled_div_by_zero [08:18:56] [PASSED] drm_test_rect_clip_scaled_not_clipped [08:18:56] [PASSED] drm_test_rect_clip_scaled_clipped [08:18:56] [PASSED] drm_test_rect_clip_scaled_signed_vs_unsigned [08:18:56] ================= drm_test_rect_intersect ================= [08:18:56] [PASSED] top-left x bottom-right: 2x2+1+1 x 2x2+0+0 [08:18:56] [PASSED] top-right x bottom-left: 2x2+0+0 x 2x2+1-1 [08:18:56] [PASSED] bottom-left x top-right: 2x2+1-1 x 2x2+0+0 [08:18:56] [PASSED] bottom-right x top-left: 2x2+0+0 x 2x2+1+1 [08:18:56] [PASSED] right x left: 2x1+0+0 x 3x1+1+0 [08:18:56] [PASSED] left x right: 3x1+1+0 x 2x1+0+0 [08:18:56] [PASSED] up x bottom: 1x2+0+0 x 1x3+0-1 [08:18:56] [PASSED] bottom x up: 1x3+0-1 x 1x2+0+0 [08:18:56] [PASSED] touching corner: 1x1+0+0 x 2x2+1+1 [08:18:56] [PASSED] touching side: 1x1+0+0 x 1x1+1+0 [08:18:56] [PASSED] equal rects: 2x2+0+0 x 2x2+0+0 [08:18:56] [PASSED] inside another: 2x2+0+0 x 1x1+1+1 [08:18:56] [PASSED] far away: 1x1+0+0 x 1x1+3+6 [08:18:56] [PASSED] points intersecting: 0x0+5+10 x 0x0+5+10 [08:18:56] [PASSED] points not intersecting: 0x0+0+0 x 0x0+5+10 [08:18:56] ============= [PASSED] drm_test_rect_intersect ============= [08:18:56] ================ drm_test_rect_calc_hscale ================ [08:18:56] [PASSED] normal use [08:18:56] [PASSED] out of max range [08:18:56] [PASSED] out of min range [08:18:56] [PASSED] zero dst [08:18:56] [PASSED] negative src [08:18:56] [PASSED] negative dst [08:18:56] ============ [PASSED] drm_test_rect_calc_hscale ============ [08:18:56] ================ drm_test_rect_calc_vscale ================ [08:18:56] [PASSED] normal use [08:18:56] [PASSED] out of max range [08:18:56] [PASSED] out of min range [08:18:56] [PASSED] zero dst [08:18:56] [PASSED] negative src [08:18:56] [PASSED] negative dst [08:18:56] ============ [PASSED] drm_test_rect_calc_vscale ============ [08:18:56] ================== drm_test_rect_rotate =================== [08:18:56] [PASSED] reflect-x [08:18:56] [PASSED] reflect-y [08:18:56] [PASSED] rotate-0 [08:18:56] [PASSED] rotate-90 [08:18:56] [PASSED] rotate-180 [08:18:56] [PASSED] rotate-270 stty: 'standard input': Inappropriate ioctl for device [08:18:56] ============== [PASSED] drm_test_rect_rotate =============== [08:18:56] ================ drm_test_rect_rotate_inv ================= [08:18:56] [PASSED] reflect-x [08:18:56] [PASSED] reflect-y [08:18:56] [PASSED] rotate-0 [08:18:56] [PASSED] rotate-90 [08:18:56] [PASSED] rotate-180 [08:18:56] [PASSED] rotate-270 [08:18:56] ============ [PASSED] drm_test_rect_rotate_inv ============= [08:18:56] ==================== [PASSED] drm_rect ===================== [08:18:56] ============ drm_sysfb_modeset_test (1 subtest) ============ [08:18:56] ============ drm_test_sysfb_build_fourcc_list ============= [08:18:56] [PASSED] no native formats [08:18:56] [PASSED] XRGB8888 as native format [08:18:56] [PASSED] remove duplicates [08:18:56] [PASSED] convert alpha formats [08:18:56] [PASSED] random formats [08:18:56] ======== [PASSED] drm_test_sysfb_build_fourcc_list ========= [08:18:56] ============= [PASSED] drm_sysfb_modeset_test ============== [08:18:56] ============================================================ [08:18:56] Testing complete. Ran 616 tests: passed: 616 [08:18:56] Elapsed time: 23.481s total, 1.666s configuring, 21.645s building, 0.143s running + /kernel/tools/testing/kunit/kunit.py run --kunitconfig /kernel/drivers/gpu/drm/ttm/tests/.kunitconfig [08:18:56] Configuring KUnit Kernel ... Regenerating .config ... Populating config with: $ make ARCH=um O=.kunit olddefconfig [08:18:58] Building KUnit Kernel ... Populating config with: $ make ARCH=um O=.kunit olddefconfig Building with: $ make all compile_commands.json scripts_gdb ARCH=um O=.kunit --jobs=48 [08:19:06] Starting KUnit Kernel (1/1)... [08:19:06] ============================================================ Running tests with: $ .kunit/linux kunit.enable=1 mem=1G console=tty kunit_shutdown=halt [08:19:06] ================= ttm_device (5 subtests) ================== [08:19:06] [PASSED] ttm_device_init_basic [08:19:06] [PASSED] ttm_device_init_multiple [08:19:06] [PASSED] ttm_device_fini_basic [08:19:06] [PASSED] ttm_device_init_no_vma_man [08:19:06] ================== ttm_device_init_pools ================== [08:19:06] [PASSED] No DMA allocations, no DMA32 required [08:19:06] [PASSED] DMA allocations, DMA32 required [08:19:06] [PASSED] No DMA allocations, DMA32 required [08:19:06] [PASSED] DMA allocations, no DMA32 required [08:19:06] ============== [PASSED] ttm_device_init_pools ============== [08:19:06] =================== [PASSED] ttm_device ==================== [08:19:06] ================== ttm_pool (8 subtests) =================== [08:19:06] ================== ttm_pool_alloc_basic =================== [08:19:06] [PASSED] One page [08:19:06] [PASSED] More than one page [08:19:06] [PASSED] Above the allocation limit [08:19:06] [PASSED] One page, with coherent DMA mappings enabled [08:19:06] [PASSED] Above the allocation limit, with coherent DMA mappings enabled [08:19:06] ============== [PASSED] ttm_pool_alloc_basic =============== [08:19:06] ============== ttm_pool_alloc_basic_dma_addr ============== [08:19:06] [PASSED] One page [08:19:06] [PASSED] More than one page [08:19:06] [PASSED] Above the allocation limit [08:19:06] [PASSED] One page, with coherent DMA mappings enabled [08:19:06] [PASSED] Above the allocation limit, with coherent DMA mappings enabled [08:19:06] ========== [PASSED] ttm_pool_alloc_basic_dma_addr ========== [08:19:06] [PASSED] ttm_pool_alloc_order_caching_match [08:19:06] [PASSED] ttm_pool_alloc_caching_mismatch [08:19:06] [PASSED] ttm_pool_alloc_order_mismatch [08:19:06] [PASSED] ttm_pool_free_dma_alloc [08:19:06] [PASSED] ttm_pool_free_no_dma_alloc [08:19:06] [PASSED] ttm_pool_fini_basic [08:19:06] ==================== [PASSED] ttm_pool ===================== [08:19:06] ================ ttm_resource (8 subtests) ================= [08:19:06] ================= ttm_resource_init_basic ================= [08:19:06] [PASSED] Init resource in TTM_PL_SYSTEM [08:19:06] [PASSED] Init resource in TTM_PL_VRAM [08:19:06] [PASSED] Init resource in a private placement [08:19:06] [PASSED] Init resource in TTM_PL_SYSTEM, set placement flags [08:19:06] ============= [PASSED] ttm_resource_init_basic ============= [08:19:06] [PASSED] ttm_resource_init_pinned [08:19:06] [PASSED] ttm_resource_fini_basic [08:19:06] [PASSED] ttm_resource_manager_init_basic [08:19:06] [PASSED] ttm_resource_manager_usage_basic [08:19:06] [PASSED] ttm_resource_manager_set_used_basic [08:19:06] [PASSED] ttm_sys_man_alloc_basic [08:19:06] [PASSED] ttm_sys_man_free_basic [08:19:06] ================== [PASSED] ttm_resource =================== [08:19:06] =================== ttm_tt (15 subtests) =================== [08:19:06] ==================== ttm_tt_init_basic ==================== [08:19:06] [PASSED] Page-aligned size [08:19:06] [PASSED] Extra pages requested [08:19:06] ================ [PASSED] ttm_tt_init_basic ================ [08:19:06] [PASSED] ttm_tt_init_misaligned [08:19:06] [PASSED] ttm_tt_fini_basic [08:19:06] [PASSED] ttm_tt_fini_sg [08:19:06] [PASSED] ttm_tt_fini_shmem [08:19:06] [PASSED] ttm_tt_create_basic [08:19:06] [PASSED] ttm_tt_create_invalid_bo_type [08:19:06] [PASSED] ttm_tt_create_ttm_exists [08:19:06] [PASSED] ttm_tt_create_failed [08:19:06] [PASSED] ttm_tt_destroy_basic [08:19:06] [PASSED] ttm_tt_populate_null_ttm [08:19:06] [PASSED] ttm_tt_populate_populated_ttm [08:19:06] [PASSED] ttm_tt_unpopulate_basic [08:19:06] [PASSED] ttm_tt_unpopulate_empty_ttm [08:19:06] [PASSED] ttm_tt_swapin_basic [08:19:06] ===================== [PASSED] ttm_tt ====================== [08:19:06] =================== ttm_bo (14 subtests) =================== [08:19:06] =========== ttm_bo_reserve_optimistic_no_ticket =========== [08:19:06] [PASSED] Cannot be interrupted and sleeps [08:19:06] [PASSED] Cannot be interrupted, locks straight away [08:19:06] [PASSED] Can be interrupted, sleeps [08:19:06] ======= [PASSED] ttm_bo_reserve_optimistic_no_ticket ======= [08:19:06] [PASSED] ttm_bo_reserve_locked_no_sleep [08:19:06] [PASSED] ttm_bo_reserve_no_wait_ticket [08:19:06] [PASSED] ttm_bo_reserve_double_resv [08:19:06] [PASSED] ttm_bo_reserve_interrupted [08:19:06] [PASSED] ttm_bo_reserve_deadlock [08:19:06] [PASSED] ttm_bo_unreserve_basic [08:19:06] [PASSED] ttm_bo_unreserve_pinned [08:19:06] [PASSED] ttm_bo_unreserve_bulk [08:19:06] [PASSED] ttm_bo_put_basic [08:19:06] [PASSED] ttm_bo_put_shared_resv [08:19:06] [PASSED] ttm_bo_pin_basic [08:19:06] [PASSED] ttm_bo_pin_unpin_resource [08:19:06] [PASSED] ttm_bo_multiple_pin_one_unpin [08:19:06] ===================== [PASSED] ttm_bo ====================== [08:19:06] ============== ttm_bo_validate (21 subtests) =============== [08:19:06] ============== ttm_bo_init_reserved_sys_man =============== [08:19:06] [PASSED] Buffer object for userspace [08:19:06] [PASSED] Kernel buffer object [08:19:06] [PASSED] Shared buffer object [08:19:06] ========== [PASSED] ttm_bo_init_reserved_sys_man =========== [08:19:06] ============== ttm_bo_init_reserved_mock_man ============== [08:19:06] [PASSED] Buffer object for userspace [08:19:06] [PASSED] Kernel buffer object [08:19:06] [PASSED] Shared buffer object [08:19:06] ========== [PASSED] ttm_bo_init_reserved_mock_man ========== [08:19:06] [PASSED] ttm_bo_init_reserved_resv [08:19:06] ================== ttm_bo_validate_basic ================== [08:19:06] [PASSED] Buffer object for userspace [08:19:06] [PASSED] Kernel buffer object [08:19:06] [PASSED] Shared buffer object [08:19:06] ============== [PASSED] ttm_bo_validate_basic ============== [08:19:06] [PASSED] ttm_bo_validate_invalid_placement [08:19:06] ============= ttm_bo_validate_same_placement ============== [08:19:06] [PASSED] System manager [08:19:06] [PASSED] VRAM manager [08:19:06] ========= [PASSED] ttm_bo_validate_same_placement ========== [08:19:06] [PASSED] ttm_bo_validate_failed_alloc [08:19:06] [PASSED] ttm_bo_validate_pinned [08:19:06] [PASSED] ttm_bo_validate_busy_placement [08:19:06] ================ ttm_bo_validate_multihop ================= [08:19:06] [PASSED] Buffer object for userspace [08:19:06] [PASSED] Kernel buffer object [08:19:06] [PASSED] Shared buffer object [08:19:06] ============ [PASSED] ttm_bo_validate_multihop ============= [08:19:06] ========== ttm_bo_validate_no_placement_signaled ========== [08:19:06] [PASSED] Buffer object in system domain, no page vector [08:19:06] [PASSED] Buffer object in system domain with an existing page vector [08:19:06] ====== [PASSED] ttm_bo_validate_no_placement_signaled ====== [08:19:06] ======== ttm_bo_validate_no_placement_not_signaled ======== [08:19:06] [PASSED] Buffer object for userspace [08:19:06] [PASSED] Kernel buffer object [08:19:06] [PASSED] Shared buffer object [08:19:06] ==== [PASSED] ttm_bo_validate_no_placement_not_signaled ==== [08:19:06] [PASSED] ttm_bo_validate_move_fence_signaled [08:19:06] ========= ttm_bo_validate_move_fence_not_signaled ========= [08:19:06] [PASSED] Waits for GPU [08:19:06] [PASSED] Tries to lock straight away [08:19:06] ===== [PASSED] ttm_bo_validate_move_fence_not_signaled ===== [08:19:06] [PASSED] ttm_bo_validate_happy_evict [08:19:06] [PASSED] ttm_bo_validate_all_pinned_evict [08:19:06] [PASSED] ttm_bo_validate_allowed_only_evict [08:19:06] [PASSED] ttm_bo_validate_deleted_evict [08:19:06] [PASSED] ttm_bo_validate_busy_domain_evict [08:19:06] [PASSED] ttm_bo_validate_evict_gutting [08:19:06] [PASSED] ttm_bo_validate_recrusive_evict stty: 'standard input': Inappropriate ioctl for device [08:19:06] ================= [PASSED] ttm_bo_validate ================= [08:19:06] ============================================================ [08:19:06] Testing complete. Ran 101 tests: passed: 101 [08:19:06] Elapsed time: 9.735s total, 1.685s configuring, 7.833s building, 0.179s running + cleanup ++ stat -c %u:%g /kernel + chown -R 1003:1003 /kernel ^ permalink raw reply [flat|nested] 15+ messages in thread
* [PATCH v3 1/2] drm/xe/vf: Refactor CCS save/restore to use default migration context 2025-08-06 8:29 [PATCH v3 0/2] Improve CCS save restore series Satyanarayana K V P 2025-08-06 8:19 ` ✓ CI.KUnit: success for Improve CCS save restore series (rev3) Patchwork @ 2025-08-06 8:29 ` Satyanarayana K V P 2025-08-06 16:08 ` Summers, Stuart 2025-08-06 18:50 ` John Harrison 2025-08-06 8:29 ` [PATCH v3 2/2] drm/xe/guc: Scale mmio send/recv timeout for CCS save/restore with smem size Satyanarayana K V P ` (2 subsequent siblings) 4 siblings, 2 replies; 15+ messages in thread From: Satyanarayana K V P @ 2025-08-06 8:29 UTC (permalink / raw) To: intel-xe; +Cc: Satyanarayana K V P, Matthew Brost, Michal Wajdeczko Previously, CCS save/restore operations created separate migration contexts with new VM memory allocations, resulting in significant overhead. This commit eliminates redundant context creation reusing the default migration context by registering new execution queues for CCS save and restore on the existing migrate VM. Signed-off-by: Satyanarayana K V P <satyanarayana.k.v.p@intel.com> Suggested-by: Matthew Brost <matthew.brost@intel.com> Cc: Michal Wajdeczko <michal.wajdeczko@intel.com> --- V2 -> V3: - Fixed review comments (Matthew Brost). V1 -> V2: - Fixed kernel-doc issues reported by patchworks. --- drivers/gpu/drm/xe/xe_migrate.c | 18 ++++---- drivers/gpu/drm/xe/xe_migrate.h | 2 +- drivers/gpu/drm/xe/xe_pm.c | 3 ++ drivers/gpu/drm/xe/xe_sriov_vf_ccs.c | 49 ++++++++++++---------- drivers/gpu/drm/xe/xe_sriov_vf_ccs_types.h | 6 +-- 5 files changed, 43 insertions(+), 35 deletions(-) diff --git a/drivers/gpu/drm/xe/xe_migrate.c b/drivers/gpu/drm/xe/xe_migrate.c index 3a276e2348a2..7d3c7c4e2185 100644 --- a/drivers/gpu/drm/xe/xe_migrate.c +++ b/drivers/gpu/drm/xe/xe_migrate.c @@ -960,14 +960,14 @@ struct xe_lrc *xe_migrate_lrc(struct xe_migrate *migrate) return migrate->q->lrc[0]; } -static int emit_flush_invalidate(struct xe_migrate *m, u32 *dw, int i, +static int emit_flush_invalidate(struct xe_exec_queue *q, u32 *dw, int i, u32 flags) { dw[i++] = MI_FLUSH_DW | MI_INVALIDATE_TLB | MI_FLUSH_DW_OP_STOREDW | MI_FLUSH_IMM_DW | flags; - dw[i++] = lower_32_bits(xe_lrc_start_seqno_ggtt_addr(xe_migrate_lrc(m))) | + dw[i++] = lower_32_bits(xe_lrc_start_seqno_ggtt_addr(q->lrc[0])) | MI_FLUSH_DW_USE_GTT; - dw[i++] = upper_32_bits(xe_lrc_start_seqno_ggtt_addr(xe_migrate_lrc(m))); + dw[i++] = upper_32_bits(xe_lrc_start_seqno_ggtt_addr(q->lrc[0])); dw[i++] = MI_NOOP; dw[i++] = MI_NOOP; @@ -976,7 +976,8 @@ static int emit_flush_invalidate(struct xe_migrate *m, u32 *dw, int i, /** * xe_migrate_ccs_rw_copy() - Copy content of TTM resources. - * @m: The migration context. + * @tile: Tile whose migration context to be used. + * @q : Execution to be used along with migration context. * @src_bo: The buffer object @src is currently bound to. * @read_write : Creates BB commands for CCS read/write. * @@ -987,7 +988,7 @@ static int emit_flush_invalidate(struct xe_migrate *m, u32 *dw, int i, * * Return: 0 if successful, negative error code on failure. */ -int xe_migrate_ccs_rw_copy(struct xe_migrate *m, +int xe_migrate_ccs_rw_copy(struct xe_tile *tile, struct xe_exec_queue *q, struct xe_bo *src_bo, enum xe_sriov_vf_ccs_rw_ctxs read_write) @@ -995,7 +996,8 @@ int xe_migrate_ccs_rw_copy(struct xe_migrate *m, bool src_is_pltt = read_write == XE_SRIOV_VF_CCS_READ_CTX; bool dst_is_pltt = read_write == XE_SRIOV_VF_CCS_WRITE_CTX; struct ttm_resource *src = src_bo->ttm.resource; - struct xe_gt *gt = m->tile->primary_gt; + struct xe_migrate *m = tile->migrate; + struct xe_gt *gt = tile->primary_gt; u32 batch_size, batch_size_allocated; struct xe_device *xe = gt_to_xe(gt); struct xe_res_cursor src_it, ccs_it; @@ -1078,11 +1080,11 @@ int xe_migrate_ccs_rw_copy(struct xe_migrate *m, emit_pte(m, bb, ccs_pt, false, false, &ccs_it, ccs_size, src); - bb->len = emit_flush_invalidate(m, bb->cs, bb->len, flush_flags); + bb->len = emit_flush_invalidate(q, bb->cs, bb->len, flush_flags); flush_flags = xe_migrate_ccs_copy(m, bb, src_L0_ofs, src_is_pltt, src_L0_ofs, dst_is_pltt, src_L0, ccs_ofs, true); - bb->len = emit_flush_invalidate(m, bb->cs, bb->len, flush_flags); + bb->len = emit_flush_invalidate(q, bb->cs, bb->len, flush_flags); size -= src_L0; } diff --git a/drivers/gpu/drm/xe/xe_migrate.h b/drivers/gpu/drm/xe/xe_migrate.h index e81ea6b27fb5..9e20da6d58c2 100644 --- a/drivers/gpu/drm/xe/xe_migrate.h +++ b/drivers/gpu/drm/xe/xe_migrate.h @@ -124,7 +124,7 @@ struct dma_fence *xe_migrate_copy(struct xe_migrate *m, struct ttm_resource *dst, bool copy_only_ccs); -int xe_migrate_ccs_rw_copy(struct xe_migrate *m, +int xe_migrate_ccs_rw_copy(struct xe_tile *tile, struct xe_exec_queue *q, struct xe_bo *src_bo, enum xe_sriov_vf_ccs_rw_ctxs read_write); diff --git a/drivers/gpu/drm/xe/xe_pm.c b/drivers/gpu/drm/xe/xe_pm.c index 44aaf154ddf7..5e8126ca8e27 100644 --- a/drivers/gpu/drm/xe/xe_pm.c +++ b/drivers/gpu/drm/xe/xe_pm.c @@ -209,6 +209,9 @@ int xe_pm_resume(struct xe_device *xe) xe_pxp_pm_resume(xe->pxp); + if (IS_SRIOV_VF(xe)) + xe_sriov_vf_ccs_register_context(xe); + drm_dbg(&xe->drm, "Device resumed\n"); return 0; err: diff --git a/drivers/gpu/drm/xe/xe_sriov_vf_ccs.c b/drivers/gpu/drm/xe/xe_sriov_vf_ccs.c index f0ca2a9b2bb7..a87f39eae4dc 100644 --- a/drivers/gpu/drm/xe/xe_sriov_vf_ccs.c +++ b/drivers/gpu/drm/xe/xe_sriov_vf_ccs.c @@ -8,6 +8,7 @@ #include "xe_bb.h" #include "xe_bo.h" #include "xe_device.h" +#include "xe_exec_queue.h" #include "xe_exec_queue_types.h" #include "xe_guc_submit.h" #include "xe_lrc.h" @@ -168,7 +169,7 @@ static int alloc_bb_pool(struct xe_tile *tile, struct xe_tile_vf_ccs *ctx) static void ccs_rw_update_ring(struct xe_tile_vf_ccs *ctx) { - struct xe_lrc *lrc = xe_migrate_lrc(ctx->migrate); + struct xe_lrc *lrc = ctx->q->lrc[0]; u64 addr = xe_sa_manager_gpu_addr(ctx->mem.ccs_bb_pool); u32 dw[10], i = 0; @@ -183,13 +184,12 @@ static void ccs_rw_update_ring(struct xe_tile_vf_ccs *ctx) xe_lrc_set_ring_tail(lrc, lrc->ring.tail); } -static int register_save_restore_context(struct xe_migrate *m, - enum xe_sriov_vf_ccs_rw_ctxs ctx_id) +static int register_save_restore_context(struct xe_tile_vf_ccs *ctx) { int err = -EINVAL; int ctx_type; - switch (ctx_id) { + switch (ctx->ctx_id) { case XE_SRIOV_VF_CCS_READ_CTX: ctx_type = GUC_CONTEXT_COMPRESSION_SAVE; break; @@ -200,7 +200,7 @@ static int register_save_restore_context(struct xe_migrate *m, return err; } - xe_guc_register_exec_queue(xe_migrate_exec_queue(m), ctx_type); + xe_guc_register_exec_queue(ctx->q, ctx_type); return 0; } @@ -225,7 +225,7 @@ int xe_sriov_vf_ccs_register_context(struct xe_device *xe) for_each_ccs_rw_ctx(ctx_id) { ctx = &tile->sriov.vf.ccs[ctx_id]; - err = register_save_restore_context(ctx->migrate, ctx_id); + err = register_save_restore_context(ctx); if (err) return err; } @@ -236,13 +236,14 @@ int xe_sriov_vf_ccs_register_context(struct xe_device *xe) static void xe_sriov_vf_ccs_fini(void *arg) { struct xe_tile_vf_ccs *ctx = arg; - struct xe_lrc *lrc = xe_migrate_lrc(ctx->migrate); + struct xe_lrc *lrc = ctx->q->lrc[0]; /* * Make TAIL = HEAD in the ring so that no issues are seen if Guc * submits this context to HW on VF pause after unbinding device. */ xe_lrc_set_ring_tail(lrc, xe_lrc_ring_head(lrc)); + xe_exec_queue_put(ctx->q); } /** @@ -258,8 +259,9 @@ int xe_sriov_vf_ccs_init(struct xe_device *xe) { struct xe_tile *tile = xe_device_get_root_tile(xe); enum xe_sriov_vf_ccs_rw_ctxs ctx_id; - struct xe_migrate *migrate; struct xe_tile_vf_ccs *ctx; + struct xe_exec_queue *q; + u32 flags; int err; xe_assert(xe, IS_SRIOV_VF(xe)); @@ -270,27 +272,25 @@ int xe_sriov_vf_ccs_init(struct xe_device *xe) ctx = &tile->sriov.vf.ccs[ctx_id]; ctx->ctx_id = ctx_id; - migrate = xe_migrate_alloc(tile); - if (!migrate) { - err = -ENOMEM; + flags = EXEC_QUEUE_FLAG_KERNEL | + EXEC_QUEUE_FLAG_PERMANENT | + EXEC_QUEUE_FLAG_MIGRATE; + q = xe_exec_queue_create_bind(xe, tile, flags, 0); + if (IS_ERR(q)) { + err = PTR_ERR(q); goto err_ret; } - - err = xe_migrate_init(migrate); - if (err) - goto err_ret; - - ctx->migrate = migrate; + ctx->q = q; err = alloc_bb_pool(tile, ctx); if (err) - goto err_ret; + goto err_free_queue; ccs_rw_update_ring(ctx); - err = register_save_restore_context(ctx->migrate, ctx_id); + err = register_save_restore_context(ctx); if (err) - goto err_ret; + goto err_free_queue; err = devm_add_action_or_reset(xe->drm.dev, xe_sriov_vf_ccs_fini, @@ -301,6 +301,9 @@ int xe_sriov_vf_ccs_init(struct xe_device *xe) return 0; +err_free_queue: + xe_exec_queue_put(q); + err_ret: return err; } @@ -319,7 +322,7 @@ int xe_sriov_vf_ccs_attach_bo(struct xe_bo *bo) { struct xe_device *xe = xe_bo_device(bo); enum xe_sriov_vf_ccs_rw_ctxs ctx_id; - struct xe_migrate *migrate; + struct xe_tile_vf_ccs *ctx; struct xe_tile *tile; struct xe_bb *bb; int err = 0; @@ -334,8 +337,8 @@ int xe_sriov_vf_ccs_attach_bo(struct xe_bo *bo) /* bb should be NULL here. Assert if not NULL */ xe_assert(xe, !bb); - migrate = tile->sriov.vf.ccs[ctx_id].migrate; - err = xe_migrate_ccs_rw_copy(migrate, bo, ctx_id); + ctx = &tile->sriov.vf.ccs[ctx_id]; + err = xe_migrate_ccs_rw_copy(tile, ctx->q, bo, ctx_id); } return err; } diff --git a/drivers/gpu/drm/xe/xe_sriov_vf_ccs_types.h b/drivers/gpu/drm/xe/xe_sriov_vf_ccs_types.h index e240f3fd18af..1add0541aed8 100644 --- a/drivers/gpu/drm/xe/xe_sriov_vf_ccs_types.h +++ b/drivers/gpu/drm/xe/xe_sriov_vf_ccs_types.h @@ -41,11 +41,11 @@ struct xe_sa_manager; struct xe_tile_vf_ccs { /** @id: Id to which context it belongs to */ enum xe_sriov_vf_ccs_rw_ctxs ctx_id; - /** @migrate: Migration helper for save/restore of CCS data */ - struct xe_migrate *migrate; + /** @q: exec queues used for migration */ + struct xe_exec_queue *q; struct { - /** @ccs_rw_bb_pool: Pool from which batch buffers are allocated. */ + /** @ccs_bb_pool: Pool from which batch buffers are allocated. */ struct xe_sa_manager *ccs_bb_pool; } mem; }; -- 2.43.0 ^ permalink raw reply related [flat|nested] 15+ messages in thread
* Re: [PATCH v3 1/2] drm/xe/vf: Refactor CCS save/restore to use default migration context 2025-08-06 8:29 ` [PATCH v3 1/2] drm/xe/vf: Refactor CCS save/restore to use default migration context Satyanarayana K V P @ 2025-08-06 16:08 ` Summers, Stuart 2025-08-06 16:20 ` Matthew Brost 2025-08-06 18:50 ` John Harrison 1 sibling, 1 reply; 15+ messages in thread From: Summers, Stuart @ 2025-08-06 16:08 UTC (permalink / raw) To: intel-xe@lists.freedesktop.org, K V P, Satyanarayana Cc: Brost, Matthew, Wajdeczko, Michal On Wed, 2025-08-06 at 13:59 +0530, Satyanarayana K V P wrote: > Previously, CCS save/restore operations created separate migration > contexts with new VM memory allocations, resulting in significant > overhead. > > This commit eliminates redundant context creation reusing the default > migration context by registering new execution queues for CCS save > and > restore on the existing migrate VM. > > Signed-off-by: Satyanarayana K V P <satyanarayana.k.v.p@intel.com> > Suggested-by: Matthew Brost <matthew.brost@intel.com> > Cc: Michal Wajdeczko <michal.wajdeczko@intel.com> > > --- > V2 -> V3: > - Fixed review comments (Matthew Brost). > > V1 -> V2: > - Fixed kernel-doc issues reported by patchworks. > --- > drivers/gpu/drm/xe/xe_migrate.c | 18 ++++---- > drivers/gpu/drm/xe/xe_migrate.h | 2 +- > drivers/gpu/drm/xe/xe_pm.c | 3 ++ > drivers/gpu/drm/xe/xe_sriov_vf_ccs.c | 49 ++++++++++++-------- > -- > drivers/gpu/drm/xe/xe_sriov_vf_ccs_types.h | 6 +-- > 5 files changed, 43 insertions(+), 35 deletions(-) > > diff --git a/drivers/gpu/drm/xe/xe_migrate.c > b/drivers/gpu/drm/xe/xe_migrate.c > index 3a276e2348a2..7d3c7c4e2185 100644 > --- a/drivers/gpu/drm/xe/xe_migrate.c > +++ b/drivers/gpu/drm/xe/xe_migrate.c > @@ -960,14 +960,14 @@ struct xe_lrc *xe_migrate_lrc(struct xe_migrate > *migrate) > return migrate->q->lrc[0]; > } > > -static int emit_flush_invalidate(struct xe_migrate *m, u32 *dw, int > i, > +static int emit_flush_invalidate(struct xe_exec_queue *q, u32 *dw, > int i, > u32 flags) > { > dw[i++] = MI_FLUSH_DW | MI_INVALIDATE_TLB | > MI_FLUSH_DW_OP_STOREDW | > MI_FLUSH_IMM_DW | flags; > - dw[i++] = > lower_32_bits(xe_lrc_start_seqno_ggtt_addr(xe_migrate_lrc(m))) | > + dw[i++] = lower_32_bits(xe_lrc_start_seqno_ggtt_addr(q- > >lrc[0])) | > MI_FLUSH_DW_USE_GTT; > - dw[i++] = > upper_32_bits(xe_lrc_start_seqno_ggtt_addr(xe_migrate_lrc(m))); > + dw[i++] = upper_32_bits(xe_lrc_start_seqno_ggtt_addr(q- > >lrc[0])); > dw[i++] = MI_NOOP; > dw[i++] = MI_NOOP; > > @@ -976,7 +976,8 @@ static int emit_flush_invalidate(struct > xe_migrate *m, u32 *dw, int i, > > /** > * xe_migrate_ccs_rw_copy() - Copy content of TTM resources. > - * @m: The migration context. > + * @tile: Tile whose migration context to be used. > + * @q : Execution to be used along with migration context. > * @src_bo: The buffer object @src is currently bound to. > * @read_write : Creates BB commands for CCS read/write. > * > @@ -987,7 +988,7 @@ static int emit_flush_invalidate(struct > xe_migrate *m, u32 *dw, int i, > * > * Return: 0 if successful, negative error code on failure. > */ > -int xe_migrate_ccs_rw_copy(struct xe_migrate *m, > +int xe_migrate_ccs_rw_copy(struct xe_tile *tile, struct > xe_exec_queue *q, > struct xe_bo *src_bo, > enum xe_sriov_vf_ccs_rw_ctxs read_write) > > @@ -995,7 +996,8 @@ int xe_migrate_ccs_rw_copy(struct xe_migrate *m, > bool src_is_pltt = read_write == XE_SRIOV_VF_CCS_READ_CTX; > bool dst_is_pltt = read_write == XE_SRIOV_VF_CCS_WRITE_CTX; > struct ttm_resource *src = src_bo->ttm.resource; > - struct xe_gt *gt = m->tile->primary_gt; > + struct xe_migrate *m = tile->migrate; > + struct xe_gt *gt = tile->primary_gt; > u32 batch_size, batch_size_allocated; > struct xe_device *xe = gt_to_xe(gt); > struct xe_res_cursor src_it, ccs_it; > @@ -1078,11 +1080,11 @@ int xe_migrate_ccs_rw_copy(struct xe_migrate > *m, > > emit_pte(m, bb, ccs_pt, false, false, &ccs_it, > ccs_size, src); > > - bb->len = emit_flush_invalidate(m, bb->cs, bb->len, > flush_flags); > + bb->len = emit_flush_invalidate(q, bb->cs, bb->len, > flush_flags); > flush_flags = xe_migrate_ccs_copy(m, bb, src_L0_ofs, > src_is_pltt, > src_L0_ofs, > dst_is_pltt, > src_L0, ccs_ofs, > true); > - bb->len = emit_flush_invalidate(m, bb->cs, bb->len, > flush_flags); > + bb->len = emit_flush_invalidate(q, bb->cs, bb->len, > flush_flags); > > size -= src_L0; > } > diff --git a/drivers/gpu/drm/xe/xe_migrate.h > b/drivers/gpu/drm/xe/xe_migrate.h > index e81ea6b27fb5..9e20da6d58c2 100644 > --- a/drivers/gpu/drm/xe/xe_migrate.h > +++ b/drivers/gpu/drm/xe/xe_migrate.h > @@ -124,7 +124,7 @@ struct dma_fence *xe_migrate_copy(struct > xe_migrate *m, > struct ttm_resource *dst, > bool copy_only_ccs); > > -int xe_migrate_ccs_rw_copy(struct xe_migrate *m, > +int xe_migrate_ccs_rw_copy(struct xe_tile *tile, struct > xe_exec_queue *q, > struct xe_bo *src_bo, > enum xe_sriov_vf_ccs_rw_ctxs read_write); > > diff --git a/drivers/gpu/drm/xe/xe_pm.c b/drivers/gpu/drm/xe/xe_pm.c > index 44aaf154ddf7..5e8126ca8e27 100644 > --- a/drivers/gpu/drm/xe/xe_pm.c > +++ b/drivers/gpu/drm/xe/xe_pm.c > @@ -209,6 +209,9 @@ int xe_pm_resume(struct xe_device *xe) > > xe_pxp_pm_resume(xe->pxp); > > + if (IS_SRIOV_VF(xe)) > + xe_sriov_vf_ccs_register_context(xe); > + > drm_dbg(&xe->drm, "Device resumed\n"); > return 0; > err: > diff --git a/drivers/gpu/drm/xe/xe_sriov_vf_ccs.c > b/drivers/gpu/drm/xe/xe_sriov_vf_ccs.c > index f0ca2a9b2bb7..a87f39eae4dc 100644 > --- a/drivers/gpu/drm/xe/xe_sriov_vf_ccs.c > +++ b/drivers/gpu/drm/xe/xe_sriov_vf_ccs.c > @@ -8,6 +8,7 @@ > #include "xe_bb.h" > #include "xe_bo.h" > #include "xe_device.h" > +#include "xe_exec_queue.h" > #include "xe_exec_queue_types.h" > #include "xe_guc_submit.h" > #include "xe_lrc.h" > @@ -168,7 +169,7 @@ static int alloc_bb_pool(struct xe_tile *tile, > struct xe_tile_vf_ccs *ctx) > > static void ccs_rw_update_ring(struct xe_tile_vf_ccs *ctx) > { > - struct xe_lrc *lrc = xe_migrate_lrc(ctx->migrate); > + struct xe_lrc *lrc = ctx->q->lrc[0]; > u64 addr = xe_sa_manager_gpu_addr(ctx->mem.ccs_bb_pool); > u32 dw[10], i = 0; > > @@ -183,13 +184,12 @@ static void ccs_rw_update_ring(struct > xe_tile_vf_ccs *ctx) > xe_lrc_set_ring_tail(lrc, lrc->ring.tail); > } > > -static int register_save_restore_context(struct xe_migrate *m, > - enum xe_sriov_vf_ccs_rw_ctxs > ctx_id) > +static int register_save_restore_context(struct xe_tile_vf_ccs *ctx) > { > int err = -EINVAL; > int ctx_type; > > - switch (ctx_id) { > + switch (ctx->ctx_id) { > case XE_SRIOV_VF_CCS_READ_CTX: > ctx_type = GUC_CONTEXT_COMPRESSION_SAVE; > break; > @@ -200,7 +200,7 @@ static int register_save_restore_context(struct > xe_migrate *m, > return err; > } > > - xe_guc_register_exec_queue(xe_migrate_exec_queue(m), > ctx_type); > + xe_guc_register_exec_queue(ctx->q, ctx_type); > return 0; > } > > @@ -225,7 +225,7 @@ int xe_sriov_vf_ccs_register_context(struct > xe_device *xe) > > for_each_ccs_rw_ctx(ctx_id) { > ctx = &tile->sriov.vf.ccs[ctx_id]; > - err = register_save_restore_context(ctx->migrate, > ctx_id); > + err = register_save_restore_context(ctx); > if (err) > return err; > } > @@ -236,13 +236,14 @@ int xe_sriov_vf_ccs_register_context(struct > xe_device *xe) > static void xe_sriov_vf_ccs_fini(void *arg) > { > struct xe_tile_vf_ccs *ctx = arg; > - struct xe_lrc *lrc = xe_migrate_lrc(ctx->migrate); > + struct xe_lrc *lrc = ctx->q->lrc[0]; > > /* > * Make TAIL = HEAD in the ring so that no issues are seen if > Guc > * submits this context to HW on VF pause after unbinding > device. > */ > xe_lrc_set_ring_tail(lrc, xe_lrc_ring_head(lrc)); > + xe_exec_queue_put(ctx->q); > } > > /** > @@ -258,8 +259,9 @@ int xe_sriov_vf_ccs_init(struct xe_device *xe) > { > struct xe_tile *tile = xe_device_get_root_tile(xe); > enum xe_sriov_vf_ccs_rw_ctxs ctx_id; > - struct xe_migrate *migrate; > struct xe_tile_vf_ccs *ctx; > + struct xe_exec_queue *q; > + u32 flags; > int err; > > xe_assert(xe, IS_SRIOV_VF(xe)); > @@ -270,27 +272,25 @@ int xe_sriov_vf_ccs_init(struct xe_device *xe) > ctx = &tile->sriov.vf.ccs[ctx_id]; > ctx->ctx_id = ctx_id; > > - migrate = xe_migrate_alloc(tile); > - if (!migrate) { > - err = -ENOMEM; > + flags = EXEC_QUEUE_FLAG_KERNEL | > + EXEC_QUEUE_FLAG_PERMANENT | > + EXEC_QUEUE_FLAG_MIGRATE; When USM is supported, we also set EXEC_QUEUE_FLAG_HIGH_PRIORITY for the migration context. Is there a reason not to do that here? Otherwise the change makes sense to me. We still have a unique queue here, just not the VM creation per VF which I agree seems like a good idea. Thanks, Stuart > + q = xe_exec_queue_create_bind(xe, tile, flags, 0); > + if (IS_ERR(q)) { > + err = PTR_ERR(q); > goto err_ret; > } > - > - err = xe_migrate_init(migrate); > - if (err) > - goto err_ret; > - > - ctx->migrate = migrate; > + ctx->q = q; > > err = alloc_bb_pool(tile, ctx); > if (err) > - goto err_ret; > + goto err_free_queue; > > ccs_rw_update_ring(ctx); > > - err = register_save_restore_context(ctx->migrate, > ctx_id); > + err = register_save_restore_context(ctx); > if (err) > - goto err_ret; > + goto err_free_queue; > > err = devm_add_action_or_reset(xe->drm.dev, > xe_sriov_vf_ccs_fini, > @@ -301,6 +301,9 @@ int xe_sriov_vf_ccs_init(struct xe_device *xe) > > return 0; > > +err_free_queue: > + xe_exec_queue_put(q); > + > err_ret: > return err; > } > @@ -319,7 +322,7 @@ int xe_sriov_vf_ccs_attach_bo(struct xe_bo *bo) > { > struct xe_device *xe = xe_bo_device(bo); > enum xe_sriov_vf_ccs_rw_ctxs ctx_id; > - struct xe_migrate *migrate; > + struct xe_tile_vf_ccs *ctx; > struct xe_tile *tile; > struct xe_bb *bb; > int err = 0; > @@ -334,8 +337,8 @@ int xe_sriov_vf_ccs_attach_bo(struct xe_bo *bo) > /* bb should be NULL here. Assert if not NULL */ > xe_assert(xe, !bb); > > - migrate = tile->sriov.vf.ccs[ctx_id].migrate; > - err = xe_migrate_ccs_rw_copy(migrate, bo, ctx_id); > + ctx = &tile->sriov.vf.ccs[ctx_id]; > + err = xe_migrate_ccs_rw_copy(tile, ctx->q, bo, > ctx_id); > } > return err; > } > diff --git a/drivers/gpu/drm/xe/xe_sriov_vf_ccs_types.h > b/drivers/gpu/drm/xe/xe_sriov_vf_ccs_types.h > index e240f3fd18af..1add0541aed8 100644 > --- a/drivers/gpu/drm/xe/xe_sriov_vf_ccs_types.h > +++ b/drivers/gpu/drm/xe/xe_sriov_vf_ccs_types.h > @@ -41,11 +41,11 @@ struct xe_sa_manager; > struct xe_tile_vf_ccs { > /** @id: Id to which context it belongs to */ > enum xe_sriov_vf_ccs_rw_ctxs ctx_id; > - /** @migrate: Migration helper for save/restore of CCS data > */ > - struct xe_migrate *migrate; > + /** @q: exec queues used for migration */ > + struct xe_exec_queue *q; > > struct { > - /** @ccs_rw_bb_pool: Pool from which batch buffers > are allocated. */ > + /** @ccs_bb_pool: Pool from which batch buffers are > allocated. */ > struct xe_sa_manager *ccs_bb_pool; > } mem; > }; ^ permalink raw reply [flat|nested] 15+ messages in thread
* Re: [PATCH v3 1/2] drm/xe/vf: Refactor CCS save/restore to use default migration context 2025-08-06 16:08 ` Summers, Stuart @ 2025-08-06 16:20 ` Matthew Brost 2025-08-06 16:22 ` Summers, Stuart 0 siblings, 1 reply; 15+ messages in thread From: Matthew Brost @ 2025-08-06 16:20 UTC (permalink / raw) To: Summers, Stuart Cc: intel-xe@lists.freedesktop.org, K V P, Satyanarayana, Wajdeczko, Michal On Wed, Aug 06, 2025 at 10:08:01AM -0600, Summers, Stuart wrote: > On Wed, 2025-08-06 at 13:59 +0530, Satyanarayana K V P wrote: > > Previously, CCS save/restore operations created separate migration > > contexts with new VM memory allocations, resulting in significant > > overhead. > > > > This commit eliminates redundant context creation reusing the default > > migration context by registering new execution queues for CCS save > > and > > restore on the existing migrate VM. > > > > Signed-off-by: Satyanarayana K V P <satyanarayana.k.v.p@intel.com> > > Suggested-by: Matthew Brost <matthew.brost@intel.com> > > Cc: Michal Wajdeczko <michal.wajdeczko@intel.com> > > > > --- > > V2 -> V3: > > - Fixed review comments (Matthew Brost). > > > > V1 -> V2: > > - Fixed kernel-doc issues reported by patchworks. > > --- > > drivers/gpu/drm/xe/xe_migrate.c | 18 ++++---- > > drivers/gpu/drm/xe/xe_migrate.h | 2 +- > > drivers/gpu/drm/xe/xe_pm.c | 3 ++ > > drivers/gpu/drm/xe/xe_sriov_vf_ccs.c | 49 ++++++++++++-------- > > -- > > drivers/gpu/drm/xe/xe_sriov_vf_ccs_types.h | 6 +-- > > 5 files changed, 43 insertions(+), 35 deletions(-) > > > > diff --git a/drivers/gpu/drm/xe/xe_migrate.c > > b/drivers/gpu/drm/xe/xe_migrate.c > > index 3a276e2348a2..7d3c7c4e2185 100644 > > --- a/drivers/gpu/drm/xe/xe_migrate.c > > +++ b/drivers/gpu/drm/xe/xe_migrate.c > > @@ -960,14 +960,14 @@ struct xe_lrc *xe_migrate_lrc(struct xe_migrate > > *migrate) > > return migrate->q->lrc[0]; > > } > > > > -static int emit_flush_invalidate(struct xe_migrate *m, u32 *dw, int > > i, > > +static int emit_flush_invalidate(struct xe_exec_queue *q, u32 *dw, > > int i, > > u32 flags) > > { > > dw[i++] = MI_FLUSH_DW | MI_INVALIDATE_TLB | > > MI_FLUSH_DW_OP_STOREDW | > > MI_FLUSH_IMM_DW | flags; > > - dw[i++] = > > lower_32_bits(xe_lrc_start_seqno_ggtt_addr(xe_migrate_lrc(m))) | > > + dw[i++] = lower_32_bits(xe_lrc_start_seqno_ggtt_addr(q- > > >lrc[0])) | > > MI_FLUSH_DW_USE_GTT; > > - dw[i++] = > > upper_32_bits(xe_lrc_start_seqno_ggtt_addr(xe_migrate_lrc(m))); > > + dw[i++] = upper_32_bits(xe_lrc_start_seqno_ggtt_addr(q- > > >lrc[0])); > > dw[i++] = MI_NOOP; > > dw[i++] = MI_NOOP; > > > > @@ -976,7 +976,8 @@ static int emit_flush_invalidate(struct > > xe_migrate *m, u32 *dw, int i, > > > > /** > > * xe_migrate_ccs_rw_copy() - Copy content of TTM resources. > > - * @m: The migration context. > > + * @tile: Tile whose migration context to be used. > > + * @q : Execution to be used along with migration context. > > * @src_bo: The buffer object @src is currently bound to. > > * @read_write : Creates BB commands for CCS read/write. > > * > > @@ -987,7 +988,7 @@ static int emit_flush_invalidate(struct > > xe_migrate *m, u32 *dw, int i, > > * > > * Return: 0 if successful, negative error code on failure. > > */ > > -int xe_migrate_ccs_rw_copy(struct xe_migrate *m, > > +int xe_migrate_ccs_rw_copy(struct xe_tile *tile, struct > > xe_exec_queue *q, > > struct xe_bo *src_bo, > > enum xe_sriov_vf_ccs_rw_ctxs read_write) > > > > @@ -995,7 +996,8 @@ int xe_migrate_ccs_rw_copy(struct xe_migrate *m, > > bool src_is_pltt = read_write == XE_SRIOV_VF_CCS_READ_CTX; > > bool dst_is_pltt = read_write == XE_SRIOV_VF_CCS_WRITE_CTX; > > struct ttm_resource *src = src_bo->ttm.resource; > > - struct xe_gt *gt = m->tile->primary_gt; > > + struct xe_migrate *m = tile->migrate; > > + struct xe_gt *gt = tile->primary_gt; > > u32 batch_size, batch_size_allocated; > > struct xe_device *xe = gt_to_xe(gt); > > struct xe_res_cursor src_it, ccs_it; > > @@ -1078,11 +1080,11 @@ int xe_migrate_ccs_rw_copy(struct xe_migrate > > *m, > > > > emit_pte(m, bb, ccs_pt, false, false, &ccs_it, > > ccs_size, src); > > > > - bb->len = emit_flush_invalidate(m, bb->cs, bb->len, > > flush_flags); > > + bb->len = emit_flush_invalidate(q, bb->cs, bb->len, > > flush_flags); > > flush_flags = xe_migrate_ccs_copy(m, bb, src_L0_ofs, > > src_is_pltt, > > src_L0_ofs, > > dst_is_pltt, > > src_L0, ccs_ofs, > > true); > > - bb->len = emit_flush_invalidate(m, bb->cs, bb->len, > > flush_flags); > > + bb->len = emit_flush_invalidate(q, bb->cs, bb->len, > > flush_flags); > > > > size -= src_L0; > > } > > diff --git a/drivers/gpu/drm/xe/xe_migrate.h > > b/drivers/gpu/drm/xe/xe_migrate.h > > index e81ea6b27fb5..9e20da6d58c2 100644 > > --- a/drivers/gpu/drm/xe/xe_migrate.h > > +++ b/drivers/gpu/drm/xe/xe_migrate.h > > @@ -124,7 +124,7 @@ struct dma_fence *xe_migrate_copy(struct > > xe_migrate *m, > > struct ttm_resource *dst, > > bool copy_only_ccs); > > > > -int xe_migrate_ccs_rw_copy(struct xe_migrate *m, > > +int xe_migrate_ccs_rw_copy(struct xe_tile *tile, struct > > xe_exec_queue *q, > > struct xe_bo *src_bo, > > enum xe_sriov_vf_ccs_rw_ctxs read_write); > > > > diff --git a/drivers/gpu/drm/xe/xe_pm.c b/drivers/gpu/drm/xe/xe_pm.c > > index 44aaf154ddf7..5e8126ca8e27 100644 > > --- a/drivers/gpu/drm/xe/xe_pm.c > > +++ b/drivers/gpu/drm/xe/xe_pm.c > > @@ -209,6 +209,9 @@ int xe_pm_resume(struct xe_device *xe) > > > > xe_pxp_pm_resume(xe->pxp); > > > > + if (IS_SRIOV_VF(xe)) > > + xe_sriov_vf_ccs_register_context(xe); > > + > > drm_dbg(&xe->drm, "Device resumed\n"); > > return 0; > > err: > > diff --git a/drivers/gpu/drm/xe/xe_sriov_vf_ccs.c > > b/drivers/gpu/drm/xe/xe_sriov_vf_ccs.c > > index f0ca2a9b2bb7..a87f39eae4dc 100644 > > --- a/drivers/gpu/drm/xe/xe_sriov_vf_ccs.c > > +++ b/drivers/gpu/drm/xe/xe_sriov_vf_ccs.c > > @@ -8,6 +8,7 @@ > > #include "xe_bb.h" > > #include "xe_bo.h" > > #include "xe_device.h" > > +#include "xe_exec_queue.h" > > #include "xe_exec_queue_types.h" > > #include "xe_guc_submit.h" > > #include "xe_lrc.h" > > @@ -168,7 +169,7 @@ static int alloc_bb_pool(struct xe_tile *tile, > > struct xe_tile_vf_ccs *ctx) > > > > static void ccs_rw_update_ring(struct xe_tile_vf_ccs *ctx) > > { > > - struct xe_lrc *lrc = xe_migrate_lrc(ctx->migrate); > > + struct xe_lrc *lrc = ctx->q->lrc[0]; > > u64 addr = xe_sa_manager_gpu_addr(ctx->mem.ccs_bb_pool); > > u32 dw[10], i = 0; > > > > @@ -183,13 +184,12 @@ static void ccs_rw_update_ring(struct > > xe_tile_vf_ccs *ctx) > > xe_lrc_set_ring_tail(lrc, lrc->ring.tail); > > } > > > > -static int register_save_restore_context(struct xe_migrate *m, > > - enum xe_sriov_vf_ccs_rw_ctxs > > ctx_id) > > +static int register_save_restore_context(struct xe_tile_vf_ccs *ctx) > > { > > int err = -EINVAL; > > int ctx_type; > > > > - switch (ctx_id) { > > + switch (ctx->ctx_id) { > > case XE_SRIOV_VF_CCS_READ_CTX: > > ctx_type = GUC_CONTEXT_COMPRESSION_SAVE; > > break; > > @@ -200,7 +200,7 @@ static int register_save_restore_context(struct > > xe_migrate *m, > > return err; > > } > > > > - xe_guc_register_exec_queue(xe_migrate_exec_queue(m), > > ctx_type); > > + xe_guc_register_exec_queue(ctx->q, ctx_type); > > return 0; > > } > > > > @@ -225,7 +225,7 @@ int xe_sriov_vf_ccs_register_context(struct > > xe_device *xe) > > > > for_each_ccs_rw_ctx(ctx_id) { > > ctx = &tile->sriov.vf.ccs[ctx_id]; > > - err = register_save_restore_context(ctx->migrate, > > ctx_id); > > + err = register_save_restore_context(ctx); > > if (err) > > return err; > > } > > @@ -236,13 +236,14 @@ int xe_sriov_vf_ccs_register_context(struct > > xe_device *xe) > > static void xe_sriov_vf_ccs_fini(void *arg) > > { > > struct xe_tile_vf_ccs *ctx = arg; > > - struct xe_lrc *lrc = xe_migrate_lrc(ctx->migrate); > > + struct xe_lrc *lrc = ctx->q->lrc[0]; > > > > /* > > * Make TAIL = HEAD in the ring so that no issues are seen if > > Guc > > * submits this context to HW on VF pause after unbinding > > device. > > */ > > xe_lrc_set_ring_tail(lrc, xe_lrc_ring_head(lrc)); > > + xe_exec_queue_put(ctx->q); > > } > > > > /** > > @@ -258,8 +259,9 @@ int xe_sriov_vf_ccs_init(struct xe_device *xe) > > { > > struct xe_tile *tile = xe_device_get_root_tile(xe); > > enum xe_sriov_vf_ccs_rw_ctxs ctx_id; > > - struct xe_migrate *migrate; > > struct xe_tile_vf_ccs *ctx; > > + struct xe_exec_queue *q; > > + u32 flags; > > int err; > > > > xe_assert(xe, IS_SRIOV_VF(xe)); > > @@ -270,27 +272,25 @@ int xe_sriov_vf_ccs_init(struct xe_device *xe) > > ctx = &tile->sriov.vf.ccs[ctx_id]; > > ctx->ctx_id = ctx_id; > > > > - migrate = xe_migrate_alloc(tile); > > - if (!migrate) { > > - err = -ENOMEM; > > + flags = EXEC_QUEUE_FLAG_KERNEL | > > + EXEC_QUEUE_FLAG_PERMANENT | > > + EXEC_QUEUE_FLAG_MIGRATE; > > When USM is supported, we also set EXEC_QUEUE_FLAG_HIGH_PRIORITY for > the migration context. Is there a reason not to do that here? > I don't think EXEC_QUEUE_FLAG_HIGH_PRIORITY applies here as this is a special queue that is only run upon VF save / restore, so I don't think it would be subject to normal scheduling polices and also it should have exclusive execution when it runs, at least within a VF. > Otherwise the change makes sense to me. We still have a unique queue > here, just not the VM creation per VF which I agree seems like a good > idea. > I agree this patch LGTM: Reviewed-by: Matthew Brost <matthew.brost@intel.com> > Thanks, > Stuart > > > + q = xe_exec_queue_create_bind(xe, tile, flags, 0); > > + if (IS_ERR(q)) { > > + err = PTR_ERR(q); > > goto err_ret; > > } > > - > > - err = xe_migrate_init(migrate); > > - if (err) > > - goto err_ret; > > - > > - ctx->migrate = migrate; > > + ctx->q = q; > > > > err = alloc_bb_pool(tile, ctx); > > if (err) > > - goto err_ret; > > + goto err_free_queue; > > > > ccs_rw_update_ring(ctx); > > > > - err = register_save_restore_context(ctx->migrate, > > ctx_id); > > + err = register_save_restore_context(ctx); > > if (err) > > - goto err_ret; > > + goto err_free_queue; > > > > err = devm_add_action_or_reset(xe->drm.dev, > > xe_sriov_vf_ccs_fini, > > @@ -301,6 +301,9 @@ int xe_sriov_vf_ccs_init(struct xe_device *xe) > > > > return 0; > > > > +err_free_queue: > > + xe_exec_queue_put(q); > > + > > err_ret: > > return err; > > } > > @@ -319,7 +322,7 @@ int xe_sriov_vf_ccs_attach_bo(struct xe_bo *bo) > > { > > struct xe_device *xe = xe_bo_device(bo); > > enum xe_sriov_vf_ccs_rw_ctxs ctx_id; > > - struct xe_migrate *migrate; > > + struct xe_tile_vf_ccs *ctx; > > struct xe_tile *tile; > > struct xe_bb *bb; > > int err = 0; > > @@ -334,8 +337,8 @@ int xe_sriov_vf_ccs_attach_bo(struct xe_bo *bo) > > /* bb should be NULL here. Assert if not NULL */ > > xe_assert(xe, !bb); > > > > - migrate = tile->sriov.vf.ccs[ctx_id].migrate; > > - err = xe_migrate_ccs_rw_copy(migrate, bo, ctx_id); > > + ctx = &tile->sriov.vf.ccs[ctx_id]; > > + err = xe_migrate_ccs_rw_copy(tile, ctx->q, bo, > > ctx_id); > > } > > return err; > > } > > diff --git a/drivers/gpu/drm/xe/xe_sriov_vf_ccs_types.h > > b/drivers/gpu/drm/xe/xe_sriov_vf_ccs_types.h > > index e240f3fd18af..1add0541aed8 100644 > > --- a/drivers/gpu/drm/xe/xe_sriov_vf_ccs_types.h > > +++ b/drivers/gpu/drm/xe/xe_sriov_vf_ccs_types.h > > @@ -41,11 +41,11 @@ struct xe_sa_manager; > > struct xe_tile_vf_ccs { > > /** @id: Id to which context it belongs to */ > > enum xe_sriov_vf_ccs_rw_ctxs ctx_id; > > - /** @migrate: Migration helper for save/restore of CCS data > > */ > > - struct xe_migrate *migrate; > > + /** @q: exec queues used for migration */ > > + struct xe_exec_queue *q; > > > > struct { > > - /** @ccs_rw_bb_pool: Pool from which batch buffers > > are allocated. */ > > + /** @ccs_bb_pool: Pool from which batch buffers are > > allocated. */ > > struct xe_sa_manager *ccs_bb_pool; > > } mem; > > }; > ^ permalink raw reply [flat|nested] 15+ messages in thread
* Re: [PATCH v3 1/2] drm/xe/vf: Refactor CCS save/restore to use default migration context 2025-08-06 16:20 ` Matthew Brost @ 2025-08-06 16:22 ` Summers, Stuart 0 siblings, 0 replies; 15+ messages in thread From: Summers, Stuart @ 2025-08-06 16:22 UTC (permalink / raw) To: Brost, Matthew Cc: intel-xe@lists.freedesktop.org, K V P, Satyanarayana, Wajdeczko, Michal On Wed, 2025-08-06 at 09:20 -0700, Matthew Brost wrote: > On Wed, Aug 06, 2025 at 10:08:01AM -0600, Summers, Stuart wrote: > > On Wed, 2025-08-06 at 13:59 +0530, Satyanarayana K V P wrote: > > > Previously, CCS save/restore operations created separate > > > migration > > > contexts with new VM memory allocations, resulting in significant > > > overhead. > > > > > > This commit eliminates redundant context creation reusing the > > > default > > > migration context by registering new execution queues for CCS > > > save > > > and > > > restore on the existing migrate VM. > > > > > > Signed-off-by: Satyanarayana K V P > > > <satyanarayana.k.v.p@intel.com> > > > Suggested-by: Matthew Brost <matthew.brost@intel.com> > > > Cc: Michal Wajdeczko <michal.wajdeczko@intel.com> > > > > > > --- > > > V2 -> V3: > > > - Fixed review comments (Matthew Brost). > > > > > > V1 -> V2: > > > - Fixed kernel-doc issues reported by patchworks. > > > --- > > > drivers/gpu/drm/xe/xe_migrate.c | 18 ++++---- > > > drivers/gpu/drm/xe/xe_migrate.h | 2 +- > > > drivers/gpu/drm/xe/xe_pm.c | 3 ++ > > > drivers/gpu/drm/xe/xe_sriov_vf_ccs.c | 49 ++++++++++++---- > > > ---- > > > -- > > > drivers/gpu/drm/xe/xe_sriov_vf_ccs_types.h | 6 +-- > > > 5 files changed, 43 insertions(+), 35 deletions(-) > > > > > > diff --git a/drivers/gpu/drm/xe/xe_migrate.c > > > b/drivers/gpu/drm/xe/xe_migrate.c > > > index 3a276e2348a2..7d3c7c4e2185 100644 > > > --- a/drivers/gpu/drm/xe/xe_migrate.c > > > +++ b/drivers/gpu/drm/xe/xe_migrate.c > > > @@ -960,14 +960,14 @@ struct xe_lrc *xe_migrate_lrc(struct > > > xe_migrate > > > *migrate) > > > return migrate->q->lrc[0]; > > > } > > > > > > -static int emit_flush_invalidate(struct xe_migrate *m, u32 *dw, > > > int > > > i, > > > +static int emit_flush_invalidate(struct xe_exec_queue *q, u32 > > > *dw, > > > int i, > > > u32 flags) > > > { > > > dw[i++] = MI_FLUSH_DW | MI_INVALIDATE_TLB | > > > MI_FLUSH_DW_OP_STOREDW | > > > MI_FLUSH_IMM_DW | flags; > > > - dw[i++] = > > > lower_32_bits(xe_lrc_start_seqno_ggtt_addr(xe_migrate_lrc(m))) | > > > + dw[i++] = lower_32_bits(xe_lrc_start_seqno_ggtt_addr(q- > > > > lrc[0])) | > > > MI_FLUSH_DW_USE_GTT; > > > - dw[i++] = > > > upper_32_bits(xe_lrc_start_seqno_ggtt_addr(xe_migrate_lrc(m))); > > > + dw[i++] = upper_32_bits(xe_lrc_start_seqno_ggtt_addr(q- > > > > lrc[0])); > > > dw[i++] = MI_NOOP; > > > dw[i++] = MI_NOOP; > > > > > > @@ -976,7 +976,8 @@ static int emit_flush_invalidate(struct > > > xe_migrate *m, u32 *dw, int i, > > > > > > /** > > > * xe_migrate_ccs_rw_copy() - Copy content of TTM resources. > > > - * @m: The migration context. > > > + * @tile: Tile whose migration context to be used. > > > + * @q : Execution to be used along with migration context. > > > * @src_bo: The buffer object @src is currently bound to. > > > * @read_write : Creates BB commands for CCS read/write. > > > * > > > @@ -987,7 +988,7 @@ static int emit_flush_invalidate(struct > > > xe_migrate *m, u32 *dw, int i, > > > * > > > * Return: 0 if successful, negative error code on failure. > > > */ > > > -int xe_migrate_ccs_rw_copy(struct xe_migrate *m, > > > +int xe_migrate_ccs_rw_copy(struct xe_tile *tile, struct > > > xe_exec_queue *q, > > > struct xe_bo *src_bo, > > > enum xe_sriov_vf_ccs_rw_ctxs > > > read_write) > > > > > > @@ -995,7 +996,8 @@ int xe_migrate_ccs_rw_copy(struct xe_migrate > > > *m, > > > bool src_is_pltt = read_write == > > > XE_SRIOV_VF_CCS_READ_CTX; > > > bool dst_is_pltt = read_write == > > > XE_SRIOV_VF_CCS_WRITE_CTX; > > > struct ttm_resource *src = src_bo->ttm.resource; > > > - struct xe_gt *gt = m->tile->primary_gt; > > > + struct xe_migrate *m = tile->migrate; > > > + struct xe_gt *gt = tile->primary_gt; > > > u32 batch_size, batch_size_allocated; > > > struct xe_device *xe = gt_to_xe(gt); > > > struct xe_res_cursor src_it, ccs_it; > > > @@ -1078,11 +1080,11 @@ int xe_migrate_ccs_rw_copy(struct > > > xe_migrate > > > *m, > > > > > > emit_pte(m, bb, ccs_pt, false, false, &ccs_it, > > > ccs_size, src); > > > > > > - bb->len = emit_flush_invalidate(m, bb->cs, bb- > > > >len, > > > flush_flags); > > > + bb->len = emit_flush_invalidate(q, bb->cs, bb- > > > >len, > > > flush_flags); > > > flush_flags = xe_migrate_ccs_copy(m, bb, > > > src_L0_ofs, > > > src_is_pltt, > > > src_L0_ofs, > > > dst_is_pltt, > > > src_L0, > > > ccs_ofs, > > > true); > > > - bb->len = emit_flush_invalidate(m, bb->cs, bb- > > > >len, > > > flush_flags); > > > + bb->len = emit_flush_invalidate(q, bb->cs, bb- > > > >len, > > > flush_flags); > > > > > > size -= src_L0; > > > } > > > diff --git a/drivers/gpu/drm/xe/xe_migrate.h > > > b/drivers/gpu/drm/xe/xe_migrate.h > > > index e81ea6b27fb5..9e20da6d58c2 100644 > > > --- a/drivers/gpu/drm/xe/xe_migrate.h > > > +++ b/drivers/gpu/drm/xe/xe_migrate.h > > > @@ -124,7 +124,7 @@ struct dma_fence *xe_migrate_copy(struct > > > xe_migrate *m, > > > struct ttm_resource *dst, > > > bool copy_only_ccs); > > > > > > -int xe_migrate_ccs_rw_copy(struct xe_migrate *m, > > > +int xe_migrate_ccs_rw_copy(struct xe_tile *tile, struct > > > xe_exec_queue *q, > > > struct xe_bo *src_bo, > > > enum xe_sriov_vf_ccs_rw_ctxs > > > read_write); > > > > > > diff --git a/drivers/gpu/drm/xe/xe_pm.c > > > b/drivers/gpu/drm/xe/xe_pm.c > > > index 44aaf154ddf7..5e8126ca8e27 100644 > > > --- a/drivers/gpu/drm/xe/xe_pm.c > > > +++ b/drivers/gpu/drm/xe/xe_pm.c > > > @@ -209,6 +209,9 @@ int xe_pm_resume(struct xe_device *xe) > > > > > > xe_pxp_pm_resume(xe->pxp); > > > > > > + if (IS_SRIOV_VF(xe)) > > > + xe_sriov_vf_ccs_register_context(xe); > > > + > > > drm_dbg(&xe->drm, "Device resumed\n"); > > > return 0; > > > err: > > > diff --git a/drivers/gpu/drm/xe/xe_sriov_vf_ccs.c > > > b/drivers/gpu/drm/xe/xe_sriov_vf_ccs.c > > > index f0ca2a9b2bb7..a87f39eae4dc 100644 > > > --- a/drivers/gpu/drm/xe/xe_sriov_vf_ccs.c > > > +++ b/drivers/gpu/drm/xe/xe_sriov_vf_ccs.c > > > @@ -8,6 +8,7 @@ > > > #include "xe_bb.h" > > > #include "xe_bo.h" > > > #include "xe_device.h" > > > +#include "xe_exec_queue.h" > > > #include "xe_exec_queue_types.h" > > > #include "xe_guc_submit.h" > > > #include "xe_lrc.h" > > > @@ -168,7 +169,7 @@ static int alloc_bb_pool(struct xe_tile > > > *tile, > > > struct xe_tile_vf_ccs *ctx) > > > > > > static void ccs_rw_update_ring(struct xe_tile_vf_ccs *ctx) > > > { > > > - struct xe_lrc *lrc = xe_migrate_lrc(ctx->migrate); > > > + struct xe_lrc *lrc = ctx->q->lrc[0]; > > > u64 addr = xe_sa_manager_gpu_addr(ctx->mem.ccs_bb_pool); > > > u32 dw[10], i = 0; > > > > > > @@ -183,13 +184,12 @@ static void ccs_rw_update_ring(struct > > > xe_tile_vf_ccs *ctx) > > > xe_lrc_set_ring_tail(lrc, lrc->ring.tail); > > > } > > > > > > -static int register_save_restore_context(struct xe_migrate *m, > > > - enum > > > xe_sriov_vf_ccs_rw_ctxs > > > ctx_id) > > > +static int register_save_restore_context(struct xe_tile_vf_ccs > > > *ctx) > > > { > > > int err = -EINVAL; > > > int ctx_type; > > > > > > - switch (ctx_id) { > > > + switch (ctx->ctx_id) { > > > case XE_SRIOV_VF_CCS_READ_CTX: > > > ctx_type = GUC_CONTEXT_COMPRESSION_SAVE; > > > break; > > > @@ -200,7 +200,7 @@ static int > > > register_save_restore_context(struct > > > xe_migrate *m, > > > return err; > > > } > > > > > > - xe_guc_register_exec_queue(xe_migrate_exec_queue(m), > > > ctx_type); > > > + xe_guc_register_exec_queue(ctx->q, ctx_type); > > > return 0; > > > } > > > > > > @@ -225,7 +225,7 @@ int xe_sriov_vf_ccs_register_context(struct > > > xe_device *xe) > > > > > > for_each_ccs_rw_ctx(ctx_id) { > > > ctx = &tile->sriov.vf.ccs[ctx_id]; > > > - err = register_save_restore_context(ctx->migrate, > > > ctx_id); > > > + err = register_save_restore_context(ctx); > > > if (err) > > > return err; > > > } > > > @@ -236,13 +236,14 @@ int xe_sriov_vf_ccs_register_context(struct > > > xe_device *xe) > > > static void xe_sriov_vf_ccs_fini(void *arg) > > > { > > > struct xe_tile_vf_ccs *ctx = arg; > > > - struct xe_lrc *lrc = xe_migrate_lrc(ctx->migrate); > > > + struct xe_lrc *lrc = ctx->q->lrc[0]; > > > > > > /* > > > * Make TAIL = HEAD in the ring so that no issues are > > > seen if > > > Guc > > > * submits this context to HW on VF pause after unbinding > > > device. > > > */ > > > xe_lrc_set_ring_tail(lrc, xe_lrc_ring_head(lrc)); > > > + xe_exec_queue_put(ctx->q); > > > } > > > > > > /** > > > @@ -258,8 +259,9 @@ int xe_sriov_vf_ccs_init(struct xe_device > > > *xe) > > > { > > > struct xe_tile *tile = xe_device_get_root_tile(xe); > > > enum xe_sriov_vf_ccs_rw_ctxs ctx_id; > > > - struct xe_migrate *migrate; > > > struct xe_tile_vf_ccs *ctx; > > > + struct xe_exec_queue *q; > > > + u32 flags; > > > int err; > > > > > > xe_assert(xe, IS_SRIOV_VF(xe)); > > > @@ -270,27 +272,25 @@ int xe_sriov_vf_ccs_init(struct xe_device > > > *xe) > > > ctx = &tile->sriov.vf.ccs[ctx_id]; > > > ctx->ctx_id = ctx_id; > > > > > > - migrate = xe_migrate_alloc(tile); > > > - if (!migrate) { > > > - err = -ENOMEM; > > > + flags = EXEC_QUEUE_FLAG_KERNEL | > > > + EXEC_QUEUE_FLAG_PERMANENT | > > > + EXEC_QUEUE_FLAG_MIGRATE; > > > > When USM is supported, we also set EXEC_QUEUE_FLAG_HIGH_PRIORITY > > for > > the migration context. Is there a reason not to do that here? > > > > I don't think EXEC_QUEUE_FLAG_HIGH_PRIORITY applies here as this is a > special queue that is only run upon VF save / restore, so I don't > think > it would be subject to normal scheduling polices and also it should > have > exclusive execution when it runs, at least within a VF. Thanks Matt yeah makes sense to me too. Reviewed-by: Stuart Summers <stuart.summers@intel.com> > > > Otherwise the change makes sense to me. We still have a unique > > queue > > here, just not the VM creation per VF which I agree seems like a > > good > > idea. > > > > I agree this patch LGTM: > Reviewed-by: Matthew Brost <matthew.brost@intel.com> > > > Thanks, > > Stuart > > > > > + q = xe_exec_queue_create_bind(xe, tile, flags, > > > 0); > > > + if (IS_ERR(q)) { > > > + err = PTR_ERR(q); > > > goto err_ret; > > > } > > > - > > > - err = xe_migrate_init(migrate); > > > - if (err) > > > - goto err_ret; > > > - > > > - ctx->migrate = migrate; > > > + ctx->q = q; > > > > > > err = alloc_bb_pool(tile, ctx); > > > if (err) > > > - goto err_ret; > > > + goto err_free_queue; > > > > > > ccs_rw_update_ring(ctx); > > > > > > - err = register_save_restore_context(ctx->migrate, > > > ctx_id); > > > + err = register_save_restore_context(ctx); > > > if (err) > > > - goto err_ret; > > > + goto err_free_queue; > > > > > > err = devm_add_action_or_reset(xe->drm.dev, > > > > > > xe_sriov_vf_ccs_fini, > > > @@ -301,6 +301,9 @@ int xe_sriov_vf_ccs_init(struct xe_device > > > *xe) > > > > > > return 0; > > > > > > +err_free_queue: > > > + xe_exec_queue_put(q); > > > + > > > err_ret: > > > return err; > > > } > > > @@ -319,7 +322,7 @@ int xe_sriov_vf_ccs_attach_bo(struct xe_bo > > > *bo) > > > { > > > struct xe_device *xe = xe_bo_device(bo); > > > enum xe_sriov_vf_ccs_rw_ctxs ctx_id; > > > - struct xe_migrate *migrate; > > > + struct xe_tile_vf_ccs *ctx; > > > struct xe_tile *tile; > > > struct xe_bb *bb; > > > int err = 0; > > > @@ -334,8 +337,8 @@ int xe_sriov_vf_ccs_attach_bo(struct xe_bo > > > *bo) > > > /* bb should be NULL here. Assert if not NULL */ > > > xe_assert(xe, !bb); > > > > > > - migrate = tile->sriov.vf.ccs[ctx_id].migrate; > > > - err = xe_migrate_ccs_rw_copy(migrate, bo, > > > ctx_id); > > > + ctx = &tile->sriov.vf.ccs[ctx_id]; > > > + err = xe_migrate_ccs_rw_copy(tile, ctx->q, bo, > > > ctx_id); > > > } > > > return err; > > > } > > > diff --git a/drivers/gpu/drm/xe/xe_sriov_vf_ccs_types.h > > > b/drivers/gpu/drm/xe/xe_sriov_vf_ccs_types.h > > > index e240f3fd18af..1add0541aed8 100644 > > > --- a/drivers/gpu/drm/xe/xe_sriov_vf_ccs_types.h > > > +++ b/drivers/gpu/drm/xe/xe_sriov_vf_ccs_types.h > > > @@ -41,11 +41,11 @@ struct xe_sa_manager; > > > struct xe_tile_vf_ccs { > > > /** @id: Id to which context it belongs to */ > > > enum xe_sriov_vf_ccs_rw_ctxs ctx_id; > > > - /** @migrate: Migration helper for save/restore of CCS > > > data > > > */ > > > - struct xe_migrate *migrate; > > > + /** @q: exec queues used for migration */ > > > + struct xe_exec_queue *q; > > > > > > struct { > > > - /** @ccs_rw_bb_pool: Pool from which batch > > > buffers > > > are allocated. */ > > > + /** @ccs_bb_pool: Pool from which batch buffers > > > are > > > allocated. */ > > > struct xe_sa_manager *ccs_bb_pool; > > > } mem; > > > }; > > ^ permalink raw reply [flat|nested] 15+ messages in thread
* Re: [PATCH v3 1/2] drm/xe/vf: Refactor CCS save/restore to use default migration context 2025-08-06 8:29 ` [PATCH v3 1/2] drm/xe/vf: Refactor CCS save/restore to use default migration context Satyanarayana K V P 2025-08-06 16:08 ` Summers, Stuart @ 2025-08-06 18:50 ` John Harrison 2025-08-07 11:15 ` K V P, Satyanarayana 1 sibling, 1 reply; 15+ messages in thread From: John Harrison @ 2025-08-06 18:50 UTC (permalink / raw) To: Satyanarayana K V P, intel-xe; +Cc: Matthew Brost, Michal Wajdeczko On 8/6/2025 1:29 AM, Satyanarayana K V P wrote: > Previously, CCS save/restore operations created separate migration > contexts with new VM memory allocations, resulting in significant > overhead. > > This commit eliminates redundant context creation reusing the default > migration context by registering new execution queues for CCS save and > restore on the existing migrate VM. > > Signed-off-by: Satyanarayana K V P <satyanarayana.k.v.p@intel.com> > Suggested-by: Matthew Brost <matthew.brost@intel.com> > Cc: Michal Wajdeczko <michal.wajdeczko@intel.com> > > --- > V2 -> V3: > - Fixed review comments (Matthew Brost). > > V1 -> V2: > - Fixed kernel-doc issues reported by patchworks. > --- > drivers/gpu/drm/xe/xe_migrate.c | 18 ++++---- > drivers/gpu/drm/xe/xe_migrate.h | 2 +- > drivers/gpu/drm/xe/xe_pm.c | 3 ++ > drivers/gpu/drm/xe/xe_sriov_vf_ccs.c | 49 ++++++++++++---------- > drivers/gpu/drm/xe/xe_sriov_vf_ccs_types.h | 6 +-- > 5 files changed, 43 insertions(+), 35 deletions(-) > > diff --git a/drivers/gpu/drm/xe/xe_migrate.c b/drivers/gpu/drm/xe/xe_migrate.c > index 3a276e2348a2..7d3c7c4e2185 100644 > --- a/drivers/gpu/drm/xe/xe_migrate.c > +++ b/drivers/gpu/drm/xe/xe_migrate.c > @@ -960,14 +960,14 @@ struct xe_lrc *xe_migrate_lrc(struct xe_migrate *migrate) > return migrate->q->lrc[0]; > } > > -static int emit_flush_invalidate(struct xe_migrate *m, u32 *dw, int i, > +static int emit_flush_invalidate(struct xe_exec_queue *q, u32 *dw, int i, > u32 flags) > { > dw[i++] = MI_FLUSH_DW | MI_INVALIDATE_TLB | MI_FLUSH_DW_OP_STOREDW | > MI_FLUSH_IMM_DW | flags; > - dw[i++] = lower_32_bits(xe_lrc_start_seqno_ggtt_addr(xe_migrate_lrc(m))) | > + dw[i++] = lower_32_bits(xe_lrc_start_seqno_ggtt_addr(q->lrc[0])) | > MI_FLUSH_DW_USE_GTT; > - dw[i++] = upper_32_bits(xe_lrc_start_seqno_ggtt_addr(xe_migrate_lrc(m))); > + dw[i++] = upper_32_bits(xe_lrc_start_seqno_ggtt_addr(q->lrc[0])); Is it worth keeping a helper function here to abstract out future changes? E.g. "xe_migrate_lrc(ctx) { return ctx->q->lrc[0] };". Using "q->lrc[0]" everywhere seems very like magic number usage. It is not obvious why that is correct given the very generic naming. > dw[i++] = MI_NOOP; > dw[i++] = MI_NOOP; > > @@ -976,7 +976,8 @@ static int emit_flush_invalidate(struct xe_migrate *m, u32 *dw, int i, > > /** > * xe_migrate_ccs_rw_copy() - Copy content of TTM resources. > - * @m: The migration context. > + * @tile: Tile whose migration context to be used. > + * @q : Execution to be used along with migration context. > * @src_bo: The buffer object @src is currently bound to. > * @read_write : Creates BB commands for CCS read/write. > * > @@ -987,7 +988,7 @@ static int emit_flush_invalidate(struct xe_migrate *m, u32 *dw, int i, > * > * Return: 0 if successful, negative error code on failure. > */ > -int xe_migrate_ccs_rw_copy(struct xe_migrate *m, > +int xe_migrate_ccs_rw_copy(struct xe_tile *tile, struct xe_exec_queue *q, > struct xe_bo *src_bo, > enum xe_sriov_vf_ccs_rw_ctxs read_write) > > @@ -995,7 +996,8 @@ int xe_migrate_ccs_rw_copy(struct xe_migrate *m, > bool src_is_pltt = read_write == XE_SRIOV_VF_CCS_READ_CTX; > bool dst_is_pltt = read_write == XE_SRIOV_VF_CCS_WRITE_CTX; > struct ttm_resource *src = src_bo->ttm.resource; > - struct xe_gt *gt = m->tile->primary_gt; > + struct xe_migrate *m = tile->migrate; > + struct xe_gt *gt = tile->primary_gt; > u32 batch_size, batch_size_allocated; > struct xe_device *xe = gt_to_xe(gt); > struct xe_res_cursor src_it, ccs_it; > @@ -1078,11 +1080,11 @@ int xe_migrate_ccs_rw_copy(struct xe_migrate *m, > > emit_pte(m, bb, ccs_pt, false, false, &ccs_it, ccs_size, src); > > - bb->len = emit_flush_invalidate(m, bb->cs, bb->len, flush_flags); > + bb->len = emit_flush_invalidate(q, bb->cs, bb->len, flush_flags); > flush_flags = xe_migrate_ccs_copy(m, bb, src_L0_ofs, src_is_pltt, > src_L0_ofs, dst_is_pltt, > src_L0, ccs_ofs, true); > - bb->len = emit_flush_invalidate(m, bb->cs, bb->len, flush_flags); > + bb->len = emit_flush_invalidate(q, bb->cs, bb->len, flush_flags); > > size -= src_L0; > } > diff --git a/drivers/gpu/drm/xe/xe_migrate.h b/drivers/gpu/drm/xe/xe_migrate.h > index e81ea6b27fb5..9e20da6d58c2 100644 > --- a/drivers/gpu/drm/xe/xe_migrate.h > +++ b/drivers/gpu/drm/xe/xe_migrate.h > @@ -124,7 +124,7 @@ struct dma_fence *xe_migrate_copy(struct xe_migrate *m, > struct ttm_resource *dst, > bool copy_only_ccs); > > -int xe_migrate_ccs_rw_copy(struct xe_migrate *m, > +int xe_migrate_ccs_rw_copy(struct xe_tile *tile, struct xe_exec_queue *q, > struct xe_bo *src_bo, > enum xe_sriov_vf_ccs_rw_ctxs read_write); > > diff --git a/drivers/gpu/drm/xe/xe_pm.c b/drivers/gpu/drm/xe/xe_pm.c > index 44aaf154ddf7..5e8126ca8e27 100644 > --- a/drivers/gpu/drm/xe/xe_pm.c > +++ b/drivers/gpu/drm/xe/xe_pm.c > @@ -209,6 +209,9 @@ int xe_pm_resume(struct xe_device *xe) > > xe_pxp_pm_resume(xe->pxp); > > + if (IS_SRIOV_VF(xe)) > + xe_sriov_vf_ccs_register_context(xe); > + > drm_dbg(&xe->drm, "Device resumed\n"); > return 0; > err: > diff --git a/drivers/gpu/drm/xe/xe_sriov_vf_ccs.c b/drivers/gpu/drm/xe/xe_sriov_vf_ccs.c > index f0ca2a9b2bb7..a87f39eae4dc 100644 > --- a/drivers/gpu/drm/xe/xe_sriov_vf_ccs.c > +++ b/drivers/gpu/drm/xe/xe_sriov_vf_ccs.c > @@ -8,6 +8,7 @@ > #include "xe_bb.h" > #include "xe_bo.h" > #include "xe_device.h" > +#include "xe_exec_queue.h" > #include "xe_exec_queue_types.h" > #include "xe_guc_submit.h" > #include "xe_lrc.h" > @@ -168,7 +169,7 @@ static int alloc_bb_pool(struct xe_tile *tile, struct xe_tile_vf_ccs *ctx) > > static void ccs_rw_update_ring(struct xe_tile_vf_ccs *ctx) > { > - struct xe_lrc *lrc = xe_migrate_lrc(ctx->migrate); > + struct xe_lrc *lrc = ctx->q->lrc[0]; > u64 addr = xe_sa_manager_gpu_addr(ctx->mem.ccs_bb_pool); > u32 dw[10], i = 0; > > @@ -183,13 +184,12 @@ static void ccs_rw_update_ring(struct xe_tile_vf_ccs *ctx) > xe_lrc_set_ring_tail(lrc, lrc->ring.tail); > } > > -static int register_save_restore_context(struct xe_migrate *m, > - enum xe_sriov_vf_ccs_rw_ctxs ctx_id) > +static int register_save_restore_context(struct xe_tile_vf_ccs *ctx) > { > int err = -EINVAL; > int ctx_type; > > - switch (ctx_id) { > + switch (ctx->ctx_id) { > case XE_SRIOV_VF_CCS_READ_CTX: > ctx_type = GUC_CONTEXT_COMPRESSION_SAVE; > break; > @@ -200,7 +200,7 @@ static int register_save_restore_context(struct xe_migrate *m, > return err; > } > > - xe_guc_register_exec_queue(xe_migrate_exec_queue(m), ctx_type); > + xe_guc_register_exec_queue(ctx->q, ctx_type); > return 0; > } > > @@ -225,7 +225,7 @@ int xe_sriov_vf_ccs_register_context(struct xe_device *xe) > > for_each_ccs_rw_ctx(ctx_id) { > ctx = &tile->sriov.vf.ccs[ctx_id]; > - err = register_save_restore_context(ctx->migrate, ctx_id); > + err = register_save_restore_context(ctx); > if (err) > return err; > } > @@ -236,13 +236,14 @@ int xe_sriov_vf_ccs_register_context(struct xe_device *xe) > static void xe_sriov_vf_ccs_fini(void *arg) > { > struct xe_tile_vf_ccs *ctx = arg; > - struct xe_lrc *lrc = xe_migrate_lrc(ctx->migrate); > + struct xe_lrc *lrc = ctx->q->lrc[0]; > > /* > * Make TAIL = HEAD in the ring so that no issues are seen if Guc > * submits this context to HW on VF pause after unbinding device. > */ > xe_lrc_set_ring_tail(lrc, xe_lrc_ring_head(lrc)); > + xe_exec_queue_put(ctx->q); > } > > /** > @@ -258,8 +259,9 @@ int xe_sriov_vf_ccs_init(struct xe_device *xe) > { > struct xe_tile *tile = xe_device_get_root_tile(xe); > enum xe_sriov_vf_ccs_rw_ctxs ctx_id; > - struct xe_migrate *migrate; > struct xe_tile_vf_ccs *ctx; > + struct xe_exec_queue *q; > + u32 flags; > int err; > > xe_assert(xe, IS_SRIOV_VF(xe)); > @@ -270,27 +272,25 @@ int xe_sriov_vf_ccs_init(struct xe_device *xe) > ctx = &tile->sriov.vf.ccs[ctx_id]; > ctx->ctx_id = ctx_id; > > - migrate = xe_migrate_alloc(tile); > - if (!migrate) { > - err = -ENOMEM; > + flags = EXEC_QUEUE_FLAG_KERNEL | > + EXEC_QUEUE_FLAG_PERMANENT | > + EXEC_QUEUE_FLAG_MIGRATE; > + q = xe_exec_queue_create_bind(xe, tile, flags, 0); > + if (IS_ERR(q)) { > + err = PTR_ERR(q); > goto err_ret; > } > - > - err = xe_migrate_init(migrate); > - if (err) > - goto err_ret; > - > - ctx->migrate = migrate; > + ctx->q = q; > > err = alloc_bb_pool(tile, ctx); > if (err) > - goto err_ret; > + goto err_free_queue; > > ccs_rw_update_ring(ctx); > > - err = register_save_restore_context(ctx->migrate, ctx_id); > + err = register_save_restore_context(ctx); > if (err) > - goto err_ret; > + goto err_free_queue; > > err = devm_add_action_or_reset(xe->drm.dev, > xe_sriov_vf_ccs_fini, > @@ -301,6 +301,9 @@ int xe_sriov_vf_ccs_init(struct xe_device *xe) > > return 0; > > +err_free_queue: > + xe_exec_queue_put(q); > + > err_ret: > return err; > } > @@ -319,7 +322,7 @@ int xe_sriov_vf_ccs_attach_bo(struct xe_bo *bo) > { > struct xe_device *xe = xe_bo_device(bo); > enum xe_sriov_vf_ccs_rw_ctxs ctx_id; > - struct xe_migrate *migrate; > + struct xe_tile_vf_ccs *ctx; > struct xe_tile *tile; > struct xe_bb *bb; > int err = 0; > @@ -334,8 +337,8 @@ int xe_sriov_vf_ccs_attach_bo(struct xe_bo *bo) > /* bb should be NULL here. Assert if not NULL */ > xe_assert(xe, !bb); > > - migrate = tile->sriov.vf.ccs[ctx_id].migrate; > - err = xe_migrate_ccs_rw_copy(migrate, bo, ctx_id); > + ctx = &tile->sriov.vf.ccs[ctx_id]; > + err = xe_migrate_ccs_rw_copy(tile, ctx->q, bo, ctx_id); > } > return err; > } > diff --git a/drivers/gpu/drm/xe/xe_sriov_vf_ccs_types.h b/drivers/gpu/drm/xe/xe_sriov_vf_ccs_types.h > index e240f3fd18af..1add0541aed8 100644 > --- a/drivers/gpu/drm/xe/xe_sriov_vf_ccs_types.h > +++ b/drivers/gpu/drm/xe/xe_sriov_vf_ccs_types.h > @@ -41,11 +41,11 @@ struct xe_sa_manager; > struct xe_tile_vf_ccs { > /** @id: Id to which context it belongs to */ > enum xe_sriov_vf_ccs_rw_ctxs ctx_id; > - /** @migrate: Migration helper for save/restore of CCS data */ > - struct xe_migrate *migrate; > + /** @q: exec queues used for migration */ > + struct xe_exec_queue *q; Should this be 'migrate_q' or some such to identify what its purpose is? Just calling it 'q' is very generic and open to use by other things (accidentally or deliberately). John. > > struct { > - /** @ccs_rw_bb_pool: Pool from which batch buffers are allocated. */ > + /** @ccs_bb_pool: Pool from which batch buffers are allocated. */ > struct xe_sa_manager *ccs_bb_pool; > } mem; > }; ^ permalink raw reply [flat|nested] 15+ messages in thread
* Re: [PATCH v3 1/2] drm/xe/vf: Refactor CCS save/restore to use default migration context 2025-08-06 18:50 ` John Harrison @ 2025-08-07 11:15 ` K V P, Satyanarayana 0 siblings, 0 replies; 15+ messages in thread From: K V P, Satyanarayana @ 2025-08-07 11:15 UTC (permalink / raw) To: John Harrison, intel-xe; +Cc: Matthew Brost, Michal Wajdeczko On 07-08-2025 00:20, John Harrison wrote: > On 8/6/2025 1:29 AM, Satyanarayana K V P wrote: >> Previously, CCS save/restore operations created separate migration >> contexts with new VM memory allocations, resulting in significant >> overhead. >> >> This commit eliminates redundant context creation reusing the default >> migration context by registering new execution queues for CCS save and >> restore on the existing migrate VM. >> >> Signed-off-by: Satyanarayana K V P <satyanarayana.k.v.p@intel.com> >> Suggested-by: Matthew Brost <matthew.brost@intel.com> >> Cc: Michal Wajdeczko <michal.wajdeczko@intel.com> >> >> --- >> V2 -> V3: >> - Fixed review comments (Matthew Brost). >> >> V1 -> V2: >> - Fixed kernel-doc issues reported by patchworks. >> --- >> drivers/gpu/drm/xe/xe_migrate.c | 18 ++++---- >> drivers/gpu/drm/xe/xe_migrate.h | 2 +- >> drivers/gpu/drm/xe/xe_pm.c | 3 ++ >> drivers/gpu/drm/xe/xe_sriov_vf_ccs.c | 49 ++++++++++++---------- >> drivers/gpu/drm/xe/xe_sriov_vf_ccs_types.h | 6 +-- >> 5 files changed, 43 insertions(+), 35 deletions(-) >> >> diff --git a/drivers/gpu/drm/xe/xe_migrate.c b/drivers/gpu/drm/xe/ >> xe_migrate.c >> index 3a276e2348a2..7d3c7c4e2185 100644 >> --- a/drivers/gpu/drm/xe/xe_migrate.c >> +++ b/drivers/gpu/drm/xe/xe_migrate.c >> @@ -960,14 +960,14 @@ struct xe_lrc *xe_migrate_lrc(struct xe_migrate >> *migrate) >> return migrate->q->lrc[0]; >> } >> -static int emit_flush_invalidate(struct xe_migrate *m, u32 *dw, int i, >> +static int emit_flush_invalidate(struct xe_exec_queue *q, u32 *dw, >> int i, >> u32 flags) >> { >> dw[i++] = MI_FLUSH_DW | MI_INVALIDATE_TLB | >> MI_FLUSH_DW_OP_STOREDW | >> MI_FLUSH_IMM_DW | flags; >> - dw[i++] = >> lower_32_bits(xe_lrc_start_seqno_ggtt_addr(xe_migrate_lrc(m))) | >> + dw[i++] = lower_32_bits(xe_lrc_start_seqno_ggtt_addr(q->lrc[0])) | >> MI_FLUSH_DW_USE_GTT; >> - dw[i++] = >> upper_32_bits(xe_lrc_start_seqno_ggtt_addr(xe_migrate_lrc(m))); >> + dw[i++] = upper_32_bits(xe_lrc_start_seqno_ggtt_addr(q->lrc[0])); > Is it worth keeping a helper function here to abstract out future > changes? E.g. "xe_migrate_lrc(ctx) { return ctx->q->lrc[0] };". Using > "q->lrc[0]" everywhere seems very like magic number usage. It is not > obvious why that is correct given the very generic naming. > > Fixed and sent new version.>> dw[i++] = MI_NOOP; >> dw[i++] = MI_NOOP; >> @@ -976,7 +976,8 @@ static int emit_flush_invalidate(struct xe_migrate >> *m, u32 *dw, int i, >> /** >> * xe_migrate_ccs_rw_copy() - Copy content of TTM resources. >> - * @m: The migration context. >> + * @tile: Tile whose migration context to be used. >> + * @q : Execution to be used along with migration context. >> * @src_bo: The buffer object @src is currently bound to. >> * @read_write : Creates BB commands for CCS read/write. >> * >> @@ -987,7 +988,7 @@ static int emit_flush_invalidate(struct xe_migrate >> *m, u32 *dw, int i, >> * >> * Return: 0 if successful, negative error code on failure. >> */ >> -int xe_migrate_ccs_rw_copy(struct xe_migrate *m, >> +int xe_migrate_ccs_rw_copy(struct xe_tile *tile, struct xe_exec_queue >> *q, >> struct xe_bo *src_bo, >> enum xe_sriov_vf_ccs_rw_ctxs read_write) >> @@ -995,7 +996,8 @@ int xe_migrate_ccs_rw_copy(struct xe_migrate *m, >> bool src_is_pltt = read_write == XE_SRIOV_VF_CCS_READ_CTX; >> bool dst_is_pltt = read_write == XE_SRIOV_VF_CCS_WRITE_CTX; >> struct ttm_resource *src = src_bo->ttm.resource; >> - struct xe_gt *gt = m->tile->primary_gt; >> + struct xe_migrate *m = tile->migrate; >> + struct xe_gt *gt = tile->primary_gt; >> u32 batch_size, batch_size_allocated; >> struct xe_device *xe = gt_to_xe(gt); >> struct xe_res_cursor src_it, ccs_it; >> @@ -1078,11 +1080,11 @@ int xe_migrate_ccs_rw_copy(struct xe_migrate *m, >> emit_pte(m, bb, ccs_pt, false, false, &ccs_it, ccs_size, src); >> - bb->len = emit_flush_invalidate(m, bb->cs, bb->len, >> flush_flags); >> + bb->len = emit_flush_invalidate(q, bb->cs, bb->len, >> flush_flags); >> flush_flags = xe_migrate_ccs_copy(m, bb, src_L0_ofs, >> src_is_pltt, >> src_L0_ofs, dst_is_pltt, >> src_L0, ccs_ofs, true); >> - bb->len = emit_flush_invalidate(m, bb->cs, bb->len, >> flush_flags); >> + bb->len = emit_flush_invalidate(q, bb->cs, bb->len, >> flush_flags); >> size -= src_L0; >> } >> diff --git a/drivers/gpu/drm/xe/xe_migrate.h b/drivers/gpu/drm/xe/ >> xe_migrate.h >> index e81ea6b27fb5..9e20da6d58c2 100644 >> --- a/drivers/gpu/drm/xe/xe_migrate.h >> +++ b/drivers/gpu/drm/xe/xe_migrate.h >> @@ -124,7 +124,7 @@ struct dma_fence *xe_migrate_copy(struct >> xe_migrate *m, >> struct ttm_resource *dst, >> bool copy_only_ccs); >> -int xe_migrate_ccs_rw_copy(struct xe_migrate *m, >> +int xe_migrate_ccs_rw_copy(struct xe_tile *tile, struct xe_exec_queue >> *q, >> struct xe_bo *src_bo, >> enum xe_sriov_vf_ccs_rw_ctxs read_write); >> diff --git a/drivers/gpu/drm/xe/xe_pm.c b/drivers/gpu/drm/xe/xe_pm.c >> index 44aaf154ddf7..5e8126ca8e27 100644 >> --- a/drivers/gpu/drm/xe/xe_pm.c >> +++ b/drivers/gpu/drm/xe/xe_pm.c >> @@ -209,6 +209,9 @@ int xe_pm_resume(struct xe_device *xe) >> xe_pxp_pm_resume(xe->pxp); >> + if (IS_SRIOV_VF(xe)) >> + xe_sriov_vf_ccs_register_context(xe); >> + >> drm_dbg(&xe->drm, "Device resumed\n"); >> return 0; >> err: >> diff --git a/drivers/gpu/drm/xe/xe_sriov_vf_ccs.c b/drivers/gpu/drm/ >> xe/xe_sriov_vf_ccs.c >> index f0ca2a9b2bb7..a87f39eae4dc 100644 >> --- a/drivers/gpu/drm/xe/xe_sriov_vf_ccs.c >> +++ b/drivers/gpu/drm/xe/xe_sriov_vf_ccs.c >> @@ -8,6 +8,7 @@ >> #include "xe_bb.h" >> #include "xe_bo.h" >> #include "xe_device.h" >> +#include "xe_exec_queue.h" >> #include "xe_exec_queue_types.h" >> #include "xe_guc_submit.h" >> #include "xe_lrc.h" >> @@ -168,7 +169,7 @@ static int alloc_bb_pool(struct xe_tile *tile, >> struct xe_tile_vf_ccs *ctx) >> static void ccs_rw_update_ring(struct xe_tile_vf_ccs *ctx) >> { >> - struct xe_lrc *lrc = xe_migrate_lrc(ctx->migrate); >> + struct xe_lrc *lrc = ctx->q->lrc[0]; >> u64 addr = xe_sa_manager_gpu_addr(ctx->mem.ccs_bb_pool); >> u32 dw[10], i = 0; >> @@ -183,13 +184,12 @@ static void ccs_rw_update_ring(struct >> xe_tile_vf_ccs *ctx) >> xe_lrc_set_ring_tail(lrc, lrc->ring.tail); >> } >> -static int register_save_restore_context(struct xe_migrate *m, >> - enum xe_sriov_vf_ccs_rw_ctxs ctx_id) >> +static int register_save_restore_context(struct xe_tile_vf_ccs *ctx) >> { >> int err = -EINVAL; >> int ctx_type; >> - switch (ctx_id) { >> + switch (ctx->ctx_id) { >> case XE_SRIOV_VF_CCS_READ_CTX: >> ctx_type = GUC_CONTEXT_COMPRESSION_SAVE; >> break; >> @@ -200,7 +200,7 @@ static int register_save_restore_context(struct >> xe_migrate *m, >> return err; >> } >> - xe_guc_register_exec_queue(xe_migrate_exec_queue(m), ctx_type); >> + xe_guc_register_exec_queue(ctx->q, ctx_type); >> return 0; >> } >> @@ -225,7 +225,7 @@ int xe_sriov_vf_ccs_register_context(struct >> xe_device *xe) >> for_each_ccs_rw_ctx(ctx_id) { >> ctx = &tile->sriov.vf.ccs[ctx_id]; >> - err = register_save_restore_context(ctx->migrate, ctx_id); >> + err = register_save_restore_context(ctx); >> if (err) >> return err; >> } >> @@ -236,13 +236,14 @@ int xe_sriov_vf_ccs_register_context(struct >> xe_device *xe) >> static void xe_sriov_vf_ccs_fini(void *arg) >> { >> struct xe_tile_vf_ccs *ctx = arg; >> - struct xe_lrc *lrc = xe_migrate_lrc(ctx->migrate); >> + struct xe_lrc *lrc = ctx->q->lrc[0]; >> /* >> * Make TAIL = HEAD in the ring so that no issues are seen if Guc >> * submits this context to HW on VF pause after unbinding device. >> */ >> xe_lrc_set_ring_tail(lrc, xe_lrc_ring_head(lrc)); >> + xe_exec_queue_put(ctx->q); >> } >> /** >> @@ -258,8 +259,9 @@ int xe_sriov_vf_ccs_init(struct xe_device *xe) >> { >> struct xe_tile *tile = xe_device_get_root_tile(xe); >> enum xe_sriov_vf_ccs_rw_ctxs ctx_id; >> - struct xe_migrate *migrate; >> struct xe_tile_vf_ccs *ctx; >> + struct xe_exec_queue *q; >> + u32 flags; >> int err; >> xe_assert(xe, IS_SRIOV_VF(xe)); >> @@ -270,27 +272,25 @@ int xe_sriov_vf_ccs_init(struct xe_device *xe) >> ctx = &tile->sriov.vf.ccs[ctx_id]; >> ctx->ctx_id = ctx_id; >> - migrate = xe_migrate_alloc(tile); >> - if (!migrate) { >> - err = -ENOMEM; >> + flags = EXEC_QUEUE_FLAG_KERNEL | >> + EXEC_QUEUE_FLAG_PERMANENT | >> + EXEC_QUEUE_FLAG_MIGRATE; >> + q = xe_exec_queue_create_bind(xe, tile, flags, 0); >> + if (IS_ERR(q)) { >> + err = PTR_ERR(q); >> goto err_ret; >> } >> - >> - err = xe_migrate_init(migrate); >> - if (err) >> - goto err_ret; >> - >> - ctx->migrate = migrate; >> + ctx->q = q; >> err = alloc_bb_pool(tile, ctx); >> if (err) >> - goto err_ret; >> + goto err_free_queue; >> ccs_rw_update_ring(ctx); >> - err = register_save_restore_context(ctx->migrate, ctx_id); >> + err = register_save_restore_context(ctx); >> if (err) >> - goto err_ret; >> + goto err_free_queue; >> err = devm_add_action_or_reset(xe->drm.dev, >> xe_sriov_vf_ccs_fini, >> @@ -301,6 +301,9 @@ int xe_sriov_vf_ccs_init(struct xe_device *xe) >> return 0; >> +err_free_queue: >> + xe_exec_queue_put(q); >> + >> err_ret: >> return err; >> } >> @@ -319,7 +322,7 @@ int xe_sriov_vf_ccs_attach_bo(struct xe_bo *bo) >> { >> struct xe_device *xe = xe_bo_device(bo); >> enum xe_sriov_vf_ccs_rw_ctxs ctx_id; >> - struct xe_migrate *migrate; >> + struct xe_tile_vf_ccs *ctx; >> struct xe_tile *tile; >> struct xe_bb *bb; >> int err = 0; >> @@ -334,8 +337,8 @@ int xe_sriov_vf_ccs_attach_bo(struct xe_bo *bo) >> /* bb should be NULL here. Assert if not NULL */ >> xe_assert(xe, !bb); >> - migrate = tile->sriov.vf.ccs[ctx_id].migrate; >> - err = xe_migrate_ccs_rw_copy(migrate, bo, ctx_id); >> + ctx = &tile->sriov.vf.ccs[ctx_id]; >> + err = xe_migrate_ccs_rw_copy(tile, ctx->q, bo, ctx_id); >> } >> return err; >> } >> diff --git a/drivers/gpu/drm/xe/xe_sriov_vf_ccs_types.h b/drivers/gpu/ >> drm/xe/xe_sriov_vf_ccs_types.h >> index e240f3fd18af..1add0541aed8 100644 >> --- a/drivers/gpu/drm/xe/xe_sriov_vf_ccs_types.h >> +++ b/drivers/gpu/drm/xe/xe_sriov_vf_ccs_types.h >> @@ -41,11 +41,11 @@ struct xe_sa_manager; >> struct xe_tile_vf_ccs { >> /** @id: Id to which context it belongs to */ >> enum xe_sriov_vf_ccs_rw_ctxs ctx_id; >> - /** @migrate: Migration helper for save/restore of CCS data */ >> - struct xe_migrate *migrate; >> + /** @q: exec queues used for migration */ >> + struct xe_exec_queue *q; > Should this be 'migrate_q' or some such to identify what its purpose is? > Just calling it 'q' is very generic and open to use by other things > (accidentally or deliberately). > > John. Fixed and sent new version.> >> struct { >> - /** @ccs_rw_bb_pool: Pool from which batch buffers are >> allocated. */ >> + /** @ccs_bb_pool: Pool from which batch buffers are >> allocated. */ >> struct xe_sa_manager *ccs_bb_pool; >> } mem; >> }; > ^ permalink raw reply [flat|nested] 15+ messages in thread
* [PATCH v3 2/2] drm/xe/guc: Scale mmio send/recv timeout for CCS save/restore with smem size 2025-08-06 8:29 [PATCH v3 0/2] Improve CCS save restore series Satyanarayana K V P 2025-08-06 8:19 ` ✓ CI.KUnit: success for Improve CCS save restore series (rev3) Patchwork 2025-08-06 8:29 ` [PATCH v3 1/2] drm/xe/vf: Refactor CCS save/restore to use default migration context Satyanarayana K V P @ 2025-08-06 8:29 ` Satyanarayana K V P 2025-08-06 16:28 ` Matthew Brost 2025-08-06 9:21 ` ✓ Xe.CI.BAT: success for Improve CCS save restore series (rev3) Patchwork 2025-08-06 10:23 ` ✓ Xe.CI.Full: " Patchwork 4 siblings, 1 reply; 15+ messages in thread From: Satyanarayana K V P @ 2025-08-06 8:29 UTC (permalink / raw) To: intel-xe; +Cc: Satyanarayana K V P, John Harrison, Matthew Brost After VF migration, GUC restores CCS metadata scaled to system memory size. The default timeout (50ms) is calibrated for 4GB memory capacity per specification. Timeouts for other memory sizes are proportionally derived from this baseline. This ensures adequate restoration time for CCS metadata across different hardware configurations while maintaining spec compliance. Signed-off-by: Satyanarayana K V P <satyanarayana.k.v.p@intel.com> Cc: John Harrison <John.C.Harrison@Intel.com> Cc: Matthew Brost <matthew.brost@intel.com> --- drivers/gpu/drm/xe/xe_guc.c | 33 ++++++++++++++++++++++++++++++++- 1 file changed, 32 insertions(+), 1 deletion(-) diff --git a/drivers/gpu/drm/xe/xe_guc.c b/drivers/gpu/drm/xe/xe_guc.c index 9e34401e4489..d836ded83491 100644 --- a/drivers/gpu/drm/xe/xe_guc.c +++ b/drivers/gpu/drm/xe/xe_guc.c @@ -10,6 +10,7 @@ #include <generated/xe_wa_oob.h> #include "abi/guc_actions_abi.h" +#include "abi/guc_actions_sriov_abi.h" #include "abi/guc_errors_abi.h" #include "regs/xe_gt_regs.h" #include "regs/xe_gtt_defs.h" @@ -1397,6 +1398,36 @@ int xe_guc_auth_huc(struct xe_guc *guc, u32 rsa_addr) return xe_guc_ct_send_block(&guc->ct, action, ARRAY_SIZE(action)); } +/* + * After VF migration, GUC restores CCS metadata scaled to system memory size. + * Default timeout (50ms) is calibrated for 4GB memory capacity per + * specification. Timeouts for other memory sizes are proportionally derived + * from this baseline. + */ +static u32 guc_mmio_send_recv_timeout(struct xe_guc *guc, const u32 *request) +{ + struct xe_device *xe = guc_to_xe(guc); + u32 timeout = 50000; + u32 action, factor; + struct sysinfo si; + u64 sys_mem_size; + + action = FIELD_GET(GUC_HXG_REQUEST_MSG_0_ACTION, request[0]); + if (action != GUC_ACTION_VF2GUC_NOTIFY_RESFIX_DONE || IS_DGFX(xe) || + !xe_device_has_flat_ccs(xe)) + return timeout; + + si_meminfo(&si); + sys_mem_size = si.totalram * si.mem_unit; + + if (sys_mem_size <= SZ_4G) + return timeout; + + factor = (sys_mem_size + SZ_4G) / SZ_4G; + timeout *= factor; + + return timeout; +} int xe_guc_mmio_send_recv(struct xe_guc *guc, const u32 *request, u32 len, u32 *response_buf) { @@ -1439,7 +1470,7 @@ int xe_guc_mmio_send_recv(struct xe_guc *guc, const u32 *request, ret = xe_mmio_wait32(mmio, reply_reg, GUC_HXG_MSG_0_ORIGIN, FIELD_PREP(GUC_HXG_MSG_0_ORIGIN, GUC_HXG_ORIGIN_GUC), - 50000, &reply, false); + guc_mmio_send_recv_timeout(guc, request), &reply, false); if (ret) { /* scratch registers might be cleared during FLR, try once more */ if (!reply && !lost) { -- 2.43.0 ^ permalink raw reply related [flat|nested] 15+ messages in thread
* Re: [PATCH v3 2/2] drm/xe/guc: Scale mmio send/recv timeout for CCS save/restore with smem size 2025-08-06 8:29 ` [PATCH v3 2/2] drm/xe/guc: Scale mmio send/recv timeout for CCS save/restore with smem size Satyanarayana K V P @ 2025-08-06 16:28 ` Matthew Brost 2025-08-06 19:57 ` John Harrison 0 siblings, 1 reply; 15+ messages in thread From: Matthew Brost @ 2025-08-06 16:28 UTC (permalink / raw) To: Satyanarayana K V P; +Cc: intel-xe, John Harrison On Wed, Aug 06, 2025 at 01:59:10PM +0530, Satyanarayana K V P wrote: > After VF migration, GUC restores CCS metadata scaled to system memory size. > The default timeout (50ms) is calibrated for 4GB memory capacity per > specification. Timeouts for other memory sizes are proportionally derived > from this baseline. > > This ensures adequate restoration time for CCS metadata across > different hardware configurations while maintaining spec compliance. > > Signed-off-by: Satyanarayana K V P <satyanarayana.k.v.p@intel.com> > Cc: John Harrison <John.C.Harrison@Intel.com> > Cc: Matthew Brost <matthew.brost@intel.com> > --- > drivers/gpu/drm/xe/xe_guc.c | 33 ++++++++++++++++++++++++++++++++- > 1 file changed, 32 insertions(+), 1 deletion(-) > > diff --git a/drivers/gpu/drm/xe/xe_guc.c b/drivers/gpu/drm/xe/xe_guc.c > index 9e34401e4489..d836ded83491 100644 > --- a/drivers/gpu/drm/xe/xe_guc.c > +++ b/drivers/gpu/drm/xe/xe_guc.c > @@ -10,6 +10,7 @@ > #include <generated/xe_wa_oob.h> > > #include "abi/guc_actions_abi.h" > +#include "abi/guc_actions_sriov_abi.h" > #include "abi/guc_errors_abi.h" > #include "regs/xe_gt_regs.h" > #include "regs/xe_gtt_defs.h" > @@ -1397,6 +1398,36 @@ int xe_guc_auth_huc(struct xe_guc *guc, u32 rsa_addr) > return xe_guc_ct_send_block(&guc->ct, action, ARRAY_SIZE(action)); > } > > +/* > + * After VF migration, GUC restores CCS metadata scaled to system memory size. > + * Default timeout (50ms) is calibrated for 4GB memory capacity per > + * specification. Timeouts for other memory sizes are proportionally derived > + * from this baseline. > + */ > +static u32 guc_mmio_send_recv_timeout(struct xe_guc *guc, const u32 *request) > +{ > + struct xe_device *xe = guc_to_xe(guc); > + u32 timeout = 50000; Is this really the upper bound? It seems like if could be signicantly higher if multiple VFs are trying to do things all at the same time. Scaling the timeout itself, does make sense though. Matt > + u32 action, factor; > + struct sysinfo si; > + u64 sys_mem_size; > + > + action = FIELD_GET(GUC_HXG_REQUEST_MSG_0_ACTION, request[0]); > + if (action != GUC_ACTION_VF2GUC_NOTIFY_RESFIX_DONE || IS_DGFX(xe) || > + !xe_device_has_flat_ccs(xe)) > + return timeout; > + > + si_meminfo(&si); > + sys_mem_size = si.totalram * si.mem_unit; > + > + if (sys_mem_size <= SZ_4G) > + return timeout; > + > + factor = (sys_mem_size + SZ_4G) / SZ_4G; > + timeout *= factor; > + > + return timeout; > +} > int xe_guc_mmio_send_recv(struct xe_guc *guc, const u32 *request, > u32 len, u32 *response_buf) > { > @@ -1439,7 +1470,7 @@ int xe_guc_mmio_send_recv(struct xe_guc *guc, const u32 *request, > > ret = xe_mmio_wait32(mmio, reply_reg, GUC_HXG_MSG_0_ORIGIN, > FIELD_PREP(GUC_HXG_MSG_0_ORIGIN, GUC_HXG_ORIGIN_GUC), > - 50000, &reply, false); > + guc_mmio_send_recv_timeout(guc, request), &reply, false); > if (ret) { > /* scratch registers might be cleared during FLR, try once more */ > if (!reply && !lost) { > -- > 2.43.0 > ^ permalink raw reply [flat|nested] 15+ messages in thread
* Re: [PATCH v3 2/2] drm/xe/guc: Scale mmio send/recv timeout for CCS save/restore with smem size 2025-08-06 16:28 ` Matthew Brost @ 2025-08-06 19:57 ` John Harrison 2025-08-06 23:01 ` Matthew Brost 2025-08-07 6:22 ` K V P, Satyanarayana 0 siblings, 2 replies; 15+ messages in thread From: John Harrison @ 2025-08-06 19:57 UTC (permalink / raw) To: Matthew Brost, Satyanarayana K V P; +Cc: intel-xe On 8/6/2025 9:28 AM, Matthew Brost wrote: > On Wed, Aug 06, 2025 at 01:59:10PM +0530, Satyanarayana K V P wrote: >> After VF migration, GUC restores CCS metadata scaled to system memory size. >> The default timeout (50ms) is calibrated for 4GB memory capacity per >> specification. Timeouts for other memory sizes are proportionally derived >> from this baseline. >> >> This ensures adequate restoration time for CCS metadata across >> different hardware configurations while maintaining spec compliance. >> >> Signed-off-by: Satyanarayana K V P <satyanarayana.k.v.p@intel.com> >> Cc: John Harrison <John.C.Harrison@Intel.com> >> Cc: Matthew Brost <matthew.brost@intel.com> >> --- >> drivers/gpu/drm/xe/xe_guc.c | 33 ++++++++++++++++++++++++++++++++- >> 1 file changed, 32 insertions(+), 1 deletion(-) >> >> diff --git a/drivers/gpu/drm/xe/xe_guc.c b/drivers/gpu/drm/xe/xe_guc.c >> index 9e34401e4489..d836ded83491 100644 >> --- a/drivers/gpu/drm/xe/xe_guc.c >> +++ b/drivers/gpu/drm/xe/xe_guc.c >> @@ -10,6 +10,7 @@ >> #include <generated/xe_wa_oob.h> >> >> #include "abi/guc_actions_abi.h" >> +#include "abi/guc_actions_sriov_abi.h" >> #include "abi/guc_errors_abi.h" >> #include "regs/xe_gt_regs.h" >> #include "regs/xe_gtt_defs.h" >> @@ -1397,6 +1398,36 @@ int xe_guc_auth_huc(struct xe_guc *guc, u32 rsa_addr) >> return xe_guc_ct_send_block(&guc->ct, action, ARRAY_SIZE(action)); >> } >> >> +/* >> + * After VF migration, GUC restores CCS metadata scaled to system memory size. >> + * Default timeout (50ms) is calibrated for 4GB memory capacity per >> + * specification. Timeouts for other memory sizes are proportionally derived >> + * from this baseline. >> + */ >> +static u32 guc_mmio_send_recv_timeout(struct xe_guc *guc, const u32 *request) >> +{ >> + struct xe_device *xe = guc_to_xe(guc); >> + u32 timeout = 50000; > Is this really the upper bound? It seems like if could be signicantly > higher if multiple VFs are trying to do things all at the same time. That is really a problem with the wait function itself rather than the timeout. The timeout is meant to be the maximum expectation for how long the operation will take once started. Unfortunately, we currently have no checks on whether GuC has actually read the message itself before starting that timer. There is also the opposite concern - what happens to any other VF (or PF) that is trying to get work done while the GPU is tied up migrating this VF? A stall of multiple seconds will cause all sorts of timeouts to trip. I think the expectation is that migration is a deliberate act and the system is not going to be doing anything else at the time. It is not something that just randomly occurs in the middle of a heavily loaded system. But I may be wrong on that? > > Scaling the timeout itself, does make sense though. > > Matt > >> + u32 action, factor; >> + struct sysinfo si; >> + u64 sys_mem_size; >> + >> + action = FIELD_GET(GUC_HXG_REQUEST_MSG_0_ACTION, request[0]); >> + if (action != GUC_ACTION_VF2GUC_NOTIFY_RESFIX_DONE || IS_DGFX(xe) || >> + !xe_device_has_flat_ccs(xe)) >> + return timeout; >> + >> + si_meminfo(&si); >> + sys_mem_size = si.totalram * si.mem_unit; Do we have to worry about Linux supporting >64bit addressing any time soon? I assume that is the reason for having separated units here is that the total might be over 64bits? Or are there no plans for 6-level page tables yet? John. >> + >> + if (sys_mem_size <= SZ_4G) >> + return timeout; >> + >> + factor = (sys_mem_size + SZ_4G) / SZ_4G; >> + timeout *= factor; >> + >> + return timeout; >> +} >> int xe_guc_mmio_send_recv(struct xe_guc *guc, const u32 *request, >> u32 len, u32 *response_buf) >> { >> @@ -1439,7 +1470,7 @@ int xe_guc_mmio_send_recv(struct xe_guc *guc, const u32 *request, >> >> ret = xe_mmio_wait32(mmio, reply_reg, GUC_HXG_MSG_0_ORIGIN, >> FIELD_PREP(GUC_HXG_MSG_0_ORIGIN, GUC_HXG_ORIGIN_GUC), >> - 50000, &reply, false); >> + guc_mmio_send_recv_timeout(guc, request), &reply, false); >> if (ret) { >> /* scratch registers might be cleared during FLR, try once more */ >> if (!reply && !lost) { >> -- >> 2.43.0 >> ^ permalink raw reply [flat|nested] 15+ messages in thread
* Re: [PATCH v3 2/2] drm/xe/guc: Scale mmio send/recv timeout for CCS save/restore with smem size 2025-08-06 19:57 ` John Harrison @ 2025-08-06 23:01 ` Matthew Brost 2025-08-07 6:22 ` K V P, Satyanarayana 1 sibling, 0 replies; 15+ messages in thread From: Matthew Brost @ 2025-08-06 23:01 UTC (permalink / raw) To: John Harrison; +Cc: Satyanarayana K V P, intel-xe On Wed, Aug 06, 2025 at 12:57:40PM -0700, John Harrison wrote: > On 8/6/2025 9:28 AM, Matthew Brost wrote: > > On Wed, Aug 06, 2025 at 01:59:10PM +0530, Satyanarayana K V P wrote: > > > After VF migration, GUC restores CCS metadata scaled to system memory size. > > > The default timeout (50ms) is calibrated for 4GB memory capacity per > > > specification. Timeouts for other memory sizes are proportionally derived > > > from this baseline. > > > > > > This ensures adequate restoration time for CCS metadata across > > > different hardware configurations while maintaining spec compliance. > > > > > > Signed-off-by: Satyanarayana K V P <satyanarayana.k.v.p@intel.com> > > > Cc: John Harrison <John.C.Harrison@Intel.com> > > > Cc: Matthew Brost <matthew.brost@intel.com> > > > --- > > > drivers/gpu/drm/xe/xe_guc.c | 33 ++++++++++++++++++++++++++++++++- > > > 1 file changed, 32 insertions(+), 1 deletion(-) > > > > > > diff --git a/drivers/gpu/drm/xe/xe_guc.c b/drivers/gpu/drm/xe/xe_guc.c > > > index 9e34401e4489..d836ded83491 100644 > > > --- a/drivers/gpu/drm/xe/xe_guc.c > > > +++ b/drivers/gpu/drm/xe/xe_guc.c > > > @@ -10,6 +10,7 @@ > > > #include <generated/xe_wa_oob.h> > > > #include "abi/guc_actions_abi.h" > > > +#include "abi/guc_actions_sriov_abi.h" > > > #include "abi/guc_errors_abi.h" > > > #include "regs/xe_gt_regs.h" > > > #include "regs/xe_gtt_defs.h" > > > @@ -1397,6 +1398,36 @@ int xe_guc_auth_huc(struct xe_guc *guc, u32 rsa_addr) > > > return xe_guc_ct_send_block(&guc->ct, action, ARRAY_SIZE(action)); > > > } > > > +/* > > > + * After VF migration, GUC restores CCS metadata scaled to system memory size. > > > + * Default timeout (50ms) is calibrated for 4GB memory capacity per > > > + * specification. Timeouts for other memory sizes are proportionally derived > > > + * from this baseline. > > > + */ > > > +static u32 guc_mmio_send_recv_timeout(struct xe_guc *guc, const u32 *request) > > > +{ > > > + struct xe_device *xe = guc_to_xe(guc); > > > + u32 timeout = 50000; > > Is this really the upper bound? It seems like if could be signicantly > > higher if multiple VFs are trying to do things all at the same time. > That is really a problem with the wait function itself rather than the > timeout. The timeout is meant to be the maximum expectation for how long the > operation will take once started. Unfortunately, we currently have no checks > on whether GuC has actually read the message itself before starting that > timer. > > There is also the opposite concern - what happens to any other VF (or PF) > that is trying to get work done while the GPU is tied up migrating this VF? > A stall of multiple seconds will cause all sorts of timeouts to trip. > It should only tie up the migration engine, I think GuC is free to do other work here when that is running, right? Sure, the migration engine is used by lot of things - clears for new memory allocations, bind, etc... but I don't think anything would timeout rather just experience a pretty heavy delay. Could be wrong this. > I think the expectation is that migration is a deliberate act and the system > is not going to be doing anything else at the time. It is not something that > just randomly occurs in the middle of a heavily loaded system. But I may be > wrong on that? I'm unsure on this part too. If is not some random event, then my original concern would be invalid. Matt > > > > > Scaling the timeout itself, does make sense though. > > > > Matt > > > > > + u32 action, factor; > > > + struct sysinfo si; > > > + u64 sys_mem_size; > > > + > > > + action = FIELD_GET(GUC_HXG_REQUEST_MSG_0_ACTION, request[0]); > > > + if (action != GUC_ACTION_VF2GUC_NOTIFY_RESFIX_DONE || IS_DGFX(xe) || > > > + !xe_device_has_flat_ccs(xe)) > > > + return timeout; > > > + > > > + si_meminfo(&si); > > > + sys_mem_size = si.totalram * si.mem_unit; > Do we have to worry about Linux supporting >64bit addressing any time soon? > I assume that is the reason for having separated units here is that the > total might be over 64bits? Or are there no plans for 6-level page tables > yet? > > John. > > > > + > > > + if (sys_mem_size <= SZ_4G) > > > + return timeout; > > > + > > > + factor = (sys_mem_size + SZ_4G) / SZ_4G; > > > + timeout *= factor; > > > + > > > + return timeout; > > > +} > > > int xe_guc_mmio_send_recv(struct xe_guc *guc, const u32 *request, > > > u32 len, u32 *response_buf) > > > { > > > @@ -1439,7 +1470,7 @@ int xe_guc_mmio_send_recv(struct xe_guc *guc, const u32 *request, > > > ret = xe_mmio_wait32(mmio, reply_reg, GUC_HXG_MSG_0_ORIGIN, > > > FIELD_PREP(GUC_HXG_MSG_0_ORIGIN, GUC_HXG_ORIGIN_GUC), > > > - 50000, &reply, false); > > > + guc_mmio_send_recv_timeout(guc, request), &reply, false); > > > if (ret) { > > > /* scratch registers might be cleared during FLR, try once more */ > > > if (!reply && !lost) { > > > -- > > > 2.43.0 > > > > ^ permalink raw reply [flat|nested] 15+ messages in thread
* Re: [PATCH v3 2/2] drm/xe/guc: Scale mmio send/recv timeout for CCS save/restore with smem size 2025-08-06 19:57 ` John Harrison 2025-08-06 23:01 ` Matthew Brost @ 2025-08-07 6:22 ` K V P, Satyanarayana 1 sibling, 0 replies; 15+ messages in thread From: K V P, Satyanarayana @ 2025-08-07 6:22 UTC (permalink / raw) To: John Harrison, Matthew Brost; +Cc: intel-xe On 07-08-2025 01:27, John Harrison wrote: > On 8/6/2025 9:28 AM, Matthew Brost wrote: >> On Wed, Aug 06, 2025 at 01:59:10PM +0530, Satyanarayana K V P wrote: >>> After VF migration, GUC restores CCS metadata scaled to system memory >>> size. >>> The default timeout (50ms) is calibrated for 4GB memory capacity per >>> specification. Timeouts for other memory sizes are proportionally >>> derived >>> from this baseline. >>> >>> This ensures adequate restoration time for CCS metadata across >>> different hardware configurations while maintaining spec compliance. >>> >>> Signed-off-by: Satyanarayana K V P <satyanarayana.k.v.p@intel.com> >>> Cc: John Harrison <John.C.Harrison@Intel.com> >>> Cc: Matthew Brost <matthew.brost@intel.com> >>> --- >>> drivers/gpu/drm/xe/xe_guc.c | 33 ++++++++++++++++++++++++++++++++- >>> 1 file changed, 32 insertions(+), 1 deletion(-) >>> >>> diff --git a/drivers/gpu/drm/xe/xe_guc.c b/drivers/gpu/drm/xe/xe_guc.c >>> index 9e34401e4489..d836ded83491 100644 >>> --- a/drivers/gpu/drm/xe/xe_guc.c >>> +++ b/drivers/gpu/drm/xe/xe_guc.c >>> @@ -10,6 +10,7 @@ >>> #include <generated/xe_wa_oob.h> >>> #include "abi/guc_actions_abi.h" >>> +#include "abi/guc_actions_sriov_abi.h" >>> #include "abi/guc_errors_abi.h" >>> #include "regs/xe_gt_regs.h" >>> #include "regs/xe_gtt_defs.h" >>> @@ -1397,6 +1398,36 @@ int xe_guc_auth_huc(struct xe_guc *guc, u32 >>> rsa_addr) >>> return xe_guc_ct_send_block(&guc->ct, action, ARRAY_SIZE(action)); >>> } >>> +/* >>> + * After VF migration, GUC restores CCS metadata scaled to system >>> memory size. >>> + * Default timeout (50ms) is calibrated for 4GB memory capacity per >>> + * specification. Timeouts for other memory sizes are proportionally >>> derived >>> + * from this baseline. >>> + */ >>> +static u32 guc_mmio_send_recv_timeout(struct xe_guc *guc, const u32 >>> *request) >>> +{ >>> + struct xe_device *xe = guc_to_xe(guc); >>> + u32 timeout = 50000; >> Is this really the upper bound? It seems like if could be signicantly >> higher if multiple VFs are trying to do things all at the same time. > That is really a problem with the wait function itself rather than the > timeout. The timeout is meant to be the maximum expectation for how long > the operation will take once started. Unfortunately, we currently have > no checks on whether GuC has actually read the message itself before > starting that timer. > > There is also the opposite concern - what happens to any other VF (or > PF) that is trying to get work done while the GPU is tied up migrating > this VF? A stall of multiple seconds will cause all sorts of timeouts to > trip. > > I think the expectation is that migration is a deliberate act and the > system is not going to be doing anything else at the time. It is not > something that just randomly occurs in the middle of a heavily loaded > system. But I may be wrong on that? > >> >> Scaling the timeout itself, does make sense though. >> >> Matt >> >>> + u32 action, factor; >>> + struct sysinfo si; >>> + u64 sys_mem_size; >>> + >>> + action = FIELD_GET(GUC_HXG_REQUEST_MSG_0_ACTION, request[0]); >>> + if (action != GUC_ACTION_VF2GUC_NOTIFY_RESFIX_DONE || >>> IS_DGFX(xe) || >>> + !xe_device_has_flat_ccs(xe)) >>> + return timeout; >>> + >>> + si_meminfo(&si); >>> + sys_mem_size = si.totalram * si.mem_unit; > Do we have to worry about Linux supporting >64bit addressing any time > soon? I assume that is the reason for having separated units here is > that the total might be over 64bits? Or are there no plans for 6-level > page tables yet? > > John. > I do not think we need to worry about >64 bit for now. As per lwn.net, we may get OS supporting 128 bit by 2035 which is long way to go. -Satya. >>> + >>> + if (sys_mem_size <= SZ_4G) >>> + return timeout; >>> + >>> + factor = (sys_mem_size + SZ_4G) / SZ_4G; >>> + timeout *= factor; >>> + >>> + return timeout; >>> +} >>> int xe_guc_mmio_send_recv(struct xe_guc *guc, const u32 *request, >>> u32 len, u32 *response_buf) >>> { >>> @@ -1439,7 +1470,7 @@ int xe_guc_mmio_send_recv(struct xe_guc *guc, >>> const u32 *request, >>> ret = xe_mmio_wait32(mmio, reply_reg, GUC_HXG_MSG_0_ORIGIN, >>> FIELD_PREP(GUC_HXG_MSG_0_ORIGIN, GUC_HXG_ORIGIN_GUC), >>> - 50000, &reply, false); >>> + guc_mmio_send_recv_timeout(guc, request), &reply, >>> false); >>> if (ret) { >>> /* scratch registers might be cleared during FLR, try once >>> more */ >>> if (!reply && !lost) { >>> -- >>> 2.43.0 >>> > ^ permalink raw reply [flat|nested] 15+ messages in thread
* ✓ Xe.CI.BAT: success for Improve CCS save restore series (rev3) 2025-08-06 8:29 [PATCH v3 0/2] Improve CCS save restore series Satyanarayana K V P ` (2 preceding siblings ...) 2025-08-06 8:29 ` [PATCH v3 2/2] drm/xe/guc: Scale mmio send/recv timeout for CCS save/restore with smem size Satyanarayana K V P @ 2025-08-06 9:21 ` Patchwork 2025-08-06 10:23 ` ✓ Xe.CI.Full: " Patchwork 4 siblings, 0 replies; 15+ messages in thread From: Patchwork @ 2025-08-06 9:21 UTC (permalink / raw) To: Satyanarayana K V P; +Cc: intel-xe [-- Attachment #1: Type: text/plain, Size: 1456 bytes --] == Series Details == Series: Improve CCS save restore series (rev3) URL : https://patchwork.freedesktop.org/series/152316/ State : success == Summary == CI Bug Log - changes from xe-3509-7b7457e249a1f7db97122bc6b9384e5e2f45475c_BAT -> xe-pw-152316v3_BAT ==================================================== Summary ------- **SUCCESS** No regressions found. Participating hosts (8 -> 7) ------------------------------ Missing (1): bat-adlp-vm Known issues ------------ Here are the changes found in xe-pw-152316v3_BAT that come from known issues: ### IGT changes ### #### Possible fixes #### * igt@kms_flip@basic-plain-flip@c-edp1: - bat-adlp-7: [DMESG-WARN][1] ([Intel XE#4543]) -> [PASS][2] +1 other test pass [1]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-3509-7b7457e249a1f7db97122bc6b9384e5e2f45475c/bat-adlp-7/igt@kms_flip@basic-plain-flip@c-edp1.html [2]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-152316v3/bat-adlp-7/igt@kms_flip@basic-plain-flip@c-edp1.html [Intel XE#4543]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/4543 Build changes ------------- * Linux: xe-3509-7b7457e249a1f7db97122bc6b9384e5e2f45475c -> xe-pw-152316v3 IGT_8487: 8487 xe-3509-7b7457e249a1f7db97122bc6b9384e5e2f45475c: 7b7457e249a1f7db97122bc6b9384e5e2f45475c xe-pw-152316v3: 152316v3 == Logs == For more details see: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-152316v3/index.html [-- Attachment #2: Type: text/html, Size: 2021 bytes --] ^ permalink raw reply [flat|nested] 15+ messages in thread
* ✓ Xe.CI.Full: success for Improve CCS save restore series (rev3) 2025-08-06 8:29 [PATCH v3 0/2] Improve CCS save restore series Satyanarayana K V P ` (3 preceding siblings ...) 2025-08-06 9:21 ` ✓ Xe.CI.BAT: success for Improve CCS save restore series (rev3) Patchwork @ 2025-08-06 10:23 ` Patchwork 4 siblings, 0 replies; 15+ messages in thread From: Patchwork @ 2025-08-06 10:23 UTC (permalink / raw) To: Satyanarayana K V P; +Cc: intel-xe [-- Attachment #1: Type: text/plain, Size: 23763 bytes --] == Series Details == Series: Improve CCS save restore series (rev3) URL : https://patchwork.freedesktop.org/series/152316/ State : success == Summary == CI Bug Log - changes from xe-3509-7b7457e249a1f7db97122bc6b9384e5e2f45475c_FULL -> xe-pw-152316v3_FULL ==================================================== Summary ------- **SUCCESS** No regressions found. Participating hosts (4 -> 4) ------------------------------ No changes in participating hosts Known issues ------------ Here are the changes found in xe-pw-152316v3_FULL that come from known issues: ### IGT changes ### #### Issues hit #### * igt@kms_big_fb@4-tiled-32bpp-rotate-270: - shard-dg2-set2: NOTRUN -> [SKIP][1] ([Intel XE#316]) +1 other test skip [1]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-152316v3/shard-dg2-434/igt@kms_big_fb@4-tiled-32bpp-rotate-270.html * igt@kms_big_fb@yf-tiled-16bpp-rotate-270: - shard-dg2-set2: NOTRUN -> [SKIP][2] ([Intel XE#1124]) +2 other tests skip [2]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-152316v3/shard-dg2-466/igt@kms_big_fb@yf-tiled-16bpp-rotate-270.html * igt@kms_bw@connected-linear-tiling-3-displays-3840x2160p: - shard-dg2-set2: NOTRUN -> [SKIP][3] ([Intel XE#2191]) [3]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-152316v3/shard-dg2-434/igt@kms_bw@connected-linear-tiling-3-displays-3840x2160p.html * igt@kms_ccs@crc-primary-basic-4-tiled-mtl-rc-ccs-cc@pipe-d-dp-2: - shard-dg2-set2: NOTRUN -> [SKIP][4] ([Intel XE#455] / [Intel XE#787]) +15 other tests skip [4]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-152316v3/shard-dg2-432/igt@kms_ccs@crc-primary-basic-4-tiled-mtl-rc-ccs-cc@pipe-d-dp-2.html * igt@kms_ccs@crc-primary-suspend-4-tiled-bmg-ccs: - shard-bmg: [PASS][5] -> [INCOMPLETE][6] ([Intel XE#3862]) +1 other test incomplete [5]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-3509-7b7457e249a1f7db97122bc6b9384e5e2f45475c/shard-bmg-1/igt@kms_ccs@crc-primary-suspend-4-tiled-bmg-ccs.html [6]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-152316v3/shard-bmg-2/igt@kms_ccs@crc-primary-suspend-4-tiled-bmg-ccs.html * igt@kms_ccs@missing-ccs-buffer-4-tiled-mtl-rc-ccs@pipe-c-hdmi-a-6: - shard-dg2-set2: NOTRUN -> [SKIP][7] ([Intel XE#787]) +97 other tests skip [7]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-152316v3/shard-dg2-464/igt@kms_ccs@missing-ccs-buffer-4-tiled-mtl-rc-ccs@pipe-c-hdmi-a-6.html * igt@kms_ccs@random-ccs-data-4-tiled-dg2-mc-ccs@pipe-a-dp-4: - shard-dg2-set2: NOTRUN -> [INCOMPLETE][8] ([Intel XE#1727] / [Intel XE#3113] / [Intel XE#3124]) [8]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-152316v3/shard-dg2-463/igt@kms_ccs@random-ccs-data-4-tiled-dg2-mc-ccs@pipe-a-dp-4.html * igt@kms_cdclk@mode-transition@pipe-a-dp-2: - shard-dg2-set2: NOTRUN -> [SKIP][9] ([Intel XE#4417]) +3 other tests skip [9]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-152316v3/shard-dg2-432/igt@kms_cdclk@mode-transition@pipe-a-dp-2.html * igt@kms_chamelium_color@ctm-0-25: - shard-dg2-set2: NOTRUN -> [SKIP][10] ([Intel XE#306]) [10]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-152316v3/shard-dg2-434/igt@kms_chamelium_color@ctm-0-25.html * igt@kms_chamelium_frames@hdmi-aspect-ratio: - shard-dg2-set2: NOTRUN -> [SKIP][11] ([Intel XE#373]) +2 other tests skip [11]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-152316v3/shard-dg2-434/igt@kms_chamelium_frames@hdmi-aspect-ratio.html * igt@kms_cursor_crc@cursor-sliding-max-size: - shard-dg2-set2: NOTRUN -> [SKIP][12] ([Intel XE#455]) +3 other tests skip [12]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-152316v3/shard-dg2-466/igt@kms_cursor_crc@cursor-sliding-max-size.html * igt@kms_cursor_legacy@flip-vs-cursor-legacy: - shard-bmg: [PASS][13] -> [FAIL][14] ([Intel XE#4633]) [13]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-3509-7b7457e249a1f7db97122bc6b9384e5e2f45475c/shard-bmg-5/igt@kms_cursor_legacy@flip-vs-cursor-legacy.html [14]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-152316v3/shard-bmg-2/igt@kms_cursor_legacy@flip-vs-cursor-legacy.html * igt@kms_fbc_dirty_rect@fbc-dirty-rectangle-dirtyfb-tests: - shard-dg2-set2: NOTRUN -> [SKIP][15] ([Intel XE#4422]) [15]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-152316v3/shard-dg2-434/igt@kms_fbc_dirty_rect@fbc-dirty-rectangle-dirtyfb-tests.html * igt@kms_feature_discovery@psr2: - shard-dg2-set2: NOTRUN -> [SKIP][16] ([Intel XE#1135]) [16]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-152316v3/shard-dg2-434/igt@kms_feature_discovery@psr2.html * igt@kms_flip@flip-vs-blocking-wf-vblank: - shard-adlp: [PASS][17] -> [DMESG-WARN][18] ([Intel XE#4543]) +2 other tests dmesg-warn [17]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-3509-7b7457e249a1f7db97122bc6b9384e5e2f45475c/shard-adlp-3/igt@kms_flip@flip-vs-blocking-wf-vblank.html [18]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-152316v3/shard-adlp-4/igt@kms_flip@flip-vs-blocking-wf-vblank.html * igt@kms_flip@flip-vs-suspend-interruptible: - shard-bmg: [PASS][19] -> [INCOMPLETE][20] ([Intel XE#2049] / [Intel XE#2597]) +1 other test incomplete [19]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-3509-7b7457e249a1f7db97122bc6b9384e5e2f45475c/shard-bmg-2/igt@kms_flip@flip-vs-suspend-interruptible.html [20]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-152316v3/shard-bmg-5/igt@kms_flip@flip-vs-suspend-interruptible.html - shard-dg2-set2: [PASS][21] -> [INCOMPLETE][22] ([Intel XE#2049] / [Intel XE#2597]) +1 other test incomplete [21]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-3509-7b7457e249a1f7db97122bc6b9384e5e2f45475c/shard-dg2-463/igt@kms_flip@flip-vs-suspend-interruptible.html [22]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-152316v3/shard-dg2-433/igt@kms_flip@flip-vs-suspend-interruptible.html * igt@kms_flip@modeset-vs-vblank-race: - shard-adlp: [PASS][23] -> [DMESG-WARN][24] ([Intel XE#2953] / [Intel XE#4173] / [Intel XE#5208]) [23]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-3509-7b7457e249a1f7db97122bc6b9384e5e2f45475c/shard-adlp-3/igt@kms_flip@modeset-vs-vblank-race.html [24]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-152316v3/shard-adlp-2/igt@kms_flip@modeset-vs-vblank-race.html * igt@kms_frontbuffer_tracking@drrs-2p-primscrn-shrfb-msflip-blt: - shard-dg2-set2: NOTRUN -> [SKIP][25] ([Intel XE#651]) +7 other tests skip [25]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-152316v3/shard-dg2-466/igt@kms_frontbuffer_tracking@drrs-2p-primscrn-shrfb-msflip-blt.html * igt@kms_frontbuffer_tracking@psr-2p-primscrn-pri-shrfb-draw-blt: - shard-dg2-set2: NOTRUN -> [SKIP][26] ([Intel XE#653]) +5 other tests skip [26]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-152316v3/shard-dg2-434/igt@kms_frontbuffer_tracking@psr-2p-primscrn-pri-shrfb-draw-blt.html * igt@kms_hdr@invalid-hdr: - shard-bmg: [PASS][27] -> [SKIP][28] ([Intel XE#1503]) [27]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-3509-7b7457e249a1f7db97122bc6b9384e5e2f45475c/shard-bmg-7/igt@kms_hdr@invalid-hdr.html [28]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-152316v3/shard-bmg-1/igt@kms_hdr@invalid-hdr.html * igt@kms_plane@plane-panning-bottom-right-suspend: - shard-adlp: [PASS][29] -> [DMESG-WARN][30] ([Intel XE#2953] / [Intel XE#4173]) +5 other tests dmesg-warn [29]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-3509-7b7457e249a1f7db97122bc6b9384e5e2f45475c/shard-adlp-4/igt@kms_plane@plane-panning-bottom-right-suspend.html [30]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-152316v3/shard-adlp-4/igt@kms_plane@plane-panning-bottom-right-suspend.html * igt@kms_psr2_sf@psr2-overlay-plane-move-continuous-sf: - shard-dg2-set2: NOTRUN -> [SKIP][31] ([Intel XE#1489]) +1 other test skip [31]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-152316v3/shard-dg2-434/igt@kms_psr2_sf@psr2-overlay-plane-move-continuous-sf.html * igt@kms_psr@psr2-basic: - shard-dg2-set2: NOTRUN -> [SKIP][32] ([Intel XE#2850] / [Intel XE#929]) +1 other test skip [32]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-152316v3/shard-dg2-434/igt@kms_psr@psr2-basic.html * igt@xe_compute_preempt@compute-preempt-many: - shard-dg2-set2: NOTRUN -> [SKIP][33] ([Intel XE#1280] / [Intel XE#455]) +1 other test skip [33]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-152316v3/shard-dg2-466/igt@xe_compute_preempt@compute-preempt-many.html * igt@xe_eu_stall@non-blocking-re-enable: - shard-bmg: [PASS][34] -> [FAIL][35] ([Intel XE#5420]) [34]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-3509-7b7457e249a1f7db97122bc6b9384e5e2f45475c/shard-bmg-3/igt@xe_eu_stall@non-blocking-re-enable.html [35]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-152316v3/shard-bmg-5/igt@xe_eu_stall@non-blocking-re-enable.html * igt@xe_exec_basic@multigpu-no-exec-bindexecqueue-userptr-rebind: - shard-dg2-set2: [PASS][36] -> [SKIP][37] ([Intel XE#1392]) +4 other tests skip [36]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-3509-7b7457e249a1f7db97122bc6b9384e5e2f45475c/shard-dg2-433/igt@xe_exec_basic@multigpu-no-exec-bindexecqueue-userptr-rebind.html [37]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-152316v3/shard-dg2-432/igt@xe_exec_basic@multigpu-no-exec-bindexecqueue-userptr-rebind.html * igt@xe_exec_fault_mode@many-execqueues-bindexecqueue-userptr-rebind-prefetch: - shard-dg2-set2: NOTRUN -> [SKIP][38] ([Intel XE#288]) +1 other test skip [38]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-152316v3/shard-dg2-466/igt@xe_exec_fault_mode@many-execqueues-bindexecqueue-userptr-rebind-prefetch.html * igt@xe_exec_reset@parallel-gt-reset: - shard-adlp: [PASS][39] -> [DMESG-WARN][40] ([Intel XE#3876]) [39]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-3509-7b7457e249a1f7db97122bc6b9384e5e2f45475c/shard-adlp-4/igt@xe_exec_reset@parallel-gt-reset.html [40]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-152316v3/shard-adlp-4/igt@xe_exec_reset@parallel-gt-reset.html * igt@xe_exec_sip_eudebug@breakpoint-writesip-twice: - shard-dg2-set2: NOTRUN -> [SKIP][41] ([Intel XE#4837]) [41]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-152316v3/shard-dg2-466/igt@xe_exec_sip_eudebug@breakpoint-writesip-twice.html * igt@xe_exec_system_allocator@threads-shared-vm-many-execqueues-malloc-busy-nomemset: - shard-dg2-set2: NOTRUN -> [SKIP][42] ([Intel XE#4915]) +48 other tests skip [42]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-152316v3/shard-dg2-434/igt@xe_exec_system_allocator@threads-shared-vm-many-execqueues-malloc-busy-nomemset.html * igt@xe_exec_system_allocator@threads-shared-vm-many-stride-new-bo-map-nomemset: - shard-lnl: [PASS][43] -> [FAIL][44] ([Intel XE#5018]) [43]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-3509-7b7457e249a1f7db97122bc6b9384e5e2f45475c/shard-lnl-5/igt@xe_exec_system_allocator@threads-shared-vm-many-stride-new-bo-map-nomemset.html [44]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-152316v3/shard-lnl-8/igt@xe_exec_system_allocator@threads-shared-vm-many-stride-new-bo-map-nomemset.html * igt@xe_exec_threads@threads-hang-shared-vm-userptr: - shard-adlp: [PASS][45] -> [DMESG-FAIL][46] ([Intel XE#3876]) [45]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-3509-7b7457e249a1f7db97122bc6b9384e5e2f45475c/shard-adlp-4/igt@xe_exec_threads@threads-hang-shared-vm-userptr.html [46]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-152316v3/shard-adlp-4/igt@xe_exec_threads@threads-hang-shared-vm-userptr.html * igt@xe_oa@mmio-triggered-reports: - shard-dg2-set2: NOTRUN -> [SKIP][47] ([Intel XE#3573]) +1 other test skip [47]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-152316v3/shard-dg2-434/igt@xe_oa@mmio-triggered-reports.html * igt@xe_pm@d3cold-i2c: - shard-dg2-set2: NOTRUN -> [SKIP][48] ([Intel XE#5694]) [48]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-152316v3/shard-dg2-434/igt@xe_pm@d3cold-i2c.html #### Possible fixes #### * igt@kms_big_fb@x-tiled-max-hw-stride-64bpp-rotate-180-hflip-async-flip: - shard-adlp: [DMESG-FAIL][49] ([Intel XE#4543]) -> [PASS][50] [49]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-3509-7b7457e249a1f7db97122bc6b9384e5e2f45475c/shard-adlp-9/igt@kms_big_fb@x-tiled-max-hw-stride-64bpp-rotate-180-hflip-async-flip.html [50]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-152316v3/shard-adlp-9/igt@kms_big_fb@x-tiled-max-hw-stride-64bpp-rotate-180-hflip-async-flip.html * igt@kms_ccs@random-ccs-data-4-tiled-dg2-mc-ccs@pipe-a-hdmi-a-6: - shard-dg2-set2: [INCOMPLETE][51] ([Intel XE#1727] / [Intel XE#3113] / [Intel XE#3124]) -> [PASS][52] [51]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-3509-7b7457e249a1f7db97122bc6b9384e5e2f45475c/shard-dg2-436/igt@kms_ccs@random-ccs-data-4-tiled-dg2-mc-ccs@pipe-a-hdmi-a-6.html [52]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-152316v3/shard-dg2-463/igt@kms_ccs@random-ccs-data-4-tiled-dg2-mc-ccs@pipe-a-hdmi-a-6.html * igt@kms_cursor_legacy@cursorb-vs-flipb-toggle: - shard-bmg: [SKIP][53] ([Intel XE#2291]) -> [PASS][54] [53]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-3509-7b7457e249a1f7db97122bc6b9384e5e2f45475c/shard-bmg-6/igt@kms_cursor_legacy@cursorb-vs-flipb-toggle.html [54]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-152316v3/shard-bmg-8/igt@kms_cursor_legacy@cursorb-vs-flipb-toggle.html * igt@kms_flip@2x-flip-vs-blocking-wf-vblank: - shard-bmg: [SKIP][55] ([Intel XE#2316]) -> [PASS][56] [55]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-3509-7b7457e249a1f7db97122bc6b9384e5e2f45475c/shard-bmg-6/igt@kms_flip@2x-flip-vs-blocking-wf-vblank.html [56]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-152316v3/shard-bmg-8/igt@kms_flip@2x-flip-vs-blocking-wf-vblank.html * igt@kms_flip@basic-flip-vs-dpms@c-hdmi-a1: - shard-adlp: [DMESG-WARN][57] ([Intel XE#4543]) -> [PASS][58] +4 other tests pass [57]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-3509-7b7457e249a1f7db97122bc6b9384e5e2f45475c/shard-adlp-6/igt@kms_flip@basic-flip-vs-dpms@c-hdmi-a1.html [58]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-152316v3/shard-adlp-4/igt@kms_flip@basic-flip-vs-dpms@c-hdmi-a1.html * igt@kms_hdr@static-toggle-suspend: - shard-bmg: [SKIP][59] ([Intel XE#1503]) -> [PASS][60] [59]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-3509-7b7457e249a1f7db97122bc6b9384e5e2f45475c/shard-bmg-6/igt@kms_hdr@static-toggle-suspend.html [60]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-152316v3/shard-bmg-8/igt@kms_hdr@static-toggle-suspend.html * igt@kms_plane_cursor@overlay: - shard-dg2-set2: [FAIL][61] ([Intel XE#616]) -> [PASS][62] [61]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-3509-7b7457e249a1f7db97122bc6b9384e5e2f45475c/shard-dg2-432/igt@kms_plane_cursor@overlay.html [62]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-152316v3/shard-dg2-463/igt@kms_plane_cursor@overlay.html * igt@kms_plane_scaling@2x-scaler-multi-pipe: - shard-bmg: [SKIP][63] ([Intel XE#2571]) -> [PASS][64] [63]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-3509-7b7457e249a1f7db97122bc6b9384e5e2f45475c/shard-bmg-6/igt@kms_plane_scaling@2x-scaler-multi-pipe.html [64]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-152316v3/shard-bmg-8/igt@kms_plane_scaling@2x-scaler-multi-pipe.html * igt@kms_vblank@query-forked-busy-hang@pipe-a-hdmi-a-1: - shard-adlp: [DMESG-WARN][65] ([Intel XE#2953] / [Intel XE#4173]) -> [PASS][66] +2 other tests pass [65]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-3509-7b7457e249a1f7db97122bc6b9384e5e2f45475c/shard-adlp-3/igt@kms_vblank@query-forked-busy-hang@pipe-a-hdmi-a-1.html [66]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-152316v3/shard-adlp-2/igt@kms_vblank@query-forked-busy-hang@pipe-a-hdmi-a-1.html * igt@xe_exec_basic@multigpu-no-exec-bindexecqueue-userptr-invalidate: - shard-dg2-set2: [SKIP][67] ([Intel XE#1392]) -> [PASS][68] +3 other tests pass [67]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-3509-7b7457e249a1f7db97122bc6b9384e5e2f45475c/shard-dg2-432/igt@xe_exec_basic@multigpu-no-exec-bindexecqueue-userptr-invalidate.html [68]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-152316v3/shard-dg2-464/igt@xe_exec_basic@multigpu-no-exec-bindexecqueue-userptr-invalidate.html * igt@xe_exec_system_allocator@threads-shared-vm-many-large-execqueues-new-bo-map-nomemset: - shard-lnl: [FAIL][69] ([Intel XE#5018]) -> [PASS][70] [69]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-3509-7b7457e249a1f7db97122bc6b9384e5e2f45475c/shard-lnl-5/igt@xe_exec_system_allocator@threads-shared-vm-many-large-execqueues-new-bo-map-nomemset.html [70]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-152316v3/shard-lnl-8/igt@xe_exec_system_allocator@threads-shared-vm-many-large-execqueues-new-bo-map-nomemset.html * igt@xe_exec_system_allocator@threads-shared-vm-many-stride-new-bo-map-nomemset: - shard-bmg: [FAIL][71] ([Intel XE#4937]) -> [PASS][72] [71]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-3509-7b7457e249a1f7db97122bc6b9384e5e2f45475c/shard-bmg-1/igt@xe_exec_system_allocator@threads-shared-vm-many-stride-new-bo-map-nomemset.html [72]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-152316v3/shard-bmg-7/igt@xe_exec_system_allocator@threads-shared-vm-many-stride-new-bo-map-nomemset.html #### Warnings #### * igt@kms_frontbuffer_tracking@drrs-2p-scndscrn-pri-indfb-draw-blt: - shard-bmg: [SKIP][73] ([Intel XE#2312]) -> [SKIP][74] ([Intel XE#2311]) +4 other tests skip [73]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-3509-7b7457e249a1f7db97122bc6b9384e5e2f45475c/shard-bmg-6/igt@kms_frontbuffer_tracking@drrs-2p-scndscrn-pri-indfb-draw-blt.html [74]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-152316v3/shard-bmg-8/igt@kms_frontbuffer_tracking@drrs-2p-scndscrn-pri-indfb-draw-blt.html * igt@kms_frontbuffer_tracking@fbc-2p-primscrn-shrfb-plflip-blt: - shard-bmg: [SKIP][75] ([Intel XE#5390]) -> [SKIP][76] ([Intel XE#2312]) [75]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-3509-7b7457e249a1f7db97122bc6b9384e5e2f45475c/shard-bmg-7/igt@kms_frontbuffer_tracking@fbc-2p-primscrn-shrfb-plflip-blt.html [76]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-152316v3/shard-bmg-6/igt@kms_frontbuffer_tracking@fbc-2p-primscrn-shrfb-plflip-blt.html * igt@kms_frontbuffer_tracking@fbcpsr-2p-scndscrn-pri-indfb-draw-render: - shard-bmg: [SKIP][77] ([Intel XE#2312]) -> [SKIP][78] ([Intel XE#2313]) +3 other tests skip [77]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-3509-7b7457e249a1f7db97122bc6b9384e5e2f45475c/shard-bmg-6/igt@kms_frontbuffer_tracking@fbcpsr-2p-scndscrn-pri-indfb-draw-render.html [78]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-152316v3/shard-bmg-8/igt@kms_frontbuffer_tracking@fbcpsr-2p-scndscrn-pri-indfb-draw-render.html * igt@kms_tiled_display@basic-test-pattern: - shard-bmg: [FAIL][79] ([Intel XE#1729]) -> [SKIP][80] ([Intel XE#2426]) [79]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-3509-7b7457e249a1f7db97122bc6b9384e5e2f45475c/shard-bmg-5/igt@kms_tiled_display@basic-test-pattern.html [80]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-152316v3/shard-bmg-4/igt@kms_tiled_display@basic-test-pattern.html {name}: This element is suppressed. This means it is ignored when computing the status of the difference (SUCCESS, WARNING, or FAILURE). [Intel XE#1124]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/1124 [Intel XE#1135]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/1135 [Intel XE#1280]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/1280 [Intel XE#1392]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/1392 [Intel XE#1489]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/1489 [Intel XE#1503]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/1503 [Intel XE#1727]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/1727 [Intel XE#1729]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/1729 [Intel XE#2049]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/2049 [Intel XE#2191]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/2191 [Intel XE#2291]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/2291 [Intel XE#2311]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/2311 [Intel XE#2312]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/2312 [Intel XE#2313]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/2313 [Intel XE#2316]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/2316 [Intel XE#2426]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/2426 [Intel XE#2571]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/2571 [Intel XE#2597]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/2597 [Intel XE#2850]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/2850 [Intel XE#288]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/288 [Intel XE#2953]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/2953 [Intel XE#306]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/306 [Intel XE#3113]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/3113 [Intel XE#3124]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/3124 [Intel XE#316]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/316 [Intel XE#3573]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/3573 [Intel XE#373]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/373 [Intel XE#3862]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/3862 [Intel XE#3876]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/3876 [Intel XE#4173]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/4173 [Intel XE#4417]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/4417 [Intel XE#4422]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/4422 [Intel XE#4543]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/4543 [Intel XE#455]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/455 [Intel XE#4633]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/4633 [Intel XE#4837]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/4837 [Intel XE#4915]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/4915 [Intel XE#4937]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/4937 [Intel XE#5018]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/5018 [Intel XE#5208]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/5208 [Intel XE#5390]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/5390 [Intel XE#5420]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/5420 [Intel XE#5694]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/5694 [Intel XE#616]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/616 [Intel XE#651]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/651 [Intel XE#653]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/653 [Intel XE#787]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/787 [Intel XE#929]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/929 Build changes ------------- * Linux: xe-3509-7b7457e249a1f7db97122bc6b9384e5e2f45475c -> xe-pw-152316v3 IGT_8487: 8487 xe-3509-7b7457e249a1f7db97122bc6b9384e5e2f45475c: 7b7457e249a1f7db97122bc6b9384e5e2f45475c xe-pw-152316v3: 152316v3 == Logs == For more details see: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-152316v3/index.html [-- Attachment #2: Type: text/html, Size: 26829 bytes --] ^ permalink raw reply [flat|nested] 15+ messages in thread
end of thread, other threads:[~2025-08-07 11:15 UTC | newest] Thread overview: 15+ messages (download: mbox.gz follow: Atom feed -- links below jump to the message on this page -- 2025-08-06 8:29 [PATCH v3 0/2] Improve CCS save restore series Satyanarayana K V P 2025-08-06 8:19 ` ✓ CI.KUnit: success for Improve CCS save restore series (rev3) Patchwork 2025-08-06 8:29 ` [PATCH v3 1/2] drm/xe/vf: Refactor CCS save/restore to use default migration context Satyanarayana K V P 2025-08-06 16:08 ` Summers, Stuart 2025-08-06 16:20 ` Matthew Brost 2025-08-06 16:22 ` Summers, Stuart 2025-08-06 18:50 ` John Harrison 2025-08-07 11:15 ` K V P, Satyanarayana 2025-08-06 8:29 ` [PATCH v3 2/2] drm/xe/guc: Scale mmio send/recv timeout for CCS save/restore with smem size Satyanarayana K V P 2025-08-06 16:28 ` Matthew Brost 2025-08-06 19:57 ` John Harrison 2025-08-06 23:01 ` Matthew Brost 2025-08-07 6:22 ` K V P, Satyanarayana 2025-08-06 9:21 ` ✓ Xe.CI.BAT: success for Improve CCS save restore series (rev3) Patchwork 2025-08-06 10:23 ` ✓ Xe.CI.Full: " Patchwork
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