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From: Heiko Stuebner <heiko-4mtYJXux2i+zQB+pC5nmwQ@public.gmane.org>
To: Frank Wang <frank.wang-TNX95d0MmH7DzftRWevZcw@public.gmane.org>
Cc: huangtao-TNX95d0MmH7DzftRWevZcw@public.gmane.org,
	johnyoun-HKixBCOQz3hWk0Htik3J/w@public.gmane.org,
	gregkh-hQyY1W1yCW8ekmWlsbkhG0B+6BGkLq7r@public.gmane.org,
	linux-usb-u79uwXL29TY76Z2rM5mHXA@public.gmane.org,
	linux-kernel-u79uwXL29TY76Z2rM5mHXA@public.gmane.org,
	kever.yang-TNX95d0MmH7DzftRWevZcw@public.gmane.org,
	linux-rockchip-IAPFreCvJWM7uuMidbF8XUB+6BGkLq7r@public.gmane.org,
	william.wu-TNX95d0MmH7DzftRWevZcw@public.gmane.org
Subject: Re: [RESEND PATCH 0/1] add multiple clock handling for dwc2 driver
Date: Sun, 05 Feb 2017 10:41:23 +0100	[thread overview]
Message-ID: <3508420.z4eX5F6ytJ@phil> (raw)
In-Reply-To: <1486263061-10681-1-git-send-email-frank.wang-TNX95d0MmH7DzftRWevZcw@public.gmane.org>

Hi Frank,

Am Sonntag, 5. Februar 2017, 10:51:00 CET schrieb Frank Wang:
> The original posting on Jan 19th have not received any responses, so I
> resend them.
> 
> The Current default dwc2 just handle one clock named otg, however, it may
> have two or more clock need to manage for some new SoCs(such as RK3328), so
> this adds change clk to clk's array of dwc2_hsotg to handle more clocks
> operation.

can you please give a bit more detail on the specific layout.

I guess you're talking about hclk_otg_pmu, right? What component does it 
supply, because I didn't find anything in the partial TRM in the PMU section 
relating to the "otg".

This meant to make sure, you're actually controlling some part of the dwc2 
with that second/third/... clock and not some separate component.


Heiko

WARNING: multiple messages have this Message-ID (diff)
From: Heiko Stuebner <heiko@sntech.de>
To: Frank Wang <frank.wang@rock-chips.com>
Cc: johnyoun@synopsys.com, gregkh@linuxfoundation.org,
	linux-kernel@vger.kernel.org, linux-usb@vger.kernel.org,
	linux-rockchip@lists.infradead.org, huangtao@rock-chips.com,
	kever.yang@rock-chips.com, william.wu@rock-chips.com
Subject: Re: [RESEND PATCH 0/1] add multiple clock handling for dwc2 driver
Date: Sun, 05 Feb 2017 10:41:23 +0100	[thread overview]
Message-ID: <3508420.z4eX5F6ytJ@phil> (raw)
In-Reply-To: <1486263061-10681-1-git-send-email-frank.wang@rock-chips.com>

Hi Frank,

Am Sonntag, 5. Februar 2017, 10:51:00 CET schrieb Frank Wang:
> The original posting on Jan 19th have not received any responses, so I
> resend them.
> 
> The Current default dwc2 just handle one clock named otg, however, it may
> have two or more clock need to manage for some new SoCs(such as RK3328), so
> this adds change clk to clk's array of dwc2_hsotg to handle more clocks
> operation.

can you please give a bit more detail on the specific layout.

I guess you're talking about hclk_otg_pmu, right? What component does it 
supply, because I didn't find anything in the partial TRM in the PMU section 
relating to the "otg".

This meant to make sure, you're actually controlling some part of the dwc2 
with that second/third/... clock and not some separate component.


Heiko

  parent reply	other threads:[~2017-02-05  9:41 UTC|newest]

Thread overview: 13+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2017-02-05  2:51 [RESEND PATCH 0/1] add multiple clock handling for dwc2 driver Frank Wang
     [not found] ` <1486263061-10681-1-git-send-email-frank.wang-TNX95d0MmH7DzftRWevZcw@public.gmane.org>
2017-02-05  2:51   ` [RESEND PATCH 1/1] usb: dwc2: add multiple clock handling Frank Wang
2017-02-05  2:51     ` Frank Wang
2017-02-07  0:06     ` Heiko Stuebner
2017-02-07  3:18       ` Frank Wang
2017-02-07  9:51         ` John Youn
2017-02-07  9:51           ` John Youn
2017-02-05  9:41   ` Heiko Stuebner [this message]
2017-02-05  9:41     ` [RESEND PATCH 0/1] add multiple clock handling for dwc2 driver Heiko Stuebner
2017-02-06  1:40     ` Frank Wang
2017-02-06  1:40       ` Frank Wang
2017-02-06 23:53       ` Heiko Stuebner
     [not found] <eb6931a1-4679-1579-27fe-d444ae84a122@rock-chips.com>
2017-02-06  2:20 ` Frank Wang

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