* [PATCH v5 1/5] lib: sbi_pmu: move pmu irq information into pmu itself
2022-10-04 16:42 [PATCH v5 0/5] Add support for T-HEAD C9xx PMU extensions Heiko Stuebner
@ 2022-10-04 16:42 ` Heiko Stuebner
2022-10-13 4:03 ` Anup Patel
2022-10-04 16:42 ` [PATCH v5 2/5] lib: sbi_hart: move hart_features struct to a public location Heiko Stuebner
` (5 subsequent siblings)
6 siblings, 1 reply; 16+ messages in thread
From: Heiko Stuebner @ 2022-10-04 16:42 UTC (permalink / raw)
To: opensbi
Don't spread checking for pmu extensions through the code
but instead introduce a sbi-pmu function that other code can
call to get the correct information about the existence of the
pmu interrupt.
Add a sbi_pmu_device override function to allow overridung this
bit as well if needed.
Reviewed-by: Atish Patra <atishp@rivosinc.com>
Reviewed-by: Guo Ren <guoren@kernel.org>
Signed-off-by: Heiko Stuebner <heiko@sntech.de>
---
include/sbi/sbi_pmu.h | 8 ++++++++
lib/sbi/sbi_hart.c | 4 ++--
lib/sbi/sbi_pmu.c | 12 ++++++++++++
3 files changed, 22 insertions(+), 2 deletions(-)
diff --git a/include/sbi/sbi_pmu.h b/include/sbi/sbi_pmu.h
index a2ce42d..c365243 100644
--- a/include/sbi/sbi_pmu.h
+++ b/include/sbi/sbi_pmu.h
@@ -73,6 +73,11 @@ struct sbi_pmu_device {
* Note: 0 <= counter_index < SBI_PMU_HW_CTR_MAX
*/
void (*hw_counter_disable_irq)(uint32_t counter_index);
+
+ /**
+ * Custom function returning the machine-specific irq-bit.
+ */
+ int (*hw_counter_irq_bit)(void);
};
/** Get the PMU platform device */
@@ -87,6 +92,9 @@ int sbi_pmu_init(struct sbi_scratch *scratch, bool cold_boot);
/** Reset PMU during hart exit */
void sbi_pmu_exit(struct sbi_scratch *scratch);
+/** Return the pmu irq bit depending on extension existence */
+int sbi_pmu_irq_bit(void);
+
/**
* Add the hardware event to counter mapping information. This should be called
* from the platform code to update the mapping table.
diff --git a/lib/sbi/sbi_hart.c b/lib/sbi/sbi_hart.c
index 1294868..447f99e 100644
--- a/lib/sbi/sbi_hart.c
+++ b/lib/sbi/sbi_hart.c
@@ -19,6 +19,7 @@
#include <sbi/sbi_hart.h>
#include <sbi/sbi_math.h>
#include <sbi/sbi_platform.h>
+#include <sbi/sbi_pmu.h>
#include <sbi/sbi_string.h>
#include <sbi/sbi_trap.h>
@@ -208,8 +209,7 @@ static int delegate_traps(struct sbi_scratch *scratch)
/* Send M-mode interrupts and most exceptions to S-mode */
interrupts = MIP_SSIP | MIP_STIP | MIP_SEIP;
- if (sbi_hart_has_extension(scratch, SBI_HART_EXT_SSCOFPMF))
- interrupts |= MIP_LCOFIP;
+ interrupts |= sbi_pmu_irq_bit();
exceptions = (1U << CAUSE_MISALIGNED_FETCH) | (1U << CAUSE_BREAKPOINT) |
(1U << CAUSE_USER_ECALL);
diff --git a/lib/sbi/sbi_pmu.c b/lib/sbi/sbi_pmu.c
index 214d5e8..91d9ccc 100644
--- a/lib/sbi/sbi_pmu.c
+++ b/lib/sbi/sbi_pmu.c
@@ -344,6 +344,18 @@ skip_inhibit_update:
return 0;
}
+int sbi_pmu_irq_bit(void)
+{
+ struct sbi_scratch *scratch = sbi_scratch_thishart_ptr();
+
+ if (sbi_hart_has_extension(scratch, SBI_HART_EXT_SSCOFPMF))
+ return MIP_LCOFIP;
+ if (pmu_dev && pmu_dev->hw_counter_irq_bit)
+ return pmu_dev->hw_counter_irq_bit();
+
+ return 0;
+}
+
static int pmu_ctr_start_fw(uint32_t cidx, uint32_t event_code,
uint64_t ival, bool ival_update)
{
--
2.35.1
^ permalink raw reply related [flat|nested] 16+ messages in thread* [PATCH v5 1/5] lib: sbi_pmu: move pmu irq information into pmu itself
2022-10-04 16:42 ` [PATCH v5 1/5] lib: sbi_pmu: move pmu irq information into pmu itself Heiko Stuebner
@ 2022-10-13 4:03 ` Anup Patel
0 siblings, 0 replies; 16+ messages in thread
From: Anup Patel @ 2022-10-13 4:03 UTC (permalink / raw)
To: opensbi
On Tue, Oct 4, 2022 at 10:12 PM Heiko Stuebner <heiko@sntech.de> wrote:
>
> Don't spread checking for pmu extensions through the code
> but instead introduce a sbi-pmu function that other code can
> call to get the correct information about the existence of the
> pmu interrupt.
>
> Add a sbi_pmu_device override function to allow overridung this
> bit as well if needed.
>
> Reviewed-by: Atish Patra <atishp@rivosinc.com>
> Reviewed-by: Guo Ren <guoren@kernel.org>
> Signed-off-by: Heiko Stuebner <heiko@sntech.de>
Looks good to me.
Reviewed-by: Anup Patel <anup@brainfault.org>
Regards,
Anup
> ---
> include/sbi/sbi_pmu.h | 8 ++++++++
> lib/sbi/sbi_hart.c | 4 ++--
> lib/sbi/sbi_pmu.c | 12 ++++++++++++
> 3 files changed, 22 insertions(+), 2 deletions(-)
>
> diff --git a/include/sbi/sbi_pmu.h b/include/sbi/sbi_pmu.h
> index a2ce42d..c365243 100644
> --- a/include/sbi/sbi_pmu.h
> +++ b/include/sbi/sbi_pmu.h
> @@ -73,6 +73,11 @@ struct sbi_pmu_device {
> * Note: 0 <= counter_index < SBI_PMU_HW_CTR_MAX
> */
> void (*hw_counter_disable_irq)(uint32_t counter_index);
> +
> + /**
> + * Custom function returning the machine-specific irq-bit.
> + */
> + int (*hw_counter_irq_bit)(void);
> };
>
> /** Get the PMU platform device */
> @@ -87,6 +92,9 @@ int sbi_pmu_init(struct sbi_scratch *scratch, bool cold_boot);
> /** Reset PMU during hart exit */
> void sbi_pmu_exit(struct sbi_scratch *scratch);
>
> +/** Return the pmu irq bit depending on extension existence */
> +int sbi_pmu_irq_bit(void);
> +
> /**
> * Add the hardware event to counter mapping information. This should be called
> * from the platform code to update the mapping table.
> diff --git a/lib/sbi/sbi_hart.c b/lib/sbi/sbi_hart.c
> index 1294868..447f99e 100644
> --- a/lib/sbi/sbi_hart.c
> +++ b/lib/sbi/sbi_hart.c
> @@ -19,6 +19,7 @@
> #include <sbi/sbi_hart.h>
> #include <sbi/sbi_math.h>
> #include <sbi/sbi_platform.h>
> +#include <sbi/sbi_pmu.h>
> #include <sbi/sbi_string.h>
> #include <sbi/sbi_trap.h>
>
> @@ -208,8 +209,7 @@ static int delegate_traps(struct sbi_scratch *scratch)
>
> /* Send M-mode interrupts and most exceptions to S-mode */
> interrupts = MIP_SSIP | MIP_STIP | MIP_SEIP;
> - if (sbi_hart_has_extension(scratch, SBI_HART_EXT_SSCOFPMF))
> - interrupts |= MIP_LCOFIP;
> + interrupts |= sbi_pmu_irq_bit();
>
> exceptions = (1U << CAUSE_MISALIGNED_FETCH) | (1U << CAUSE_BREAKPOINT) |
> (1U << CAUSE_USER_ECALL);
> diff --git a/lib/sbi/sbi_pmu.c b/lib/sbi/sbi_pmu.c
> index 214d5e8..91d9ccc 100644
> --- a/lib/sbi/sbi_pmu.c
> +++ b/lib/sbi/sbi_pmu.c
> @@ -344,6 +344,18 @@ skip_inhibit_update:
> return 0;
> }
>
> +int sbi_pmu_irq_bit(void)
> +{
> + struct sbi_scratch *scratch = sbi_scratch_thishart_ptr();
> +
> + if (sbi_hart_has_extension(scratch, SBI_HART_EXT_SSCOFPMF))
> + return MIP_LCOFIP;
> + if (pmu_dev && pmu_dev->hw_counter_irq_bit)
> + return pmu_dev->hw_counter_irq_bit();
> +
> + return 0;
> +}
> +
> static int pmu_ctr_start_fw(uint32_t cidx, uint32_t event_code,
> uint64_t ival, bool ival_update)
> {
> --
> 2.35.1
>
>
> --
> opensbi mailing list
> opensbi at lists.infradead.org
> http://lists.infradead.org/mailman/listinfo/opensbi
^ permalink raw reply [flat|nested] 16+ messages in thread
* [PATCH v5 2/5] lib: sbi_hart: move hart_features struct to a public location
2022-10-04 16:42 [PATCH v5 0/5] Add support for T-HEAD C9xx PMU extensions Heiko Stuebner
2022-10-04 16:42 ` [PATCH v5 1/5] lib: sbi_pmu: move pmu irq information into pmu itself Heiko Stuebner
@ 2022-10-04 16:42 ` Heiko Stuebner
2022-10-13 4:05 ` Anup Patel
2022-10-04 16:42 ` [PATCH v5 3/5] lib: sbi_platform: expose hart_features to extension_init callback Heiko Stuebner
` (4 subsequent siblings)
6 siblings, 1 reply; 16+ messages in thread
From: Heiko Stuebner @ 2022-10-04 16:42 UTC (permalink / raw)
To: opensbi
Platforms may need to override auto-detected hart features
in their override functions. So move the hart_features
struct to the sbi_hart.h header allowing us to pass it over
to platform-handlers.
Suggested-by: Atish Patra <atishp@atishpatra.org>
Signed-off-by: Heiko Stuebner <heiko@sntech.de>
---
include/sbi/sbi_hart.h | 11 +++++++++++
lib/sbi/sbi_hart.c | 36 +++++++++++++-----------------------
2 files changed, 24 insertions(+), 23 deletions(-)
diff --git a/include/sbi/sbi_hart.h b/include/sbi/sbi_hart.h
index 0032364..95b40e7 100644
--- a/include/sbi/sbi_hart.h
+++ b/include/sbi/sbi_hart.h
@@ -41,6 +41,17 @@ enum sbi_hart_extensions {
SBI_HART_EXT_MAX,
};
+struct sbi_hart_features {
+ bool detected;
+ int priv_version;
+ unsigned long extensions;
+ unsigned int pmp_count;
+ unsigned int pmp_addr_bits;
+ unsigned long pmp_gran;
+ unsigned int mhpm_count;
+ unsigned int mhpm_bits;
+};
+
struct sbi_scratch;
int sbi_hart_reinit(struct sbi_scratch *scratch);
diff --git a/lib/sbi/sbi_hart.c b/lib/sbi/sbi_hart.c
index 447f99e..d0a6295 100644
--- a/lib/sbi/sbi_hart.c
+++ b/lib/sbi/sbi_hart.c
@@ -28,16 +28,6 @@ extern void __sbi_expected_trap_hext(void);
void (*sbi_hart_expected_trap)(void) = &__sbi_expected_trap;
-struct hart_features {
- bool detected;
- int priv_version;
- unsigned long extensions;
- unsigned int pmp_count;
- unsigned int pmp_addr_bits;
- unsigned long pmp_gran;
- unsigned int mhpm_count;
- unsigned int mhpm_bits;
-};
static unsigned long hart_features_offset;
static void mstatus_init(struct sbi_scratch *scratch)
@@ -254,7 +244,7 @@ void sbi_hart_delegation_dump(struct sbi_scratch *scratch,
unsigned int sbi_hart_mhpm_count(struct sbi_scratch *scratch)
{
- struct hart_features *hfeatures =
+ struct sbi_hart_features *hfeatures =
sbi_scratch_offset_ptr(scratch, hart_features_offset);
return hfeatures->mhpm_count;
@@ -262,7 +252,7 @@ unsigned int sbi_hart_mhpm_count(struct sbi_scratch *scratch)
unsigned int sbi_hart_pmp_count(struct sbi_scratch *scratch)
{
- struct hart_features *hfeatures =
+ struct sbi_hart_features *hfeatures =
sbi_scratch_offset_ptr(scratch, hart_features_offset);
return hfeatures->pmp_count;
@@ -270,7 +260,7 @@ unsigned int sbi_hart_pmp_count(struct sbi_scratch *scratch)
unsigned long sbi_hart_pmp_granularity(struct sbi_scratch *scratch)
{
- struct hart_features *hfeatures =
+ struct sbi_hart_features *hfeatures =
sbi_scratch_offset_ptr(scratch, hart_features_offset);
return hfeatures->pmp_gran;
@@ -278,7 +268,7 @@ unsigned long sbi_hart_pmp_granularity(struct sbi_scratch *scratch)
unsigned int sbi_hart_pmp_addrbits(struct sbi_scratch *scratch)
{
- struct hart_features *hfeatures =
+ struct sbi_hart_features *hfeatures =
sbi_scratch_offset_ptr(scratch, hart_features_offset);
return hfeatures->pmp_addr_bits;
@@ -286,7 +276,7 @@ unsigned int sbi_hart_pmp_addrbits(struct sbi_scratch *scratch)
unsigned int sbi_hart_mhpm_bits(struct sbi_scratch *scratch)
{
- struct hart_features *hfeatures =
+ struct sbi_hart_features *hfeatures =
sbi_scratch_offset_ptr(scratch, hart_features_offset);
return hfeatures->mhpm_bits;
@@ -336,7 +326,7 @@ int sbi_hart_pmp_configure(struct sbi_scratch *scratch)
int sbi_hart_priv_version(struct sbi_scratch *scratch)
{
- struct hart_features *hfeatures =
+ struct sbi_hart_features *hfeatures =
sbi_scratch_offset_ptr(scratch, hart_features_offset);
return hfeatures->priv_version;
@@ -346,7 +336,7 @@ void sbi_hart_get_priv_version_str(struct sbi_scratch *scratch,
char *version_str, int nvstr)
{
char *temp;
- struct hart_features *hfeatures =
+ struct sbi_hart_features *hfeatures =
sbi_scratch_offset_ptr(scratch, hart_features_offset);
switch (hfeatures->priv_version) {
@@ -368,7 +358,7 @@ void sbi_hart_get_priv_version_str(struct sbi_scratch *scratch,
}
static inline void __sbi_hart_update_extension(
- struct hart_features *hfeatures,
+ struct sbi_hart_features *hfeatures,
enum sbi_hart_extensions ext,
bool enable)
{
@@ -389,7 +379,7 @@ void sbi_hart_update_extension(struct sbi_scratch *scratch,
enum sbi_hart_extensions ext,
bool enable)
{
- struct hart_features *hfeatures =
+ struct sbi_hart_features *hfeatures =
sbi_scratch_offset_ptr(scratch, hart_features_offset);
__sbi_hart_update_extension(hfeatures, ext, enable);
@@ -405,7 +395,7 @@ void sbi_hart_update_extension(struct sbi_scratch *scratch,
bool sbi_hart_has_extension(struct sbi_scratch *scratch,
enum sbi_hart_extensions ext)
{
- struct hart_features *hfeatures =
+ struct sbi_hart_features *hfeatures =
sbi_scratch_offset_ptr(scratch, hart_features_offset);
if (hfeatures->extensions & BIT(ext))
@@ -453,7 +443,7 @@ static inline char *sbi_hart_extension_id2string(int ext)
void sbi_hart_get_extensions_str(struct sbi_scratch *scratch,
char *extensions_str, int nestr)
{
- struct hart_features *hfeatures =
+ struct sbi_hart_features *hfeatures =
sbi_scratch_offset_ptr(scratch, hart_features_offset);
int offset = 0, ext = 0;
char *temp;
@@ -539,7 +529,7 @@ static int hart_pmu_get_allowed_bits(void)
static int hart_detect_features(struct sbi_scratch *scratch)
{
struct sbi_trap_info trap = {0};
- struct hart_features *hfeatures =
+ struct sbi_hart_features *hfeatures =
sbi_scratch_offset_ptr(scratch, hart_features_offset);
unsigned long val, oldval;
int rc;
@@ -718,7 +708,7 @@ int sbi_hart_init(struct sbi_scratch *scratch, bool cold_boot)
sbi_hart_expected_trap = &__sbi_expected_trap_hext;
hart_features_offset = sbi_scratch_alloc_offset(
- sizeof(struct hart_features));
+ sizeof(struct sbi_hart_features));
if (!hart_features_offset)
return SBI_ENOMEM;
}
--
2.35.1
^ permalink raw reply related [flat|nested] 16+ messages in thread* [PATCH v5 2/5] lib: sbi_hart: move hart_features struct to a public location
2022-10-04 16:42 ` [PATCH v5 2/5] lib: sbi_hart: move hart_features struct to a public location Heiko Stuebner
@ 2022-10-13 4:05 ` Anup Patel
0 siblings, 0 replies; 16+ messages in thread
From: Anup Patel @ 2022-10-13 4:05 UTC (permalink / raw)
To: opensbi
On Tue, Oct 4, 2022 at 10:13 PM Heiko Stuebner <heiko@sntech.de> wrote:
>
> Platforms may need to override auto-detected hart features
> in their override functions. So move the hart_features
> struct to the sbi_hart.h header allowing us to pass it over
> to platform-handlers.
>
> Suggested-by: Atish Patra <atishp@atishpatra.org>
> Signed-off-by: Heiko Stuebner <heiko@sntech.de>
Looks good to me.
Reviewed-by: Anup Patel <anup@brainfault.org>
Regards,
Anup
> ---
> include/sbi/sbi_hart.h | 11 +++++++++++
> lib/sbi/sbi_hart.c | 36 +++++++++++++-----------------------
> 2 files changed, 24 insertions(+), 23 deletions(-)
>
> diff --git a/include/sbi/sbi_hart.h b/include/sbi/sbi_hart.h
> index 0032364..95b40e7 100644
> --- a/include/sbi/sbi_hart.h
> +++ b/include/sbi/sbi_hart.h
> @@ -41,6 +41,17 @@ enum sbi_hart_extensions {
> SBI_HART_EXT_MAX,
> };
>
> +struct sbi_hart_features {
> + bool detected;
> + int priv_version;
> + unsigned long extensions;
> + unsigned int pmp_count;
> + unsigned int pmp_addr_bits;
> + unsigned long pmp_gran;
> + unsigned int mhpm_count;
> + unsigned int mhpm_bits;
> +};
> +
> struct sbi_scratch;
>
> int sbi_hart_reinit(struct sbi_scratch *scratch);
> diff --git a/lib/sbi/sbi_hart.c b/lib/sbi/sbi_hart.c
> index 447f99e..d0a6295 100644
> --- a/lib/sbi/sbi_hart.c
> +++ b/lib/sbi/sbi_hart.c
> @@ -28,16 +28,6 @@ extern void __sbi_expected_trap_hext(void);
>
> void (*sbi_hart_expected_trap)(void) = &__sbi_expected_trap;
>
> -struct hart_features {
> - bool detected;
> - int priv_version;
> - unsigned long extensions;
> - unsigned int pmp_count;
> - unsigned int pmp_addr_bits;
> - unsigned long pmp_gran;
> - unsigned int mhpm_count;
> - unsigned int mhpm_bits;
> -};
> static unsigned long hart_features_offset;
>
> static void mstatus_init(struct sbi_scratch *scratch)
> @@ -254,7 +244,7 @@ void sbi_hart_delegation_dump(struct sbi_scratch *scratch,
>
> unsigned int sbi_hart_mhpm_count(struct sbi_scratch *scratch)
> {
> - struct hart_features *hfeatures =
> + struct sbi_hart_features *hfeatures =
> sbi_scratch_offset_ptr(scratch, hart_features_offset);
>
> return hfeatures->mhpm_count;
> @@ -262,7 +252,7 @@ unsigned int sbi_hart_mhpm_count(struct sbi_scratch *scratch)
>
> unsigned int sbi_hart_pmp_count(struct sbi_scratch *scratch)
> {
> - struct hart_features *hfeatures =
> + struct sbi_hart_features *hfeatures =
> sbi_scratch_offset_ptr(scratch, hart_features_offset);
>
> return hfeatures->pmp_count;
> @@ -270,7 +260,7 @@ unsigned int sbi_hart_pmp_count(struct sbi_scratch *scratch)
>
> unsigned long sbi_hart_pmp_granularity(struct sbi_scratch *scratch)
> {
> - struct hart_features *hfeatures =
> + struct sbi_hart_features *hfeatures =
> sbi_scratch_offset_ptr(scratch, hart_features_offset);
>
> return hfeatures->pmp_gran;
> @@ -278,7 +268,7 @@ unsigned long sbi_hart_pmp_granularity(struct sbi_scratch *scratch)
>
> unsigned int sbi_hart_pmp_addrbits(struct sbi_scratch *scratch)
> {
> - struct hart_features *hfeatures =
> + struct sbi_hart_features *hfeatures =
> sbi_scratch_offset_ptr(scratch, hart_features_offset);
>
> return hfeatures->pmp_addr_bits;
> @@ -286,7 +276,7 @@ unsigned int sbi_hart_pmp_addrbits(struct sbi_scratch *scratch)
>
> unsigned int sbi_hart_mhpm_bits(struct sbi_scratch *scratch)
> {
> - struct hart_features *hfeatures =
> + struct sbi_hart_features *hfeatures =
> sbi_scratch_offset_ptr(scratch, hart_features_offset);
>
> return hfeatures->mhpm_bits;
> @@ -336,7 +326,7 @@ int sbi_hart_pmp_configure(struct sbi_scratch *scratch)
>
> int sbi_hart_priv_version(struct sbi_scratch *scratch)
> {
> - struct hart_features *hfeatures =
> + struct sbi_hart_features *hfeatures =
> sbi_scratch_offset_ptr(scratch, hart_features_offset);
>
> return hfeatures->priv_version;
> @@ -346,7 +336,7 @@ void sbi_hart_get_priv_version_str(struct sbi_scratch *scratch,
> char *version_str, int nvstr)
> {
> char *temp;
> - struct hart_features *hfeatures =
> + struct sbi_hart_features *hfeatures =
> sbi_scratch_offset_ptr(scratch, hart_features_offset);
>
> switch (hfeatures->priv_version) {
> @@ -368,7 +358,7 @@ void sbi_hart_get_priv_version_str(struct sbi_scratch *scratch,
> }
>
> static inline void __sbi_hart_update_extension(
> - struct hart_features *hfeatures,
> + struct sbi_hart_features *hfeatures,
> enum sbi_hart_extensions ext,
> bool enable)
> {
> @@ -389,7 +379,7 @@ void sbi_hart_update_extension(struct sbi_scratch *scratch,
> enum sbi_hart_extensions ext,
> bool enable)
> {
> - struct hart_features *hfeatures =
> + struct sbi_hart_features *hfeatures =
> sbi_scratch_offset_ptr(scratch, hart_features_offset);
>
> __sbi_hart_update_extension(hfeatures, ext, enable);
> @@ -405,7 +395,7 @@ void sbi_hart_update_extension(struct sbi_scratch *scratch,
> bool sbi_hart_has_extension(struct sbi_scratch *scratch,
> enum sbi_hart_extensions ext)
> {
> - struct hart_features *hfeatures =
> + struct sbi_hart_features *hfeatures =
> sbi_scratch_offset_ptr(scratch, hart_features_offset);
>
> if (hfeatures->extensions & BIT(ext))
> @@ -453,7 +443,7 @@ static inline char *sbi_hart_extension_id2string(int ext)
> void sbi_hart_get_extensions_str(struct sbi_scratch *scratch,
> char *extensions_str, int nestr)
> {
> - struct hart_features *hfeatures =
> + struct sbi_hart_features *hfeatures =
> sbi_scratch_offset_ptr(scratch, hart_features_offset);
> int offset = 0, ext = 0;
> char *temp;
> @@ -539,7 +529,7 @@ static int hart_pmu_get_allowed_bits(void)
> static int hart_detect_features(struct sbi_scratch *scratch)
> {
> struct sbi_trap_info trap = {0};
> - struct hart_features *hfeatures =
> + struct sbi_hart_features *hfeatures =
> sbi_scratch_offset_ptr(scratch, hart_features_offset);
> unsigned long val, oldval;
> int rc;
> @@ -718,7 +708,7 @@ int sbi_hart_init(struct sbi_scratch *scratch, bool cold_boot)
> sbi_hart_expected_trap = &__sbi_expected_trap_hext;
>
> hart_features_offset = sbi_scratch_alloc_offset(
> - sizeof(struct hart_features));
> + sizeof(struct sbi_hart_features));
> if (!hart_features_offset)
> return SBI_ENOMEM;
> }
> --
> 2.35.1
>
>
> --
> opensbi mailing list
> opensbi at lists.infradead.org
> http://lists.infradead.org/mailman/listinfo/opensbi
^ permalink raw reply [flat|nested] 16+ messages in thread
* [PATCH v5 3/5] lib: sbi_platform: expose hart_features to extension_init callback
2022-10-04 16:42 [PATCH v5 0/5] Add support for T-HEAD C9xx PMU extensions Heiko Stuebner
2022-10-04 16:42 ` [PATCH v5 1/5] lib: sbi_pmu: move pmu irq information into pmu itself Heiko Stuebner
2022-10-04 16:42 ` [PATCH v5 2/5] lib: sbi_hart: move hart_features struct to a public location Heiko Stuebner
@ 2022-10-04 16:42 ` Heiko Stuebner
2022-10-13 4:08 ` Anup Patel
2022-10-04 16:42 ` [PATCH v5 4/5] platform: generic: add extensions_init handler and platform-override Heiko Stuebner
` (3 subsequent siblings)
6 siblings, 1 reply; 16+ messages in thread
From: Heiko Stuebner @ 2022-10-04 16:42 UTC (permalink / raw)
To: opensbi
The platform-specific extension_init callback is supposed to
set specific things for the platform opensbi is running on.
So it's also the right place to override specific hart_features
if needed - when it's know that autodetection has provided
wrong results for example.
Suggested-by: Atish Patra <atishp@atishpatra.org>
Signed-off-by: Heiko Stuebner <heiko@sntech.de>
---
include/sbi/sbi_platform.h | 8 +++++---
lib/sbi/sbi_hart.c | 3 ++-
2 files changed, 7 insertions(+), 4 deletions(-)
diff --git a/include/sbi/sbi_platform.h b/include/sbi/sbi_platform.h
index 87024db..722f27a 100644
--- a/include/sbi/sbi_platform.h
+++ b/include/sbi/sbi_platform.h
@@ -48,6 +48,7 @@
struct sbi_domain_memregion;
struct sbi_trap_info;
struct sbi_trap_regs;
+struct sbi_hart_features;
/** Possible feature flags of a platform */
enum sbi_platform_features {
@@ -90,7 +91,7 @@ struct sbi_platform_operations {
int (*misa_get_xlen)(void);
/** Initialize (or populate) HART extensions for the platform */
- int (*extensions_init)(void);
+ int (*extensions_init)(struct sbi_hart_features *hfeatures);
/** Initialize (or populate) domains for the platform */
int (*domains_init)(void);
@@ -464,10 +465,11 @@ static inline int sbi_platform_misa_xlen(const struct sbi_platform *plat)
* @return 0 on success and negative error code on failure
*/
static inline int sbi_platform_extensions_init(
- const struct sbi_platform *plat)
+ const struct sbi_platform *plat,
+ struct sbi_hart_features *hfeatures)
{
if (plat && sbi_platform_ops(plat)->extensions_init)
- return sbi_platform_ops(plat)->extensions_init();
+ return sbi_platform_ops(plat)->extensions_init(hfeatures);
return 0;
}
diff --git a/lib/sbi/sbi_hart.c b/lib/sbi/sbi_hart.c
index d0a6295..dacab1a 100644
--- a/lib/sbi/sbi_hart.c
+++ b/lib/sbi/sbi_hart.c
@@ -672,7 +672,8 @@ __mhpm_skip:
}
/* Let platform populate extensions */
- rc = sbi_platform_extensions_init(sbi_platform_thishart_ptr());
+ rc = sbi_platform_extensions_init(sbi_platform_thishart_ptr(),
+ hfeatures);
if (rc)
return rc;
--
2.35.1
^ permalink raw reply related [flat|nested] 16+ messages in thread* [PATCH v5 3/5] lib: sbi_platform: expose hart_features to extension_init callback
2022-10-04 16:42 ` [PATCH v5 3/5] lib: sbi_platform: expose hart_features to extension_init callback Heiko Stuebner
@ 2022-10-13 4:08 ` Anup Patel
0 siblings, 0 replies; 16+ messages in thread
From: Anup Patel @ 2022-10-13 4:08 UTC (permalink / raw)
To: opensbi
On Tue, Oct 4, 2022 at 10:13 PM Heiko Stuebner <heiko@sntech.de> wrote:
>
> The platform-specific extension_init callback is supposed to
> set specific things for the platform opensbi is running on.
>
> So it's also the right place to override specific hart_features
> if needed - when it's know that autodetection has provided
> wrong results for example.
>
> Suggested-by: Atish Patra <atishp@atishpatra.org>
> Signed-off-by: Heiko Stuebner <heiko@sntech.de>
Looks good to me.
Reviewed-by: Anup Patel <anup@brainfault.org>
Regards,
Anup
> ---
> include/sbi/sbi_platform.h | 8 +++++---
> lib/sbi/sbi_hart.c | 3 ++-
> 2 files changed, 7 insertions(+), 4 deletions(-)
>
> diff --git a/include/sbi/sbi_platform.h b/include/sbi/sbi_platform.h
> index 87024db..722f27a 100644
> --- a/include/sbi/sbi_platform.h
> +++ b/include/sbi/sbi_platform.h
> @@ -48,6 +48,7 @@
> struct sbi_domain_memregion;
> struct sbi_trap_info;
> struct sbi_trap_regs;
> +struct sbi_hart_features;
>
> /** Possible feature flags of a platform */
> enum sbi_platform_features {
> @@ -90,7 +91,7 @@ struct sbi_platform_operations {
> int (*misa_get_xlen)(void);
>
> /** Initialize (or populate) HART extensions for the platform */
> - int (*extensions_init)(void);
> + int (*extensions_init)(struct sbi_hart_features *hfeatures);
>
> /** Initialize (or populate) domains for the platform */
> int (*domains_init)(void);
> @@ -464,10 +465,11 @@ static inline int sbi_platform_misa_xlen(const struct sbi_platform *plat)
> * @return 0 on success and negative error code on failure
> */
> static inline int sbi_platform_extensions_init(
> - const struct sbi_platform *plat)
> + const struct sbi_platform *plat,
> + struct sbi_hart_features *hfeatures)
> {
> if (plat && sbi_platform_ops(plat)->extensions_init)
> - return sbi_platform_ops(plat)->extensions_init();
> + return sbi_platform_ops(plat)->extensions_init(hfeatures);
> return 0;
> }
>
> diff --git a/lib/sbi/sbi_hart.c b/lib/sbi/sbi_hart.c
> index d0a6295..dacab1a 100644
> --- a/lib/sbi/sbi_hart.c
> +++ b/lib/sbi/sbi_hart.c
> @@ -672,7 +672,8 @@ __mhpm_skip:
> }
>
> /* Let platform populate extensions */
> - rc = sbi_platform_extensions_init(sbi_platform_thishart_ptr());
> + rc = sbi_platform_extensions_init(sbi_platform_thishart_ptr(),
> + hfeatures);
> if (rc)
> return rc;
>
> --
> 2.35.1
>
>
> --
> opensbi mailing list
> opensbi at lists.infradead.org
> http://lists.infradead.org/mailman/listinfo/opensbi
^ permalink raw reply [flat|nested] 16+ messages in thread
* [PATCH v5 4/5] platform: generic: add extensions_init handler and platform-override
2022-10-04 16:42 [PATCH v5 0/5] Add support for T-HEAD C9xx PMU extensions Heiko Stuebner
` (2 preceding siblings ...)
2022-10-04 16:42 ` [PATCH v5 3/5] lib: sbi_platform: expose hart_features to extension_init callback Heiko Stuebner
@ 2022-10-04 16:42 ` Heiko Stuebner
2022-10-13 4:08 ` Anup Patel
2022-10-04 16:42 ` [PATCH v5 5/5] platform: generic: allwinner: add support for c9xx pmu Heiko Stuebner
` (2 subsequent siblings)
6 siblings, 1 reply; 16+ messages in thread
From: Heiko Stuebner @ 2022-10-04 16:42 UTC (permalink / raw)
To: opensbi
Init of non-standard extensions is a platform-specific thing,
so allow generic platforms to do this via a platform-override.
Signed-off-by: Heiko Stuebner <heiko@sntech.de>
---
platform/generic/include/platform_override.h | 3 +++
platform/generic/platform.c | 10 ++++++++++
2 files changed, 13 insertions(+)
diff --git a/platform/generic/include/platform_override.h b/platform/generic/include/platform_override.h
index e55da25..7f1558d 100644
--- a/platform/generic/include/platform_override.h
+++ b/platform/generic/include/platform_override.h
@@ -10,6 +10,7 @@
#ifndef __PLATFORM_OVERRIDE_H__
#define __PLATFORM_OVERRIDE_H__
+#include <sbi/sbi_hart.h>
#include <sbi/sbi_types.h>
#include <sbi/sbi_trap.h>
@@ -22,6 +23,8 @@ struct platform_override {
void (*early_exit)(const struct fdt_match *match);
void (*final_exit)(const struct fdt_match *match);
int (*fdt_fixup)(void *fdt, const struct fdt_match *match);
+ int (*extensions_init)(const struct fdt_match *match,
+ struct sbi_hart_features *hfeatures);
int (*vendor_ext_check)(long extid, const struct fdt_match *match);
int (*vendor_ext_provider)(long extid, long funcid,
const struct sbi_trap_regs *regs,
diff --git a/platform/generic/platform.c b/platform/generic/platform.c
index bf51aba..595b0fd 100644
--- a/platform/generic/platform.c
+++ b/platform/generic/platform.c
@@ -204,6 +204,15 @@ static void generic_final_exit(void)
generic_plat->final_exit(generic_plat_match);
}
+static int generic_extensions_init(struct sbi_hart_features *hfeatures)
+{
+ if (generic_plat && generic_plat->extensions_init)
+ return generic_plat->extensions_init(generic_plat_match,
+ hfeatures);
+
+ return 0;
+}
+
static int generic_domains_init(void)
{
return fdt_domains_populate(fdt_get_address());
@@ -257,6 +266,7 @@ const struct sbi_platform_operations platform_ops = {
.final_init = generic_final_init,
.early_exit = generic_early_exit,
.final_exit = generic_final_exit,
+ .extensions_init = generic_extensions_init,
.domains_init = generic_domains_init,
.console_init = generic_console_init,
.irqchip_init = fdt_irqchip_init,
--
2.35.1
^ permalink raw reply related [flat|nested] 16+ messages in thread* [PATCH v5 4/5] platform: generic: add extensions_init handler and platform-override
2022-10-04 16:42 ` [PATCH v5 4/5] platform: generic: add extensions_init handler and platform-override Heiko Stuebner
@ 2022-10-13 4:08 ` Anup Patel
0 siblings, 0 replies; 16+ messages in thread
From: Anup Patel @ 2022-10-13 4:08 UTC (permalink / raw)
To: opensbi
On Tue, Oct 4, 2022 at 10:13 PM Heiko Stuebner <heiko@sntech.de> wrote:
>
> Init of non-standard extensions is a platform-specific thing,
> so allow generic platforms to do this via a platform-override.
>
> Signed-off-by: Heiko Stuebner <heiko@sntech.de>
Looks good to me.
Reviewed-by: Anup Patel <anup@brainfault.org>
Regards,
Anup
> ---
> platform/generic/include/platform_override.h | 3 +++
> platform/generic/platform.c | 10 ++++++++++
> 2 files changed, 13 insertions(+)
>
> diff --git a/platform/generic/include/platform_override.h b/platform/generic/include/platform_override.h
> index e55da25..7f1558d 100644
> --- a/platform/generic/include/platform_override.h
> +++ b/platform/generic/include/platform_override.h
> @@ -10,6 +10,7 @@
> #ifndef __PLATFORM_OVERRIDE_H__
> #define __PLATFORM_OVERRIDE_H__
>
> +#include <sbi/sbi_hart.h>
> #include <sbi/sbi_types.h>
> #include <sbi/sbi_trap.h>
>
> @@ -22,6 +23,8 @@ struct platform_override {
> void (*early_exit)(const struct fdt_match *match);
> void (*final_exit)(const struct fdt_match *match);
> int (*fdt_fixup)(void *fdt, const struct fdt_match *match);
> + int (*extensions_init)(const struct fdt_match *match,
> + struct sbi_hart_features *hfeatures);
> int (*vendor_ext_check)(long extid, const struct fdt_match *match);
> int (*vendor_ext_provider)(long extid, long funcid,
> const struct sbi_trap_regs *regs,
> diff --git a/platform/generic/platform.c b/platform/generic/platform.c
> index bf51aba..595b0fd 100644
> --- a/platform/generic/platform.c
> +++ b/platform/generic/platform.c
> @@ -204,6 +204,15 @@ static void generic_final_exit(void)
> generic_plat->final_exit(generic_plat_match);
> }
>
> +static int generic_extensions_init(struct sbi_hart_features *hfeatures)
> +{
> + if (generic_plat && generic_plat->extensions_init)
> + return generic_plat->extensions_init(generic_plat_match,
> + hfeatures);
> +
> + return 0;
> +}
> +
> static int generic_domains_init(void)
> {
> return fdt_domains_populate(fdt_get_address());
> @@ -257,6 +266,7 @@ const struct sbi_platform_operations platform_ops = {
> .final_init = generic_final_init,
> .early_exit = generic_early_exit,
> .final_exit = generic_final_exit,
> + .extensions_init = generic_extensions_init,
> .domains_init = generic_domains_init,
> .console_init = generic_console_init,
> .irqchip_init = fdt_irqchip_init,
> --
> 2.35.1
>
>
> --
> opensbi mailing list
> opensbi at lists.infradead.org
> http://lists.infradead.org/mailman/listinfo/opensbi
^ permalink raw reply [flat|nested] 16+ messages in thread
* [PATCH v5 5/5] platform: generic: allwinner: add support for c9xx pmu
2022-10-04 16:42 [PATCH v5 0/5] Add support for T-HEAD C9xx PMU extensions Heiko Stuebner
` (3 preceding siblings ...)
2022-10-04 16:42 ` [PATCH v5 4/5] platform: generic: add extensions_init handler and platform-override Heiko Stuebner
@ 2022-10-04 16:42 ` Heiko Stuebner
2022-10-13 4:09 ` Anup Patel
2022-10-04 17:15 ` [PATCH v5 0/5] Add support for T-HEAD C9xx PMU extensions Andrew Jones
2022-10-13 4:26 ` Anup Patel
6 siblings, 1 reply; 16+ messages in thread
From: Heiko Stuebner @ 2022-10-04 16:42 UTC (permalink / raw)
To: opensbi
With the T-HEAD C9XX cores being designed before or during ratification
of the SSCOFPMF extension, they implement a PMU extension that behaves
very similar but not equal to it by providing overflow interrupts though
in a slightly different registers format.
The sun20i-d1 is using this core. So implement the necessary overrides
to allow its pmu to be used via the standard sbi-pmu extension.
For now it's also the only soc using this core, so keep the additional
code in the d1-space for now.
Reviewed-by: Guo Ren <guoren@kernel.org>
Signed-off-by: Heiko Stuebner <heiko@sntech.de>
---
platform/generic/allwinner/sun20i-d1.c | 60 ++++++++++++
platform/generic/include/thead_c9xx.h | 127 +++++++++++++++++++++++++
2 files changed, 187 insertions(+)
create mode 100644 platform/generic/include/thead_c9xx.h
diff --git a/platform/generic/allwinner/sun20i-d1.c b/platform/generic/allwinner/sun20i-d1.c
index 5b2656c..6a502e5 100644
--- a/platform/generic/allwinner/sun20i-d1.c
+++ b/platform/generic/allwinner/sun20i-d1.c
@@ -5,11 +5,13 @@
*/
#include <platform_override.h>
+#include <thead_c9xx.h>
#include <sbi/riscv_io.h>
#include <sbi/sbi_bitops.h>
#include <sbi/sbi_ecall_interface.h>
#include <sbi/sbi_error.h>
#include <sbi/sbi_hsm.h>
+#include <sbi/sbi_pmu.h>
#include <sbi_utils/fdt/fdt_helper.h>
#include <sbi_utils/irqchip/fdt_irqchip_plic.h>
@@ -199,6 +201,63 @@ static int sun20i_d1_final_init(bool cold_boot, const struct fdt_match *match)
return 0;
}
+#include <sbi/sbi_console.h>
+
+static void thead_c9xx_pmu_ctr_enable_irq(uint32_t ctr_idx)
+{
+ unsigned long mip_val;
+
+ if (ctr_idx >= SBI_PMU_HW_CTR_MAX)
+ return;
+
+ mip_val = csr_read(CSR_MIP);
+ /**
+ * Clear out the OF bit so that next interrupt can be enabled.
+ * This should be done only when the corresponding overflow interrupt
+ * bit is cleared. That indicates that software has already handled the
+ * previous interrupts or the hardware yet to set an overflow interrupt.
+ * Otherwise, there will be race conditions where we may clear the bit
+ * the software is yet to handle the interrupt.
+ */
+ if (!(mip_val & THEAD_C9XX_MIP_MOIP))
+ csr_clear(THEAD_C9XX_CSR_MCOUNTEROF, BIT(ctr_idx));
+
+ /**
+ * SSCOFPMF uses the OF bit for enabling/disabling the interrupt,
+ * while the C9XX has designated enable bits.
+ * So enable per-counter interrupt on C9xx here.
+ */
+ csr_set(THEAD_C9XX_CSR_MCOUNTERINTEN, BIT(ctr_idx));
+}
+
+static void thead_c9xx_pmu_ctr_disable_irq(uint32_t ctr_idx)
+{
+ csr_clear(THEAD_C9XX_CSR_MCOUNTERINTEN, BIT(ctr_idx));
+}
+
+static int thead_c9xx_pmu_irq_bit(void)
+{
+ return THEAD_C9XX_MIP_MOIP;
+}
+
+const struct sbi_pmu_device thead_c9xx_pmu_device = {
+ .hw_counter_enable_irq = thead_c9xx_pmu_ctr_enable_irq,
+ .hw_counter_disable_irq = thead_c9xx_pmu_ctr_disable_irq,
+ .hw_counter_irq_bit = thead_c9xx_pmu_irq_bit,
+};
+
+static int sun20i_d1_extensions_init(const struct fdt_match *match,
+ struct sbi_hart_features *hfeatures)
+{
+ sbi_pmu_set_device(&thead_c9xx_pmu_device);
+
+ /* auto-detection doesn't work on t-head c9xx cores */
+ hfeatures->mhpm_count = 29;
+ hfeatures->mhpm_bits = 64;
+
+ return 0;
+}
+
static const struct fdt_match sun20i_d1_match[] = {
{ .compatible = "allwinner,sun20i-d1" },
{ },
@@ -207,4 +266,5 @@ static const struct fdt_match sun20i_d1_match[] = {
const struct platform_override sun20i_d1 = {
.match_table = sun20i_d1_match,
.final_init = sun20i_d1_final_init,
+ .extensions_init = sun20i_d1_extensions_init,
};
diff --git a/platform/generic/include/thead_c9xx.h b/platform/generic/include/thead_c9xx.h
new file mode 100644
index 0000000..bab0408
--- /dev/null
+++ b/platform/generic/include/thead_c9xx.h
@@ -0,0 +1,127 @@
+#ifndef __RISCV_THEAD_C9XX_H____
+#define __RISCV_THEAD_C9XX_H____
+
+/* T-HEAD C9xx M mode CSR. */
+#define THEAD_C9XX_CSR_MXSTATUS 0x7c0
+#define THEAD_C9XX_CSR_MHCR 0x7c1
+#define THEAD_C9XX_CSR_MCOR 0x7c2
+#define THEAD_C9XX_CSR_MCCR2 0x7c3
+#define THEAD_C9XX_CSR_MCER2 0x7c4
+#define THEAD_C9XX_CSR_MHINT 0x7c5
+#define THEAD_C9XX_CSR_MRMR 0x7c6
+#define THEAD_C9XX_CSR_MRVBR 0x7c7
+#define THEAD_C9XX_CSR_MCER 0x7c8
+#define THEAD_C9XX_CSR_MCOUNTERWEN 0x7c9
+#define THEAD_C9XX_CSR_MCOUNTERINTEN 0x7ca
+#define THEAD_C9XX_CSR_MCOUNTEROF 0x7cb
+#define THEAD_C9XX_CSR_MHINT2 0x7cc
+#define THEAD_C9XX_CSR_MHINT3 0x7cd
+#define THEAD_C9XX_CSR_MRADDR 0x7e0
+#define THEAD_C9XX_CSR_MEXSTATUS 0x7e1
+#define THEAD_C9XX_CSR_MNMICAUSE 0x7e2
+#define THEAD_C9XX_CSR_MNMIPC 0x7e3
+#define THEAD_C9XX_CSR_MHPMCR 0x7f0
+#define THEAD_C9XX_CSR_MHPMSR 0x7f1
+#define THEAD_C9XX_CSR_MHPMER 0x7f2
+#define THEAD_C9XX_CSR_MSMPR 0x7f3
+#define THEAD_C9XX_CSR_MTEECFG 0x7f4
+#define THEAD_C9XX_CSR_MZONEID 0x7f5
+#define THEAD_C9XX_CSR_ML2CPID 0x7f6
+#define THEAD_C9XX_CSR_ML2WP 0x7f7
+#define THEAD_C9XX_CSR_MDTCMCR 0x7f8
+#define THEAD_C9XX_CSR_USP 0x7d1
+#define THEAD_C9XX_CSR_MCINS 0x7d2
+#define THEAD_C9XX_CSR_MCINDEX 0x7d3
+#define THEAD_C9XX_CSR_MCDATA0 0x7d4
+#define THEAD_C9XX_CSR_MCDATA1 0x7d5
+#define THEAD_C9XX_CSR_MEICR 0x7d6
+#define THEAD_C9XX_CSR_MEICR2 0x7d7
+#define THEAD_C9XX_CSR_MBEADDR 0x7d8
+#define THEAD_C9XX_CSR_MCPUID 0xfc0
+#define THEAD_C9XX_CSR_MAPBADDR 0xfc1
+#define THEAD_C9XX_CSR_MWMSR 0xfc2
+#define THEAD_C9XX_CSR_MHALTCAUSE 0xfe0
+#define THEAD_C9XX_CSR_MDBGINFO 0xfe1
+#define THEAD_C9XX_CSR_MPCFIFO 0xfe2
+
+/* T-HEAD C9xx S mode CSR. */
+#define THEAD_C9XX_CSR_SXSTATUS 0x5c0
+#define THEAD_C9XX_CSR_SHCR 0x5c1
+#define THEAD_C9XX_CSR_SCER2 0x5c2
+#define THEAD_C9XX_CSR_SCER 0x5c3
+#define THEAD_C9XX_CSR_SCOUNTERINTEN 0x5c4
+#define THEAD_C9XX_CSR_SCOUNTEROF 0x5c5
+#define THEAD_C9XX_CSR_SHINT 0x5c6
+#define THEAD_C9XX_CSR_SHINT2 0x5c7
+#define THEAD_C9XX_CSR_SHPMINHIBIT 0x5c8
+#define THEAD_C9XX_CSR_SHPMCR 0x5c9
+#define THEAD_C9XX_CSR_SHPMSR 0x5ca
+#define THEAD_C9XX_CSR_SHPMER 0x5cb
+#define THEAD_C9XX_CSR_SL2CPID 0x5cc
+#define THEAD_C9XX_CSR_SL2WP 0x5cd
+#define THEAD_C9XX_CSR_SBEADDR 0x5d0
+#define THEAD_C9XX_CSR_SCYCLE 0x5e0
+#define THEAD_C9XX_CSR_SHPMCOUNTER1 0x5e1
+#define THEAD_C9XX_CSR_SHPMCOUNTER2 0x5e2
+#define THEAD_C9XX_CSR_SHPMCOUNTER3 0x5e3
+#define THEAD_C9XX_CSR_SHPMCOUNTER4 0x5e4
+#define THEAD_C9XX_CSR_SHPMCOUNTER5 0x5e5
+#define THEAD_C9XX_CSR_SHPMCOUNTER6 0x5e6
+#define THEAD_C9XX_CSR_SHPMCOUNTER7 0x5e7
+#define THEAD_C9XX_CSR_SHPMCOUNTER8 0x5e8
+#define THEAD_C9XX_CSR_SHPMCOUNTER9 0x5e9
+#define THEAD_C9XX_CSR_SHPMCOUNTER10 0x5ea
+#define THEAD_C9XX_CSR_SHPMCOUNTER11 0x5eb
+#define THEAD_C9XX_CSR_SHPMCOUNTER12 0x5ec
+#define THEAD_C9XX_CSR_SHPMCOUNTER13 0x5ed
+#define THEAD_C9XX_CSR_SHPMCOUNTER14 0x5ee
+#define THEAD_C9XX_CSR_SHPMCOUNTER15 0x5ef
+#define THEAD_C9XX_CSR_SHPMCOUNTER16 0x5f0
+#define THEAD_C9XX_CSR_SHPMCOUNTER17 0x5f1
+#define THEAD_C9XX_CSR_SHPMCOUNTER18 0x5f2
+#define THEAD_C9XX_CSR_SHPMCOUNTER19 0x5f3
+#define THEAD_C9XX_CSR_SHPMCOUNTER20 0x5f4
+#define THEAD_C9XX_CSR_SHPMCOUNTER21 0x5f5
+#define THEAD_C9XX_CSR_SHPMCOUNTER22 0x5f6
+#define THEAD_C9XX_CSR_SHPMCOUNTER23 0x5f7
+#define THEAD_C9XX_CSR_SHPMCOUNTER24 0x5f8
+#define THEAD_C9XX_CSR_SHPMCOUNTER25 0x5f9
+#define THEAD_C9XX_CSR_SHPMCOUNTER26 0x5fa
+#define THEAD_C9XX_CSR_SHPMCOUNTER27 0x5fb
+#define THEAD_C9XX_CSR_SHPMCOUNTER28 0x5fc
+#define THEAD_C9XX_CSR_SHPMCOUNTER29 0x5fd
+#define THEAD_C9XX_CSR_SHPMCOUNTER30 0x5fe
+#define THEAD_C9XX_CSR_SHPMCOUNTER31 0x5ff
+
+/* T-HEAD C9xx U mode CSR. */
+#define THEAD_C9XX_CSR_FXCR 0x800
+
+/* T-HEAD C9xx MMU extentions. */
+#define THEAD_C9XX_CSR_SMIR 0x9c0
+#define THEAD_C9XX_CSR_SMEL 0x9c1
+#define THEAD_C9XX_CSR_SMEH 0x9c2
+#define THEAD_C9XX_CSR_SMCIR 0x9c3
+
+/* T-HEAD C9xx Security CSR(May be droped). */
+#define THEAD_C9XX_CSR_MEBR 0xbe0
+#define THEAD_C9XX_CSR_NT_MSTATUS 0xbe1
+#define THEAD_C9XX_CSR_NT_MIE 0xbe2
+#define THEAD_C9XX_CSR_NT_MTVEC 0xbe3
+#define THEAD_C9XX_CSR_NT_MTVT 0xbe4
+#define THEAD_C9XX_CSR_NT_MEPC 0xbe5
+#define THEAD_C9XX_CSR_NT_MCAUSE 0xbe6
+#define THEAD_C9XX_CSR_NT_MIP 0xbe7
+#define THEAD_C9XX_CSR_NT_MINTSTATE 0xbe8
+#define THEAD_C9XX_CSR_NT_MXSTATUS 0xbe9
+#define THEAD_C9XX_CSR_NT_MEBR 0xbea
+#define THEAD_C9XX_CSR_NT_MSP 0xbeb
+#define THEAD_C9XX_CSR_T_USP 0xbec
+#define THEAD_C9XX_CSR_T_MDCR 0xbed
+#define THEAD_C9XX_CSR_T_MPCR 0xbee
+#define THEAD_C9XX_CSR_PMPTEECFG 0xbef
+
+/* T-HEAD C9xx MIP CSR extension */
+#define THEAD_C9XX_IRQ_PMU_OVF 17
+#define THEAD_C9XX_MIP_MOIP (_UL(1) << THEAD_C9XX_IRQ_PMU_OVF)
+
+#endif
--
2.35.1
^ permalink raw reply related [flat|nested] 16+ messages in thread* [PATCH v5 5/5] platform: generic: allwinner: add support for c9xx pmu
2022-10-04 16:42 ` [PATCH v5 5/5] platform: generic: allwinner: add support for c9xx pmu Heiko Stuebner
@ 2022-10-13 4:09 ` Anup Patel
0 siblings, 0 replies; 16+ messages in thread
From: Anup Patel @ 2022-10-13 4:09 UTC (permalink / raw)
To: opensbi
On Tue, Oct 4, 2022 at 10:13 PM Heiko Stuebner <heiko@sntech.de> wrote:
>
> With the T-HEAD C9XX cores being designed before or during ratification
> of the SSCOFPMF extension, they implement a PMU extension that behaves
> very similar but not equal to it by providing overflow interrupts though
> in a slightly different registers format.
>
> The sun20i-d1 is using this core. So implement the necessary overrides
> to allow its pmu to be used via the standard sbi-pmu extension.
>
> For now it's also the only soc using this core, so keep the additional
> code in the d1-space for now.
>
> Reviewed-by: Guo Ren <guoren@kernel.org>
> Signed-off-by: Heiko Stuebner <heiko@sntech.de>
Looks good to me.
Reviewed-by: Anup Patel <anup@brainfault.org>
Regards,
Anup
> ---
> platform/generic/allwinner/sun20i-d1.c | 60 ++++++++++++
> platform/generic/include/thead_c9xx.h | 127 +++++++++++++++++++++++++
> 2 files changed, 187 insertions(+)
> create mode 100644 platform/generic/include/thead_c9xx.h
>
> diff --git a/platform/generic/allwinner/sun20i-d1.c b/platform/generic/allwinner/sun20i-d1.c
> index 5b2656c..6a502e5 100644
> --- a/platform/generic/allwinner/sun20i-d1.c
> +++ b/platform/generic/allwinner/sun20i-d1.c
> @@ -5,11 +5,13 @@
> */
>
> #include <platform_override.h>
> +#include <thead_c9xx.h>
> #include <sbi/riscv_io.h>
> #include <sbi/sbi_bitops.h>
> #include <sbi/sbi_ecall_interface.h>
> #include <sbi/sbi_error.h>
> #include <sbi/sbi_hsm.h>
> +#include <sbi/sbi_pmu.h>
> #include <sbi_utils/fdt/fdt_helper.h>
> #include <sbi_utils/irqchip/fdt_irqchip_plic.h>
>
> @@ -199,6 +201,63 @@ static int sun20i_d1_final_init(bool cold_boot, const struct fdt_match *match)
> return 0;
> }
>
> +#include <sbi/sbi_console.h>
> +
> +static void thead_c9xx_pmu_ctr_enable_irq(uint32_t ctr_idx)
> +{
> + unsigned long mip_val;
> +
> + if (ctr_idx >= SBI_PMU_HW_CTR_MAX)
> + return;
> +
> + mip_val = csr_read(CSR_MIP);
> + /**
> + * Clear out the OF bit so that next interrupt can be enabled.
> + * This should be done only when the corresponding overflow interrupt
> + * bit is cleared. That indicates that software has already handled the
> + * previous interrupts or the hardware yet to set an overflow interrupt.
> + * Otherwise, there will be race conditions where we may clear the bit
> + * the software is yet to handle the interrupt.
> + */
> + if (!(mip_val & THEAD_C9XX_MIP_MOIP))
> + csr_clear(THEAD_C9XX_CSR_MCOUNTEROF, BIT(ctr_idx));
> +
> + /**
> + * SSCOFPMF uses the OF bit for enabling/disabling the interrupt,
> + * while the C9XX has designated enable bits.
> + * So enable per-counter interrupt on C9xx here.
> + */
> + csr_set(THEAD_C9XX_CSR_MCOUNTERINTEN, BIT(ctr_idx));
> +}
> +
> +static void thead_c9xx_pmu_ctr_disable_irq(uint32_t ctr_idx)
> +{
> + csr_clear(THEAD_C9XX_CSR_MCOUNTERINTEN, BIT(ctr_idx));
> +}
> +
> +static int thead_c9xx_pmu_irq_bit(void)
> +{
> + return THEAD_C9XX_MIP_MOIP;
> +}
> +
> +const struct sbi_pmu_device thead_c9xx_pmu_device = {
> + .hw_counter_enable_irq = thead_c9xx_pmu_ctr_enable_irq,
> + .hw_counter_disable_irq = thead_c9xx_pmu_ctr_disable_irq,
> + .hw_counter_irq_bit = thead_c9xx_pmu_irq_bit,
> +};
> +
> +static int sun20i_d1_extensions_init(const struct fdt_match *match,
> + struct sbi_hart_features *hfeatures)
> +{
> + sbi_pmu_set_device(&thead_c9xx_pmu_device);
> +
> + /* auto-detection doesn't work on t-head c9xx cores */
> + hfeatures->mhpm_count = 29;
> + hfeatures->mhpm_bits = 64;
> +
> + return 0;
> +}
> +
> static const struct fdt_match sun20i_d1_match[] = {
> { .compatible = "allwinner,sun20i-d1" },
> { },
> @@ -207,4 +266,5 @@ static const struct fdt_match sun20i_d1_match[] = {
> const struct platform_override sun20i_d1 = {
> .match_table = sun20i_d1_match,
> .final_init = sun20i_d1_final_init,
> + .extensions_init = sun20i_d1_extensions_init,
> };
> diff --git a/platform/generic/include/thead_c9xx.h b/platform/generic/include/thead_c9xx.h
> new file mode 100644
> index 0000000..bab0408
> --- /dev/null
> +++ b/platform/generic/include/thead_c9xx.h
> @@ -0,0 +1,127 @@
> +#ifndef __RISCV_THEAD_C9XX_H____
> +#define __RISCV_THEAD_C9XX_H____
> +
> +/* T-HEAD C9xx M mode CSR. */
> +#define THEAD_C9XX_CSR_MXSTATUS 0x7c0
> +#define THEAD_C9XX_CSR_MHCR 0x7c1
> +#define THEAD_C9XX_CSR_MCOR 0x7c2
> +#define THEAD_C9XX_CSR_MCCR2 0x7c3
> +#define THEAD_C9XX_CSR_MCER2 0x7c4
> +#define THEAD_C9XX_CSR_MHINT 0x7c5
> +#define THEAD_C9XX_CSR_MRMR 0x7c6
> +#define THEAD_C9XX_CSR_MRVBR 0x7c7
> +#define THEAD_C9XX_CSR_MCER 0x7c8
> +#define THEAD_C9XX_CSR_MCOUNTERWEN 0x7c9
> +#define THEAD_C9XX_CSR_MCOUNTERINTEN 0x7ca
> +#define THEAD_C9XX_CSR_MCOUNTEROF 0x7cb
> +#define THEAD_C9XX_CSR_MHINT2 0x7cc
> +#define THEAD_C9XX_CSR_MHINT3 0x7cd
> +#define THEAD_C9XX_CSR_MRADDR 0x7e0
> +#define THEAD_C9XX_CSR_MEXSTATUS 0x7e1
> +#define THEAD_C9XX_CSR_MNMICAUSE 0x7e2
> +#define THEAD_C9XX_CSR_MNMIPC 0x7e3
> +#define THEAD_C9XX_CSR_MHPMCR 0x7f0
> +#define THEAD_C9XX_CSR_MHPMSR 0x7f1
> +#define THEAD_C9XX_CSR_MHPMER 0x7f2
> +#define THEAD_C9XX_CSR_MSMPR 0x7f3
> +#define THEAD_C9XX_CSR_MTEECFG 0x7f4
> +#define THEAD_C9XX_CSR_MZONEID 0x7f5
> +#define THEAD_C9XX_CSR_ML2CPID 0x7f6
> +#define THEAD_C9XX_CSR_ML2WP 0x7f7
> +#define THEAD_C9XX_CSR_MDTCMCR 0x7f8
> +#define THEAD_C9XX_CSR_USP 0x7d1
> +#define THEAD_C9XX_CSR_MCINS 0x7d2
> +#define THEAD_C9XX_CSR_MCINDEX 0x7d3
> +#define THEAD_C9XX_CSR_MCDATA0 0x7d4
> +#define THEAD_C9XX_CSR_MCDATA1 0x7d5
> +#define THEAD_C9XX_CSR_MEICR 0x7d6
> +#define THEAD_C9XX_CSR_MEICR2 0x7d7
> +#define THEAD_C9XX_CSR_MBEADDR 0x7d8
> +#define THEAD_C9XX_CSR_MCPUID 0xfc0
> +#define THEAD_C9XX_CSR_MAPBADDR 0xfc1
> +#define THEAD_C9XX_CSR_MWMSR 0xfc2
> +#define THEAD_C9XX_CSR_MHALTCAUSE 0xfe0
> +#define THEAD_C9XX_CSR_MDBGINFO 0xfe1
> +#define THEAD_C9XX_CSR_MPCFIFO 0xfe2
> +
> +/* T-HEAD C9xx S mode CSR. */
> +#define THEAD_C9XX_CSR_SXSTATUS 0x5c0
> +#define THEAD_C9XX_CSR_SHCR 0x5c1
> +#define THEAD_C9XX_CSR_SCER2 0x5c2
> +#define THEAD_C9XX_CSR_SCER 0x5c3
> +#define THEAD_C9XX_CSR_SCOUNTERINTEN 0x5c4
> +#define THEAD_C9XX_CSR_SCOUNTEROF 0x5c5
> +#define THEAD_C9XX_CSR_SHINT 0x5c6
> +#define THEAD_C9XX_CSR_SHINT2 0x5c7
> +#define THEAD_C9XX_CSR_SHPMINHIBIT 0x5c8
> +#define THEAD_C9XX_CSR_SHPMCR 0x5c9
> +#define THEAD_C9XX_CSR_SHPMSR 0x5ca
> +#define THEAD_C9XX_CSR_SHPMER 0x5cb
> +#define THEAD_C9XX_CSR_SL2CPID 0x5cc
> +#define THEAD_C9XX_CSR_SL2WP 0x5cd
> +#define THEAD_C9XX_CSR_SBEADDR 0x5d0
> +#define THEAD_C9XX_CSR_SCYCLE 0x5e0
> +#define THEAD_C9XX_CSR_SHPMCOUNTER1 0x5e1
> +#define THEAD_C9XX_CSR_SHPMCOUNTER2 0x5e2
> +#define THEAD_C9XX_CSR_SHPMCOUNTER3 0x5e3
> +#define THEAD_C9XX_CSR_SHPMCOUNTER4 0x5e4
> +#define THEAD_C9XX_CSR_SHPMCOUNTER5 0x5e5
> +#define THEAD_C9XX_CSR_SHPMCOUNTER6 0x5e6
> +#define THEAD_C9XX_CSR_SHPMCOUNTER7 0x5e7
> +#define THEAD_C9XX_CSR_SHPMCOUNTER8 0x5e8
> +#define THEAD_C9XX_CSR_SHPMCOUNTER9 0x5e9
> +#define THEAD_C9XX_CSR_SHPMCOUNTER10 0x5ea
> +#define THEAD_C9XX_CSR_SHPMCOUNTER11 0x5eb
> +#define THEAD_C9XX_CSR_SHPMCOUNTER12 0x5ec
> +#define THEAD_C9XX_CSR_SHPMCOUNTER13 0x5ed
> +#define THEAD_C9XX_CSR_SHPMCOUNTER14 0x5ee
> +#define THEAD_C9XX_CSR_SHPMCOUNTER15 0x5ef
> +#define THEAD_C9XX_CSR_SHPMCOUNTER16 0x5f0
> +#define THEAD_C9XX_CSR_SHPMCOUNTER17 0x5f1
> +#define THEAD_C9XX_CSR_SHPMCOUNTER18 0x5f2
> +#define THEAD_C9XX_CSR_SHPMCOUNTER19 0x5f3
> +#define THEAD_C9XX_CSR_SHPMCOUNTER20 0x5f4
> +#define THEAD_C9XX_CSR_SHPMCOUNTER21 0x5f5
> +#define THEAD_C9XX_CSR_SHPMCOUNTER22 0x5f6
> +#define THEAD_C9XX_CSR_SHPMCOUNTER23 0x5f7
> +#define THEAD_C9XX_CSR_SHPMCOUNTER24 0x5f8
> +#define THEAD_C9XX_CSR_SHPMCOUNTER25 0x5f9
> +#define THEAD_C9XX_CSR_SHPMCOUNTER26 0x5fa
> +#define THEAD_C9XX_CSR_SHPMCOUNTER27 0x5fb
> +#define THEAD_C9XX_CSR_SHPMCOUNTER28 0x5fc
> +#define THEAD_C9XX_CSR_SHPMCOUNTER29 0x5fd
> +#define THEAD_C9XX_CSR_SHPMCOUNTER30 0x5fe
> +#define THEAD_C9XX_CSR_SHPMCOUNTER31 0x5ff
> +
> +/* T-HEAD C9xx U mode CSR. */
> +#define THEAD_C9XX_CSR_FXCR 0x800
> +
> +/* T-HEAD C9xx MMU extentions. */
> +#define THEAD_C9XX_CSR_SMIR 0x9c0
> +#define THEAD_C9XX_CSR_SMEL 0x9c1
> +#define THEAD_C9XX_CSR_SMEH 0x9c2
> +#define THEAD_C9XX_CSR_SMCIR 0x9c3
> +
> +/* T-HEAD C9xx Security CSR(May be droped). */
> +#define THEAD_C9XX_CSR_MEBR 0xbe0
> +#define THEAD_C9XX_CSR_NT_MSTATUS 0xbe1
> +#define THEAD_C9XX_CSR_NT_MIE 0xbe2
> +#define THEAD_C9XX_CSR_NT_MTVEC 0xbe3
> +#define THEAD_C9XX_CSR_NT_MTVT 0xbe4
> +#define THEAD_C9XX_CSR_NT_MEPC 0xbe5
> +#define THEAD_C9XX_CSR_NT_MCAUSE 0xbe6
> +#define THEAD_C9XX_CSR_NT_MIP 0xbe7
> +#define THEAD_C9XX_CSR_NT_MINTSTATE 0xbe8
> +#define THEAD_C9XX_CSR_NT_MXSTATUS 0xbe9
> +#define THEAD_C9XX_CSR_NT_MEBR 0xbea
> +#define THEAD_C9XX_CSR_NT_MSP 0xbeb
> +#define THEAD_C9XX_CSR_T_USP 0xbec
> +#define THEAD_C9XX_CSR_T_MDCR 0xbed
> +#define THEAD_C9XX_CSR_T_MPCR 0xbee
> +#define THEAD_C9XX_CSR_PMPTEECFG 0xbef
> +
> +/* T-HEAD C9xx MIP CSR extension */
> +#define THEAD_C9XX_IRQ_PMU_OVF 17
> +#define THEAD_C9XX_MIP_MOIP (_UL(1) << THEAD_C9XX_IRQ_PMU_OVF)
> +
> +#endif
> --
> 2.35.1
>
>
> --
> opensbi mailing list
> opensbi at lists.infradead.org
> http://lists.infradead.org/mailman/listinfo/opensbi
^ permalink raw reply [flat|nested] 16+ messages in thread
* [PATCH v5 0/5] Add support for T-HEAD C9xx PMU extensions
2022-10-04 16:42 [PATCH v5 0/5] Add support for T-HEAD C9xx PMU extensions Heiko Stuebner
` (4 preceding siblings ...)
2022-10-04 16:42 ` [PATCH v5 5/5] platform: generic: allwinner: add support for c9xx pmu Heiko Stuebner
@ 2022-10-04 17:15 ` Andrew Jones
2022-10-05 0:31 ` Guo Ren
2022-10-13 4:26 ` Anup Patel
6 siblings, 1 reply; 16+ messages in thread
From: Andrew Jones @ 2022-10-04 17:15 UTC (permalink / raw)
To: opensbi
On Tue, Oct 04, 2022 at 06:42:22PM +0200, Heiko Stuebner wrote:
> The T-HEAD C9XX cores implement functionality very similar to SSCOFPMF.
> Instead of implementing a separate interface into SBI as done in v1,
> we can add the C9XX tidbits with quite minimal overhead and leaverage
> the existing SBI pmu interface including giving access to the firmware
> counters.
>
> The current only hickup is the detection override in sbi_hart, where
> I still need to find out why the MHPMCOUNTERs are not writeable
> at _that_ point of the boot, but with this series on top of openSBI 1.1
> and the matching kernel perf patch I get reasonable results for example
> for:
>
> perf stat -e cycles -e instructions -e L1-icache-load-misses -e L1-icache-loads ls
>
> Performance counter stats for 'ls':
>
> 17119496 cycles
> 2867765 instructions # 0.17 insn per cycle
> 55929 L1-icache-load-misses # 1.61% of all L1-icache accesses
> 3467346 L1-icache-loads
>
> 0.030156216 seconds time elapsed
>
> 0.000000000 seconds user
> 0.023496000 seconds sys
>
> changes in v5:
> - use csr_set, csr_clear in allwinner pmu functions
> - expose hart_features struct into header
> - make hart_features param for extension_init callback
> to allow platforms to override specific settings
>
> changes in v4:
> - use the new sbi_pmu_device structure for holding the
> overrides and extend it where needed
>
> changes in v3:
> - follow Atish's advice and implement an abstraction
> to not pollute the core pmu with cpu-specific variants
>
> changes in v2:
> - don't implement a separate interface but instead modify
> the sbi-pmu to allow the c9xx to use standard pmu interface
>
>
> Heiko Stuebner (5):
> lib: sbi_pmu: move pmu irq information into pmu itself
> lib: sbi_hart: move hart_features struct to a public location
> lib: sbi_platform: expose hart_features to extension_init callback
> platform: generic: add extensions_init handler and platform-override
> platform: generic: allwinner: add support for c9xx pmu
>
> include/sbi/sbi_hart.h | 11 ++
> include/sbi/sbi_platform.h | 8 +-
> include/sbi/sbi_pmu.h | 8 ++
> lib/sbi/sbi_hart.c | 43 +++----
> lib/sbi/sbi_pmu.c | 12 ++
> platform/generic/allwinner/sun20i-d1.c | 60 +++++++++
> platform/generic/include/platform_override.h | 3 +
> platform/generic/include/thead_c9xx.h | 127 +++++++++++++++++++
> platform/generic/platform.c | 10 ++
> 9 files changed, 253 insertions(+), 29 deletions(-)
> create mode 100644 platform/generic/include/thead_c9xx.h
>
> --
> 2.35.1
>
>
> --
> opensbi mailing list
> opensbi at lists.infradead.org
> http://lists.infradead.org/mailman/listinfo/opensbi
For the series
Reviewed-by: Andrew Jones <ajones@ventanamicro.com>
^ permalink raw reply [flat|nested] 16+ messages in thread* [PATCH v5 0/5] Add support for T-HEAD C9xx PMU extensions
2022-10-04 17:15 ` [PATCH v5 0/5] Add support for T-HEAD C9xx PMU extensions Andrew Jones
@ 2022-10-05 0:31 ` Guo Ren
0 siblings, 0 replies; 16+ messages in thread
From: Guo Ren @ 2022-10-05 0:31 UTC (permalink / raw)
To: opensbi
For the series
Reviewed-by: Guo Ren <guoren@kernel.org>
On Wed, Oct 5, 2022 at 1:16 AM Andrew Jones <ajones@ventanamicro.com> wrote:
>
> On Tue, Oct 04, 2022 at 06:42:22PM +0200, Heiko Stuebner wrote:
> > The T-HEAD C9XX cores implement functionality very similar to SSCOFPMF.
> > Instead of implementing a separate interface into SBI as done in v1,
> > we can add the C9XX tidbits with quite minimal overhead and leaverage
> > the existing SBI pmu interface including giving access to the firmware
> > counters.
> >
> > The current only hickup is the detection override in sbi_hart, where
> > I still need to find out why the MHPMCOUNTERs are not writeable
> > at _that_ point of the boot, but with this series on top of openSBI 1.1
> > and the matching kernel perf patch I get reasonable results for example
> > for:
> >
> > perf stat -e cycles -e instructions -e L1-icache-load-misses -e L1-icache-loads ls
> >
> > Performance counter stats for 'ls':
> >
> > 17119496 cycles
> > 2867765 instructions # 0.17 insn per cycle
> > 55929 L1-icache-load-misses # 1.61% of all L1-icache accesses
> > 3467346 L1-icache-loads
> >
> > 0.030156216 seconds time elapsed
> >
> > 0.000000000 seconds user
> > 0.023496000 seconds sys
> >
> > changes in v5:
> > - use csr_set, csr_clear in allwinner pmu functions
> > - expose hart_features struct into header
> > - make hart_features param for extension_init callback
> > to allow platforms to override specific settings
> >
> > changes in v4:
> > - use the new sbi_pmu_device structure for holding the
> > overrides and extend it where needed
> >
> > changes in v3:
> > - follow Atish's advice and implement an abstraction
> > to not pollute the core pmu with cpu-specific variants
> >
> > changes in v2:
> > - don't implement a separate interface but instead modify
> > the sbi-pmu to allow the c9xx to use standard pmu interface
> >
> >
> > Heiko Stuebner (5):
> > lib: sbi_pmu: move pmu irq information into pmu itself
> > lib: sbi_hart: move hart_features struct to a public location
> > lib: sbi_platform: expose hart_features to extension_init callback
> > platform: generic: add extensions_init handler and platform-override
> > platform: generic: allwinner: add support for c9xx pmu
> >
> > include/sbi/sbi_hart.h | 11 ++
> > include/sbi/sbi_platform.h | 8 +-
> > include/sbi/sbi_pmu.h | 8 ++
> > lib/sbi/sbi_hart.c | 43 +++----
> > lib/sbi/sbi_pmu.c | 12 ++
> > platform/generic/allwinner/sun20i-d1.c | 60 +++++++++
> > platform/generic/include/platform_override.h | 3 +
> > platform/generic/include/thead_c9xx.h | 127 +++++++++++++++++++
> > platform/generic/platform.c | 10 ++
> > 9 files changed, 253 insertions(+), 29 deletions(-)
> > create mode 100644 platform/generic/include/thead_c9xx.h
> >
> > --
> > 2.35.1
> >
> >
> > --
> > opensbi mailing list
> > opensbi at lists.infradead.org
> > http://lists.infradead.org/mailman/listinfo/opensbi
>
> For the series
>
> Reviewed-by: Andrew Jones <ajones@ventanamicro.com>
--
Best Regards
Guo Ren
^ permalink raw reply [flat|nested] 16+ messages in thread
* [PATCH v5 0/5] Add support for T-HEAD C9xx PMU extensions
2022-10-04 16:42 [PATCH v5 0/5] Add support for T-HEAD C9xx PMU extensions Heiko Stuebner
` (5 preceding siblings ...)
2022-10-04 17:15 ` [PATCH v5 0/5] Add support for T-HEAD C9xx PMU extensions Andrew Jones
@ 2022-10-13 4:26 ` Anup Patel
2022-10-13 7:03 ` Heiko Stuebner
6 siblings, 1 reply; 16+ messages in thread
From: Anup Patel @ 2022-10-13 4:26 UTC (permalink / raw)
To: opensbi
On Tue, Oct 4, 2022 at 10:13 PM Heiko Stuebner <heiko@sntech.de> wrote:
>
> The T-HEAD C9XX cores implement functionality very similar to SSCOFPMF.
> Instead of implementing a separate interface into SBI as done in v1,
> we can add the C9XX tidbits with quite minimal overhead and leaverage
> the existing SBI pmu interface including giving access to the firmware
> counters.
>
> The current only hickup is the detection override in sbi_hart, where
> I still need to find out why the MHPMCOUNTERs are not writeable
> at _that_ point of the boot, but with this series on top of openSBI 1.1
> and the matching kernel perf patch I get reasonable results for example
> for:
>
> perf stat -e cycles -e instructions -e L1-icache-load-misses -e L1-icache-loads ls
>
> Performance counter stats for 'ls':
>
> 17119496 cycles
> 2867765 instructions # 0.17 insn per cycle
> 55929 L1-icache-load-misses # 1.61% of all L1-icache accesses
> 3467346 L1-icache-loads
>
> 0.030156216 seconds time elapsed
>
> 0.000000000 seconds user
> 0.023496000 seconds sys
>
> changes in v5:
> - use csr_set, csr_clear in allwinner pmu functions
> - expose hart_features struct into header
> - make hart_features param for extension_init callback
> to allow platforms to override specific settings
>
> changes in v4:
> - use the new sbi_pmu_device structure for holding the
> overrides and extend it where needed
>
> changes in v3:
> - follow Atish's advice and implement an abstraction
> to not pollute the core pmu with cpu-specific variants
>
> changes in v2:
> - don't implement a separate interface but instead modify
> the sbi-pmu to allow the c9xx to use standard pmu interface
>
>
> Heiko Stuebner (5):
> lib: sbi_pmu: move pmu irq information into pmu itself
> lib: sbi_hart: move hart_features struct to a public location
> lib: sbi_platform: expose hart_features to extension_init callback
> platform: generic: add extensions_init handler and platform-override
> platform: generic: allwinner: add support for c9xx pmu
Applied this series to the riscv/opensbi repo.
Thanks,
Anup
>
> include/sbi/sbi_hart.h | 11 ++
> include/sbi/sbi_platform.h | 8 +-
> include/sbi/sbi_pmu.h | 8 ++
> lib/sbi/sbi_hart.c | 43 +++----
> lib/sbi/sbi_pmu.c | 12 ++
> platform/generic/allwinner/sun20i-d1.c | 60 +++++++++
> platform/generic/include/platform_override.h | 3 +
> platform/generic/include/thead_c9xx.h | 127 +++++++++++++++++++
> platform/generic/platform.c | 10 ++
> 9 files changed, 253 insertions(+), 29 deletions(-)
> create mode 100644 platform/generic/include/thead_c9xx.h
>
> --
> 2.35.1
>
>
> --
> opensbi mailing list
> opensbi at lists.infradead.org
> http://lists.infradead.org/mailman/listinfo/opensbi
^ permalink raw reply [flat|nested] 16+ messages in thread* [PATCH v5 0/5] Add support for T-HEAD C9xx PMU extensions
2022-10-13 4:26 ` Anup Patel
@ 2022-10-13 7:03 ` Heiko Stuebner
2022-10-13 16:44 ` Guo Ren
0 siblings, 1 reply; 16+ messages in thread
From: Heiko Stuebner @ 2022-10-13 7:03 UTC (permalink / raw)
To: opensbi
Am Donnerstag, 13. Oktober 2022, 06:26:43 CEST schrieb Anup Patel:
> On Tue, Oct 4, 2022 at 10:13 PM Heiko Stuebner <heiko@sntech.de> wrote:
> >
> > The T-HEAD C9XX cores implement functionality very similar to SSCOFPMF.
> > Instead of implementing a separate interface into SBI as done in v1,
> > we can add the C9XX tidbits with quite minimal overhead and leaverage
> > the existing SBI pmu interface including giving access to the firmware
> > counters.
> >
> > The current only hickup is the detection override in sbi_hart, where
> > I still need to find out why the MHPMCOUNTERs are not writeable
> > at _that_ point of the boot, but with this series on top of openSBI 1.1
> > and the matching kernel perf patch I get reasonable results for example
> > for:
> >
> > perf stat -e cycles -e instructions -e L1-icache-load-misses -e L1-icache-loads ls
> >
> > Performance counter stats for 'ls':
> >
> > 17119496 cycles
> > 2867765 instructions # 0.17 insn per cycle
> > 55929 L1-icache-load-misses # 1.61% of all L1-icache accesses
> > 3467346 L1-icache-loads
> >
> > 0.030156216 seconds time elapsed
> >
> > 0.000000000 seconds user
> > 0.023496000 seconds sys
> >
> > changes in v5:
> > - use csr_set, csr_clear in allwinner pmu functions
> > - expose hart_features struct into header
> > - make hart_features param for extension_init callback
> > to allow platforms to override specific settings
> >
> > changes in v4:
> > - use the new sbi_pmu_device structure for holding the
> > overrides and extend it where needed
> >
> > changes in v3:
> > - follow Atish's advice and implement an abstraction
> > to not pollute the core pmu with cpu-specific variants
> >
> > changes in v2:
> > - don't implement a separate interface but instead modify
> > the sbi-pmu to allow the c9xx to use standard pmu interface
> >
> >
> > Heiko Stuebner (5):
> > lib: sbi_pmu: move pmu irq information into pmu itself
> > lib: sbi_hart: move hart_features struct to a public location
> > lib: sbi_platform: expose hart_features to extension_init callback
> > platform: generic: add extensions_init handler and platform-override
> > platform: generic: allwinner: add support for c9xx pmu
>
> Applied this series to the riscv/opensbi repo.
Very cool, thanks a lot for picking this up :-)
Thanks
Heiko
> > include/sbi/sbi_hart.h | 11 ++
> > include/sbi/sbi_platform.h | 8 +-
> > include/sbi/sbi_pmu.h | 8 ++
> > lib/sbi/sbi_hart.c | 43 +++----
> > lib/sbi/sbi_pmu.c | 12 ++
> > platform/generic/allwinner/sun20i-d1.c | 60 +++++++++
> > platform/generic/include/platform_override.h | 3 +
> > platform/generic/include/thead_c9xx.h | 127 +++++++++++++++++++
> > platform/generic/platform.c | 10 ++
> > 9 files changed, 253 insertions(+), 29 deletions(-)
> > create mode 100644 platform/generic/include/thead_c9xx.h
> >
> > --
> > 2.35.1
> >
> >
> > --
> > opensbi mailing list
> > opensbi at lists.infradead.org
> > http://lists.infradead.org/mailman/listinfo/opensbi
>
^ permalink raw reply [flat|nested] 16+ messages in thread
* [PATCH v5 0/5] Add support for T-HEAD C9xx PMU extensions
2022-10-13 7:03 ` Heiko Stuebner
@ 2022-10-13 16:44 ` Guo Ren
0 siblings, 0 replies; 16+ messages in thread
From: Guo Ren @ 2022-10-13 16:44 UTC (permalink / raw)
To: opensbi
Great! Thx Anup, and Heiko.
On Thu, Oct 13, 2022 at 3:04 PM Heiko Stuebner <heiko@sntech.de> wrote:
>
> Am Donnerstag, 13. Oktober 2022, 06:26:43 CEST schrieb Anup Patel:
> > On Tue, Oct 4, 2022 at 10:13 PM Heiko Stuebner <heiko@sntech.de> wrote:
> > >
> > > The T-HEAD C9XX cores implement functionality very similar to SSCOFPMF.
> > > Instead of implementing a separate interface into SBI as done in v1,
> > > we can add the C9XX tidbits with quite minimal overhead and leaverage
> > > the existing SBI pmu interface including giving access to the firmware
> > > counters.
> > >
> > > The current only hickup is the detection override in sbi_hart, where
> > > I still need to find out why the MHPMCOUNTERs are not writeable
> > > at _that_ point of the boot, but with this series on top of openSBI 1.1
> > > and the matching kernel perf patch I get reasonable results for example
> > > for:
> > >
> > > perf stat -e cycles -e instructions -e L1-icache-load-misses -e L1-icache-loads ls
> > >
> > > Performance counter stats for 'ls':
> > >
> > > 17119496 cycles
> > > 2867765 instructions # 0.17 insn per cycle
> > > 55929 L1-icache-load-misses # 1.61% of all L1-icache accesses
> > > 3467346 L1-icache-loads
> > >
> > > 0.030156216 seconds time elapsed
> > >
> > > 0.000000000 seconds user
> > > 0.023496000 seconds sys
> > >
> > > changes in v5:
> > > - use csr_set, csr_clear in allwinner pmu functions
> > > - expose hart_features struct into header
> > > - make hart_features param for extension_init callback
> > > to allow platforms to override specific settings
> > >
> > > changes in v4:
> > > - use the new sbi_pmu_device structure for holding the
> > > overrides and extend it where needed
> > >
> > > changes in v3:
> > > - follow Atish's advice and implement an abstraction
> > > to not pollute the core pmu with cpu-specific variants
> > >
> > > changes in v2:
> > > - don't implement a separate interface but instead modify
> > > the sbi-pmu to allow the c9xx to use standard pmu interface
> > >
> > >
> > > Heiko Stuebner (5):
> > > lib: sbi_pmu: move pmu irq information into pmu itself
> > > lib: sbi_hart: move hart_features struct to a public location
> > > lib: sbi_platform: expose hart_features to extension_init callback
> > > platform: generic: add extensions_init handler and platform-override
> > > platform: generic: allwinner: add support for c9xx pmu
> >
> > Applied this series to the riscv/opensbi repo.
>
> Very cool, thanks a lot for picking this up :-)
>
> Thanks
> Heiko
>
>
> > > include/sbi/sbi_hart.h | 11 ++
> > > include/sbi/sbi_platform.h | 8 +-
> > > include/sbi/sbi_pmu.h | 8 ++
> > > lib/sbi/sbi_hart.c | 43 +++----
> > > lib/sbi/sbi_pmu.c | 12 ++
> > > platform/generic/allwinner/sun20i-d1.c | 60 +++++++++
> > > platform/generic/include/platform_override.h | 3 +
> > > platform/generic/include/thead_c9xx.h | 127 +++++++++++++++++++
> > > platform/generic/platform.c | 10 ++
> > > 9 files changed, 253 insertions(+), 29 deletions(-)
> > > create mode 100644 platform/generic/include/thead_c9xx.h
> > >
> > > --
> > > 2.35.1
> > >
> > >
> > > --
> > > opensbi mailing list
> > > opensbi at lists.infradead.org
> > > http://lists.infradead.org/mailman/listinfo/opensbi
> >
>
>
>
>
--
Best Regards
Guo Ren
^ permalink raw reply [flat|nested] 16+ messages in thread