Re: [PATCH v3 1/6] drm/bridge: tc358767: Split tc_pxl_pll_en() into parameter calculation and enablement

[Alexander Stein <alexander.stein@ew.tq-group.com>]

Am Sonntag, 23. Juni 2024, 16:38:33 CEST schrieb Marek Vasut:
> Split tc_pxl_pll_en() into tc_pxl_pll_calc() which does only Pixel PLL
> parameter calculation and tc_pxl_pll_en() which calls tc_pxl_pll_calc()
> and then configures the Pixel PLL register.
> 
> This is a preparatory patch for further rework, where tc_pxl_pll_calc()
> will also be used to find out the exact clock frequency generated by the
> Pixel PLL. This frequency will be used as adjusted_mode clock frequency
> and passed down the display pipeline to obtain exactly this frequency
> on input into this bridge.
> 
> The precise input frequency that matches the Pixel PLL frequency is
> important for this bridge, as if the frequencies do not match, the
> bridge does suffer VFIFO overruns or underruns.
> 
> Signed-off-by: Marek Vasut <marex@denx.de>
> ---
> Cc: Andrzej Hajda <andrzej.hajda@intel.com>
> Cc: Daniel Vetter <daniel@ffwll.ch>
> Cc: David Airlie <airlied@gmail.com>
> Cc: Jernej Skrabec <jernej.skrabec@gmail.com>
> Cc: Jonas Karlman <jonas@kwiboo.se>
> Cc: Laurent Pinchart <Laurent.pinchart@ideasonboard.com>
> Cc: Lucas Stach <l.stach@pengutronix.de>
> Cc: Maarten Lankhorst <maarten.lankhorst@linux.intel.com>
> Cc: Maxime Ripard <mripard@kernel.org>
> Cc: Neil Armstrong <neil.armstrong@linaro.org>
> Cc: Robert Foss <rfoss@kernel.org>
> Cc: Thomas Zimmermann <tzimmermann@suse.de>
> Cc: dri-devel@lists.freedesktop.org
> Cc: kernel@dh-electronics.com
> ---
> V2: No change
> V3: No change
> ---
>  drivers/gpu/drm/bridge/tc358767.c | 37 +++++++++++++++++++++----------
>  1 file changed, 25 insertions(+), 12 deletions(-)
> 
> diff --git a/drivers/gpu/drm/bridge/tc358767.c b/drivers/gpu/drm/bridge/tc358767.c
> index b0435c8b754b4..cbb342d811ac3 100644
> --- a/drivers/gpu/drm/bridge/tc358767.c
> +++ b/drivers/gpu/drm/bridge/tc358767.c
> @@ -580,14 +580,9 @@ static int tc_pllupdate(struct tc_data *tc, unsigned int pllctrl)
>  	return 0;
>  }
>  
> -static u32 div64_round_up(u64 v, u32 d)
> +static int tc_pxl_pll_calc(struct tc_data *tc, u32 refclk, u32 pixelclock,
> +			   int *out_best_pixelclock, u32 *out_pxl_pllparam)
>  {
> -	return div_u64(v + d - 1, d);
> -}

There seems to be a rebase mishap. The removal of div64_round_up should be
put into patch 3. With that fixed:
Reviewed-by: Alexander Stein <alexander.stein@ew.tq-group.com>

Best regards,
Alexander
> -
> -static int tc_pxl_pll_en(struct tc_data *tc, u32 refclk, u32 pixelclock)
> -{
> -	int ret;
>  	int i_pre, best_pre = 1;
>  	int i_post, best_post = 1;
>  	int div, best_div = 1;
> @@ -683,11 +678,6 @@ static int tc_pxl_pll_en(struct tc_data *tc, u32 refclk, u32 pixelclock)
>  	if (best_mul == 128)
>  		best_mul = 0;
>  
> -	/* Power up PLL and switch to bypass */
> -	ret = regmap_write(tc->regmap, PXL_PLLCTRL, PLLBYP | PLLEN);
> -	if (ret)
> -		return ret;
> -
>  	pxl_pllparam  = vco_hi << 24; /* For PLL VCO >= 300 MHz = 1 */
>  	pxl_pllparam |= ext_div[best_pre] << 20; /* External Pre-divider */
>  	pxl_pllparam |= ext_div[best_post] << 16; /* External Post-divider */
> @@ -695,6 +685,29 @@ static int tc_pxl_pll_en(struct tc_data *tc, u32 refclk, u32 pixelclock)
>  	pxl_pllparam |= best_div << 8; /* Divider for PLL RefClk */
>  	pxl_pllparam |= best_mul; /* Multiplier for PLL */
>  
> +	if (out_best_pixelclock)
> +		*out_best_pixelclock = best_pixelclock;
> +
> +	if (out_pxl_pllparam)
> +		*out_pxl_pllparam = pxl_pllparam;
> +
> +	return 0;
> +}
> +
> +static int tc_pxl_pll_en(struct tc_data *tc, u32 refclk, u32 pixelclock)
> +{
> +	u32 pxl_pllparam = 0;
> +	int ret;
> +
> +	ret = tc_pxl_pll_calc(tc, refclk, pixelclock, NULL, &pxl_pllparam);
> +	if (ret)
> +		return ret;
> +
> +	/* Power up PLL and switch to bypass */
> +	ret = regmap_write(tc->regmap, PXL_PLLCTRL, PLLBYP | PLLEN);
> +	if (ret)
> +		return ret;
> +
>  	ret = regmap_write(tc->regmap, PXL_PLLPARAM, pxl_pllparam);
>  	if (ret)
>  		return ret;
> 


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